From: David Laight <David.Laight@ACULAB.COM>
To: "'Clément Léger'" <cleger@rivosinc.com>,
"Conor Dooley" <conor@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Atish Patra" <atishp@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Evan Green" <evan@rivosinc.com>,
"Björn Topel" <bjorn@rivosinc.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Ron Minnich" <rminnich@gmail.com>,
"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: RE: [PATCH 0/7] Add support to handle misaligned accesses in S-mode
Date: Wed, 4 Oct 2023 14:10:40 +0000 [thread overview]
Message-ID: <caa22904d2d7469595dcc5cb1f11be89@AcuMS.aculab.com> (raw)
In-Reply-To: <6ac16274-3816-4b46-9068-e97af66c815a@rivosinc.com>
...
> Saying that you support misaligned access does not mean that they are
> going to be efficient, just that they are supported (in fact, the uABI
> state that they may perform poorly). The compiler is actually not so
> stupid and will try to do as much aligned access as possible in what it
> generates (unless forced by some assembly, cast or whatever that can
> screw up alignment accesses). This is already the case and it will most
> probably not change.
I did a quick check.
https://godbolt.org/z/j3e9drv4e
The code generated by both clang and gcc for misaligned reads is horrid.
Gcc does a better job if the alignment is known but generates much
the same as the clang code when it isn't.
The C code is much shorter.
Even though both gcc and clang add a (different) instruction to it
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
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WARNING: multiple messages have this Message-ID (diff)
From: David Laight <David.Laight@ACULAB.COM>
To: "'Clément Léger'" <cleger@rivosinc.com>,
"Conor Dooley" <conor@kernel.org>
Cc: "Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Atish Patra" <atishp@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Evan Green" <evan@rivosinc.com>,
"Björn Topel" <bjorn@rivosinc.com>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Ron Minnich" <rminnich@gmail.com>,
"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: RE: [PATCH 0/7] Add support to handle misaligned accesses in S-mode
Date: Wed, 4 Oct 2023 14:10:40 +0000 [thread overview]
Message-ID: <caa22904d2d7469595dcc5cb1f11be89@AcuMS.aculab.com> (raw)
In-Reply-To: <6ac16274-3816-4b46-9068-e97af66c815a@rivosinc.com>
...
> Saying that you support misaligned access does not mean that they are
> going to be efficient, just that they are supported (in fact, the uABI
> state that they may perform poorly). The compiler is actually not so
> stupid and will try to do as much aligned access as possible in what it
> generates (unless forced by some assembly, cast or whatever that can
> screw up alignment accesses). This is already the case and it will most
> probably not change.
I did a quick check.
https://godbolt.org/z/j3e9drv4e
The code generated by both clang and gcc for misaligned reads is horrid.
Gcc does a better job if the alignment is known but generates much
the same as the clang code when it isn't.
The C code is much shorter.
Even though both gcc and clang add a (different) instruction to it
David
-
Registered Address Lakeside, Bramley Road, Mount Farm, Milton Keynes, MK1 1PT, UK
Registration No: 1397386 (Wales)
next prev parent reply other threads:[~2023-10-04 14:10 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-26 15:03 [PATCH 0/7] Add support to handle misaligned accesses in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 2/7] riscv: add support for misaligned handling in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 3/7] riscv: report perf event for misaligned fault Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 21:57 ` Evan Green
2023-09-26 21:57 ` Evan Green
2023-09-28 7:46 ` Clément Léger
2023-09-28 7:46 ` Clément Léger
2023-09-28 16:51 ` Evan Green
2023-09-28 16:51 ` Evan Green
2023-10-03 9:50 ` Atish Kumar Patra
2023-10-03 9:50 ` Atish Kumar Patra
2023-09-29 1:02 ` kernel test robot
2023-09-29 1:02 ` kernel test robot
2023-09-26 15:03 ` [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 21:43 ` [PATCH 0/7] Add support to handle misaligned accesses in S-mode Evan Green
2023-09-26 21:43 ` Evan Green
2023-09-28 7:49 ` Clément Léger
2023-09-28 7:49 ` Clément Léger
2023-09-28 16:48 ` Evan Green
2023-09-28 16:48 ` Evan Green
2023-10-03 8:40 ` Atish Kumar Patra
2023-10-03 8:40 ` Atish Kumar Patra
2023-10-03 15:39 ` ron minnich
2023-10-03 15:39 ` ron minnich
2023-09-30 9:23 ` Conor Dooley
2023-09-30 9:23 ` Conor Dooley
2023-10-02 7:40 ` Clément Léger
2023-10-02 7:40 ` Clément Léger
2023-10-02 10:49 ` Conor Dooley
2023-10-02 10:49 ` Conor Dooley
2023-10-02 11:18 ` Clément Léger
2023-10-02 11:18 ` Clément Léger
2023-10-02 15:32 ` ron minnich
2023-10-02 15:32 ` ron minnich
2023-10-02 22:22 ` Jessica Clarke
2023-10-02 22:22 ` Jessica Clarke
2023-10-03 15:37 ` ron minnich
2023-10-03 15:37 ` ron minnich
2023-10-03 8:12 ` Clément Léger
2023-10-03 8:12 ` Clément Léger
2023-10-04 8:26 ` David Laight
2023-10-04 8:26 ` David Laight
2023-10-04 10:03 ` Clément Léger
2023-10-04 10:03 ` Clément Léger
2023-10-04 14:10 ` David Laight [this message]
2023-10-04 14:10 ` David Laight
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