From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Atish Patra" <atishp@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Evan Green" <evan@rivosinc.com>,
"Björn Topel" <bjorn@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
"Ron Minnich" <rminnich@gmail.com>,
"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Date: Tue, 26 Sep 2023 17:03:16 +0200 [thread overview]
Message-ID: <20230926150316.1129648-8-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>
Now that trap support is ready to handle misalignment errors in S-mode,
allow the user to control the behavior of misaligned accesses using
prctl(PR_SET_UNALIGN). Add an align_ctl flag in thread_struct which
will be used to determine if we should SIGBUS the process or not on
such fault.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/include/asm/processor.h | 9 +++++++++
arch/riscv/kernel/process.c | 18 ++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 3e23e1786d05..adbe520d07c5 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -8,6 +8,7 @@
#include <linux/const.h>
#include <linux/cache.h>
+#include <linux/prctl.h>
#include <vdso/processor.h>
@@ -82,6 +83,7 @@ struct thread_struct {
unsigned long bad_cause;
unsigned long vstate_ctrl;
struct __riscv_v_ext_state vstate;
+ unsigned long align_ctl;
};
/* Whitelist the fstate from the task_struct for hardened usercopy */
@@ -94,6 +96,7 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
#define INIT_THREAD { \
.sp = sizeof(init_stack) + (long)&init_stack, \
+ .align_ctl = PR_UNALIGN_NOPRINT, \
}
#define task_pt_regs(tsk) \
@@ -134,6 +137,12 @@ extern long riscv_v_vstate_ctrl_set_current(unsigned long arg);
extern long riscv_v_vstate_ctrl_get_current(void);
#endif /* CONFIG_RISCV_ISA_V */
+extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr);
+extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
+
+#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
+#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index e32d737e039f..4f21d970a129 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -25,6 +25,7 @@
#include <asm/thread_info.h>
#include <asm/cpuidle.h>
#include <asm/vector.h>
+#include <asm/cpufeature.h>
register unsigned long gp_in_global __asm__("gp");
@@ -41,6 +42,23 @@ void arch_cpu_idle(void)
cpu_do_idle();
}
+int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
+{
+ if (!unaligned_ctl_available())
+ return -EINVAL;
+
+ tsk->thread.align_ctl = val;
+ return 0;
+}
+
+int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
+{
+ if (!unaligned_ctl_available())
+ return -EINVAL;
+
+ return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr);
+}
+
void __show_regs(struct pt_regs *regs)
{
show_regs_print_info(KERN_DEFAULT);
--
2.40.1
_______________________________________________
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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
"Atish Patra" <atishp@rivosinc.com>,
"Andrew Jones" <ajones@ventanamicro.com>,
"Evan Green" <evan@rivosinc.com>,
"Björn Topel" <bjorn@rivosinc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
"Ron Minnich" <rminnich@gmail.com>,
"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN
Date: Tue, 26 Sep 2023 17:03:16 +0200 [thread overview]
Message-ID: <20230926150316.1129648-8-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>
Now that trap support is ready to handle misalignment errors in S-mode,
allow the user to control the behavior of misaligned accesses using
prctl(PR_SET_UNALIGN). Add an align_ctl flag in thread_struct which
will be used to determine if we should SIGBUS the process or not on
such fault.
Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
arch/riscv/include/asm/processor.h | 9 +++++++++
arch/riscv/kernel/process.c | 18 ++++++++++++++++++
2 files changed, 27 insertions(+)
diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h
index 3e23e1786d05..adbe520d07c5 100644
--- a/arch/riscv/include/asm/processor.h
+++ b/arch/riscv/include/asm/processor.h
@@ -8,6 +8,7 @@
#include <linux/const.h>
#include <linux/cache.h>
+#include <linux/prctl.h>
#include <vdso/processor.h>
@@ -82,6 +83,7 @@ struct thread_struct {
unsigned long bad_cause;
unsigned long vstate_ctrl;
struct __riscv_v_ext_state vstate;
+ unsigned long align_ctl;
};
/* Whitelist the fstate from the task_struct for hardened usercopy */
@@ -94,6 +96,7 @@ static inline void arch_thread_struct_whitelist(unsigned long *offset,
#define INIT_THREAD { \
.sp = sizeof(init_stack) + (long)&init_stack, \
+ .align_ctl = PR_UNALIGN_NOPRINT, \
}
#define task_pt_regs(tsk) \
@@ -134,6 +137,12 @@ extern long riscv_v_vstate_ctrl_set_current(unsigned long arg);
extern long riscv_v_vstate_ctrl_get_current(void);
#endif /* CONFIG_RISCV_ISA_V */
+extern int get_unalign_ctl(struct task_struct *tsk, unsigned long addr);
+extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
+
+#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
+#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_RISCV_PROCESSOR_H */
diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c
index e32d737e039f..4f21d970a129 100644
--- a/arch/riscv/kernel/process.c
+++ b/arch/riscv/kernel/process.c
@@ -25,6 +25,7 @@
#include <asm/thread_info.h>
#include <asm/cpuidle.h>
#include <asm/vector.h>
+#include <asm/cpufeature.h>
register unsigned long gp_in_global __asm__("gp");
@@ -41,6 +42,23 @@ void arch_cpu_idle(void)
cpu_do_idle();
}
+int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
+{
+ if (!unaligned_ctl_available())
+ return -EINVAL;
+
+ tsk->thread.align_ctl = val;
+ return 0;
+}
+
+int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
+{
+ if (!unaligned_ctl_available())
+ return -EINVAL;
+
+ return put_user(tsk->thread.align_ctl, (unsigned long __user *)adr);
+}
+
void __show_regs(struct pt_regs *regs)
{
show_regs_print_info(KERN_DEFAULT);
--
2.40.1
next prev parent reply other threads:[~2023-09-26 15:04 UTC|newest]
Thread overview: 58+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-26 15:03 [PATCH 0/7] Add support to handle misaligned accesses in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 2/7] riscv: add support for misaligned handling in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 3/7] riscv: report perf event for misaligned fault Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 21:57 ` Evan Green
2023-09-26 21:57 ` Evan Green
2023-09-28 7:46 ` Clément Léger
2023-09-28 7:46 ` Clément Léger
2023-09-28 16:51 ` Evan Green
2023-09-28 16:51 ` Evan Green
2023-10-03 9:50 ` Atish Kumar Patra
2023-10-03 9:50 ` Atish Kumar Patra
2023-09-29 1:02 ` kernel test robot
2023-09-29 1:02 ` kernel test robot
2023-09-26 15:03 ` Clément Léger [this message]
2023-09-26 15:03 ` [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-09-26 21:43 ` [PATCH 0/7] Add support to handle misaligned accesses in S-mode Evan Green
2023-09-26 21:43 ` Evan Green
2023-09-28 7:49 ` Clément Léger
2023-09-28 7:49 ` Clément Léger
2023-09-28 16:48 ` Evan Green
2023-09-28 16:48 ` Evan Green
2023-10-03 8:40 ` Atish Kumar Patra
2023-10-03 8:40 ` Atish Kumar Patra
2023-10-03 15:39 ` ron minnich
2023-10-03 15:39 ` ron minnich
2023-09-30 9:23 ` Conor Dooley
2023-09-30 9:23 ` Conor Dooley
2023-10-02 7:40 ` Clément Léger
2023-10-02 7:40 ` Clément Léger
2023-10-02 10:49 ` Conor Dooley
2023-10-02 10:49 ` Conor Dooley
2023-10-02 11:18 ` Clément Léger
2023-10-02 11:18 ` Clément Léger
2023-10-02 15:32 ` ron minnich
2023-10-02 15:32 ` ron minnich
2023-10-02 22:22 ` Jessica Clarke
2023-10-02 22:22 ` Jessica Clarke
2023-10-03 15:37 ` ron minnich
2023-10-03 15:37 ` ron minnich
2023-10-03 8:12 ` Clément Léger
2023-10-03 8:12 ` Clément Léger
2023-10-04 8:26 ` David Laight
2023-10-04 8:26 ` David Laight
2023-10-04 10:03 ` Clément Léger
2023-10-04 10:03 ` Clément Léger
2023-10-04 14:10 ` David Laight
2023-10-04 14:10 ` David Laight
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