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From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 3/7] riscv: report perf event for misaligned fault
Date: Tue, 26 Sep 2023 17:03:12 +0200	[thread overview]
Message-ID: <20230926150316.1129648-4-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>

Add missing calls to account for misaligned fault event using
perf_sw_event().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 9daed7d756ae..804f6c5e0e44 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -6,6 +6,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/perf_event.h>
 #include <linux/irq.h>
 #include <linux/stringify.h>
 
@@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, fp = 0, shift = 0, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
-- 
2.40.1


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WARNING: multiple messages have this Message-ID (diff)
From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 3/7] riscv: report perf event for misaligned fault
Date: Tue, 26 Sep 2023 17:03:12 +0200	[thread overview]
Message-ID: <20230926150316.1129648-4-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>

Add missing calls to account for misaligned fault event using
perf_sw_event().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 9daed7d756ae..804f6c5e0e44 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -6,6 +6,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/perf_event.h>
 #include <linux/irq.h>
 #include <linux/stringify.h>
 
@@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, fp = 0, shift = 0, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
-- 
2.40.1


  parent reply	other threads:[~2023-09-26 15:04 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-26 15:03 [PATCH 0/7] Add support to handle misaligned accesses in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 2/7] riscv: add support for misaligned handling in S-mode Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` Clément Léger [this message]
2023-09-26 15:03   ` [PATCH 3/7] riscv: report perf event for misaligned fault Clément Léger
2023-09-26 15:03 ` [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 21:57   ` Evan Green
2023-09-26 21:57     ` Evan Green
2023-09-28  7:46     ` Clément Léger
2023-09-28  7:46       ` Clément Léger
2023-09-28 16:51       ` Evan Green
2023-09-28 16:51         ` Evan Green
2023-10-03  9:50         ` Atish Kumar Patra
2023-10-03  9:50           ` Atish Kumar Patra
2023-09-29  1:02   ` kernel test robot
2023-09-29  1:02     ` kernel test robot
2023-09-26 15:03 ` [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 21:43 ` [PATCH 0/7] Add support to handle misaligned accesses in S-mode Evan Green
2023-09-26 21:43   ` Evan Green
2023-09-28  7:49   ` Clément Léger
2023-09-28  7:49     ` Clément Léger
2023-09-28 16:48     ` Evan Green
2023-09-28 16:48       ` Evan Green
2023-10-03  8:40       ` Atish Kumar Patra
2023-10-03  8:40         ` Atish Kumar Patra
2023-10-03 15:39         ` ron minnich
2023-10-03 15:39           ` ron minnich
2023-09-30  9:23 ` Conor Dooley
2023-09-30  9:23   ` Conor Dooley
2023-10-02  7:40   ` Clément Léger
2023-10-02  7:40     ` Clément Léger
2023-10-02 10:49     ` Conor Dooley
2023-10-02 10:49       ` Conor Dooley
2023-10-02 11:18       ` Clément Léger
2023-10-02 11:18         ` Clément Léger
2023-10-02 15:32         ` ron minnich
2023-10-02 15:32           ` ron minnich
2023-10-02 22:22           ` Jessica Clarke
2023-10-02 22:22             ` Jessica Clarke
2023-10-03 15:37             ` ron minnich
2023-10-03 15:37               ` ron minnich
2023-10-03  8:12           ` Clément Léger
2023-10-03  8:12             ` Clément Léger
2023-10-04  8:26     ` David Laight
2023-10-04  8:26       ` David Laight
2023-10-04 10:03       ` Clément Léger
2023-10-04 10:03         ` Clément Léger
2023-10-04 14:10         ` David Laight
2023-10-04 14:10           ` David Laight

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