All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control
Date: Tue, 26 Sep 2023 17:03:14 +0200	[thread overview]
Message-ID: <20230926150316.1129648-6-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>

This sysctl tuning option allows the user to disable misaligned access
handling globally on the system. This will also be used by misaligned
detection code to temporarily disable misaligned access handling.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/Kconfig                   | 1 +
 arch/riscv/kernel/traps_misaligned.c | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d607ab0f7c6d..3515510fe418 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -157,6 +157,7 @@ config RISCV
 	select RISCV_TIMER if RISCV_SBI
 	select SIFIVE_PLIC
 	select SPARSE_IRQ
+	select SYSCTL_ARCH_UNALIGN_ALLOW
 	select SYSCTL_EXCEPTION_TRACE
 	select THREAD_INFO_IN_TASK
 	select TRACE_IRQFLAGS_SUPPORT
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 041fd2dbd955..b5fb1ff078e3 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -396,6 +396,9 @@ union reg_data {
 	u64 data_u64;
 };
 
+/* sysctl hooks */
+int unaligned_enabled __read_mostly = 1;	/* Enabled by default */
+
 int handle_misaligned_load(struct pt_regs *regs)
 {
 	union reg_data val;
@@ -406,6 +409,9 @@ int handle_misaligned_load(struct pt_regs *regs)
 
 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
+	if (!unaligned_enabled)
+		return -1;
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -502,6 +508,9 @@ int handle_misaligned_store(struct pt_regs *regs)
 
 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
+	if (!unaligned_enabled)
+		return -1;
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
-- 
2.40.1


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>
Subject: [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control
Date: Tue, 26 Sep 2023 17:03:14 +0200	[thread overview]
Message-ID: <20230926150316.1129648-6-cleger@rivosinc.com> (raw)
In-Reply-To: <20230926150316.1129648-1-cleger@rivosinc.com>

This sysctl tuning option allows the user to disable misaligned access
handling globally on the system. This will also be used by misaligned
detection code to temporarily disable misaligned access handling.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/Kconfig                   | 1 +
 arch/riscv/kernel/traps_misaligned.c | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index d607ab0f7c6d..3515510fe418 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -157,6 +157,7 @@ config RISCV
 	select RISCV_TIMER if RISCV_SBI
 	select SIFIVE_PLIC
 	select SPARSE_IRQ
+	select SYSCTL_ARCH_UNALIGN_ALLOW
 	select SYSCTL_EXCEPTION_TRACE
 	select THREAD_INFO_IN_TASK
 	select TRACE_IRQFLAGS_SUPPORT
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 041fd2dbd955..b5fb1ff078e3 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -396,6 +396,9 @@ union reg_data {
 	u64 data_u64;
 };
 
+/* sysctl hooks */
+int unaligned_enabled __read_mostly = 1;	/* Enabled by default */
+
 int handle_misaligned_load(struct pt_regs *regs)
 {
 	union reg_data val;
@@ -406,6 +409,9 @@ int handle_misaligned_load(struct pt_regs *regs)
 
 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
+	if (!unaligned_enabled)
+		return -1;
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -502,6 +508,9 @@ int handle_misaligned_store(struct pt_regs *regs)
 
 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
+	if (!unaligned_enabled)
+		return -1;
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
-- 
2.40.1


  parent reply	other threads:[~2023-09-26 15:04 UTC|newest]

Thread overview: 58+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-26 15:03 [PATCH 0/7] Add support to handle misaligned accesses in S-mode Clément Léger
2023-09-26 15:03 ` Clément Léger
2023-09-26 15:03 ` [PATCH 1/7] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 2/7] riscv: add support for misaligned handling in S-mode Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 3/7] riscv: report perf event for misaligned fault Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` [PATCH 4/7] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 15:03 ` Clément Léger [this message]
2023-09-26 15:03   ` [PATCH 5/7] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-09-26 15:03 ` [PATCH 6/7] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 21:57   ` Evan Green
2023-09-26 21:57     ` Evan Green
2023-09-28  7:46     ` Clément Léger
2023-09-28  7:46       ` Clément Léger
2023-09-28 16:51       ` Evan Green
2023-09-28 16:51         ` Evan Green
2023-10-03  9:50         ` Atish Kumar Patra
2023-10-03  9:50           ` Atish Kumar Patra
2023-09-29  1:02   ` kernel test robot
2023-09-29  1:02     ` kernel test robot
2023-09-26 15:03 ` [PATCH 7/7] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-09-26 15:03   ` Clément Léger
2023-09-26 21:43 ` [PATCH 0/7] Add support to handle misaligned accesses in S-mode Evan Green
2023-09-26 21:43   ` Evan Green
2023-09-28  7:49   ` Clément Léger
2023-09-28  7:49     ` Clément Léger
2023-09-28 16:48     ` Evan Green
2023-09-28 16:48       ` Evan Green
2023-10-03  8:40       ` Atish Kumar Patra
2023-10-03  8:40         ` Atish Kumar Patra
2023-10-03 15:39         ` ron minnich
2023-10-03 15:39           ` ron minnich
2023-09-30  9:23 ` Conor Dooley
2023-09-30  9:23   ` Conor Dooley
2023-10-02  7:40   ` Clément Léger
2023-10-02  7:40     ` Clément Léger
2023-10-02 10:49     ` Conor Dooley
2023-10-02 10:49       ` Conor Dooley
2023-10-02 11:18       ` Clément Léger
2023-10-02 11:18         ` Clément Léger
2023-10-02 15:32         ` ron minnich
2023-10-02 15:32           ` ron minnich
2023-10-02 22:22           ` Jessica Clarke
2023-10-02 22:22             ` Jessica Clarke
2023-10-03 15:37             ` ron minnich
2023-10-03 15:37               ` ron minnich
2023-10-03  8:12           ` Clément Léger
2023-10-03  8:12             ` Clément Léger
2023-10-04  8:26     ` David Laight
2023-10-04  8:26       ` David Laight
2023-10-04 10:03       ` Clément Léger
2023-10-04 10:03         ` Clément Léger
2023-10-04 14:10         ` David Laight
2023-10-04 14:10           ` David Laight

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20230926150316.1129648-6-cleger@rivosinc.com \
    --to=cleger@rivosinc.com \
    --cc=ajones@ventanamicro.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=atishp@rivosinc.com \
    --cc=bjorn@rivosinc.com \
    --cc=cyrevolt@googlemail.com \
    --cc=evan@rivosinc.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=paul.walmsley@sifive.com \
    --cc=rminnich@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.