* [PULL 01/51] hw/sd: give the RPMB vmstate subsection a name of its own
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 02/51] hw/sd: sdhci: Fix SDMA boundary bug Philippe Mathieu-Daudé
` (50 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: "Denis V. Lunev" <den@openvz.org>
emmc_rpmb_vmstate and emmc_extcsd_vmstate are both called
"sd-card/ext_csd_modes-state" and both sit in sd_vmstate.subsections, so
a card with an RPMB partition sends two subsections under one name:
192 bytes of ext_csd_rw and 353 bytes of RPMB state.
vmstate_get_subsection() returns the first entry whose name matches, so
the destination parses both of them as emmc_extcsd_vmstate. The RPMB
section is 161 bytes longer than the fields being loaded from it, the
stream is left mid-section, and the load fails:
(qemu) migrate file:vm.mig
... on the destination:
load of migration failed: Invalid argument:
Section footer error, section_id: 38
Reproduced with
qemu-system-x86_64 -M q35 -device sdhci-pci,id=mmc \
-drive if=none,id=d0,file=emmc.raw,format=raw \
-device emmc,bus=sd-bus,drive=d0,rpmb-partition-size=131072
Name it "sd-card/rpmb-state". A stream written by an affected version
cannot be loaded by any version, this one included, so there is no
working format to stay compatible with.
Cc: qemu-stable@nongnu.org
Fixes: 8ef4260a3f ("hw/sd/sdcard: Add basic support for RPMB partition")
Signed-off-by: Denis V. Lunev <den@openvz.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260814183859.4034017-1-den@openvz.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index a30c541df07..674ca09b49f 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -1022,7 +1022,7 @@ static bool vmstate_needed_for_rpmb(void *opaque)
}
static const VMStateDescription emmc_rpmb_vmstate = {
- .name = "sd-card/ext_csd_modes-state",
+ .name = "sd-card/rpmb-state",
.version_id = 1,
.minimum_version_id = 1,
.needed = vmstate_needed_for_rpmb,
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 02/51] hw/sd: sdhci: Fix SDMA boundary bug
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 01/51] hw/sd: give the RPMB vmstate subsection a name of its own Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 03/51] qtest: add xilinx-zynq SDHCI sdma test Philippe Mathieu-Daudé
` (49 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Tao Ding <dingtao0430@163.com>
During SDMA transfers, the controller raises an interrupt at buffer boundaries
to request a system address update. The host driver will rewrite the SDHC_SYSAD register.
(according to PartA2_SD_Host_Controller_Simplified_Specification_Ver2.00.pdf section 2.2.1)
However, the current code will ignore write operations to SDHC_SYSAD.
To fix this bug, when SDMA encounters a boundary, a state is set to record it.
In this state, SDHC_SYSAD can be written. In other cases, it is still protected by TRANSFERRING_DATA.
Meanwhile, a subsection has been added for migration.
Suggested-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tao Ding <dingtao0430@163.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-ID: <20260715160731.29969-2-dingtao0430@163.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/sd/sdhci.h | 2 ++
hw/sd/sdhci.c | 54 ++++++++++++++++++++++++++++++++++++++++++-
2 files changed, 55 insertions(+), 1 deletion(-)
diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h
index a9da6203fcb..c485277744e 100644
--- a/include/hw/sd/sdhci.h
+++ b/include/hw/sd/sdhci.h
@@ -103,6 +103,8 @@ struct SDHCIState {
* to be protected. Set wp_inverted to invert the signal.
*/
bool wp_inverted;
+ /* Indicate that SDMA transfer is paused due to hitting the boundary */
+ bool sdma_boundary_paused;
};
typedef struct SDHCIState SDHCIState;
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index e58a6103970..02f09187272 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -307,6 +307,7 @@ static void sdhci_reset(SDHCIState *s)
s->data_count = 0;
s->stopped_state = sdhc_not_stopped;
s->pending_insert_state = false;
+ s->sdma_boundary_paused = false;
if (object_dynamic_cast(OBJECT(s), TYPE_FSL_ESDHC_BE) ||
object_dynamic_cast(OBJECT(s), TYPE_FSL_ESDHC_LE)) {
s->norintstsen = 0x013f;
@@ -414,6 +415,7 @@ static void sdhci_end_transfer(SDHCIState *s)
s->norintsts |= SDHC_NIS_TRSCMP;
}
+ s->sdma_boundary_paused = false;
sdhci_update_irq(s);
}
@@ -681,6 +683,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
if (s->blkcnt == 0) {
sdhci_end_transfer(s);
} else {
+ s->sdma_boundary_paused = true;
sdhci_update_irq(s);
}
}
@@ -717,6 +720,15 @@ static void sdhci_sdma_transfer(SDHCIState *s)
}
}
+static bool sdhci_sdma_transfer_active(SDHCIState *s)
+{
+ return TRANSFERRING_DATA(s->prnsts) &&
+ (s->trnmod & SDHC_TRNS_DMA) &&
+ s->blkcnt &&
+ (s->blksize & BLOCK_SIZE_MASK) &&
+ SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA;
+}
+
typedef struct ADMADescr {
hwaddr addr;
uint16_t length;
@@ -1164,6 +1176,7 @@ static inline void sdhci_reset_write(SDHCIState *s, uint8_t value)
SDHC_DATA_INHIBIT | SDHC_DAT_LINE_ACTIVE);
s->blkgap &= ~(SDHC_STOP_AT_GAP_REQ | SDHC_CONTINUE_REQ);
s->stopped_state = sdhc_not_stopped;
+ s->sdma_boundary_paused = false;
s->norintsts &= ~(SDHC_NIS_WBUFRDY | SDHC_NIS_RBUFRDY |
SDHC_NIS_DMA | SDHC_NIS_TRSCMP | SDHC_NIS_BLKGAP);
break;
@@ -1185,7 +1198,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
switch (offset & ~0x3) {
case SDHC_SYSAD:
- if (!TRANSFERRING_DATA(s->prnsts)) {
+ if (!TRANSFERRING_DATA(s->prnsts) || s->sdma_boundary_paused) {
s->sdmasysad = (s->sdmasysad & mask) | value;
MASKED_WRITE(s->sdmasysad, mask, value);
/* Writing to last byte of sdmasysad might trigger transfer */
@@ -1464,6 +1477,31 @@ static bool sdhci_pending_insert_vmstate_needed(void *opaque)
return s->pending_insert_state;
}
+static bool sdhci_sdma_boundary_paused_vmstate_needed(void *opaque)
+{
+ SDHCIState *s = opaque;
+
+ return s->sdma_boundary_paused;
+}
+
+static int sdhci_pre_load(void *opaque)
+{
+ SDHCIState *s = opaque;
+
+ s->sdma_boundary_paused = false;
+ return 0;
+}
+
+static int sdhci_post_load(void *opaque, int version_id)
+{
+ SDHCIState *s = opaque;
+
+ if (!s->sdma_boundary_paused) {
+ s->sdma_boundary_paused = sdhci_sdma_transfer_active(s);
+ }
+ return 0;
+}
+
static const VMStateDescription sdhci_pending_insert_vmstate = {
.name = "sdhci/pending-insert",
.version_id = 1,
@@ -1475,10 +1513,23 @@ static const VMStateDescription sdhci_pending_insert_vmstate = {
},
};
+static const VMStateDescription sdhci_sdma_boundary_paused_vmstate = {
+ .name = "sdhci/sdma_boundary_paused",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = sdhci_sdma_boundary_paused_vmstate_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_BOOL(sdma_boundary_paused, SDHCIState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
const VMStateDescription sdhci_vmstate = {
.name = "sdhci",
.version_id = 1,
.minimum_version_id = 1,
+ .pre_load = sdhci_pre_load,
+ .post_load = sdhci_post_load,
.fields = (const VMStateField[]) {
VMSTATE_UINT32(sdmasysad, SDHCIState),
VMSTATE_UINT16(blksize, SDHCIState),
@@ -1512,6 +1563,7 @@ const VMStateDescription sdhci_vmstate = {
},
.subsections = (const VMStateDescription * const []) {
&sdhci_pending_insert_vmstate,
+ &sdhci_sdma_boundary_paused_vmstate,
NULL
},
};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 03/51] qtest: add xilinx-zynq SDHCI sdma test
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 01/51] hw/sd: give the RPMB vmstate subsection a name of its own Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 02/51] hw/sd: sdhci: Fix SDMA boundary bug Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 04/51] hw/sd: sdhci: Migrate the Host Control 2 register Philippe Mathieu-Daudé
` (48 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Tao Ding <dingtao0430@163.com>
Add a standalone qtest for the SDHCI controller on the
xilinx-zynq-a9 machine.
The test covers the SDMA boundary continuation case for a
multi-block read. After the controller stops at a boundary,
software updates SYSAD to continue the transfer. This verifies
the generic SDHCI behavior that previously failed when the
continuation SYSAD write was ignored and the transfer stalled.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Signed-off-by: Tao Ding <dingtao0430@163.com>
Message-ID: <20260715160731.29969-3-dingtao0430@163.com>
[PMD: Write file using GLib API, cover file in MAINTAINERS]
Co-developed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <048bfef9-53dd-489c-be73-85e2c9f759a9@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
MAINTAINERS | 1 +
tests/qtest/xilinx-zynq-sdhci-test.c | 185 +++++++++++++++++++++++++++
tests/qtest/meson.build | 1 +
3 files changed, 187 insertions(+)
create mode 100644 tests/qtest/xilinx-zynq-sdhci-test.c
diff --git a/MAINTAINERS b/MAINTAINERS
index a1830cdad15..a898162cea5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2417,6 +2417,7 @@ F: hw/sd/sd*
F: hw/sd/ssi-sd.c
F: tests/qtest/fuzz-sdcard-test.c
F: tests/qtest/sdhci-test.c
+F: tests/qtest/xilinx-zynq-sdhci-test.c
USB
S: Orphan
diff --git a/tests/qtest/xilinx-zynq-sdhci-test.c b/tests/qtest/xilinx-zynq-sdhci-test.c
new file mode 100644
index 00000000000..7957358cf5d
--- /dev/null
+++ b/tests/qtest/xilinx-zynq-sdhci-test.c
@@ -0,0 +1,185 @@
+/*
+ * QTests for the Xilinx Zynq SDHCI controller.
+ *
+ * Copyright (c) 2026 Tao Ding <dingtao0430@163.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/sd/sdhci.h"
+#include "hw/sd/sdhci-internal.h"
+
+#include "libqtest.h"
+#include "libqtest-single.h"
+#include "libqos/sdhci-cmd.h"
+
+#define XILINX_ZYNQ_MMC_BA 0xE0100000
+#define XILINX_ZYNQ_BLK_SIZE 512
+#define XILINX_ZYNQ_TEST_IMAGE_SIZE (1 << 20)
+#define XILINX_ZYNQ_SDMA_BOUNDARY_ARG 7
+#define XILINX_ZYNQ_SDMA_BOUNDARY_SIZE (512 * 1024)
+#define XILINX_ZYNQ_SDMA_BLOCK_COUNT \
+ ((XILINX_ZYNQ_SDMA_BOUNDARY_SIZE / XILINX_ZYNQ_BLK_SIZE) + 1)
+#define XILINX_ZYNQ_SDMA_TRANSFER_SIZE \
+ (XILINX_ZYNQ_SDMA_BLOCK_COUNT * XILINX_ZYNQ_BLK_SIZE)
+#define XILINX_ZYNQ_DMA_ADDR 0x00100000
+
+#define SDHC_MAKE_BLKSZ(boundary, size) (((boundary) << 12) | (size))
+
+static char *sd_path;
+
+static QTestState *setup_sd_card(void)
+{
+ QTestState *qts;
+ uint16_t rca;
+
+ qts = qtest_initf(
+ "-machine xilinx-zynq-a9 "
+ "-drive if=sd,index=0,file=%s,format=raw,auto-read-only=off",
+ sd_path);
+
+ qtest_writew(qts, XILINX_ZYNQ_MMC_BA + SDHC_SWRST, SDHC_RESET_ALL);
+ qtest_writew(qts, XILINX_ZYNQ_MMC_BA + SDHC_CLKCON,
+ SDHC_CLOCK_SDCLK_EN | SDHC_CLOCK_INT_STABLE |
+ SDHC_CLOCK_INT_EN);
+ sdhci_cmd_regs(qts, XILINX_ZYNQ_MMC_BA, 0, 0, 0, 0, SDHC_APP_CMD);
+ sdhci_cmd_regs(qts, XILINX_ZYNQ_MMC_BA, 0, 0, 0x41200000, 0,
+ (41 << 8));
+ sdhci_cmd_regs(qts, XILINX_ZYNQ_MMC_BA, 0, 0, 0, 0, SDHC_ALL_SEND_CID);
+ sdhci_cmd_regs(qts, XILINX_ZYNQ_MMC_BA, 0, 0, 0, 0,
+ SDHC_SEND_RELATIVE_ADDR | SDHC_CMD_RESPONSE);
+ rca = qtest_readl(qts, XILINX_ZYNQ_MMC_BA + SDHC_RSPREG0) >> 16;
+ sdhci_cmd_regs(qts, XILINX_ZYNQ_MMC_BA, 0, 0, rca << 16, 0,
+ SDHC_SELECT_DESELECT_CARD);
+
+ return qts;
+}
+
+static void write_pattern_to_image(size_t offset, size_t len)
+{
+ gchar *buf = g_malloc(len);
+ GError *err = NULL;
+ gsize bytes_written;
+ GIOChannel *chan;
+
+ for (size_t i = 0; i < len; i++) {
+ buf[i] = (i * 13 + 7) & 0xff;
+ }
+
+ chan = g_io_channel_new_file(sd_path, "w", &err);
+ g_assert_no_error(err);
+ g_io_channel_set_encoding(chan, NULL, &err);
+ g_assert_no_error(err);
+ g_io_channel_seek_position(chan, offset, G_SEEK_SET, &err);
+ g_assert_no_error(err);
+ g_io_channel_write_chars(chan, buf, len, &bytes_written, &err);
+ g_assert_no_error(err);
+ g_assert_cmpint(bytes_written, ==, len);
+ g_io_channel_shutdown(chan, TRUE, &err);
+ g_assert_no_error(err);
+
+ g_free(buf);
+}
+
+static void wait_for_block_count(QTestState *qts, uint16_t expected)
+{
+ int i;
+
+ for (i = 0; i < 1000; i++) {
+ if (qtest_readw(qts, XILINX_ZYNQ_MMC_BA + SDHC_BLKCNT) == expected) {
+ return;
+ }
+ g_usleep(100);
+ }
+
+ g_assert_cmpuint(qtest_readw(qts, XILINX_ZYNQ_MMC_BA + SDHC_BLKCNT),
+ ==, expected);
+}
+
+/*
+ * SDMA stops at each boundary and requires software to update SYSAD
+ * to continue. The bug this test covers leaves DOING_READ/WRITE asserted,
+ * so the continuation SYSAD write is ignored and the transfer stalls.
+ */
+static void test_read_sdma_boundary_continue(void)
+{
+ QTestState *qts = setup_sd_card();
+ uint8_t *actual = g_malloc0(XILINX_ZYNQ_SDMA_TRANSFER_SIZE);
+ uint8_t *expected = g_malloc(XILINX_ZYNQ_SDMA_TRANSFER_SIZE);
+
+ write_pattern_to_image(0, XILINX_ZYNQ_SDMA_TRANSFER_SIZE);
+
+ for (size_t i = 0; i < XILINX_ZYNQ_SDMA_TRANSFER_SIZE; i++) {
+ expected[i] = (i * 13 + 7) & 0xff;
+ }
+
+ qtest_writel(qts, XILINX_ZYNQ_DMA_ADDR, 0xdeadbeef);
+ qtest_writel(qts, XILINX_ZYNQ_DMA_ADDR + XILINX_ZYNQ_SDMA_BOUNDARY_SIZE,
+ 0xcafef00d);
+
+ qtest_writel(qts, XILINX_ZYNQ_MMC_BA + SDHC_SYSAD, XILINX_ZYNQ_DMA_ADDR);
+ sdhci_cmd_regs(qts, XILINX_ZYNQ_MMC_BA,
+ SDHC_MAKE_BLKSZ(XILINX_ZYNQ_SDMA_BOUNDARY_ARG,
+ XILINX_ZYNQ_BLK_SIZE),
+ XILINX_ZYNQ_SDMA_BLOCK_COUNT, 0,
+ SDHC_TRNS_DMA | SDHC_TRNS_MULTI | SDHC_TRNS_READ |
+ SDHC_TRNS_BLK_CNT_EN,
+ SDHC_READ_MULTIPLE_BLOCK | SDHC_CMD_DATA_PRESENT);
+
+ wait_for_block_count(qts, 1);
+
+ qtest_writew(qts, XILINX_ZYNQ_MMC_BA + SDHC_NORINTSTS, 0xffff);
+ qtest_writel(qts, XILINX_ZYNQ_MMC_BA + SDHC_SYSAD,
+ XILINX_ZYNQ_DMA_ADDR + XILINX_ZYNQ_SDMA_BOUNDARY_SIZE);
+
+ wait_for_block_count(qts, 0);
+
+ qtest_memread(qts, XILINX_ZYNQ_DMA_ADDR, actual,
+ XILINX_ZYNQ_SDMA_TRANSFER_SIZE);
+ g_assert_cmpmem(actual, XILINX_ZYNQ_SDMA_TRANSFER_SIZE,
+ expected, XILINX_ZYNQ_SDMA_TRANSFER_SIZE);
+
+ g_free(expected);
+ g_free(actual);
+ qtest_quit(qts);
+}
+
+static void drive_destroy(void)
+{
+ unlink(sd_path);
+ g_free(sd_path);
+}
+
+static void drive_create(void)
+{
+ int fd;
+ int ret;
+ GError *error = NULL;
+
+ fd = g_file_open_tmp("xilinx-zynq-sdhci.XXXXXX", &sd_path, &error);
+ if (fd == -1) {
+ fprintf(stderr, "unable to create sdhci file: %s\n", error->message);
+ g_error_free(error);
+ }
+ g_assert_nonnull(sd_path);
+
+ ret = ftruncate(fd, XILINX_ZYNQ_TEST_IMAGE_SIZE);
+ g_assert_cmpint(ret, ==, 0);
+ close(fd);
+}
+
+int main(int argc, char **argv)
+{
+ int ret;
+
+ drive_create();
+
+ g_test_init(&argc, &argv, NULL);
+ qtest_add_func("xilinx-zynq-sdhci/sdma/read-boundary-continue",
+ test_read_sdma_boundary_continue);
+
+ ret = g_test_run();
+ drive_destroy();
+ return ret;
+}
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
index 50a1a5272fa..17870e339b4 100644
--- a/tests/qtest/meson.build
+++ b/tests/qtest/meson.build
@@ -255,6 +255,7 @@ qtests_arm = \
config_all_devices.has_key('CONFIG_MPS2') ? ['cmsdk-apb-watchdog-test'] : []) + \
(config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \
(config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \
+ (config_all_devices.has_key('CONFIG_ZYNQ') ? ['xilinx-zynq-sdhci-test'] : []) + \
(config_all_devices.has_key('CONFIG_GENERIC_LOADER') ? ['hexloader-test'] : []) + \
(config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test', 'tpm-tis-i2c-swtpm-test'] : []) + \
(config_all_devices.has_key('CONFIG_VEXPRESS') ? ['test-arm-mptimer'] : []) + \
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 04/51] hw/sd: sdhci: Migrate the Host Control 2 register
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (2 preceding siblings ...)
2026-09-03 10:38 ` [PULL 03/51] qtest: add xilinx-zynq SDHCI sdma test Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 05/51] hw/sd: sdhci: Accept version 4 enable without UHS-I Philippe Mathieu-Daudé
` (47 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
The Host Control 2 register has been part of SDHCIState since its
initial implementation, but it was omitted from sdhci_vmstate.
Migration therefore resets the register to zero and can change tuning,
voltage, or DMA behavior.
Migrate nonzero values in an optional subsection. Clear the register
before loading so older streams retain the reset default without
changing the main stream version.
Fixes: ea55a221bfc0 ("sdhci: implement the Host Control 2 register (tuning sequence)")
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260723151853.2143177-8-bin.meng@processmission.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 02f09187272..101fbcf2ff9 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1470,6 +1470,24 @@ void sdhci_common_unrealize(SDHCIState *s)
s->fifo_buffer = NULL;
}
+static bool sdhci_hostctl2_vmstate_needed(void *opaque)
+{
+ SDHCIState *s = opaque;
+
+ return s->hostctl2;
+}
+
+static const VMStateDescription sdhci_hostctl2_vmstate = {
+ .name = "sdhci/hostctl2",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = sdhci_hostctl2_vmstate_needed,
+ .fields = (const VMStateField[]) {
+ VMSTATE_UINT16(hostctl2, SDHCIState),
+ VMSTATE_END_OF_LIST()
+ },
+};
+
static bool sdhci_pending_insert_vmstate_needed(void *opaque)
{
SDHCIState *s = opaque;
@@ -1488,6 +1506,7 @@ static int sdhci_pre_load(void *opaque)
{
SDHCIState *s = opaque;
+ s->hostctl2 = 0;
s->sdma_boundary_paused = false;
return 0;
}
@@ -1562,6 +1581,7 @@ const VMStateDescription sdhci_vmstate = {
VMSTATE_END_OF_LIST()
},
.subsections = (const VMStateDescription * const []) {
+ &sdhci_hostctl2_vmstate,
&sdhci_pending_insert_vmstate,
&sdhci_sdma_boundary_paused_vmstate,
NULL
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 05/51] hw/sd: sdhci: Accept version 4 enable without UHS-I
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (3 preceding siblings ...)
2026-09-03 10:38 ` [PULL 04/51] hw/sd: sdhci: Migrate the Host Control 2 register Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 06/51] hw/sd: sdhci: Factor sdhci_advance_sdma_address() helper out Philippe Mathieu-Daudé
` (46 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
Host Control 2 writes have been conditional on modeled UHS-I support
since commit 0034ebe6ee31. Host Version 4 Enable does not control UHS
signaling, so controllers without modeled UHS-I cannot enter version
4 mode.
Retain Host Version 4 Enable independently of UHS-I while continuing
to reject UHS-specific fields and keeping voltage changes UHS-gated.
Cc: qemu-stable@nongnu.org
Fixes: 0034ebe6ee31 ("sdhci: implement UHS-I voltage switch")
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260723151853.2143177-9-bin.meng@processmission.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci.c | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 101fbcf2ff9..586e4680bee 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -1358,11 +1358,24 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
}
sdhci_update_irq(s);
break;
- case SDHC_ACMD12ERRSTS:
- MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
- if (s->uhs_mode >= UHS_I) {
- MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16);
+ case SDHC_ACMD12ERRSTS: {
+ uint16_t hostctl2_mask = mask >> 16;
+ uint16_t hostctl2_value = value >> 16;
+ MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
+ if (s->uhs_mode < UHS_I) {
+ /*
+ * VERSION4 is writable even without UHS-I. Preserve all other
+ * Host Control 2 bits when UHS-I is not supported.
+ */
+ uint16_t independent = R_SDHC_HOSTCTL2_VERSION4_MASK;
+
+ hostctl2_mask |= ~independent;
+ hostctl2_value &= independent;
+ }
+ MASKED_WRITE(s->hostctl2, hostctl2_mask, hostctl2_value);
+
+ if (s->uhs_mode >= UHS_I) {
if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) {
sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V);
} else {
@@ -1370,6 +1383,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
}
}
break;
+ }
case SDHC_CAPAB:
case SDHC_CAPAB + 4:
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 06/51] hw/sd: sdhci: Factor sdhci_advance_sdma_address() helper out
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (4 preceding siblings ...)
2026-09-03 10:38 ` [PULL 05/51] hw/sd: sdhci: Accept version 4 enable without UHS-I Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 07/51] hw/sd: sdhci: Factor sdhci_sdma_address() " Philippe Mathieu-Daudé
` (45 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Message-ID: <20260723151853.2143177-10-bin.meng@processmission.com>
[PMD: Split of bigger patch]
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 586e4680bee..ad370407c6e 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -598,6 +598,11 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
* Single DMA data transfer
*/
+static void sdhci_advance_sdma_address(SDHCIState *s, uint32_t bytes)
+{
+ s->sdmasysad += bytes;
+}
+
/* Multi block SDMA transfer */
static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
{
@@ -641,7 +646,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
}
dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin],
s->data_count - begin, MEMTXATTRS_UNSPECIFIED);
- s->sdmasysad += s->data_count - begin;
+ sdhci_advance_sdma_address(s, s->data_count - begin);
if (s->data_count == block_size) {
s->data_count = 0;
}
@@ -662,7 +667,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
}
dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin],
s->data_count - begin, MEMTXATTRS_UNSPECIFIED);
- s->sdmasysad += s->data_count - begin;
+ sdhci_advance_sdma_address(s, s->data_count - begin);
if (s->data_count == block_size) {
sdbus_write_data(&s->sdbus, s->fifo_buffer, block_size);
s->data_count = 0;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 07/51] hw/sd: sdhci: Factor sdhci_sdma_address() helper out
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (5 preceding siblings ...)
2026-09-03 10:38 ` [PULL 06/51] hw/sd: sdhci: Factor sdhci_advance_sdma_address() helper out Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 08/51] hw/sd: sdhci: Use version 4 system address for SDMA Philippe Mathieu-Daudé
` (44 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Message-ID: <20260723151853.2143177-10-bin.meng@processmission.com>
[PMD: Split of bigger patch]
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index ad370407c6e..93e1687dbe5 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -598,6 +598,11 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
* Single DMA data transfer
*/
+static uint64_t sdhci_sdma_address(SDHCIState *s)
+{
+ return s->sdmasysad;
+}
+
static void sdhci_advance_sdma_address(SDHCIState *s, uint32_t bytes)
{
s->sdmasysad += bytes;
@@ -610,7 +615,8 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
unsigned int begin;
const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK;
uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12);
- uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk);
+ uint64_t sdma_address = sdhci_sdma_address(s);
+ uint32_t boundary_count = boundary_chk - (sdma_address % boundary_chk);
if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) {
qemu_log_mask(LOG_UNIMP, "infinite transfer is not supported\n");
@@ -622,7 +628,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
* possible stop at page boundary if initial address is not page aligned,
* allow them to work properly
*/
- if ((s->sdmasysad % boundary_chk) == 0) {
+ if ((sdma_address % boundary_chk) == 0) {
page_aligned = true;
}
@@ -644,7 +650,8 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
s->blkcnt--;
}
}
- dma_memory_write(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin],
+ dma_memory_write(s->dma_as, sdhci_sdma_address(s),
+ &s->fifo_buffer[begin],
s->data_count - begin, MEMTXATTRS_UNSPECIFIED);
sdhci_advance_sdma_address(s, s->data_count - begin);
if (s->data_count == block_size) {
@@ -665,7 +672,8 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s)
s->data_count = block_size;
boundary_count -= block_size - begin;
}
- dma_memory_read(s->dma_as, s->sdmasysad, &s->fifo_buffer[begin],
+ dma_memory_read(s->dma_as, sdhci_sdma_address(s),
+ &s->fifo_buffer[begin],
s->data_count - begin, MEMTXATTRS_UNSPECIFIED);
sdhci_advance_sdma_address(s, s->data_count - begin);
if (s->data_count == block_size) {
@@ -700,10 +708,12 @@ static void sdhci_sdma_transfer_single_block(SDHCIState *s)
if (s->trnmod & SDHC_TRNS_READ) {
sdbus_read_data(&s->sdbus, s->fifo_buffer, datacnt);
- dma_memory_write(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt,
+ dma_memory_write(s->dma_as, sdhci_sdma_address(s),
+ s->fifo_buffer, datacnt,
MEMTXATTRS_UNSPECIFIED);
} else {
- dma_memory_read(s->dma_as, s->sdmasysad, s->fifo_buffer, datacnt,
+ dma_memory_read(s->dma_as, sdhci_sdma_address(s),
+ s->fifo_buffer, datacnt,
MEMTXATTRS_UNSPECIFIED);
sdbus_write_data(&s->sdbus, s->fifo_buffer, datacnt);
}
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 08/51] hw/sd: sdhci: Use version 4 system address for SDMA
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (6 preceding siblings ...)
2026-09-03 10:38 ` [PULL 07/51] hw/sd: sdhci: Factor sdhci_sdma_address() " Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 09/51] hw/sd: sdhci: Support version 4 ADMA 64-bit addressing Philippe Mathieu-Daudé
` (43 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
SDHCI version 4 moves the SDMA system address from the legacy 32-bit
register at offset 0x00 to the address pair at offsets 0x58 and 0x5c.
At present QEMU always uses the legacy register, so guest SDHCI driver
with version 4 mode enabled uses an incorrect DMA address.
Select the address register from Host Version 4 Enable and honor 64-bit
Addressing when reading and advancing it. Keep the existing offset 0x00
behavior when version 4 mode is disabled.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Message-ID: <20260723151853.2143177-10-bin.meng@processmission.com>
[PMD: Simplified extracting the previous trivial 2 commits]
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci-internal.h | 1 +
hw/sd/sdhci.c | 32 +++++++++++++++++++++++++++++---
2 files changed, 30 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h
index 4aeed120bf1..2116995dcca 100644
--- a/hw/sd/sdhci-internal.h
+++ b/hw/sd/sdhci-internal.h
@@ -201,6 +201,7 @@ FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */
FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */
FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */
FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */
+FIELD(SDHC_HOSTCTL2, ADDRESSING_64, 13, 1); /* since v4 */
FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1);
FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1);
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 93e1687dbe5..3fba3970d4f 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -598,14 +598,39 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size)
* Single DMA data transfer
*/
+static bool sdhci_version4_enabled(SDHCIState *s)
+{
+ return FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, VERSION4);
+}
+
+static bool sdhci_64bit_addressing_enabled(SDHCIState *s)
+{
+ return FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, ADDRESSING_64);
+}
+
static uint64_t sdhci_sdma_address(SDHCIState *s)
{
+ if (!sdhci_version4_enabled(s)) {
return s->sdmasysad;
+ }
+
+ return sdhci_64bit_addressing_enabled(s) ?
+ s->admasysaddr : (uint32_t)s->admasysaddr;
}
static void sdhci_advance_sdma_address(SDHCIState *s, uint32_t bytes)
{
+ if (!sdhci_version4_enabled(s)) {
s->sdmasysad += bytes;
+ } else if (sdhci_64bit_addressing_enabled(s)) {
+ s->admasysaddr += bytes;
+ } else {
+ uint32_t address = s->admasysaddr;
+
+ address += bytes;
+ s->admasysaddr = (s->admasysaddr & 0xffffffff00000000ULL) |
+ address;
+ }
}
/* Multi block SDMA transfer */
@@ -1380,10 +1405,11 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX);
if (s->uhs_mode < UHS_I) {
/*
- * VERSION4 is writable even without UHS-I. Preserve all other
- * Host Control 2 bits when UHS-I is not supported.
+ * Version 4 fields are writable even without UHS-I. Preserve all
+ * other Host Control 2 bits when UHS-I is not supported.
*/
- uint16_t independent = R_SDHC_HOSTCTL2_VERSION4_MASK;
+ uint16_t independent = R_SDHC_HOSTCTL2_VERSION4_MASK |
+ R_SDHC_HOSTCTL2_ADDRESSING_64_MASK;
hostctl2_mask |= ~independent;
hostctl2_value &= independent;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 09/51] hw/sd: sdhci: Support version 4 ADMA 64-bit addressing
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (7 preceding siblings ...)
2026-09-03 10:38 ` [PULL 08/51] hw/sd: sdhci: Use version 4 system address for SDMA Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 10/51] hw/sd: sdhci: Resume version 4 SDMA at buffer boundaries Philippe Mathieu-Daudé
` (42 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
The Cadence Linux driver enables version 4 mode and 64-bit addressing in
Host Control 2 but retains the ADMA2 encoding in Host Control 1. QEMU
treats the transfer as 32-bit ADMA and uses 12-byte descriptors because
it only decodes Host Control 1.
Resolve the DMA type from both control registers and use 16-byte version
4 descriptors. Preserve the legacy 12-byte ADMA2 64-bit format when
version 4 mode is disabled.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260723151853.2143177-11-bin.meng@processmission.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci.c | 25 ++++++++++++++++++++++---
1 file changed, 22 insertions(+), 3 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index 3fba3970d4f..f0ba5c11dfc 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -227,6 +227,23 @@ static bool sdhci_update_irq(SDHCIState *s)
return pending;
}
+static uint8_t sdhci_get_dma_type(SDHCIState *s)
+{
+ uint8_t type = SDHC_DMA_TYPE(s->hostctl1);
+
+ /*
+ * In version 4 mode, the legacy ADMA2_32 encoding selects ADMA2,
+ * while ADDRESSING_64 determines its address width.
+ */
+ if (type == SDHC_CTRL_ADMA2_32 &&
+ FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, VERSION4) &&
+ FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, ADDRESSING_64)) {
+ return SDHC_CTRL_ADMA2_64;
+ }
+
+ return type;
+}
+
static void sdhci_raise_insertion_irq(void *opaque)
{
SDHCIState *s = (SDHCIState *)opaque;
@@ -781,7 +798,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
uint32_t adma1 = 0;
uint64_t adma2 = 0;
hwaddr entry_addr = (hwaddr)s->admasysaddr;
- switch (SDHC_DMA_TYPE(s->hostctl1)) {
+ switch (sdhci_get_dma_type(s)) {
case SDHC_CTRL_ADMA2_32:
dma_memory_read(s->dma_as, entry_addr, &adma2, sizeof(adma2),
MEMTXATTRS_UNSPECIFIED);
@@ -818,7 +835,9 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr)
MEMTXATTRS_UNSPECIFIED);
dscr->addr = le64_to_cpu(dscr->addr);
dscr->attr &= (uint8_t) ~0xC0;
- dscr->incr = 12;
+ /* Version 4 pads 64-bit ADMA2 descriptors from 96 to 128 bits */
+ dscr->incr = FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, VERSION4) ?
+ 16 : 12;
break;
}
}
@@ -998,7 +1017,7 @@ static void sdhci_data_transfer(void *opaque)
SDHCIState *s = (SDHCIState *)opaque;
if (s->trnmod & SDHC_TRNS_DMA) {
- switch (SDHC_DMA_TYPE(s->hostctl1)) {
+ switch (sdhci_get_dma_type(s)) {
case SDHC_CTRL_SDMA:
sdhci_sdma_transfer(s);
break;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 10/51] hw/sd: sdhci: Resume version 4 SDMA at buffer boundaries
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (8 preceding siblings ...)
2026-09-03 10:38 ` [PULL 09/51] hw/sd: sdhci: Support version 4 ADMA 64-bit addressing Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 11/51] hw/sd/sdcard: Register device ops in drives without media Philippe Mathieu-Daudé
` (41 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Bin Meng <bin.meng@processmission.com>
Version 4 SDMA selects its system address from the registers also named
as the ADMA System Address registers. Updating those registers does not
resume a transfer that stopped at the configured SDMA buffer boundary.
Resume 32-bit addressing after an access completes the lower 32 bits of
the ADMA System Address register. For 64-bit addressing, wait until an
access completes the upper 32 bits so software can update the low half
before the high half without starting from a mixed address.
Signed-off-by: Bin Meng <bin.meng@processmission.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260723151853.2143177-12-bin.meng@processmission.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sdhci.c | 32 ++++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c
index f0ba5c11dfc..bd74c60f728 100644
--- a/hw/sd/sdhci.c
+++ b/hw/sd/sdhci.c
@@ -786,6 +786,12 @@ static bool sdhci_sdma_transfer_active(SDHCIState *s)
SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA;
}
+static void sdhci_resume_sdma_transfer(SDHCIState *s)
+{
+ s->sdma_boundary_paused = false;
+ sdhci_sdma_transfer(s);
+}
+
typedef struct ADMADescr {
hwaddr addr;
uint16_t length;
@@ -1257,14 +1263,15 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
switch (offset & ~0x3) {
case SDHC_SYSAD:
- if (!TRANSFERRING_DATA(s->prnsts) || s->sdma_boundary_paused) {
+ if (!TRANSFERRING_DATA(s->prnsts) ||
+ (!sdhci_version4_enabled(s) && s->sdma_boundary_paused)) {
s->sdmasysad = (s->sdmasysad & mask) | value;
MASKED_WRITE(s->sdmasysad, mask, value);
- /* Writing to last byte of sdmasysad might trigger transfer */
- if (!(mask & 0xFF000000) && s->blkcnt &&
- (s->blksize & BLOCK_SIZE_MASK) &&
- SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) {
- sdhci_sdma_transfer(s);
+ /* A completed selected-address write resumes stopped SDMA */
+ if (!sdhci_version4_enabled(s) && !(mask & 0xff000000) &&
+ s->sdma_boundary_paused &&
+ sdhci_sdma_transfer_active(s)) {
+ sdhci_resume_sdma_transfer(s);
}
}
break;
@@ -1401,10 +1408,23 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
case SDHC_ADMASYSADDR:
s->admasysaddr = (s->admasysaddr & (0xFFFFFFFF00000000ULL |
(uint64_t)mask)) | (uint64_t)value;
+ if (sdhci_version4_enabled(s) &&
+ !sdhci_64bit_addressing_enabled(s) &&
+ !(mask & 0xff000000) && s->sdma_boundary_paused &&
+ sdhci_sdma_transfer_active(s)) {
+ sdhci_resume_sdma_transfer(s);
+ }
break;
case SDHC_ADMASYSADDR + 4:
s->admasysaddr = (s->admasysaddr & (0x00000000FFFFFFFFULL |
((uint64_t)mask << 32))) | ((uint64_t)value << 32);
+ /* A completed selected-address write resumes boundary-stopped SDMA */
+ if (sdhci_version4_enabled(s) &&
+ sdhci_64bit_addressing_enabled(s) &&
+ !(mask & 0xff000000) && s->sdma_boundary_paused &&
+ sdhci_sdma_transfer_active(s)) {
+ sdhci_resume_sdma_transfer(s);
+ }
break;
case SDHC_FEAER:
s->acmd12errsts |= value;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 11/51] hw/sd/sdcard: Register device ops in drives without media
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (9 preceding siblings ...)
2026-09-03 10:38 ` [PULL 10/51] hw/sd: sdhci: Resume version 4 SDMA at buffer boundaries Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 12/51] hw/cxl: fix timer leak in cxl_destroy_cci() Philippe Mathieu-Daudé
` (40 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Alberto Garcia <berto@igalia.com>
Commit a362b19a39 ("hw/sd/sdcard: Fix size check for backing block
image") accidentally moved the blk_set_dev_ops() call into the new
'if (blk_size >= 0)' block in sd_realize().
Because of that, if a drive is attached without a medium then the
condition is false (blk_size == -ENOMEDIUM) and blk_set_dev_ops() is
never called, so the drive is registered as having non-removable
media:
$QEMU -device sd-card,drive=sdcard0 -drive if=none,id=sdcard0
(qemu) change sdcard0 sd-card.qcow2
Error: Device 'sdcard0' is not removable
This patch moves the blk_set_perm() and blk_set_dev_ops() calls
outside of the 'if (blk_size >= 0)' block so the device ops and
permissions are registered when a drive is attached.
Cc: qemu-stable@nongnu.org
Fixes: a362b19a39 ("hw/sd/sdcard: Fix size check for backing block image")
Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260723205847.137001-1-berto@igalia.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/sd/sd.c | 47 +++++++++++++++++++++++------------------------
1 file changed, 23 insertions(+), 24 deletions(-)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 674ca09b49f..b1b3b1226a7 100644
--- a/hw/sd/sd.c
+++ b/hw/sd/sd.c
@@ -3100,7 +3100,6 @@ static void sd_blk_size_error(SDState *sd, int64_t blk_size,
static void sd_realize(DeviceState *dev, Error **errp)
{
SDState *sd = SDMMC_COMMON(dev);
- int64_t blk_size = -ENOMEDIUM;
int ret;
switch (sd->spec_version) {
@@ -3118,32 +3117,32 @@ static void sd_realize(DeviceState *dev, Error **errp)
return;
}
- blk_size = blk_getlength(sd->blk);
- }
- if (blk_size >= 0) {
- blk_size -= sd->boot_part_size * 2 + sd->rpmb_part_size;
- if (blk_size > SDSC_MAX_CAPACITY) {
- if (sd_is_emmc(sd) &&
- !QEMU_IS_ALIGNED(blk_size, 1 << HWBLOCK_SHIFT)) {
- int64_t blk_size_aligned =
- ((blk_size >> HWBLOCK_SHIFT) + 1) << HWBLOCK_SHIFT;
- sd_blk_size_error(sd, blk_size, blk_size_aligned,
- "multiples of 512", errp);
+ int64_t blk_size = blk_getlength(sd->blk);
+ if (blk_size >= 0) {
+ blk_size -= sd->boot_part_size * 2 + sd->rpmb_part_size;
+ if (blk_size > SDSC_MAX_CAPACITY) {
+ if (sd_is_emmc(sd) &&
+ !QEMU_IS_ALIGNED(blk_size, 1 << HWBLOCK_SHIFT)) {
+ int64_t blk_size_aligned =
+ ((blk_size >> HWBLOCK_SHIFT) + 1) << HWBLOCK_SHIFT;
+ sd_blk_size_error(sd, blk_size, blk_size_aligned,
+ "multiples of 512", errp);
+ return;
+ } else if (!sd_is_emmc(sd) &&
+ !QEMU_IS_ALIGNED(blk_size, 512 * KiB)) {
+ int64_t blk_size_aligned = ((blk_size >> 19) + 1) << 19;
+ sd_blk_size_error(sd, blk_size, blk_size_aligned,
+ "multiples of 512K", errp);
+ return;
+ }
+ } else if (blk_size > 0 && !is_power_of_2(blk_size)) {
+ sd_blk_size_error(sd, blk_size, pow2ceil(blk_size),
+ "a power of 2", errp);
return;
- } else if (!sd_is_emmc(sd) &&
- !QEMU_IS_ALIGNED(blk_size, 512 * KiB)) {
- int64_t blk_size_aligned = ((blk_size >> 19) + 1) << 19;
- sd_blk_size_error(sd, blk_size, blk_size_aligned,
- "multiples of 512K", errp);
+ } else if (blk_size < 0) {
+ error_setg(errp, "eMMC image smaller than boot partitions");
return;
}
- } else if (blk_size > 0 && !is_power_of_2(blk_size)) {
- sd_blk_size_error(sd, blk_size, pow2ceil(blk_size), "a power of 2",
- errp);
- return;
- } else if (blk_size < 0) {
- error_setg(errp, "eMMC image smaller than boot partitions");
- return;
}
ret = blk_set_perm(sd->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 12/51] hw/cxl: fix timer leak in cxl_destroy_cci()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (10 preceding siblings ...)
2026-09-03 10:38 ` [PULL 11/51] hw/sd/sdcard: Register device ops in drives without media Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 13/51] hw/sd/axiado_sdhci: Add header guard Philippe Mathieu-Daudé
` (39 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Junjie Cao <junjie.cao@intel.com>
cxl_init_cci() allocates a QEMUTimer via timer_new_ms() but
cxl_destroy_cci() never frees it. This leaks a timer object on every
device exit path and, more critically, on every device reset cycle since
the secondary CCIs (vdm_fm_owned_ld_mctp_cci, ld0_cci) are destroyed
and re-initialized each time ct3d_reset() runs.
Tear the CCI down in the reverse of cxl_init_cci()'s setup order:
destroy the mutex, then free the timer. timer_free() cancels any
pending expiry via timer_del() internally and tolerates a NULL pointer;
clear the field afterwards so that a repeated timer_free() on the same
CCI is a safe no-op.
(The function as a whole is still not idempotent: qemu_mutex_destroy()
asserts on an already-destroyed mutex. Callers must not invoke
cxl_destroy_cci() twice; the .initialized guard added in the next patch
enforces that.)
Cc: qemu-stable@nongnu.org
Fixes: 98cbac128f1c ("hw/cxl: Support aborting background commands")
Signed-off-by: Junjie Cao <junjie.cao@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260729144645.1552511-2-junjie.cao@intel.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/cxl/cxl-mailbox-utils.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index ec18338b423..603677a97bb 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -4795,6 +4795,8 @@ void cxl_init_cci(CXLCCI *cci, size_t payload_max)
void cxl_destroy_cci(CXLCCI *cci)
{
qemu_mutex_destroy(&cci->bg.lock);
+ timer_free(cci->bg.timer);
+ cci->bg.timer = NULL;
cci->initialized = false;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 13/51] hw/sd/axiado_sdhci: Add header guard
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (11 preceding siblings ...)
2026-09-03 10:38 ` [PULL 12/51] hw/cxl: fix timer leak in cxl_destroy_cci() Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 14/51] MAINTAINERS: Cover pflash QTest in pflash section Philippe Mathieu-Daudé
` (38 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Kuan-Jui Chiu <kchiu@axiado.com>
Add the missing header guards to avoid re-definition
errors when this header is included multiple times.
Fixes: 8c55a630c5b ("hw/sd: Add Axiado SD host controller with eMMC PHY")
Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>
Reviewed-by: Jack Wang <163wangjack@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260826074635.2850931-2-kchiu@axiado.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/sd/axiado_sdhci.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/include/hw/sd/axiado_sdhci.h b/include/hw/sd/axiado_sdhci.h
index 85afebad931..ab52eb8185f 100644
--- a/include/hw/sd/axiado_sdhci.h
+++ b/include/hw/sd/axiado_sdhci.h
@@ -6,6 +6,9 @@
* SPDX-License-Identifier: GPL-2.0-or-later
*/
+#ifndef AXIADO_SDHCI_H
+#define AXIADO_SDHCI_H
+
#include "hw/sd/sdhci.h"
#include "qom/object.h"
@@ -19,3 +22,5 @@ typedef struct AxiadoSDHCIState {
MemoryRegion emmc_phy;
BusState *sd_bus;
} AxiadoSDHCIState;
+
+#endif /* AXIADO_SDHCI_H */
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 14/51] MAINTAINERS: Cover pflash QTest in pflash section
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (12 preceding siblings ...)
2026-09-03 10:38 ` [PULL 13/51] hw/sd/axiado_sdhci: Add header guard Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:38 ` [PULL 15/51] hw/block/pflash_cfi01: Always set romd mode when clearing wcycle and cmd Philippe Mathieu-Daudé
` (37 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
Include the pflash-cfi02-test.c test in the "Parallel NOR
Flash devices" to be notified when patches modify it.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20260820142212.27537-1-philmd@oss.qualcomm.com>
---
MAINTAINERS | 1 +
1 file changed, 1 insertion(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a898162cea5..e3f91ff1cab 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2377,6 +2377,7 @@ M: Philippe Mathieu-Daudé <philmd@mailo.com>
S: Maintained
F: hw/block/pflash_cfi*.c
F: include/hw/block/flash.h
+F: tests/qtest/pflash-cfi02-test.c
SCSI
M: Paolo Bonzini <pbonzini@redhat.com>
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 15/51] hw/block/pflash_cfi01: Always set romd mode when clearing wcycle and cmd
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (13 preceding siblings ...)
2026-09-03 10:38 ` [PULL 14/51] MAINTAINERS: Cover pflash QTest in pflash section Philippe Mathieu-Daudé
@ 2026-09-03 10:38 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 16/51] hw/block/pflash_cfi02: Add migration support Philippe Mathieu-Daudé
` (36 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:38 UTC (permalink / raw)
To: qemu-devel
From: Peter Maydell <peter.maydell@linaro.org>
The pflash_cfi01 code has an invariant that the MemoryRegion is in
ROMD mode if and only if wcycle == 0 && cmd == 0. We rely on this
for setting ROMD mode on an inbound migration.
There is one corner case where the code clears wcycle and cmd without
also setting ROMD mode on the MR: in the "should never happen" code
path in pflash_read(). As the comment notes, that code really is
unreachable (unless an inbound migration feeds us a bogus pfl->cmd
value), so this isn't a problem in practice. But it does make the
code a little trickier to analyse.
Pull out a function which does the "clear wcycle and cmd and set mode
to ROMD", and use it in the three places that need to do this. This
makes it clearer that we are preserving our invariant, and tidies up
the loose end noted in the commit message of 60d010f66f2ad7
("hw/block/pflash_cfi01: Restore ROMD mode after migration").
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260818115742.2268257-1-peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/block/pflash_cfi01.c | 31 +++++++++++++++----------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
index a13b91967ed..486fc6350d8 100644
--- a/hw/block/pflash_cfi01.c
+++ b/hw/block/pflash_cfi01.c
@@ -243,6 +243,18 @@ static uint32_t pflash_devid_query(PFlashCFI01 *pfl, hwaddr offset)
return resp;
}
+static void pflash_set_to_read_array_mode(PFlashCFI01 *pfl)
+{
+ /*
+ * Reset the flash device to its "just read the data" mode.
+ * The command 0x00 is not assigned by the CFI open standard,
+ * but QEMU historically uses it for the READ_ARRAY command (0xff).
+ */
+ pfl->wcycle = 0;
+ pfl->cmd = 0x00;
+ memory_region_rom_device_set_romd(&pfl->mem, true);
+}
+
static uint32_t pflash_data_read(PFlashCFI01 *pfl, hwaddr offset,
int width, int be)
{
@@ -270,12 +282,7 @@ static uint32_t pflash_read(PFlashCFI01 *pfl, hwaddr offset,
default:
/* This should never happen : reset state & treat it as a read */
trace_pflash_read_unknown_state(pfl->name, pfl->cmd);
- pfl->wcycle = 0;
- /*
- * The command 0x00 is not assigned by the CFI open standard,
- * but QEMU historically uses it for the READ_ARRAY command (0xff).
- */
- pfl->cmd = 0x00;
+ pflash_set_to_read_array_mode(pfl);
/* fall through to read code */
case 0x00: /* This model reset value for READ_ARRAY (not CFI compliant) */
/* Flash area read */
@@ -652,9 +659,7 @@ static void pflash_write(PFlashCFI01 *pfl, hwaddr offset,
mode_read_array:
trace_pflash_mode_read_array(pfl->name);
- memory_region_rom_device_set_romd(&pfl->mem, true);
- pfl->wcycle = 0;
- pfl->cmd = 0x00; /* This model reset value for READ_ARRAY (not CFI) */
+ pflash_set_to_read_array_mode(pfl);
}
@@ -873,13 +878,7 @@ static void pflash_cfi01_system_reset(DeviceState *dev)
PFlashCFI01 *pfl = PFLASH_CFI01(dev);
trace_pflash_reset(pfl->name);
- /*
- * The command 0x00 is not assigned by the CFI open standard,
- * but QEMU historically uses it for the READ_ARRAY command (0xff).
- */
- pfl->cmd = 0x00;
- pfl->wcycle = 0;
- memory_region_rom_device_set_romd(&pfl->mem, true);
+ pflash_set_to_read_array_mode(pfl);
/*
* The WSM ready timer occurs at most 150ns after system reset.
* This model deliberately ignores this delay.
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 16/51] hw/block/pflash_cfi02: Add migration support
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (14 preceding siblings ...)
2026-09-03 10:38 ` [PULL 15/51] hw/block/pflash_cfi01: Always set romd mode when clearing wcycle and cmd Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 17/51] accel/tcg: Rename for exception codes named @ret as @excp Philippe Mathieu-Daudé
` (35 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Om Barkare <ombarkare123@gmail.com>
Device did not have migration support, which would result in its
internal state being lost during migration or saves.
Add VMStateDescription to serialize state and set memory regions
romd_mode to rom_mode field in post load hook
total_sectors was changed from uint32_t to int32_t to satisfy the
VMSTATE_BITMAP macro's _field_size argument, but that is OK because
it's a value is calculated using the size of the flash and it will
never be large enough to overflow int32_t
The only boards using pflash_cfi02 are the sh4 r2d and
the arm canon-a1100, musicpal and xilinx-zynq-a9
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4157
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Om Barkare <ombarkare123@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20260827193942.69406-1-ombarkare123@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/block/pflash_cfi02.c | 52 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c
index 6f952fe7de0..4f72c438c0c 100644
--- a/hw/block/pflash_cfi02.c
+++ b/hw/block/pflash_cfi02.c
@@ -46,6 +46,7 @@
#include "qemu/module.h"
#include "hw/core/sysbus.h"
#include "migration/vmstate.h"
+#include "system/runstate.h"
#include "trace.h"
#define PFLASH_LAZY_ROMD_THRESHOLD 42
@@ -71,7 +72,7 @@ struct PFlashCFI02 {
BlockBackend *blk;
uint32_t uniform_nb_blocs;
uint32_t uniform_sector_len;
- uint32_t total_sectors;
+ int32_t total_sectors;
uint32_t nb_blocs[PFLASH_MAX_ERASE_REGIONS];
uint32_t sector_len[PFLASH_MAX_ERASE_REGIONS];
uint32_t chip_len;
@@ -107,6 +108,29 @@ struct PFlashCFI02 {
unsigned long *sector_erase_map;
char *name;
void *storage;
+ VMChangeStateEntry *vmstate;
+};
+
+static int pflash_post_load(void *opaque, int version_id);
+
+static const VMStateDescription vmstate_pflash = {
+ .name = "pflash_cfi02",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .post_load = pflash_post_load,
+ .fields = (const VMStateField[]) {
+ VMSTATE_INT32(wcycle, PFlashCFI02),
+ VMSTATE_INT32(bypass, PFlashCFI02),
+ VMSTATE_UINT8(cmd, PFlashCFI02),
+ VMSTATE_UINT8(status, PFlashCFI02),
+ VMSTATE_TIMER(timer, PFlashCFI02),
+ VMSTATE_BOOL(rom_mode, PFlashCFI02),
+ VMSTATE_INT32(read_counter, PFlashCFI02),
+ VMSTATE_INT32(sectors_to_erase, PFlashCFI02),
+ VMSTATE_UINT64(erase_time_remaining, PFlashCFI02),
+ VMSTATE_BITMAP(sector_erase_map, PFlashCFI02, 1, total_sectors),
+ VMSTATE_END_OF_LIST()
+ }
};
/*
@@ -976,6 +1000,7 @@ static void pflash_cfi02_class_init(ObjectClass *klass, const void *data)
device_class_set_legacy_reset(dc, pflash_cfi02_reset);
dc->unrealize = pflash_cfi02_unrealize;
device_class_set_props(dc, pflash_cfi02_properties);
+ dc->vmsd = &vmstate_pflash;
set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
}
@@ -1028,3 +1053,28 @@ PFlashCFI02 *pflash_cfi02_register(hwaddr base,
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
return PFLASH_CFI02(dev);
}
+
+static void postload_update_cb(void *opaque, bool running, RunState state)
+{
+ PFlashCFI02 *pfl = opaque;
+
+ /* This is called after bdrv_activate_all. */
+ qemu_del_vm_change_state_handler(pfl->vmstate);
+ pfl->vmstate = NULL;
+
+ trace_pflash_postload_cb(pfl->name);
+ pflash_update(pfl, 0, pfl->chip_len);
+}
+
+static int pflash_post_load(void *opaque, int version_id)
+{
+ PFlashCFI02 *pfl = opaque;
+
+ if (!pfl->ro) {
+ pfl->vmstate = qemu_add_vm_change_state_handler(postload_update_cb, pfl);
+ }
+
+ memory_region_rom_device_set_romd(&pfl->orig_mem, pfl->rom_mode);
+
+ return 0;
+}
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 17/51] accel/tcg: Rename for exception codes named @ret as @excp
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (15 preceding siblings ...)
2026-09-03 10:39 ` [PULL 16/51] hw/block/pflash_cfi02: Add migration support Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 18/51] accel/tcg: Restrict EXCP_HALTED handling to system emulation Philippe Mathieu-Daudé
` (34 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Rename meaningless @ret or @r variables as @excp to
directly denote the value is an exception. No logical
changes, purely cosmetic/clarity improvement.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260819145649.23439-2-philmd@oss.qualcomm.com>
---
accel/tcg/cpu-exec.c | 24 ++++++++++++------------
accel/tcg/tcg-accel-ops-mttcg.c | 7 ++++---
accel/tcg/tcg-accel-ops-rr.c | 8 ++++----
accel/tcg/tcg-accel-ops.c | 7 ++++---
4 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 257211235db..53d90c400d5 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -687,7 +687,7 @@ static inline void cpu_handle_debug_exception(CPUState *cpu)
}
}
-static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
+static inline bool cpu_handle_exception(CPUState *cpu, int *excp)
{
if (cpu->exception_index < 0) {
#ifndef CONFIG_USER_ONLY
@@ -703,8 +703,8 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (cpu->exception_index >= EXCP_INTERRUPT) {
/* exit request from the cpu execution loop */
- *ret = cpu->exception_index;
- if (*ret == EXCP_DEBUG) {
+ *excp = cpu->exception_index;
+ if (*excp == EXCP_DEBUG) {
cpu_handle_debug_exception(cpu);
}
cpu->exception_index = -1;
@@ -720,7 +720,7 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
if (tcg_ops->fake_user_interrupt) {
tcg_ops->fake_user_interrupt(cpu);
}
- *ret = cpu->exception_index;
+ *excp = cpu->exception_index;
cpu->exception_index = -1;
return true;
#else
@@ -738,13 +738,13 @@ static inline bool cpu_handle_exception(CPUState *cpu, int *ret)
* raised when single-stepping so that GDB doesn't miss the
* next instruction.
*/
- *ret = EXCP_DEBUG;
+ *excp = EXCP_DEBUG;
cpu_handle_debug_exception(cpu);
return true;
}
} else if (!replay_has_interrupt()) {
/* give a chance to iothread in replay mode */
- *ret = EXCP_INTERRUPT;
+ *excp = EXCP_INTERRUPT;
return true;
}
#endif
@@ -935,10 +935,10 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
static int __attribute__((noinline))
cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
{
- int ret;
+ int excp;
/* if an exception is pending, we execute it here */
- while (!cpu_handle_exception(cpu, &ret)) {
+ while (!cpu_handle_exception(cpu, &excp)) {
TranslationBlock *last_tb = NULL;
int tb_exit = 0;
@@ -1006,7 +1006,7 @@ cpu_exec_loop(CPUState *cpu, SyncClocks *sc)
align_clocks(sc, cpu);
}
}
- return ret;
+ return excp;
}
static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc)
@@ -1021,7 +1021,7 @@ static int cpu_exec_setjmp(CPUState *cpu, SyncClocks *sc)
int cpu_exec(CPUState *cpu)
{
- int ret;
+ int excp;
SyncClocks sc = { 0 };
/* replay_interrupt may need current_cpu */
@@ -1042,10 +1042,10 @@ int cpu_exec(CPUState *cpu)
*/
init_delay_params(&sc, cpu);
- ret = cpu_exec_setjmp(cpu, &sc);
+ excp = cpu_exec_setjmp(cpu, &sc);
cpu_exec_exit(cpu);
- return ret;
+ return excp;
}
bool tcg_exec_realizefn(CPUState *cpu, Error **errp)
diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c
index 69560fdb9d8..e7edd1945f2 100644
--- a/accel/tcg/tcg-accel-ops-mttcg.c
+++ b/accel/tcg/tcg-accel-ops-mttcg.c
@@ -90,11 +90,12 @@ static void *mttcg_cpu_thread_fn(void *arg)
qemu_process_cpu_events(cpu);
if (cpu_can_run(cpu)) {
- int r;
+ int excp;
+
bql_unlock();
- r = tcg_cpu_exec(cpu);
+ excp = tcg_cpu_exec(cpu);
bql_lock();
- switch (r) {
+ switch (excp) {
case EXCP_DEBUG:
cpu_handle_guest_debug(cpu);
break;
diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c
index cdaa3e11808..d6c2fc019c9 100644
--- a/accel/tcg/tcg-accel-ops-rr.c
+++ b/accel/tcg/tcg-accel-ops-rr.c
@@ -277,22 +277,22 @@ static void *rr_cpu_thread_fn(void *arg)
(cpu->singlestep_flags & SSTEP_NOTIMER) == 0);
if (cpu_can_run(cpu)) {
- int r;
+ int excp;
bql_unlock();
if (icount_enabled()) {
icount_prepare_for_run(cpu, cpu_budget);
}
- r = tcg_cpu_exec(cpu);
+ excp = tcg_cpu_exec(cpu);
if (icount_enabled()) {
icount_process_data(cpu);
}
bql_lock();
- if (r == EXCP_DEBUG) {
+ if (excp == EXCP_DEBUG) {
cpu_handle_guest_debug(cpu);
break;
- } else if (r == EXCP_ATOMIC) {
+ } else if (excp == EXCP_ATOMIC) {
bql_unlock();
cpu_exec_step_atomic(cpu);
bql_lock();
diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c
index 560fe2554ba..9c3d2214162 100644
--- a/accel/tcg/tcg-accel-ops.c
+++ b/accel/tcg/tcg-accel-ops.c
@@ -77,13 +77,14 @@ void tcg_cpu_destroy(CPUState *cpu)
int tcg_cpu_exec(CPUState *cpu)
{
- int ret;
+ int excp;
+
assert(tcg_enabled());
cpu_exec_start(cpu);
- ret = cpu_exec(cpu);
+ excp = cpu_exec(cpu);
cpu_exec_end(cpu);
- return ret;
+ return excp;
}
static void tcg_cpu_reset_hold(CPUState *cpu)
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 18/51] accel/tcg: Restrict EXCP_HALTED handling to system emulation
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (16 preceding siblings ...)
2026-09-03 10:39 ` [PULL 17/51] accel/tcg: Rename for exception codes named @ret as @excp Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 19/51] accel/tcg: Check %halted field in cpu_handle_halt() caller Philippe Mathieu-Daudé
` (33 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
EXCP_HALTED is defined and documented in "exec/cpu-common.h" as:
#define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */
Since vCPUs can not be halted in user-mode emulation, guard the
whole block within !CONFIG_USER_ONLY section. No logic changes.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260819145649.23439-3-philmd@oss.qualcomm.com>
---
accel/tcg/cpu-exec.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 53d90c400d5..69207301d1d 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -653,9 +653,9 @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
qemu_spin_unlock(&tb_next->jmp_lock);
}
+#ifndef CONFIG_USER_ONLY
static inline bool cpu_handle_halt(CPUState *cpu)
{
-#ifndef CONFIG_USER_ONLY
if (cpu->halted) {
const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
bool leave_halt = tcg_ops->cpu_exec_halt(cpu);
@@ -666,10 +666,10 @@ static inline bool cpu_handle_halt(CPUState *cpu)
cpu->halted = 0;
}
-#endif /* !CONFIG_USER_ONLY */
return false;
}
+#endif /* !CONFIG_USER_ONLY */
static inline void cpu_handle_debug_exception(CPUState *cpu)
{
@@ -1027,9 +1027,11 @@ int cpu_exec(CPUState *cpu)
/* replay_interrupt may need current_cpu */
current_cpu = cpu;
+#ifndef CONFIG_USER_ONLY
if (cpu_handle_halt(cpu)) {
return EXCP_HALTED;
}
+#endif
RCU_READ_LOCK_GUARD();
cpu_exec_enter(cpu);
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 19/51] accel/tcg: Check %halted field in cpu_handle_halt() caller
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (17 preceding siblings ...)
2026-09-03 10:39 ` [PULL 18/51] accel/tcg: Restrict EXCP_HALTED handling to system emulation Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 20/51] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
` (32 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
In cpu_exec(), check CPUState::halted field early before
calling cpu_handle_halt(). The logic is the same but allow
to simplify the async event processing hooks that will be
added in the next commit.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260819145649.23439-4-philmd@oss.qualcomm.com>
---
accel/tcg/cpu-exec.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index 69207301d1d..46b723cb734 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -656,17 +656,15 @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
#ifndef CONFIG_USER_ONLY
static inline bool cpu_handle_halt(CPUState *cpu)
{
- if (cpu->halted) {
- const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
- bool leave_halt = tcg_ops->cpu_exec_halt(cpu);
+ const TCGCPUOps *tcg_ops = cpu->cc->tcg_ops;
+ bool leave_halt = tcg_ops->cpu_exec_halt(cpu);
- if (!leave_halt) {
- return true;
- }
-
- cpu->halted = 0;
+ if (!leave_halt) {
+ return true;
}
+ cpu->halted = 0; /* allow execution */
+
return false;
}
#endif /* !CONFIG_USER_ONLY */
@@ -1028,8 +1026,11 @@ int cpu_exec(CPUState *cpu)
current_cpu = cpu;
#ifndef CONFIG_USER_ONLY
- if (cpu_handle_halt(cpu)) {
- return EXCP_HALTED;
+ if (cpu->halted) {
+ if (cpu_handle_halt(cpu)) {
+ return EXCP_HALTED;
+ }
+ assert(!cpu->halted);
}
#endif
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 20/51] target/i386: Remove const qualifier in ptw_setl*()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (18 preceding siblings ...)
2026-09-03 10:39 ` [PULL 19/51] accel/tcg: Check %halted field in cpu_handle_halt() caller Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 21/51] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
` (31 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Both cpu_exec_start() and cpu_exec_end() take a non-const CPUState
argument, however here we get that argument via PTETranslate::env
so @in->env can not be const. Remove the const qualifier.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-Id: <20260901095229.72018-2-philmd@oss.qualcomm.com>
---
target/i386/tcg/system/excp_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c
index d7ea77c8558..44be98a3c92 100644
--- a/target/i386/tcg/system/excp_helper.c
+++ b/target/i386/tcg/system/excp_helper.c
@@ -106,7 +106,7 @@ static inline uint64_t ptw_ldq(const PTETranslate *in, uint64_t ra)
* even 64-bit ones, because PG_PRESENT_MASK, PG_ACCESSED_MASK and
* PG_DIRTY_MASK are all in the low 32 bits.
*/
-static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
+static bool ptw_setl_slow(PTETranslate *in, uint32_t old, uint32_t new)
{
uint32_t cmp;
@@ -125,7 +125,7 @@ static bool ptw_setl_slow(const PTETranslate *in, uint32_t old, uint32_t new)
return cmp == old;
}
-static inline bool ptw_setl(const PTETranslate *in, uint32_t old, uint32_t set)
+static inline bool ptw_setl(PTETranslate *in, uint32_t old, uint32_t set)
{
if (set & ~old) {
uint32_t new = old | set;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 21/51] linux-user: Uncast void pointer argument as Object in target_cpu_free()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (19 preceding siblings ...)
2026-09-03 10:39 ` [PULL 20/51] target/i386: Remove const qualifier in ptw_setl*() Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 22/51] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
` (30 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
init_main_thread() is registered as Object::free() hook, thus
take an Object* argument. Uncast the void pointer as such.
While now cpu_env() accept any pointer type, next commit will
restrict it to CPUState* type. QOM-cast the Object to CPU type,
otherwise we will get:
../linux-user/i386/cpu_loop.c: In function ‘target_cpu_free’:
include/hw/core/cpu.h:604:31: error: ‘_Generic’ selector of type ‘void’ is not compatible with any association
../linux-user/x86_64/../i386/cpu_loop.c:331:19: note: in expansion of macro ‘cpu_env’
331 | target_munmap(cpu_env(obj)->gdt.base,
| ^~~~~~~
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260901095229.72018-3-philmd@oss.qualcomm.com>
---
linux-user/i386/cpu_loop.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/linux-user/i386/cpu_loop.c b/linux-user/i386/cpu_loop.c
index fe922fceb5a..2f733b0b477 100644
--- a/linux-user/i386/cpu_loop.c
+++ b/linux-user/i386/cpu_loop.c
@@ -326,9 +326,10 @@ void cpu_loop(CPUX86State *env)
}
}
-static void target_cpu_free(void *obj)
+static void target_cpu_free(void *ptr)
{
- target_munmap(cpu_env(obj)->gdt.base,
+ Object *obj = ptr;
+ target_munmap(X86_CPU(obj)->env.gdt.base,
sizeof(uint64_t) * TARGET_GDT_ENTRIES);
g_free(obj);
}
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 22/51] cpus: Add const-qualified CPU environment accessors
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (20 preceding siblings ...)
2026-09-03 10:39 ` [PULL 21/51] linux-user: Uncast void pointer argument as Object in target_cpu_free() Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 23/51] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
` (29 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Use _Generic() controlling-expression to add the const-qualified
variants of cpu_env(), env_cpu() and env_archcpu(). This allows to
safely access CPU architecture state when it should not be modified.
Alias env_cpu_const() which is still used.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260901095229.72018-4-philmd@oss.qualcomm.com>
---
include/exec/cpu-common.h | 30 +++++++++++-------------------
include/hw/core/cpu.h | 17 ++++++++++++-----
2 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6594f7fa1be..60997628cc6 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -85,21 +85,11 @@ static inline bool cpu_loop_exit_requested(const CPUState *cpu)
*
* Return the ArchCPU associated with the environment.
*/
-static inline ArchCPU *env_archcpu(CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
-
-/**
- * env_cpu_const(env)
- * @env: The architecture environment
- *
- * Return the CPUState associated with the environment.
- */
-static inline const CPUState *env_cpu_const(const CPUArchState *env)
-{
- return (void *)env - sizeof(CPUState);
-}
+#define env_archcpu(env) _Generic(env, \
+ CPUArchState *: \
+ (ArchCPU *)((void *)env - sizeof(CPUState)), \
+ const CPUArchState *: \
+ (const ArchCPU *)((const void *)env - sizeof(CPUState)))
/**
* env_cpu(env)
@@ -107,9 +97,11 @@ static inline const CPUState *env_cpu_const(const CPUArchState *env)
*
* Return the CPUState associated with the environment.
*/
-static inline CPUState *env_cpu(CPUArchState *env)
-{
- return (CPUState *)env_cpu_const(env);
-}
+#define env_cpu(env) _Generic(env, \
+ CPUArchState *: \
+ (CPUState *)((void *)(env) - sizeof(CPUState)), \
+ const CPUArchState *: \
+ (const CPUState *)((const void *)(env) - sizeof(CPUState)))
+#define env_cpu_const(cpu) env_cpu(cpu)
#endif /* CPU_COMMON_H */
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 81af7b9ee1a..18970ea39f5 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -594,11 +594,18 @@ struct CPUState {
QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) !=
sizeof(CPUState) - sizeof(CPUNegativeOffsetState));
-static inline CPUArchState *cpu_env(CPUState *cpu)
-{
- /* We validate that CPUArchState follows CPUState in cpu-target.c */
- return (CPUArchState *)(cpu + 1);
-}
+/**
+ * cpu_env(cpu)
+ * @cpu: The vCPU
+ *
+ * Return the CPUArchState associated with the CPU.
+ */
+#define cpu_env(cpu) _Generic(cpu, \
+ /* We validate that CPUArchState follows CPUState in target-info-stub.c */ \
+ CPUState *: \
+ (CPUArchState *)((cpu) + 1), \
+ const CPUState *: \
+ (const CPUArchState *)((cpu) + 1))
#ifdef CONFIG_TCG
/*
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 23/51] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (21 preceding siblings ...)
2026-09-03 10:39 ` [PULL 22/51] cpus: Add const-qualified CPU environment accessors Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 24/51] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
` (28 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Use the generic env_cpu() macro introduced in the previous
commit and remove the few env_cpu_const() uses.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260901095229.72018-5-philmd@oss.qualcomm.com>
---
include/exec/cpu-common.h | 1 -
linux-user/elfload.c | 2 +-
linux-user/i386/elfload.c | 2 +-
linux-user/x86_64/elfload.c | 2 +-
4 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 60997628cc6..c14362f780d 100644
--- a/include/exec/cpu-common.h
+++ b/include/exec/cpu-common.h
@@ -102,6 +102,5 @@ static inline bool cpu_loop_exit_requested(const CPUState *cpu)
(CPUState *)((void *)(env) - sizeof(CPUState)), \
const CPUArchState *: \
(const CPUState *)((const void *)(env) - sizeof(CPUState)))
-#define env_cpu_const(cpu) env_cpu(cpu)
#endif /* CPU_COMMON_H */
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
index 88508deac50..c4bdaa146a7 100644
--- a/linux-user/elfload.c
+++ b/linux-user/elfload.c
@@ -2128,7 +2128,7 @@ static int wmr_write_region(void *opaque, vaddr start,
#endif
static int elf_core_dump(int signr, const CPUArchState *env)
{
- const CPUState *cpu = env_cpu_const(env);
+ const CPUState *cpu = env_cpu(env);
const TaskState *ts = (const TaskState *)get_task_state((CPUState *)cpu);
struct rlimit dumpsize;
CountAndSizeRegions css;
diff --git a/linux-user/i386/elfload.c b/linux-user/i386/elfload.c
index 26b12001a3e..2e10f38a412 100644
--- a/linux-user/i386/elfload.c
+++ b/linux-user/i386/elfload.c
@@ -38,7 +38,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CPUX86State *env)
r->pt.es = tswapal(env->segs[R_ES].selector & 0xffff);
r->pt.fs = tswapal(env->segs[R_FS].selector & 0xffff);
r->pt.gs = tswapal(env->segs[R_GS].selector & 0xffff);
- r->pt.orig_ax = tswapal(get_task_state(env_cpu_const(env))->orig_ax);
+ r->pt.orig_ax = tswapal(get_task_state(env_cpu(env))->orig_ax);
r->pt.ip = tswapal(env->eip);
r->pt.cs = tswapal(env->segs[R_CS].selector & 0xffff);
r->pt.flags = tswapal(env->eflags);
diff --git a/linux-user/x86_64/elfload.c b/linux-user/x86_64/elfload.c
index 49a6f6180e0..121a8167acc 100644
--- a/linux-user/x86_64/elfload.c
+++ b/linux-user/x86_64/elfload.c
@@ -59,7 +59,7 @@ void elf_core_copy_regs(target_elf_gregset_t *r, const CPUX86State *env)
r->pt.dx = tswapal(env->regs[R_EDX]);
r->pt.si = tswapal(env->regs[R_ESI]);
r->pt.di = tswapal(env->regs[R_EDI]);
- r->pt.orig_ax = tswapal(get_task_state(env_cpu_const(env))->orig_ax);
+ r->pt.orig_ax = tswapal(get_task_state(env_cpu(env))->orig_ax);
r->pt.ip = tswapal(env->eip);
r->pt.cs = tswapal(env->segs[R_CS].selector & 0xffff);
r->pt.flags = tswapal(env->eflags);
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 24/51] system/cpus: Constify various CPUState arguments
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (22 preceding siblings ...)
2026-09-03 10:39 ` [PULL 23/51] linux-user: Replace env_cpu_const() by generic env_cpu() equivalent Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 25/51] target/avr: Constify CPUAVRState for some cpu_*() getters Philippe Mathieu-Daudé
` (27 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Mark the CPUState structure const when it is only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260901095229.72018-6-philmd@oss.qualcomm.com>
---
include/hw/core/cpu.h | 4 ++--
include/system/cpus.h | 4 ++--
system/cpus.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 18970ea39f5..328e30045ce 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -900,7 +900,7 @@ void qemu_cpu_kick(CPUState *cpu);
* Returns: %true if run state is not running or if artificially stopped;
* %false otherwise.
*/
-bool cpu_is_stopped(CPUState *cpu);
+bool cpu_is_stopped(const CPUState *cpu);
/**
* do_run_on_cpu:
@@ -1007,7 +1007,7 @@ void cpu_interrupt(CPUState *cpu, int mask);
*
* Checks if any of interrupts in @mask are pending on @cpu.
*/
-static inline bool cpu_test_interrupt(CPUState *cpu, int mask)
+static inline bool cpu_test_interrupt(const CPUState *cpu, int mask)
{
return qatomic_load_acquire(&cpu->interrupt_request) & mask;
}
diff --git a/include/system/cpus.h b/include/system/cpus.h
index 508444ccf1c..bf36b823769 100644
--- a/include/system/cpus.h
+++ b/include/system/cpus.h
@@ -13,10 +13,10 @@ const AccelOpsClass *cpus_get_accel(void);
#define VCPU_THREAD_NAME_SIZE 16
void cpus_kick_thread(CPUState *cpu);
-bool cpu_work_list_empty(CPUState *cpu);
+bool cpu_work_list_empty(const CPUState *cpu);
bool cpu_thread_is_idle(CPUState *cpu);
bool all_cpu_threads_idle(void);
-bool cpu_can_run(CPUState *cpu);
+bool cpu_can_run(const CPUState *cpu);
void qemu_process_cpu_events_common(CPUState *cpu);
void cpu_thread_signal_created(CPUState *cpu);
void cpu_thread_signal_destroyed(CPUState *cpu);
diff --git a/system/cpus.c b/system/cpus.c
index f37e215c586..e11a5aab6a6 100644
--- a/system/cpus.c
+++ b/system/cpus.c
@@ -69,12 +69,12 @@ static QemuMutex bql;
*/
static const AccelOpsClass *cpus_accel;
-bool cpu_is_stopped(CPUState *cpu)
+bool cpu_is_stopped(const CPUState *cpu)
{
return cpu->stopped || !runstate_is_running();
}
-bool cpu_work_list_empty(CPUState *cpu)
+bool cpu_work_list_empty(const CPUState *cpu)
{
return QSIMPLEQ_EMPTY_ATOMIC(&cpu->work_list);
}
@@ -271,7 +271,7 @@ void cpu_interrupt(CPUState *cpu, int mask)
cpus_accel->handle_interrupt(cpu, mask);
}
-bool cpu_can_run(CPUState *cpu)
+bool cpu_can_run(const CPUState *cpu)
{
if (cpu->stop) {
return false;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 25/51] target/avr: Constify CPUAVRState for some cpu_*() getters
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (23 preceding siblings ...)
2026-09-03 10:39 ` [PULL 24/51] system/cpus: Constify various CPUState arguments Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 26/51] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
` (26 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Add the const qualifier to CPUAVRState when the
argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20260901095229.72018-8-philmd@oss.qualcomm.com>
---
target/avr/cpu.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index a818db753b2..1e4e839bd83 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -183,7 +183,7 @@ int avr_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
int avr_print_insn(bfd_vma addr, disassemble_info *info);
vaddr avr_cpu_gdb_adjust_breakpoint(CPUState *cpu, vaddr addr);
-static inline int avr_feature(CPUAVRState *env, AVRFeature feature)
+static inline int avr_feature(const CPUAVRState *env, AVRFeature feature)
{
return (env->features & (1U << feature)) != 0;
}
@@ -204,12 +204,12 @@ enum {
TB_FLAGS_SKIP = 2,
};
-static inline int cpu_interrupts_enabled(CPUAVRState *env)
+static inline int cpu_interrupts_enabled(const CPUAVRState *env)
{
return env->sregI != 0;
}
-static inline uint8_t cpu_get_sreg(CPUAVRState *env)
+static inline uint8_t cpu_get_sreg(const CPUAVRState *env)
{
return (env->sregC) << 0
| (env->sregZ) << 1
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 26/51] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (24 preceding siblings ...)
2026-09-03 10:39 ` [PULL 25/51] target/avr: Constify CPUAVRState for some cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 27/51] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
` (25 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
@env argument is accessed without modification in
hexagon_thread_is_enabled(), qualify it as const.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Message-Id: <20260901095229.72018-9-philmd@oss.qualcomm.com>
---
target/hexagon/cpu.h | 2 +-
target/hexagon/cpu_helper.h | 4 ++--
target/hexagon/cpu.c | 4 ++--
target/hexagon/cpu_helper.c | 6 +++---
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index ed5671abe5c..8a4a81dc26c 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -217,7 +217,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
* @return true if the @a thread_env hardware thread is
* not stopped.
*/
-bool hexagon_thread_is_enabled(CPUHexagonState *thread_env);
+bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env);
uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg);
void hexagon_cpu_soft_reset(CPUHexagonState *env);
#endif
diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index ca2e13ab1d1..12512efd74f 100644
--- a/target/hexagon/cpu_helper.h
+++ b/target/hexagon/cpu_helper.h
@@ -15,8 +15,8 @@ void hexagon_peek_memory_range(CPUHexagonState *env, uint32_t start_addr,
uint32_t length, uintptr_t retaddr);
uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index);
void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old);
-int get_cpu_mode(CPUHexagonState *env);
-int get_exe_mode(CPUHexagonState *env);
+int get_cpu_mode(const CPUHexagonState *env);
+int get_exe_mode(const CPUHexagonState *env);
void clear_wait_mode(CPUHexagonState *env);
void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause);
void hexagon_start_threads(CPUHexagonState *env, uint32_t mask);
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 0530ec3ca96..4a7b76e3bcc 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -346,9 +346,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
}
#ifndef CONFIG_USER_ONLY
-bool hexagon_thread_is_enabled(CPUHexagonState *env)
+bool hexagon_thread_is_enabled(const CPUHexagonState *env)
{
- HexagonCPU *cpu = env_archcpu(env);
+ const HexagonCPU *cpu = env_archcpu(env);
uint32_t modectl;
uint32_t thread_enabled_mask;
bool E_bit;
diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
index 17d6b4eb2b4..9ce260d7448 100644
--- a/target/hexagon/cpu_helper.c
+++ b/target/hexagon/cpu_helper.c
@@ -316,9 +316,9 @@ void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause)
}
-int get_exe_mode(CPUHexagonState *env)
+int get_exe_mode(const CPUHexagonState *env)
{
- HexagonCPU *cpu;
+ const HexagonCPU *cpu;
uint32_t modectl, thread_enabled_mask, thread_wait_mask;
uint32_t isdbst, debugmode;
bool E_bit, W_bit, D_bit;
@@ -488,7 +488,7 @@ static int sys_in_user_mode_ssr(uint32_t ssr)
return 0;
}
-int get_cpu_mode(CPUHexagonState *env)
+int get_cpu_mode(const CPUHexagonState *env)
{
uint32_t ssr = env->t_sreg[HEX_SREG_SSR];
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 27/51] target/i386: Constify CPU*State for cpu_*_interrupt() getters
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (25 preceding siblings ...)
2026-09-03 10:39 ` [PULL 26/51] target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled() Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 28/51] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
` (24 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
x86_cpu_pending_interrupt() and x86_cpu_interrupts_enabled()
only read CPU state without modification, add the const
qualifiers to CPUState and CPUX86State parameters.
Simplify directly using cpu_env() in x86_cpu_pending_interrupt.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20260901095229.72018-10-philmd@oss.qualcomm.com>
---
target/i386/cpu.h | 4 ++--
target/i386/cpu.c | 5 ++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index dc5047cfb25..9ce8ca00381 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -2596,7 +2596,7 @@ void x86_cpu_gdb_init(CPUState *cs);
int cpu_x86_support_mca_broadcast(CPUX86State *env);
#ifndef CONFIG_USER_ONLY
-int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request);
+int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request);
bool x86_cpu_translate_for_debug(CPUState *cpu, vaddr addr,
TranslateForDebugResult *result);
@@ -3104,7 +3104,7 @@ static inline bool ctl_has_irq(CPUX86State *env)
return (env->int_ctl & V_IRQ_MASK) && (int_prio >= tpr);
}
-static inline bool x86_cpu_interrupts_enabled(CPUX86State *env)
+static inline bool x86_cpu_interrupts_enabled(const CPUX86State *env)
{
return ((env->eflags & IF_MASK) &&
!(env->hflags & HF_INHIBIT_IRQ_MASK)) ||
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 84e805ee85e..d01ff1948e5 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -10601,10 +10601,9 @@ static vaddr x86_cpu_get_pc(CPUState *cs)
}
#if !defined(CONFIG_USER_ONLY)
-int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
+int x86_cpu_pending_interrupt(const CPUState *cs, int interrupt_request)
{
- X86CPU *cpu = X86_CPU(cs);
- CPUX86State *env = &cpu->env;
+ const CPUX86State *env = cpu_env(cs);
if (interrupt_request & CPU_INTERRUPT_POLL) {
return CPU_INTERRUPT_POLL;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 28/51] target/loongarch: Constify LoongArchTLB
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (26 preceding siblings ...)
2026-09-03 10:39 ` [PULL 27/51] target/i386: Constify CPU*State for cpu_*_interrupt() getters Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 29/51] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
` (23 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
The pointed LoongArchTLB is only read, not modified: mark it const.
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-Id: <20260901095229.72018-11-philmd@oss.qualcomm.com>
---
target/loongarch/tcg/tlb_helper.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_helper.c
index a4b90beca65..40cc0764248 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -238,11 +238,11 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t high)
* field in tlb entry contains bit[47:13], so need adjust.
* virt_vpn = vaddr[47:13]
*/
-static LoongArchTLB *loongarch_tlb_search_cb(CPULoongArchState *env,
- vaddr vaddr, int csr_asid,
- tlb_match func)
+static const LoongArchTLB *
+loongarch_tlb_search_cb(CPULoongArchState *env, vaddr vaddr,
+ int csr_asid, tlb_match func)
{
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
uint16_t tlb_asid, stlb_idx;
uint8_t tlb_e, tlb_ps, stlb_ps;
bool tlb_g;
@@ -296,7 +296,7 @@ static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
{
int csr_asid;
tlb_match func;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
CPUSysState *sys = env_sys(env);
func = tlb_match_any;
@@ -594,7 +594,7 @@ void helper_invtlb_page_asid(CPULoongArchState *env, target_ulong info,
target_ulong addr)
{
int asid = info & 0x3ff;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
tlb_match func;
func = tlb_match_asid;
@@ -608,7 +608,7 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
target_ulong info, target_ulong addr)
{
int asid = info & 0x3ff;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
tlb_match func;
func = tlb_match_any;
@@ -842,7 +842,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
MMUAccessType access_type, int index,
int mmu_idx)
{
- LoongArchTLB *tlb = &env->tlb[index];
+ const LoongArchTLB *tlb = &env->tlb[index];
uint8_t tlb_ps, n;
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 29/51] target/mips: Constify CPUMIPSState for various cpu_*() getters
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (27 preceding siblings ...)
2026-09-03 10:39 ` [PULL 28/51] target/loongarch: Constify LoongArchTLB Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 30/51] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
` (22 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Add the const qualifier to CPUMIPSState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20260901095229.72018-14-philmd@oss.qualcomm.com>
---
target/mips/cpu.h | 8 ++++----
target/mips/internal.h | 10 +++++-----
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 319147a948c..32549791a18 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1300,7 +1300,7 @@ static inline int hflags_mmu_index(uint32_t hflags)
}
}
-static inline int mips_env_mmu_index(CPUMIPSState *env)
+static inline int mips_env_mmu_index(const CPUMIPSState *env)
{
return hflags_mmu_index(env->hflags);
}
@@ -1372,19 +1372,19 @@ static inline bool ase_3d_available(const CPUMIPSState *env)
}
/* Check presence of MSA implementation */
-static inline bool ase_msa_available(CPUMIPSState *env)
+static inline bool ase_msa_available(const CPUMIPSState *env)
{
return env->CP0_Config3 & (1 << CP0C3_MSAP);
}
/* Check presence of Loongson CSR instructions */
-static inline bool ase_lcsr_available(CPUMIPSState *env)
+static inline bool ase_lcsr_available(const CPUMIPSState *env)
{
return env->lcsr_cpucfg2 & (1 << CPUCFG2_LCSRP);
}
/* Check presence of multi-threading ASE implementation */
-static inline bool ase_mt_available(CPUMIPSState *env)
+static inline bool ase_mt_available(const CPUMIPSState *env)
{
return env->CP0_Config3 & (1 << CP0C3_MT);
}
diff --git a/target/mips/internal.h b/target/mips/internal.h
index c5c286872eb..7dba22300b1 100644
--- a/target/mips/internal.h
+++ b/target/mips/internal.h
@@ -165,7 +165,7 @@ void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val);
extern const VMStateDescription vmstate_mips_cpu;
-static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
+static inline bool cpu_mips_hw_interrupts_enabled(const CPUMIPSState *env)
{
return (env->CP0_Status & (1 << CP0St_IE)) &&
!(env->CP0_Status & (1 << CP0St_EXL)) &&
@@ -180,7 +180,7 @@ static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env)
}
/* Check if there is pending and not masked out interrupt */
-static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env)
+static inline bool cpu_mips_hw_interrupts_pending(const CPUMIPSState *env)
{
int32_t pending;
int32_t status;
@@ -247,9 +247,9 @@ static inline void restore_pamask(CPUMIPSState *env)
}
}
-static inline int mips_vpe_active(CPUMIPSState *env)
+static inline int mips_vpe_active(const CPUMIPSState *env)
{
- MIPSCPU *cpu = env_archcpu(env);
+ const MIPSCPU *cpu = env_archcpu(env);
int active = 1;
/* Check that the VPE is enabled. */
@@ -281,7 +281,7 @@ static inline int mips_vpe_active(CPUMIPSState *env)
return active;
}
-static inline int mips_vp_active(CPUMIPSState *env)
+static inline int mips_vp_active(const CPUMIPSState *env)
{
CPUState *cs;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 30/51] target/s390x: Constify S390CPU for cpu_has_*() getters
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (28 preceding siblings ...)
2026-09-03 10:39 ` [PULL 29/51] target/mips: Constify CPUMIPSState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 31/51] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
` (21 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Add the const qualifier to S390CPU when the argument
is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Eric Farman <farman@linux.ibm.com>
Message-Id: <20260901095229.72018-15-philmd@oss.qualcomm.com>
---
target/s390x/cpu.h | 2 +-
target/s390x/s390x-internal.h | 12 ++++++------
target/s390x/interrupt.c | 22 +++++++++++-----------
3 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index f55b79ef8ac..998bbb0d7ff 100644
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -854,7 +854,7 @@ static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
return 0;
}
#endif /* CONFIG_USER_ONLY */
-static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
+static inline uint8_t s390_cpu_get_state(const S390CPU *cpu)
{
return cpu->env.cpu_state;
}
diff --git a/target/s390x/s390x-internal.h b/target/s390x/s390x-internal.h
index 81da207a5f4..da60b2b1fd4 100644
--- a/target/s390x/s390x-internal.h
+++ b/target/s390x/s390x-internal.h
@@ -334,12 +334,12 @@ void cpu_inject_clock_comparator(S390CPU *cpu);
void cpu_inject_cpu_timer(S390CPU *cpu);
void cpu_inject_emergency_signal(S390CPU *cpu, uint16_t src_cpu_addr);
int cpu_inject_external_call(S390CPU *cpu, uint16_t src_cpu_addr);
-bool s390_cpu_has_io_int(S390CPU *cpu);
-bool s390_cpu_has_ext_int(S390CPU *cpu);
-bool s390_cpu_has_mcck_int(S390CPU *cpu);
-bool s390_cpu_has_int(S390CPU *cpu);
-bool s390_cpu_has_restart_int(S390CPU *cpu);
-bool s390_cpu_has_stop_int(S390CPU *cpu);
+bool s390_cpu_has_io_int(const S390CPU *cpu);
+bool s390_cpu_has_ext_int(const S390CPU *cpu);
+bool s390_cpu_has_mcck_int(const S390CPU *cpu);
+bool s390_cpu_has_int(const S390CPU *cpu);
+bool s390_cpu_has_restart_int(const S390CPU *cpu);
+bool s390_cpu_has_stop_int(const S390CPU *cpu);
void cpu_inject_restart(S390CPU *cpu);
void cpu_inject_stop(S390CPU *cpu);
#endif /* CONFIG_USER_ONLY */
diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c
index 1dca835c5d8..d7e3fd45e4b 100644
--- a/target/s390x/interrupt.c
+++ b/target/s390x/interrupt.c
@@ -139,10 +139,10 @@ void s390_crw_mchk(void)
fsc->inject_crw_mchk(fs);
}
-bool s390_cpu_has_mcck_int(S390CPU *cpu)
+bool s390_cpu_has_mcck_int(const S390CPU *cpu)
{
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
if (!(env->psw.mask & PSW_MASK_MCHECK)) {
return false;
@@ -157,10 +157,10 @@ bool s390_cpu_has_mcck_int(S390CPU *cpu)
return false;
}
-bool s390_cpu_has_ext_int(S390CPU *cpu)
+bool s390_cpu_has_ext_int(const S390CPU *cpu)
{
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
if (!(env->psw.mask & PSW_MASK_EXT)) {
return false;
@@ -199,10 +199,10 @@ bool s390_cpu_has_ext_int(S390CPU *cpu)
return false;
}
-bool s390_cpu_has_io_int(S390CPU *cpu)
+bool s390_cpu_has_io_int(const S390CPU *cpu)
{
QEMUS390FLICState *flic = s390_get_qemu_flic(s390_get_flic());
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
if (!(env->psw.mask & PSW_MASK_IO)) {
return false;
@@ -211,21 +211,21 @@ bool s390_cpu_has_io_int(S390CPU *cpu)
return qemu_s390_flic_has_io(flic, env->cregs[6]);
}
-bool s390_cpu_has_restart_int(S390CPU *cpu)
+bool s390_cpu_has_restart_int(const S390CPU *cpu)
{
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
return env->pending_int & INTERRUPT_RESTART;
}
-bool s390_cpu_has_stop_int(S390CPU *cpu)
+bool s390_cpu_has_stop_int(const S390CPU *cpu)
{
- CPUS390XState *env = &cpu->env;
+ const CPUS390XState *env = &cpu->env;
return env->pending_int & INTERRUPT_STOP;
}
-bool s390_cpu_has_int(S390CPU *cpu)
+bool s390_cpu_has_int(const S390CPU *cpu)
{
if (!tcg_enabled()) {
return false;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 31/51] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (29 preceding siblings ...)
2026-09-03 10:39 ` [PULL 30/51] target/s390x: Constify S390CPU for cpu_has_*() getters Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 32/51] target/sparc: Constify CPUSPARCState for various cpu_*() getters Philippe Mathieu-Daudé
` (20 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
@iprio[] is an array only accessed read-only.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20260901095229.72018-16-philmd@oss.qualcomm.com>
---
target/riscv/cpu.h | 2 +-
target/riscv/cpu.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 718b66487a2..b974c2f4b4f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -646,7 +646,7 @@ int riscv_cpu_sirq_pending(CPURISCVState *env);
int riscv_cpu_vsirq_pending(CPURISCVState *env);
int riscv_cpu_pending_to_irq(CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
- uint64_t pending, uint8_t *iprio);
+ uint64_t pending, const uint8_t *iprio);
bool riscv_cpu_fp_enabled(CPURISCVState *env);
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a13177b7b77..fd1afbc7fe2 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -869,7 +869,7 @@ uint8_t riscv_cpu_default_priority(int irq)
int riscv_cpu_pending_to_irq(CPURISCVState *env,
int extirq, unsigned int extirq_def_prio,
- uint64_t pending, uint8_t *iprio)
+ uint64_t pending, const uint8_t *iprio)
{
int irq, best_irq = RISCV_EXCP_NONE;
unsigned int prio, best_prio = UINT_MAX;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 32/51] target/sparc: Constify CPUSPARCState for various cpu_*() getters
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (30 preceding siblings ...)
2026-09-03 10:39 ` [PULL 31/51] target/riscv: Constify @iprio argument in riscv_cpu_pending_to_irq() Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 33/51] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
` (19 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Add the const qualifier to CPUSPARCState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20260901095229.72018-18-philmd@oss.qualcomm.com>
---
target/sparc/cpu.h | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 5f583ed9de2..31a16c2af03 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -680,28 +680,28 @@ hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
#endif
#if defined (TARGET_SPARC64)
-static inline int cpu_has_hypervisor(CPUSPARCState *env1)
+static inline int cpu_has_hypervisor(const CPUSPARCState *env1)
{
return env1->def.features & CPU_FEATURE_HYPV;
}
-static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
+static inline int cpu_hypervisor_mode(const CPUSPARCState *env1)
{
return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
}
-static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+static inline int cpu_supervisor_mode(const CPUSPARCState *env1)
{
return env1->pstate & PS_PRIV;
}
#else
-static inline int cpu_supervisor_mode(CPUSPARCState *env1)
+static inline int cpu_supervisor_mode(const CPUSPARCState *env1)
{
return env1->psrs;
}
#endif
-static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
+static inline int cpu_interrupts_enabled(const CPUSPARCState *env1)
{
#if !defined (TARGET_SPARC64)
if (env1->psret != 0)
@@ -715,7 +715,7 @@ static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
return 0;
}
-static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
+static inline int cpu_pil_allowed(const CPUSPARCState *env1, int pil)
{
#if !defined(TARGET_SPARC64)
/* level 15 is non-maskable on sparc v8 */
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 33/51] target/tricore: Document architectural interrupts as not implemented
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (31 preceding siblings ...)
2026-09-03 10:39 ` [PULL 32/51] target/sparc: Constify CPUSPARCState for various cpu_*() getters Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 34/51] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
` (18 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
As mentioned in commit de680286b52 ("accel/tcg: Make
cpu_exec_interrupt hook mandatory"):
> Tricore doesn't currently implement the architectural
> interrupt handling.
Add a comment to help understanding why this SysemuCPUOps
has_work() handler is simply always returning %true.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260901095229.72018-19-philmd@oss.qualcomm.com>
---
target/tricore/cpu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
index dcd5c5065bc..84a05e3d363 100644
--- a/target/tricore/cpu.c
+++ b/target/tricore/cpu.c
@@ -113,6 +113,7 @@ static void tricore_cpu_reset_hold(Object *obj, ResetType type)
static bool tricore_cpu_has_work(CPUState *cs)
{
+ /* Interrupts are not implemented */
return true;
}
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 34/51] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (32 preceding siblings ...)
2026-09-03 10:39 ` [PULL 33/51] target/tricore: Document architectural interrupts as not implemented Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 35/51] target/arm: Return immediately on error in kvm_arch_init() Philippe Mathieu-Daudé
` (17 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
Add the const qualifier to CPUXtensaState when the
argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Max Filippov <jcmvbkbc@gmail.com>
Message-Id: <20260901095229.72018-20-philmd@oss.qualcomm.com>
---
target/xtensa/cpu.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 442e98bd1ba..49d6ad9083d 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -708,7 +708,7 @@ void xtensa_set_abi_call0(void);
bool xtensa_abi_call0(void);
#endif
-static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env)
+static inline uint32_t xtensa_replicate_windowstart(const CPUXtensaState *env)
{
return env->sregs[WINDOW_START] |
(env->sregs[WINDOW_START] << env->config->nareg / 4);
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 35/51] target/arm: Return immediately on error in kvm_arch_init()
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (33 preceding siblings ...)
2026-09-03 10:39 ` [PULL 34/51] target/xtensa: Constify CPUXtensaState in xtensa_replicate_windowstart() Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 36/51] qom/object: add is_available callback to TypeInfo Philippe Mathieu-Daudé
` (16 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
Returning an error to kvm_init() is fatal anyway, no need to continue
the initialization.
Leave the `ret` variable in the function scope because it will be reused
when adding RME support.
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Message-ID: <20260825220101.3443954-3-mathieu.poirier@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/arm/kvm.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index d40a6a98591..ed99be7fd80 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -596,7 +596,7 @@ int kvm_arch_get_default_type(MachineState *ms)
int kvm_arch_init(MachineState *ms, KVMState *s)
{
- int ret = 0;
+ int ret;
/* For ARM interrupt delivery is always asynchronous,
* whether we are using an in-kernel VGIC or not.
*/
@@ -618,7 +618,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
!kvm_check_extension(s, KVM_CAP_ARM_IRQ_LINE_LAYOUT_2)) {
error_report("Using more than 256 vcpus requires a host kernel "
"with KVM_CAP_ARM_IRQ_LINE_LAYOUT_2");
- ret = -EINVAL;
+ return -EINVAL;
}
if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
@@ -640,13 +640,14 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
warn_report("Eager Page Split support not available");
} else if (!(s->kvm_eager_split_size & sizes)) {
error_report("Eager Page Split requested chunk size not valid");
- ret = -EINVAL;
+ return -EINVAL;
} else {
ret = kvm_vm_enable_cap(s, KVM_CAP_ARM_EAGER_SPLIT_CHUNK_SIZE, 0,
s->kvm_eager_split_size);
if (ret < 0) {
error_report("Enabling of Eager Page Split failed: %s",
strerror(-ret));
+ return ret;
}
}
}
@@ -659,7 +660,7 @@ int kvm_arch_init(MachineState *ms, KVMState *s)
hw_breakpoints = g_array_sized_new(true, true,
sizeof(HWBreakpoint), max_hw_bps);
- return ret;
+ return 0;
}
unsigned long kvm_arch_vcpu_id(CPUState *cpu)
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 36/51] qom/object: add is_available callback to TypeInfo
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (34 preceding siblings ...)
2026-09-03 10:39 ` [PULL 35/51] target/arm: Return immediately on error in kvm_arch_init() Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 37/51] hw/arm: filter minimal set of machines Philippe Mathieu-Daudé
` (15 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
When removing target specific sections (#ifdef TARGET_X), we started
exposing types for different targets in the same file.
Previously, we implemented a filter based on interfaces, but it
proved to be too cumbersome, requiring duplication across architectures.
To simplify it, we add a new callback, is_available, to TypeInfo, that
will replace the existing filtering mechanism.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Tested-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-2-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/qom/object.h | 3 +++
qom/object.c | 4 ++++
rust/qom/src/qom.rs | 1 +
3 files changed, 8 insertions(+)
diff --git a/include/qom/object.h b/include/qom/object.h
index e24f0a2b2d0..7ecd0f210fb 100644
--- a/include/qom/object.h
+++ b/include/qom/object.h
@@ -469,6 +469,8 @@ struct Object
* @class_data: Data to pass to the @class_init,
* @class_base_init. This can be useful when building dynamic
* classes.
+ * @is_available: callback invoked at registration time, to dynamically check if
+ * this type should be available or not.
* @interfaces: The list of interfaces associated with this type. This
* should point to a static array that's terminated with a zero filled
* element.
@@ -491,6 +493,7 @@ struct TypeInfo
void (*class_base_init)(ObjectClass *klass, const void *data);
const void *class_data;
+ bool (*is_available)(void);
const InterfaceInfo *interfaces;
};
diff --git a/qom/object.c b/qom/object.c
index 85bbd7f9fe1..b1834a57cc9 100644
--- a/qom/object.c
+++ b/qom/object.c
@@ -163,6 +163,10 @@ static TypeImpl *type_register_internal(const TypeInfo *info)
abort();
}
+ if (info->is_available && !info->is_available()) {
+ return NULL;
+ }
+
ti = type_new(info);
type_table_add(ti);
diff --git a/rust/qom/src/qom.rs b/rust/qom/src/qom.rs
index cc00ddcfc98..bbb485e2cfd 100644
--- a/rust/qom/src/qom.rs
+++ b/rust/qom/src/qom.rs
@@ -691,6 +691,7 @@ pub trait ObjectImpl: ObjectType + IsA<Object> {
class_init: Some(rust_class_init::<Self>),
class_base_init: Self::CLASS_BASE_INIT,
class_data: core::ptr::null(),
+ is_available: None,
interfaces: core::ptr::null(),
};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 37/51] hw/arm: filter minimal set of machines
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (35 preceding siblings ...)
2026-09-03 10:39 ` [PULL 36/51] qom/object: add is_available callback to TypeInfo Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 38/51] system: query machines using TYPE_MACHINE Philippe Mathieu-Daudé
` (14 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
We are about to change the filtering logic for machines. These boards
are impacted and already are conditionally available. To not break
existing binaries, we need to filter them accordingly with new mechanic.
From there, we are free to remove the previous filtering mechanic
without changing any existing behaviour.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-3-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/arm/aspeed_ast27x0-fc.c | 1 +
hw/arm/aspeed_ast27x0_evb.c | 2 ++
hw/arm/raspi.c | 2 ++
hw/arm/raspi4b.c | 1 +
4 files changed, 6 insertions(+)
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index ceeae336df1..54230aa92e6 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -235,6 +235,7 @@ static const TypeInfo ast2700fc_types[] = {
.parent = TYPE_MACHINE,
.class_init = ast2700fc_class_init,
.instance_size = sizeof(Ast2700FCState),
+ .is_available = target_aarch64,
.interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index 0ff1bebeb0e..2b767808e12 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -76,12 +76,14 @@ static const TypeInfo aspeed_ast27x0_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast2700a1-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
+ .is_available = target_aarch64,
.interfaces = aarch64_machine_interfaces,
},
{
.name = MACHINE_TYPE_NAME("ast2700a2-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a2_evb_class_init,
+ .is_available = target_aarch64,
.interfaces = aarch64_machine_interfaces,
}
};
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 3f99e87428c..bbaa20bd630 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -407,11 +407,13 @@ static const TypeInfo raspi_machine_types[] = {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
+ .is_available = target_aarch64,
.interfaces = aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
+ .is_available = target_aarch64,
.interfaces = aarch64_machine_interfaces,
}, {
.name = TYPE_RASPI_MACHINE,
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index e1595a875fe..2ad561fdcfc 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -126,6 +126,7 @@ static const TypeInfo raspi4b_machine_type = {
.parent = TYPE_RASPI_BASE_MACHINE,
.instance_size = sizeof(Raspi4bMachineState),
.class_init = raspi4b_machine_class_init,
+ .is_available = target_aarch64,
.interfaces = aarch64_machine_interfaces,
};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 38/51] system: query machines using TYPE_MACHINE
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (36 preceding siblings ...)
2026-09-03 10:39 ` [PULL 37/51] hw/arm: filter minimal set of machines Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 39/51] target-info: remove machine_typename Philippe Mathieu-Daudé
` (13 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
We drop the target_machine_typename() we introduced previously, and
revert to using TYPE_MACHINE. From there, we'll make sure only the right
types are registered at startup time.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-4-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
hw/core/machine-qmp-cmds.c | 2 +-
monitor/qemu-config-qmp.c | 2 +-
system/vl.c | 5 ++---
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c
index 1aa5f262298..543dd3201b5 100644
--- a/hw/core/machine-qmp-cmds.c
+++ b/hw/core/machine-qmp-cmds.c
@@ -99,7 +99,7 @@ MachineInfoList *qmp_query_machines(bool has_compat_props, bool compat_props,
GSList *el, *machines;
MachineInfoList *mach_list = NULL;
- machines = object_class_get_list(target_machine_typename(), false);
+ machines = object_class_get_list(TYPE_MACHINE, false);
for (el = machines; el; el = el->next) {
MachineClass *mc = el->data;
const char *default_cpu_type = machine_class_default_cpu_type(mc);
diff --git a/monitor/qemu-config-qmp.c b/monitor/qemu-config-qmp.c
index 29801023564..a680c9feca5 100644
--- a/monitor/qemu-config-qmp.c
+++ b/monitor/qemu-config-qmp.c
@@ -129,7 +129,7 @@ static CommandLineParameterInfoList *query_all_machine_properties(void)
ObjectProperty *prop;
bool is_new;
- machines = object_class_get_list(target_machine_typename(), false);
+ machines = object_class_get_list(TYPE_MACHINE, false);
assert(machines);
/* Loop over all machine classes */
diff --git a/system/vl.c b/system/vl.c
index eded498fa7e..1b22a358d23 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -1570,7 +1570,7 @@ static void machine_help_func(const QDict *qdict)
GSList *el;
const char *type = qdict_get_try_str(qdict, "type");
- machines = object_class_get_list(target_machine_typename(), false);
+ machines = object_class_get_list(TYPE_MACHINE, false);
if (type) {
ObjectClass *machine_class = OBJECT_CLASS(find_machine(type, machines));
if (machine_class) {
@@ -1682,8 +1682,7 @@ static MachineClass *select_machine(QDict *qdict, Error **errp)
{
ERRP_GUARD();
const char *machine_type = qdict_get_try_str(qdict, "type");
- g_autoptr(GSList) machines = object_class_get_list(target_machine_typename(),
- false);
+ g_autoptr(GSList) machines = object_class_get_list(TYPE_MACHINE, false);
MachineClass *machine_class = NULL;
if (machine_type) {
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 39/51] target-info: remove machine_typename
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (37 preceding siblings ...)
2026-09-03 10:39 ` [PULL 38/51] system: query machines using TYPE_MACHINE Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 40/51] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE Philippe Mathieu-Daudé
` (12 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
This field is now unused, so we can remove it.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-5-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/qemu/target-info-impl.h | 2 --
include/qemu/target-info.h | 8 --------
configs/targets/aarch64-softmmu.c | 1 -
configs/targets/arm-softmmu.c | 1 -
configs/targets/riscv32-softmmu.c | 1 -
configs/targets/riscv64-softmmu.c | 1 -
target-info-stub.c | 1 -
target-info.c | 5 -----
8 files changed, 20 deletions(-)
diff --git a/include/qemu/target-info-impl.h b/include/qemu/target-info-impl.h
index c917d546eab..cf42aabbc8b 100644
--- a/include/qemu/target-info-impl.h
+++ b/include/qemu/target-info-impl.h
@@ -21,8 +21,6 @@ typedef struct TargetInfo {
unsigned long_bits;
/* runtime equivalent of CPU_RESOLVING_TYPE definition */
const char *cpu_type;
- /* QOM typename machines for this binary must implement */
- const char *machine_typename;
/* related to TARGET_BIG_ENDIAN definition */
EndianMode endianness;
/*
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 6c5b714288e..b23e5bc5865 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -23,14 +23,6 @@ const char *target_name(void);
*/
unsigned target_long_bits(void);
-/**
- * target_machine_typename:
- *
- * Returns: Name of the QOM interface implemented by machines
- * usable on this target binary.
- */
-const char *target_machine_typename(void);
-
/**
* target_cpu_type:
*
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 75d95b0e743..2200a4f19e9 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_aarch64_system = {
.target_arch = SYS_EMU_TARGET_AARCH64,
.long_bits = 64,
.cpu_type = TYPE_ARM_CPU,
- .machine_typename = TYPE_TARGET_AARCH64_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_vary = true,
.page_bits_init = TARGET_PAGE_BITS_LEGACY,
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 73546fa5737..9d558a0c1a1 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_arm_system = {
.target_arch = SYS_EMU_TARGET_ARM,
.long_bits = 32,
.cpu_type = TYPE_ARM_CPU,
- .machine_typename = TYPE_TARGET_ARM_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_vary = true,
.page_bits_init = TARGET_PAGE_BITS_LEGACY,
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index 752c813077e..c1d94679c7e 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_riscv32_system = {
.target_arch = SYS_EMU_TARGET_RISCV32,
.long_bits = 32,
.cpu_type = TYPE_RISCV_CPU,
- .machine_typename = TYPE_TARGET_RISCV32_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
};
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index 5150f0fe9d9..f648a5c8944 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -18,7 +18,6 @@ static const TargetInfo target_info_riscv64_system = {
.target_arch = SYS_EMU_TARGET_RISCV64,
.long_bits = 64,
.cpu_type = TYPE_RISCV_CPU,
- .machine_typename = TYPE_TARGET_RISCV64_MACHINE,
.endianness = ENDIAN_MODE_LITTLE,
.page_bits_init = TARGET_PAGE_BITS,
};
diff --git a/target-info-stub.c b/target-info-stub.c
index 22b7911201c..d121b8c0170 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -29,7 +29,6 @@ static const TargetInfo target_info_stub = {
.target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),
.long_bits = TARGET_LONG_BITS,
.cpu_type = CPU_RESOLVING_TYPE,
- .machine_typename = TYPE_MACHINE,
.endianness = TARGET_BIG_ENDIAN ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITTLE,
#ifdef TARGET_PAGE_BITS_VARY
.page_bits_vary = true,
diff --git a/target-info.c b/target-info.c
index 04c69c41f8a..012b384036d 100644
--- a/target-info.c
+++ b/target-info.c
@@ -32,11 +32,6 @@ const char *target_cpu_type(void)
return target_info()->cpu_type;
}
-const char *target_machine_typename(void)
-{
- return target_info()->machine_typename;
-}
-
EndianMode target_endian_mode(void)
{
return target_info()->endianness;
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 40/51] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (38 preceding siblings ...)
2026-09-03 10:39 ` [PULL 39/51] target-info: remove machine_typename Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 41/51] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces Philippe Mathieu-Daudé
` (11 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
We don't need those types anymore.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-8-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/arm/machines-qom.h | 6 ------
hw/core/null-machine.c | 2 --
hw/nitro/machine.c | 5 -----
hw/remote/machine.c | 2 --
target-info-qom.c | 8 --------
target/arm/machine.c | 5 -----
6 files changed, 28 deletions(-)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index 3ed39384e59..81ffa434303 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -11,12 +11,6 @@
#include "hw/core/boards.h"
-#define TYPE_TARGET_ARM_MACHINE \
- "target-info-arm-machine"
-
-#define TYPE_TARGET_AARCH64_MACHINE \
- "target-info-aarch64-machine"
-
/*
* A machine filtered with arm_machine_interfaces[] or
* arm_aarch64_machine_interfaces[] will be available
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index f132a7b89b4..c1ecf3214fd 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -58,8 +58,6 @@ static void machine_none_machine_init(MachineClass *mc)
}
DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
- { TYPE_TARGET_AARCH64_MACHINE },
- { TYPE_TARGET_ARM_MACHINE },
{ TYPE_TARGET_RISCV32_MACHINE },
{ TYPE_TARGET_RISCV64_MACHINE },
{ })
diff --git a/hw/nitro/machine.c b/hw/nitro/machine.c
index 8849959359c..bb8878299bc 100644
--- a/hw/nitro/machine.c
+++ b/hw/nitro/machine.c
@@ -262,11 +262,6 @@ static const TypeInfo nitro_machine_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(NitroMachineState),
.class_init = nitro_machine_class_init,
- .interfaces = (const InterfaceInfo[]) {
- /* x86_64 and aarch64 only */
- { TYPE_TARGET_AARCH64_MACHINE },
- { }
- },
};
static void nitro_machine_register(void)
diff --git a/hw/remote/machine.c b/hw/remote/machine.c
index df08f640199..6580e0d9683 100644
--- a/hw/remote/machine.c
+++ b/hw/remote/machine.c
@@ -149,8 +149,6 @@ static const TypeInfo remote_machine = {
.class_init = remote_machine_class_init,
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
- { TYPE_TARGET_AARCH64_MACHINE },
- { TYPE_TARGET_ARM_MACHINE },
{ }
}
};
diff --git a/target-info-qom.c b/target-info-qom.c
index 7958a5cc685..eb9491338ca 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -16,14 +16,6 @@
#include "hw/riscv/machines-qom.h"
static const TypeInfo target_info_types[] = {
- {
- .name = TYPE_TARGET_ARM_MACHINE,
- .parent = TYPE_INTERFACE,
- },
- {
- .name = TYPE_TARGET_AARCH64_MACHINE,
- .parent = TYPE_INTERFACE,
- },
{
.name = TYPE_TARGET_RISCV32_MACHINE,
.parent = TYPE_INTERFACE,
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 89127e5d83c..42a1427fa16 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -1348,18 +1348,13 @@ const VMStateDescription vmstate_arm_cpu = {
};
const InterfaceInfo arm_machine_interfaces[] = {
- { TYPE_TARGET_ARM_MACHINE },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
};
const InterfaceInfo arm_aarch64_machine_interfaces[] = {
- { TYPE_TARGET_ARM_MACHINE },
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
};
const InterfaceInfo aarch64_machine_interfaces[] = {
- { TYPE_TARGET_AARCH64_MACHINE },
{ }
};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 41/51] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (39 preceding siblings ...)
2026-09-03 10:39 ` [PULL 40/51] hw/arm: remove TYPE_TARGET_{AARCH64,ARM}_MACHINE Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 42/51] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM} Philippe Mathieu-Daudé
` (10 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
We can now remove those arrays.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-9-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/arm/machines-qom.h | 16 ++--------------
hw/arm/aspeed_ast1040_evb.c | 1 -
hw/arm/aspeed_ast10x0_evb.c | 2 --
hw/arm/aspeed_ast2400_palmetto.c | 1 -
hw/arm/aspeed_ast2400_quanta-q71l.c | 1 -
hw/arm/aspeed_ast2400_supermicrox11.c | 1 -
hw/arm/aspeed_ast2500_evb.c | 1 -
hw/arm/aspeed_ast2500_g220a.c | 1 -
hw/arm/aspeed_ast2500_romulus.c | 1 -
hw/arm/aspeed_ast2500_supermicro-x11spi.c | 1 -
hw/arm/aspeed_ast2500_tiogapass.c | 1 -
hw/arm/aspeed_ast2500_witherspoon.c | 1 -
hw/arm/aspeed_ast2500_yosemitev2.c | 1 -
hw/arm/aspeed_ast2600_anacapa.c | 1 -
hw/arm/aspeed_ast2600_bletchley.c | 1 -
hw/arm/aspeed_ast2600_catalina.c | 1 -
hw/arm/aspeed_ast2600_evb.c | 1 -
hw/arm/aspeed_ast2600_fby35.c | 1 -
hw/arm/aspeed_ast2600_fuji.c | 1 -
hw/arm/aspeed_ast2600_gb200nvl.c | 1 -
hw/arm/aspeed_ast2600_rainier.c | 1 -
hw/arm/aspeed_ast27x0-fc.c | 1 -
hw/arm/aspeed_ast27x0_evb.c | 2 --
hw/arm/ax3000-boards.c | 1 -
hw/arm/b-l475e-iot01a.c | 1 -
hw/arm/bananapi_m2u.c | 2 +-
hw/arm/collie.c | 1 -
hw/arm/cubieboard.c | 2 +-
hw/arm/exynos4_boards.c | 2 --
hw/arm/imx8mm-evk.c | 2 +-
hw/arm/imx8mp-evk.c | 1 -
hw/arm/integratorcp.c | 2 +-
hw/arm/mcimx7d-sabre.c | 2 +-
hw/arm/microbit.c | 1 -
hw/arm/mps2-tz.c | 5 -----
hw/arm/mps2.c | 4 ----
hw/arm/mps3r.c | 1 -
hw/arm/musca.c | 2 --
hw/arm/npcm7xx_boards.c | 5 -----
hw/arm/npcm8xx_boards.c | 1 -
hw/arm/omap_sx1.c | 2 --
hw/arm/orangepi.c | 2 +-
hw/arm/raspi.c | 5 -----
hw/arm/raspi4b.c | 1 -
hw/arm/realview.c | 4 ----
hw/arm/sabrelite.c | 1 -
hw/arm/sbsa-ref.c | 1 -
hw/arm/stellaris.c | 2 --
hw/arm/versatilepb.c | 2 --
hw/arm/vexpress.c | 2 --
hw/arm/virt.c | 1 -
hw/arm/xen-pvh.c | 1 -
hw/arm/xilinx_zynq.c | 1 -
hw/arm/xlnx-versal-virt.c | 2 --
hw/arm/xlnx-zcu102.c | 1 -
target/arm/machine.c | 12 ------------
56 files changed, 8 insertions(+), 107 deletions(-)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index 81ffa434303..449592beda0 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -11,18 +11,6 @@
#include "hw/core/boards.h"
-/*
- * A machine filtered with arm_machine_interfaces[] or
- * arm_aarch64_machine_interfaces[] will be available
- * in both qemu-system-arm and qemu-system-aarch64 binaries.
- *
- * One filtered with aarch64_machine_interfaces[] will only
- * be available in the qemu-system-aarch64 binary.
- */
-extern const InterfaceInfo arm_machine_interfaces[];
-extern const InterfaceInfo arm_aarch64_machine_interfaces[];
-extern const InterfaceInfo aarch64_machine_interfaces[];
-
/*
* A machine defined with the DEFINE_MACHINE_ARM() macro will be
* available in both qemu-system-arm and qemu-system-aarch64 binaries.
@@ -32,9 +20,9 @@ extern const InterfaceInfo aarch64_machine_interfaces[];
*/
#define DEFINE_MACHINE_ARM(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- arm_machine_interfaces)
+ NULL)
#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- aarch64_machine_interfaces)
+ NULL)
#endif
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
index 2b93d4dfbc5..dd68f9e25c7 100644
--- a/hw/arm/aspeed_ast1040_evb.c
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -81,7 +81,6 @@ static const TypeInfo aspeed_ast1040_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast1040-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast1040_evb_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c
index c19563d1f0a..f377e955adc 100644
--- a/hw/arm/aspeed_ast10x0_evb.c
+++ b/hw/arm/aspeed_ast10x0_evb.c
@@ -119,12 +119,10 @@ static const TypeInfo aspeed_ast10x0_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast1030-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1030_evb_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("ast1060-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_minibmc_machine_ast1060_evb_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palmetto.c
index 776aa43a45d..f4918683c3d 100644
--- a/hw/arm/aspeed_ast2400_palmetto.c
+++ b/hw/arm/aspeed_ast2400_palmetto.c
@@ -73,7 +73,6 @@ static const TypeInfo aspeed_ast2400_palmetto_types[] = {
.name = MACHINE_TYPE_NAME("palmetto-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_palmetto_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_quanta-q71l.c
index 42ad2a2303f..e1ddf682315 100644
--- a/hw/arm/aspeed_ast2400_quanta-q71l.c
+++ b/hw/arm/aspeed_ast2400_quanta-q71l.c
@@ -79,7 +79,6 @@ static const TypeInfo aspeed_ast2400_quanta_q71l_types[] = {
.name = MACHINE_TYPE_NAME("quanta-q71l-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_quanta_q71l_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_supermicrox11.c
index 88cdb01fc76..86d49fd1dee 100644
--- a/hw/arm/aspeed_ast2400_supermicrox11.c
+++ b/hw/arm/aspeed_ast2400_supermicrox11.c
@@ -74,7 +74,6 @@ static const TypeInfo aspeed_ast2400_supermicrox11_types[] = {
.name = MACHINE_TYPE_NAME("supermicrox11-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicrox11_bmc_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_evb.c b/hw/arm/aspeed_ast2500_evb.c
index 8b5cb67be9b..5f616252e0b 100644
--- a/hw/arm/aspeed_ast2500_evb.c
+++ b/hw/arm/aspeed_ast2500_evb.c
@@ -60,7 +60,6 @@ static const TypeInfo aspeed_ast2500_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast2500-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2500_evb_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_g220a.c b/hw/arm/aspeed_ast2500_g220a.c
index 3f979a78e57..3c654c62dd6 100644
--- a/hw/arm/aspeed_ast2500_g220a.c
+++ b/hw/arm/aspeed_ast2500_g220a.c
@@ -85,7 +85,6 @@ static const TypeInfo aspeed_ast2500_g220a_types[] = {
.name = MACHINE_TYPE_NAME("g220a-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_g220a_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulus.c
index 91b660e74bb..b2ed623f680 100644
--- a/hw/arm/aspeed_ast2500_romulus.c
+++ b/hw/arm/aspeed_ast2500_romulus.c
@@ -55,7 +55,6 @@ static const TypeInfo aspeed_ast2500_romulus_types[] = {
.name = MACHINE_TYPE_NAME("romulus-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_romulus_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
index a2450aa9623..77fa028b096 100644
--- a/hw/arm/aspeed_ast2500_supermicro-x11spi.c
+++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
@@ -70,7 +70,6 @@ static const TypeInfo aspeed_ast2500_supermicro_x11spi_types[] = {
.name = MACHINE_TYPE_NAME("supermicro-x11spi-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_supermicro_x11spi_bmc_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_tiogapass.c b/hw/arm/aspeed_ast2500_tiogapass.c
index 186dbc1da30..1771f376480 100644
--- a/hw/arm/aspeed_ast2500_tiogapass.c
+++ b/hw/arm/aspeed_ast2500_tiogapass.c
@@ -83,7 +83,6 @@ static const TypeInfo aspeed_ast2500_tiogapass_types[] = {
.name = MACHINE_TYPE_NAME("tiogapass-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_tiogapass_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_witherspoon.c
index 28d437fec08..4cc349c3236 100644
--- a/hw/arm/aspeed_ast2500_witherspoon.c
+++ b/hw/arm/aspeed_ast2500_witherspoon.c
@@ -105,7 +105,6 @@ static const TypeInfo aspeed_ast2500_witherspoon_types[] = {
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_witherspoon_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2500_yosemitev2.c b/hw/arm/aspeed_ast2500_yosemitev2.c
index eaa75bcccbb..48c813f3c8f 100644
--- a/hw/arm/aspeed_ast2500_yosemitev2.c
+++ b/hw/arm/aspeed_ast2500_yosemitev2.c
@@ -84,7 +84,6 @@ static const TypeInfo aspeed_ast2500_yosemitev2_types[] = {
.name = MACHINE_TYPE_NAME("yosemitev2-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_yosemitev2_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
index 65d6b0faa2d..e82f5c98f26 100644
--- a/hw/arm/aspeed_ast2600_anacapa.c
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -368,7 +368,6 @@ static const TypeInfo aspeed_ast2600_anacapa_types[] = {
.name = MACHINE_TYPE_NAME("anacapa-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_anacapa_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_bletchley.c
index b7e84db1438..9dda83ad4c0 100644
--- a/hw/arm/aspeed_ast2600_bletchley.c
+++ b/hw/arm/aspeed_ast2600_bletchley.c
@@ -90,7 +90,6 @@ static const TypeInfo aspeed_ast2600_bletchley_types[] = {
.name = MACHINE_TYPE_NAME("bletchley-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_bletchley_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catalina.c
index f714c9d1b32..f91e0635908 100644
--- a/hw/arm/aspeed_ast2600_catalina.c
+++ b/hw/arm/aspeed_ast2600_catalina.c
@@ -675,7 +675,6 @@ static const TypeInfo aspeed_ast2600_catalina_types[] = {
.name = MACHINE_TYPE_NAME("catalina-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_catalina_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_evb.c b/hw/arm/aspeed_ast2600_evb.c
index c43d2687c1c..404083b61dc 100644
--- a/hw/arm/aspeed_ast2600_evb.c
+++ b/hw/arm/aspeed_ast2600_evb.c
@@ -58,7 +58,6 @@ static const TypeInfo aspeed_ast2600_evb_types[] = {
.name = MACHINE_TYPE_NAME("ast2600-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2600_evb_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_fby35.c b/hw/arm/aspeed_ast2600_fby35.c
index f6244270704..6bcda0ac630 100644
--- a/hw/arm/aspeed_ast2600_fby35.c
+++ b/hw/arm/aspeed_ast2600_fby35.c
@@ -171,7 +171,6 @@ static const TypeInfo aspeed_ast2600_fby35_types[] = {
.name = MACHINE_TYPE_NAME("fby35-bmc"),
.parent = MACHINE_TYPE_NAME("ast2600-evb"),
.class_init = aspeed_machine_fby35_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_fuji.c b/hw/arm/aspeed_ast2600_fuji.c
index 37db252e276..cf49149fe9a 100644
--- a/hw/arm/aspeed_ast2600_fuji.c
+++ b/hw/arm/aspeed_ast2600_fuji.c
@@ -133,7 +133,6 @@ static const TypeInfo aspeed_ast2600_fuji_types[] = {
.name = MACHINE_TYPE_NAME("fuji-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_fuji_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200nvl.c
index ad9a10110b8..705561afe39 100644
--- a/hw/arm/aspeed_ast2600_gb200nvl.c
+++ b/hw/arm/aspeed_ast2600_gb200nvl.c
@@ -104,7 +104,6 @@ static const TypeInfo aspeed_ast2600_gb200nvl_types[] = {
.name = MACHINE_TYPE_NAME("gb200nvl-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_gb200nvl_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast2600_rainier.c b/hw/arm/aspeed_ast2600_rainier.c
index 8f0a412ddcf..6e5debc8bc1 100644
--- a/hw/arm/aspeed_ast2600_rainier.c
+++ b/hw/arm/aspeed_ast2600_rainier.c
@@ -191,7 +191,6 @@ static const TypeInfo aspeed_ast2600_rainier_types[] = {
.name = MACHINE_TYPE_NAME("rainier-bmc"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_rainier_class_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index 54230aa92e6..ccfa4ade265 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -236,7 +236,6 @@ static const TypeInfo ast2700fc_types[] = {
.class_init = ast2700fc_class_init,
.instance_size = sizeof(Ast2700FCState),
.is_available = target_aarch64,
- .interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index 2b767808e12..0deb3127c21 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -77,14 +77,12 @@ static const TypeInfo aspeed_ast27x0_evb_types[] = {
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a1_evb_class_init,
.is_available = target_aarch64,
- .interfaces = aarch64_machine_interfaces,
},
{
.name = MACHINE_TYPE_NAME("ast2700a2-evb"),
.parent = TYPE_ASPEED_MACHINE,
.class_init = aspeed_machine_ast2700a2_evb_class_init,
.is_available = target_aarch64,
- .interfaces = aarch64_machine_interfaces,
}
};
diff --git a/hw/arm/ax3000-boards.c b/hw/arm/ax3000-boards.c
index 4b8deec15cf..c7248f9f52b 100644
--- a/hw/arm/ax3000-boards.c
+++ b/hw/arm/ax3000-boards.c
@@ -48,7 +48,6 @@ static const TypeInfo ax3000_machine_types[] = {
.instance_size = sizeof(Ax3000MachineState),
.class_size = sizeof(Ax3000MachineClass),
.class_init = ax3000_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
.abstract = true,
}
};
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index ee789c8df94..04dce2d19ce 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -132,7 +132,6 @@ static const TypeInfo bl475e_machine_type[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(Bl475eMachineState),
.class_init = bl475e_machine_init,
- .interfaces = arm_machine_interfaces,
}
};
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index 0079aa1dd2b..15c878d1636 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -154,4 +154,4 @@ static void bpim2u_machine_init(MachineClass *mc)
}
DEFINE_MACHINE_EXTENDED("bpim2u", MACHINE, Bpim2uMachineState,
- bpim2u_machine_init, false, arm_machine_interfaces)
+ bpim2u_machine_init, false, NULL)
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 01d74ad38cd..4b930e6ba12 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -85,7 +85,6 @@ static const TypeInfo collie_machine_typeinfo = {
.parent = TYPE_MACHINE,
.class_init = collie_machine_class_init,
.instance_size = sizeof(CollieMachineState),
- .interfaces = arm_machine_interfaces,
};
static void collie_machine_register_types(void)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index d59c1ebba7f..511b71fbd7e 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -135,4 +135,4 @@ static void cubieboard_machine_init(MachineClass *mc)
DEFINE_MACHINE_EXTENDED("cubieboard", MACHINE, CubieboardMachineState,
cubieboard_machine_init, false,
- arm_machine_interfaces)
+ NULL)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index b7decdb2c7f..62f7cbe875e 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -169,7 +169,6 @@ static const TypeInfo nuri_type = {
.name = MACHINE_TYPE_NAME("nuri"),
.parent = TYPE_MACHINE,
.class_init = nuri_class_init,
- .interfaces = arm_machine_interfaces,
};
static void smdkc210_class_init(ObjectClass *oc, const void *data)
@@ -190,7 +189,6 @@ static const TypeInfo smdkc210_type = {
.name = MACHINE_TYPE_NAME("smdkc210"),
.parent = TYPE_MACHINE,
.class_init = smdkc210_class_init,
- .interfaces = arm_machine_interfaces,
};
static void exynos4_machines_init(void)
diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c
index 019c609c542..ffe8e494a57 100644
--- a/hw/arm/imx8mm-evk.c
+++ b/hw/arm/imx8mm-evk.c
@@ -136,4 +136,4 @@ static void imx8mm_evk_machine_init(MachineClass *mc)
DEFINE_MACHINE_EXTENDED("imx8mm-evk", MACHINE, Imx8mmEvkMachineState,
imx8mm_evk_machine_init, false,
- aarch64_machine_interfaces)
+ NULL)
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index 16e9722d146..389e7c86d21 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -162,7 +162,6 @@ static const TypeInfo imx8mp_evk_machine_types[] = {
.class_init = imx8mp_evk_machine_class_init,
.instance_init = imx8mp_evk_machine_init,
.instance_size = sizeof(FslImx8mpEvkState),
- .interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index f8bcf42c615..25ecd931e76 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -706,7 +706,7 @@ static void integratorcp_machine_init(MachineClass *mc)
DEFINE_MACHINE_EXTENDED("integratorcp", MACHINE, IntegratorcpMachineState,
integratorcp_machine_init, false,
- arm_machine_interfaces)
+ NULL)
static const Property core_properties[] = {
DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0),
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index 22fe1fa932f..cb4536faadd 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -88,4 +88,4 @@ static void mcimx7d_sabre_machine_init(MachineClass *mc)
DEFINE_MACHINE_EXTENDED("mcimx7d-sabre", MACHINE, Mcimx7dSabreMachineState,
mcimx7d_sabre_machine_init, false,
- arm_machine_interfaces)
+ NULL)
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 9d5c4898469..85285861c5f 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -75,7 +75,6 @@ static const TypeInfo microbit_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(MicrobitMachineState),
.class_init = microbit_machine_class_init,
- .interfaces = arm_machine_interfaces,
};
static void microbit_machine_init(void)
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 41dfb185353..3a384d3cdb9 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -1631,35 +1631,30 @@ static const TypeInfo mps2tz_an505_info = {
.name = TYPE_MPS2TZ_AN505_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an505_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps2tz_an521_info = {
.name = TYPE_MPS2TZ_AN521_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps2tz_an521_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps3tz_an524_info = {
.name = TYPE_MPS3TZ_AN524_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an524_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps3tz_an547_info = {
.name = TYPE_MPS3TZ_AN547_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an547_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps3tz_an555_info = {
.name = TYPE_MPS3TZ_AN555_MACHINE,
.parent = TYPE_MPS2TZ_MACHINE,
.class_init = mps3tz_an555_class_init,
- .interfaces = arm_machine_interfaces,
};
static void mps2tz_machine_init(void)
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index ac9366d8447..b13b7bc55ec 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -568,28 +568,24 @@ static const TypeInfo mps2_an385_info = {
.name = TYPE_MPS2_AN385_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an385_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps2_an386_info = {
.name = TYPE_MPS2_AN386_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an386_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps2_an500_info = {
.name = TYPE_MPS2_AN500_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an500_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo mps2_an511_info = {
.name = TYPE_MPS2_AN511_MACHINE,
.parent = TYPE_MPS2_MACHINE,
.class_init = mps2_an511_class_init,
- .interfaces = arm_machine_interfaces,
};
static void mps2_machine_init(void)
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index caad820d3bc..d6f4c1640ab 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -635,7 +635,6 @@ static const TypeInfo mps3r_machine_types[] = {
.name = TYPE_MPS3R_AN536_MACHINE,
.parent = TYPE_MPS3R_MACHINE,
.class_init = mps3r_an536_class_init,
- .interfaces = arm_machine_interfaces,
},
};
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 75d82eebcac..1b161487e7e 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -658,14 +658,12 @@ static const TypeInfo musca_a_info = {
.name = TYPE_MUSCA_A_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_a_class_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo musca_b1_info = {
.name = TYPE_MUSCA_B1_MACHINE,
.parent = TYPE_MUSCA_MACHINE,
.class_init = musca_b1_class_init,
- .interfaces = arm_machine_interfaces,
};
static void musca_machine_init(void)
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 4f14d257465..025de42dac6 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -550,27 +550,22 @@ static const TypeInfo npcm7xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm750-evb"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = npcm750_evb_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-gsj"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gsj_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("quanta-gbs-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = gbs_bmc_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("kudo-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = kudo_bmc_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("mori-bmc"),
.parent = TYPE_NPCM7XX_MACHINE,
.class_init = mori_bmc_machine_class_init,
- .interfaces = arm_machine_interfaces,
},
};
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index f462369bea3..2a04cf4f2c9 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -249,7 +249,6 @@ static const TypeInfo npcm8xx_machine_types[] = {
.name = MACHINE_TYPE_NAME("npcm845-evb"),
.parent = TYPE_NPCM8XX_MACHINE,
.class_init = npcm845_evb_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
},
};
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index 3b628d13cbc..c3fe4187b8b 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -226,7 +226,6 @@ static const TypeInfo sx1_machine_v2_type = {
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v2_class_init,
.instance_size = sizeof(Sx1MachineState),
- .interfaces = arm_machine_interfaces,
};
static void sx1_machine_v1_class_init(ObjectClass *oc, const void *data)
@@ -247,7 +246,6 @@ static const TypeInfo sx1_machine_v1_type = {
.parent = TYPE_MACHINE,
.class_init = sx1_machine_v1_class_init,
.instance_size = sizeof(Sx1MachineState),
- .interfaces = arm_machine_interfaces,
};
static void sx1_machine_init(void)
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 0e149ed6c98..3f06716c364 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -135,4 +135,4 @@ static void orangepi_machine_init(MachineClass *mc)
DEFINE_MACHINE_EXTENDED("orangepi-pc", MACHINE, OrangePiMachineState,
orangepi_machine_init, false,
- arm_machine_interfaces)
+ NULL)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index bbaa20bd630..7ff3e8400e6 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -392,29 +392,24 @@ static const TypeInfo raspi_machine_types[] = {
.name = MACHINE_TYPE_NAME("raspi0"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi0_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi1ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi1ap_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi2b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi2b_machine_class_init,
- .interfaces = arm_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi3ap"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3ap_machine_class_init,
.is_available = target_aarch64,
- .interfaces = aarch64_machine_interfaces,
}, {
.name = MACHINE_TYPE_NAME("raspi3b"),
.parent = TYPE_RASPI_MACHINE,
.class_init = raspi3b_machine_class_init,
.is_available = target_aarch64,
- .interfaces = aarch64_machine_interfaces,
}, {
.name = TYPE_RASPI_MACHINE,
.parent = TYPE_RASPI_BASE_MACHINE,
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 2ad561fdcfc..08fcdf58c9f 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -127,7 +127,6 @@ static const TypeInfo raspi4b_machine_type = {
.instance_size = sizeof(Raspi4bMachineState),
.class_init = raspi4b_machine_class_init,
.is_available = target_aarch64,
- .interfaces = aarch64_machine_interfaces,
};
static void raspi4b_machine_register_type(void)
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index 0c2daf5c01f..aee7d05c3e6 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -437,7 +437,6 @@ static const TypeInfo realview_eb_type = {
.parent = TYPE_MACHINE,
.class_init = realview_eb_class_init,
.instance_size = sizeof(RealViewMachineState),
- .interfaces = arm_machine_interfaces,
};
static void realview_eb_mpcore_class_init(ObjectClass *oc, const void *data)
@@ -460,7 +459,6 @@ static const TypeInfo realview_eb_mpcore_type = {
.parent = TYPE_MACHINE,
.class_init = realview_eb_mpcore_class_init,
.instance_size = sizeof(RealViewMachineState),
- .interfaces = arm_machine_interfaces,
};
static void realview_pb_a8_class_init(ObjectClass *oc, const void *data)
@@ -481,7 +479,6 @@ static const TypeInfo realview_pb_a8_type = {
.parent = TYPE_MACHINE,
.class_init = realview_pb_a8_class_init,
.instance_size = sizeof(RealViewMachineState),
- .interfaces = arm_machine_interfaces,
};
static void realview_pbx_a9_class_init(ObjectClass *oc, const void *data)
@@ -503,7 +500,6 @@ static const TypeInfo realview_pbx_a9_type = {
.parent = TYPE_MACHINE,
.class_init = realview_pbx_a9_class_init,
.instance_size = sizeof(RealViewMachineState),
- .interfaces = arm_machine_interfaces,
};
static void realview_machine_init(void)
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index 140b2ecb9e2..ec307388f45 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -152,7 +152,6 @@ static const TypeInfo sabrelite_machine_init_typeinfo = {
.instance_init = sabrelite_machine_instance_init,
.instance_size = sizeof(SabreliteMachineState),
.abstract = false,
- .interfaces = arm_machine_interfaces,
};
static void sabrelite_machine_init_register_types(void)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 56d08f605c8..6ba353341a1 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -946,7 +946,6 @@ static const TypeInfo sbsa_ref_info = {
.instance_finalize = sbsa_ref_instance_finalize,
.class_init = sbsa_ref_class_init,
.instance_size = sizeof(SBSAMachineState),
- .interfaces = aarch64_machine_interfaces,
};
static void sbsa_ref_machine_init(void)
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index 56ecc828f4f..f634918868b 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -1428,7 +1428,6 @@ static const TypeInfo lm3s811evb_type = {
.name = MACHINE_TYPE_NAME("lm3s811evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s811evb_class_init,
- .interfaces = arm_machine_interfaces,
};
/*
@@ -1450,7 +1449,6 @@ static const TypeInfo lm3s6965evb_type = {
.name = MACHINE_TYPE_NAME("lm3s6965evb"),
.parent = TYPE_MACHINE,
.class_init = lm3s6965evb_class_init,
- .interfaces = arm_machine_interfaces,
};
static void stellaris_machine_init(void)
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 520af79c800..1db9bc1eb24 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -438,7 +438,6 @@ static const TypeInfo versatilepb_type = {
.parent = TYPE_MACHINE,
.class_init = versatilepb_class_init,
.instance_size = sizeof(VersatileMachineState),
- .interfaces = arm_machine_interfaces,
};
static void versatileab_class_init(ObjectClass *oc, const void *data)
@@ -461,7 +460,6 @@ static const TypeInfo versatileab_type = {
.parent = TYPE_MACHINE,
.class_init = versatileab_class_init,
.instance_size = sizeof(VersatileMachineState),
- .interfaces = arm_machine_interfaces,
};
static void versatile_machine_init(void)
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index f26d8c6f8d1..1e29fe0f09c 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -850,7 +850,6 @@ static const TypeInfo vexpress_a9_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a9_class_init,
.instance_init = vexpress_a9_instance_init,
- .interfaces = arm_machine_interfaces,
};
static const TypeInfo vexpress_a15_info = {
@@ -858,7 +857,6 @@ static const TypeInfo vexpress_a15_info = {
.parent = TYPE_VEXPRESS_MACHINE,
.class_init = vexpress_a15_class_init,
.instance_init = vexpress_a15_instance_init,
- .interfaces = arm_machine_interfaces,
};
static void vexpress_machine_init(void)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index d738b95c726..eae4f0fe413 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -133,7 +133,6 @@ static void arm_virt_compat_default_set(MachineClass *mc)
.name = MACHINE_VER_TYPE_NAME("virt", __VA_ARGS__), \
.parent = TYPE_VIRT_MACHINE, \
.class_init = MACHINE_VER_SYM(class_init, virt, __VA_ARGS__), \
- .interfaces = arm_aarch64_machine_interfaces, \
}; \
static void MACHINE_VER_SYM(register, virt, __VA_ARGS__)(void) \
{ \
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index 10cac28a910..b47dd9efd81 100644
--- a/hw/arm/xen-pvh.c
+++ b/hw/arm/xen-pvh.c
@@ -96,7 +96,6 @@ static const TypeInfo xen_arm_machine_type = {
.class_init = xen_arm_machine_class_init,
.instance_size = sizeof(XenPVHMachineState),
.instance_init = xen_arm_instance_init,
- .interfaces = arm_aarch64_machine_interfaces,
};
static void xen_arm_machine_register_types(void)
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index f3148975406..8ebd8e5ccd5 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -479,7 +479,6 @@ static const TypeInfo zynq_machine_type = {
.parent = TYPE_MACHINE,
.class_init = zynq_machine_class_init,
.instance_size = sizeof(ZynqMachineState),
- .interfaces = arm_machine_interfaces,
};
static void zynq_machine_register_types(void)
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index 2b04513ba2e..e06a0c55549 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -402,14 +402,12 @@ static const TypeInfo versal_virt_machine_init_typeinfo = {
.name = TYPE_XLNX_VERSAL_VIRT_MACHINE,
.parent = TYPE_XLNX_VERSAL_VIRT_BASE_MACHINE,
.class_init = versal_virt_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
};
static const TypeInfo versal2_virt_machine_init_typeinfo = {
.name = TYPE_XLNX_VERSAL2_VIRT_MACHINE,
.parent = TYPE_XLNX_VERSAL_VIRT_BASE_MACHINE,
.class_init = versal2_virt_machine_class_init,
- .interfaces = aarch64_machine_interfaces,
};
static void versal_virt_machine_init_register_types(void)
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index 4e489702743..da8b3ede873 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -303,7 +303,6 @@ static const TypeInfo xlnx_zcu102_machine_init_typeinfo = {
.class_init = xlnx_zcu102_machine_class_init,
.instance_init = xlnx_zcu102_machine_instance_init,
.instance_size = sizeof(XlnxZCU102),
- .interfaces = aarch64_machine_interfaces,
};
static void xlnx_zcu102_machine_init_register_types(void)
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 42a1427fa16..61106f9def6 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -1346,15 +1346,3 @@ const VMStateDescription vmstate_arm_cpu = {
NULL
}
};
-
-const InterfaceInfo arm_machine_interfaces[] = {
- { }
-};
-
-const InterfaceInfo arm_aarch64_machine_interfaces[] = {
- { }
-};
-
-const InterfaceInfo aarch64_machine_interfaces[] = {
- { }
-};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 42/51] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM}
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (40 preceding siblings ...)
2026-09-03 10:39 ` [PULL 41/51] hw/arm: remove {arm, arm_aarch64, aarch64}_machine_interfaces Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 43/51] hw/arm: remove machines-qom.h Philippe Mathieu-Daudé
` (9 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-10-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/arm/machines-qom.h | 14 --------------
hw/arm/digic_boards.c | 2 +-
hw/arm/imx25_pdk.c | 2 +-
hw/arm/kzm.c | 2 +-
hw/arm/max78000fthr.c | 2 +-
hw/arm/mcimx6ul-evk.c | 2 +-
hw/arm/msf2-som.c | 2 +-
hw/arm/netduino2.c | 2 +-
hw/arm/netduinoplus2.c | 2 +-
hw/arm/olimex-stm32-h405.c | 2 +-
hw/arm/stm32vldiscovery.c | 2 +-
11 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
index 449592beda0..e3eebbdefbc 100644
--- a/include/hw/arm/machines-qom.h
+++ b/include/hw/arm/machines-qom.h
@@ -11,18 +11,4 @@
#include "hw/core/boards.h"
-/*
- * A machine defined with the DEFINE_MACHINE_ARM() macro will be
- * available in both qemu-system-arm and qemu-system-aarch64 binaries.
- *
- * One defined with DEFINE_MACHINE_AARCH64() will only be available in
- * the qemu-system-aarch64 binary.
- */
-#define DEFINE_MACHINE_ARM(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- NULL)
-#define DEFINE_MACHINE_AARCH64(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- NULL)
-
#endif
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index ed12f542001..c7ecf22a958 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -146,4 +146,4 @@ static void canon_a1100_machine_init(MachineClass *mc)
mc->default_ram_id = "ram";
}
-DEFINE_MACHINE_ARM("canon-a1100", canon_a1100_machine_init)
+DEFINE_MACHINE("canon-a1100", canon_a1100_machine_init)
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index f7a51481af0..3246512c214 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -150,4 +150,4 @@ static void imx25_pdk_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("imx25-pdk", imx25_pdk_machine_init)
+DEFINE_MACHINE("imx25-pdk", imx25_pdk_machine_init)
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 1aa5b49de92..909dd929e63 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -138,4 +138,4 @@ static void kzm_machine_init(MachineClass *mc)
mc->default_ram_id = "kzm.ram";
}
-DEFINE_MACHINE_ARM("kzm", kzm_machine_init)
+DEFINE_MACHINE("kzm", kzm_machine_init)
diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c
index 530ca9dd964..290a14c8ad9 100644
--- a/hw/arm/max78000fthr.c
+++ b/hw/arm/max78000fthr.c
@@ -48,4 +48,4 @@ static void max78000_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("max78000fthr", max78000_machine_init)
+DEFINE_MACHINE("max78000fthr", max78000_machine_init)
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index 6e9d92b1f1d..a3dafb20131 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -78,4 +78,4 @@ static void mcimx6ul_evk_machine_init(MachineClass *mc)
mc->auto_create_sdcard = true;
}
-DEFINE_MACHINE_ARM("mcimx6ul-evk", mcimx6ul_evk_machine_init)
+DEFINE_MACHINE("mcimx6ul-evk", mcimx6ul_evk_machine_init)
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 1ada1a13613..8d00fef43b0 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -109,4 +109,4 @@ static void emcraft_sf2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("emcraft-sf2", emcraft_sf2_machine_init)
+DEFINE_MACHINE("emcraft-sf2", emcraft_sf2_machine_init)
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index c32deaf43ba..6a639264d61 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -66,4 +66,4 @@ static void netduino2_machine_init(MachineClass *mc)
mc->ignore_memory_transaction_failures = true;
}
-DEFINE_MACHINE_ARM("netduino2", netduino2_machine_init)
+DEFINE_MACHINE("netduino2", netduino2_machine_init)
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index a90dcbe8c26..d04ab8aeea4 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -66,4 +66,4 @@ static void netduinoplus2_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("netduinoplus2", netduinoplus2_machine_init)
+DEFINE_MACHINE("netduinoplus2", netduinoplus2_machine_init)
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index e801e4308ed..154501fc3c7 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -72,4 +72,4 @@ static void olimex_stm32_h405_machine_init(MachineClass *mc)
mc->default_ram_size = 0;
}
-DEFINE_MACHINE_ARM("olimex-stm32-h405", olimex_stm32_h405_machine_init)
+DEFINE_MACHINE("olimex-stm32-h405", olimex_stm32_h405_machine_init)
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 8f93c0036a3..0b39543c1ff 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -69,4 +69,4 @@ static void stm32vldiscovery_machine_init(MachineClass *mc)
mc->valid_cpu_types = valid_cpu_types;
}
-DEFINE_MACHINE_ARM("stm32vldiscovery", stm32vldiscovery_machine_init)
+DEFINE_MACHINE("stm32vldiscovery", stm32vldiscovery_machine_init)
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 43/51] hw/arm: remove machines-qom.h
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (41 preceding siblings ...)
2026-09-03 10:39 ` [PULL 42/51] hw/arm: remove DEFINE_MACHINE_{AARCH64,ARM} Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 44/51] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE Philippe Mathieu-Daudé
` (8 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Header is now empty so we can remove it.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-11-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/arm/machines-qom.h | 14 --------------
configs/targets/aarch64-softmmu.c | 1 -
configs/targets/arm-softmmu.c | 1 -
hw/arm/aspeed.c | 1 -
hw/arm/aspeed_ast1040_evb.c | 1 -
hw/arm/aspeed_ast10x0_evb.c | 1 -
hw/arm/aspeed_ast2400_palmetto.c | 1 -
hw/arm/aspeed_ast2400_quanta-q71l.c | 1 -
hw/arm/aspeed_ast2400_supermicrox11.c | 1 -
hw/arm/aspeed_ast2500_evb.c | 1 -
hw/arm/aspeed_ast2500_g220a.c | 1 -
hw/arm/aspeed_ast2500_romulus.c | 1 -
hw/arm/aspeed_ast2500_supermicro-x11spi.c | 1 -
hw/arm/aspeed_ast2500_tiogapass.c | 1 -
hw/arm/aspeed_ast2500_witherspoon.c | 1 -
hw/arm/aspeed_ast2500_yosemitev2.c | 1 -
hw/arm/aspeed_ast2600_anacapa.c | 1 -
hw/arm/aspeed_ast2600_bletchley.c | 1 -
hw/arm/aspeed_ast2600_catalina.c | 1 -
hw/arm/aspeed_ast2600_evb.c | 1 -
hw/arm/aspeed_ast2600_fby35.c | 1 -
hw/arm/aspeed_ast2600_fuji.c | 1 -
hw/arm/aspeed_ast2600_gb200nvl.c | 1 -
hw/arm/aspeed_ast2600_rainier.c | 1 -
hw/arm/aspeed_ast27x0-fc.c | 1 -
hw/arm/aspeed_ast27x0_evb.c | 1 -
hw/arm/ax3000-boards.c | 1 -
hw/arm/b-l475e-iot01a.c | 1 -
hw/arm/bananapi_m2u.c | 1 -
hw/arm/collie.c | 1 -
hw/arm/cubieboard.c | 1 -
hw/arm/digic_boards.c | 1 -
hw/arm/exynos4_boards.c | 1 -
hw/arm/imx25_pdk.c | 1 -
hw/arm/imx8mm-evk.c | 1 -
hw/arm/imx8mp-evk.c | 1 -
hw/arm/integratorcp.c | 1 -
hw/arm/kzm.c | 1 -
hw/arm/max78000fthr.c | 1 -
hw/arm/mcimx6ul-evk.c | 1 -
hw/arm/mcimx7d-sabre.c | 1 -
hw/arm/microbit.c | 1 -
hw/arm/mps2-tz.c | 1 -
hw/arm/mps2.c | 1 -
hw/arm/mps3r.c | 1 -
hw/arm/msf2-som.c | 1 -
hw/arm/musca.c | 1 -
hw/arm/netduino2.c | 1 -
hw/arm/netduinoplus2.c | 1 -
hw/arm/npcm7xx_boards.c | 1 -
hw/arm/npcm8xx_boards.c | 1 -
hw/arm/olimex-stm32-h405.c | 1 -
hw/arm/omap_sx1.c | 1 -
hw/arm/orangepi.c | 1 -
hw/arm/raspi.c | 1 -
hw/arm/raspi4b.c | 1 -
hw/arm/realview.c | 1 -
hw/arm/sabrelite.c | 1 -
hw/arm/sbsa-ref.c | 1 -
hw/arm/stellaris.c | 1 -
hw/arm/stm32vldiscovery.c | 1 -
hw/arm/versatilepb.c | 1 -
hw/arm/vexpress.c | 1 -
hw/arm/virt.c | 1 -
hw/arm/xen-pvh.c | 1 -
hw/arm/xilinx_zynq.c | 1 -
hw/arm/xlnx-versal-virt.c | 1 -
hw/arm/xlnx-zcu102.c | 1 -
hw/core/null-machine.c | 1 -
hw/nitro/machine.c | 1 -
hw/remote/machine.c | 1 -
target-info-qom.c | 1 -
target/arm/machine.c | 1 -
73 files changed, 86 deletions(-)
delete mode 100644 include/hw/arm/machines-qom.h
diff --git a/include/hw/arm/machines-qom.h b/include/hw/arm/machines-qom.h
deleted file mode 100644
index e3eebbdefbc..00000000000
--- a/include/hw/arm/machines-qom.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * QOM type definitions for ARM / Aarch64 machines
- *
- * Copyright (c) Linaro
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_ARM_MACHINES_QOM_H
-#define HW_ARM_MACHINES_QOM_H
-
-#include "hw/core/boards.h"
-
-#endif
diff --git a/configs/targets/aarch64-softmmu.c b/configs/targets/aarch64-softmmu.c
index 2200a4f19e9..fdebdcc3582 100644
--- a/configs/targets/aarch64-softmmu.c
+++ b/configs/targets/aarch64-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/arm/machines-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/cpu-param.h"
diff --git a/configs/targets/arm-softmmu.c b/configs/targets/arm-softmmu.c
index 9d558a0c1a1..2b98f65a0f8 100644
--- a/configs/targets/arm-softmmu.c
+++ b/configs/targets/arm-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/arm/machines-qom.h"
#include "target/arm/cpu-qom.h"
#include "target/arm/cpu-param.h"
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index 8fa16b3831c..a7cfbd6c5e0 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -14,7 +14,6 @@
#include "hw/arm/boot.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/gpio/pca9552.h"
#include "hw/gpio/pca9554.h"
diff --git a/hw/arm/aspeed_ast1040_evb.c b/hw/arm/aspeed_ast1040_evb.c
index dd68f9e25c7..486f0f6a1ba 100644
--- a/hw/arm/aspeed_ast1040_evb.c
+++ b/hw/arm/aspeed_ast1040_evb.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/core/qdev-clock.h"
diff --git a/hw/arm/aspeed_ast10x0_evb.c b/hw/arm/aspeed_ast10x0_evb.c
index f377e955adc..c937bb74665 100644
--- a/hw/arm/aspeed_ast10x0_evb.c
+++ b/hw/arm/aspeed_ast10x0_evb.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/core/qdev-clock.h"
diff --git a/hw/arm/aspeed_ast2400_palmetto.c b/hw/arm/aspeed_ast2400_palmetto.c
index f4918683c3d..e2350e5b6ca 100644
--- a/hw/arm/aspeed_ast2400_palmetto.c
+++ b/hw/arm/aspeed_ast2400_palmetto.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2400_quanta-q71l.c b/hw/arm/aspeed_ast2400_quanta-q71l.c
index e1ddf682315..e8cbbb8a052 100644
--- a/hw/arm/aspeed_ast2400_quanta-q71l.c
+++ b/hw/arm/aspeed_ast2400_quanta-q71l.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
diff --git a/hw/arm/aspeed_ast2400_supermicrox11.c b/hw/arm/aspeed_ast2400_supermicrox11.c
index 86d49fd1dee..c75898cc6d1 100644
--- a/hw/arm/aspeed_ast2400_supermicrox11.c
+++ b/hw/arm/aspeed_ast2400_supermicrox11.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_evb.c b/hw/arm/aspeed_ast2500_evb.c
index 5f616252e0b..6ca2a36322c 100644
--- a/hw/arm/aspeed_ast2500_evb.c
+++ b/hw/arm/aspeed_ast2500_evb.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_g220a.c b/hw/arm/aspeed_ast2500_g220a.c
index 3c654c62dd6..00bb1c61053 100644
--- a/hw/arm/aspeed_ast2500_g220a.c
+++ b/hw/arm/aspeed_ast2500_g220a.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_romulus.c b/hw/arm/aspeed_ast2500_romulus.c
index b2ed623f680..340a74408b6 100644
--- a/hw/arm/aspeed_ast2500_romulus.c
+++ b/hw/arm/aspeed_ast2500_romulus.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
diff --git a/hw/arm/aspeed_ast2500_supermicro-x11spi.c b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
index 77fa028b096..5a7e49d6ccd 100644
--- a/hw/arm/aspeed_ast2500_supermicro-x11spi.c
+++ b/hw/arm/aspeed_ast2500_supermicro-x11spi.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2500_tiogapass.c b/hw/arm/aspeed_ast2500_tiogapass.c
index 1771f376480..6cb567526c4 100644
--- a/hw/arm/aspeed_ast2500_tiogapass.c
+++ b/hw/arm/aspeed_ast2500_tiogapass.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2500_witherspoon.c b/hw/arm/aspeed_ast2500_witherspoon.c
index 4cc349c3236..26ddb673470 100644
--- a/hw/arm/aspeed_ast2500_witherspoon.c
+++ b/hw/arm/aspeed_ast2500_witherspoon.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/misc/led.h"
diff --git a/hw/arm/aspeed_ast2500_yosemitev2.c b/hw/arm/aspeed_ast2500_yosemitev2.c
index 48c813f3c8f..3ba1ed5f6fa 100644
--- a/hw/arm/aspeed_ast2500_yosemitev2.c
+++ b/hw/arm/aspeed_ast2500_yosemitev2.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2600_anacapa.c b/hw/arm/aspeed_ast2600_anacapa.c
index e82f5c98f26..697be58b0e4 100644
--- a/hw/arm/aspeed_ast2600_anacapa.c
+++ b/hw/arm/aspeed_ast2600_anacapa.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "hw/sensor/adc128d818.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/i2c_mux_pca954x.h"
diff --git a/hw/arm/aspeed_ast2600_bletchley.c b/hw/arm/aspeed_ast2600_bletchley.c
index 9dda83ad4c0..2822f6bdf5a 100644
--- a/hw/arm/aspeed_ast2600_bletchley.c
+++ b/hw/arm/aspeed_ast2600_bletchley.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/gpio/pca9552.h"
diff --git a/hw/arm/aspeed_ast2600_catalina.c b/hw/arm/aspeed_ast2600_catalina.c
index f91e0635908..23636ab6985 100644
--- a/hw/arm/aspeed_ast2600_catalina.c
+++ b/hw/arm/aspeed_ast2600_catalina.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/i2c_mux_pca954x.h"
diff --git a/hw/arm/aspeed_ast2600_evb.c b/hw/arm/aspeed_ast2600_evb.c
index 404083b61dc..8a17c4453e9 100644
--- a/hw/arm/aspeed_ast2600_evb.c
+++ b/hw/arm/aspeed_ast2600_evb.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/aspeed_ast2600_fby35.c b/hw/arm/aspeed_ast2600_fby35.c
index 6bcda0ac630..65d98fafec6 100644
--- a/hw/arm/aspeed_ast2600_fby35.c
+++ b/hw/arm/aspeed_ast2600_fby35.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2600_fuji.c b/hw/arm/aspeed_ast2600_fuji.c
index cf49149fe9a..8a87c2dbee3 100644
--- a/hw/arm/aspeed_ast2600_fuji.c
+++ b/hw/arm/aspeed_ast2600_fuji.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/i2c/i2c_mux_pca954x.h"
diff --git a/hw/arm/aspeed_ast2600_gb200nvl.c b/hw/arm/aspeed_ast2600_gb200nvl.c
index 705561afe39..311feb82023 100644
--- a/hw/arm/aspeed_ast2600_gb200nvl.c
+++ b/hw/arm/aspeed_ast2600_gb200nvl.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast2600_rainier.c b/hw/arm/aspeed_ast2600_rainier.c
index 6e5debc8bc1..43a8f01a9e7 100644
--- a/hw/arm/aspeed_ast2600_rainier.c
+++ b/hw/arm/aspeed_ast2600_rainier.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/nvram/eeprom_at24c.h"
diff --git a/hw/arm/aspeed_ast27x0-fc.c b/hw/arm/aspeed_ast27x0-fc.c
index ccfa4ade265..73362b60d2a 100644
--- a/hw/arm/aspeed_ast27x0-fc.c
+++ b/hw/arm/aspeed_ast27x0-fc.c
@@ -22,7 +22,6 @@
#include "hw/arm/boot.h"
#include "hw/block/flash.h"
#include "hw/arm/aspeed_coprocessor.h"
-#include "hw/arm/machines-qom.h"
#define TYPE_AST2700FC MACHINE_TYPE_NAME("ast2700fc")
OBJECT_DECLARE_SIMPLE_TYPE(Ast2700FCState, AST2700FC);
diff --git a/hw/arm/aspeed_ast27x0_evb.c b/hw/arm/aspeed_ast27x0_evb.c
index 0deb3127c21..460c9ff0d2e 100644
--- a/hw/arm/aspeed_ast27x0_evb.c
+++ b/hw/arm/aspeed_ast27x0_evb.c
@@ -8,7 +8,6 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/aspeed.h"
#include "hw/arm/aspeed_soc.h"
#include "hw/sensor/tmp105.h"
diff --git a/hw/arm/ax3000-boards.c b/hw/arm/ax3000-boards.c
index c7248f9f52b..dc98ee7b71a 100644
--- a/hw/arm/ax3000-boards.c
+++ b/hw/arm/ax3000-boards.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "hw/arm/ax3000-boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "qemu/error-report.h"
#include "qom/object.h"
diff --git a/hw/arm/b-l475e-iot01a.c b/hw/arm/b-l475e-iot01a.c
index 04dce2d19ce..de19212ab85 100644
--- a/hw/arm/b-l475e-iot01a.c
+++ b/hw/arm/b-l475e-iot01a.c
@@ -29,7 +29,6 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/core/split-irq.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/stm32l4x5_soc.h"
#include "hw/gpio/stm32l4x5_gpio.h"
#include "hw/display/dm163.h"
diff --git a/hw/arm/bananapi_m2u.c b/hw/arm/bananapi_m2u.c
index 15c878d1636..8f59111fd4e 100644
--- a/hw/arm/bananapi_m2u.c
+++ b/hw/arm/bananapi_m2u.c
@@ -27,7 +27,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/allwinner-r40.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#define TYPE_BPIM2U_MACHINE MACHINE_TYPE_NAME("bpim2u")
OBJECT_DECLARE_SIMPLE_TYPE(Bpim2uMachineState, BPIM2U_MACHINE)
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index 4b930e6ba12..ca6b3addb7b 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -15,7 +15,6 @@
#include "hw/core/boards.h"
#include "strongarm.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/address-spaces.h"
#include "qom/object.h"
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 511b71fbd7e..ae27056938f 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -22,7 +22,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/i2c/i2c.h"
#define TYPE_CUBIEBOARD_MACHINE MACHINE_TYPE_NAME("cubieboard")
diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c
index c7ecf22a958..90c19106ad0 100644
--- a/hw/arm/digic_boards.c
+++ b/hw/arm/digic_boards.c
@@ -29,7 +29,6 @@
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "hw/arm/digic.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/core/loader.h"
#include "system/qtest.h"
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index 62f7cbe875e..78632877df8 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -28,7 +28,6 @@
#include "hw/core/sysbus.h"
#include "net/net.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "system/address-spaces.h"
#include "hw/arm/exynos4210.h"
#include "hw/net/lan9118.h"
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 3246512c214..243c30a67e7 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -28,7 +28,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/fsl-imx25.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "system/qtest.h"
diff --git a/hw/arm/imx8mm-evk.c b/hw/arm/imx8mm-evk.c
index ffe8e494a57..8a5737502fd 100644
--- a/hw/arm/imx8mm-evk.c
+++ b/hw/arm/imx8mm-evk.c
@@ -11,7 +11,6 @@
#include "system/address-spaces.h"
#include "hw/arm/boot.h"
#include "hw/arm/fsl-imx8mm.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "system/kvm.h"
diff --git a/hw/arm/imx8mp-evk.c b/hw/arm/imx8mp-evk.c
index 389e7c86d21..3f376f86d91 100644
--- a/hw/arm/imx8mp-evk.c
+++ b/hw/arm/imx8mp-evk.c
@@ -10,7 +10,6 @@
#include "system/address-spaces.h"
#include "hw/arm/boot.h"
#include "hw/arm/fsl-imx8mp.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "system/kvm.h"
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index 25ecd931e76..382ea7850d8 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -13,7 +13,6 @@
#include "migration/vmstate.h"
#include "hw/core/boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/misc/arm_integrator_debug.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c
index 909dd929e63..387bf54ced1 100644
--- a/hw/arm/kzm.c
+++ b/hw/arm/kzm.c
@@ -17,7 +17,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx31.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/max78000fthr.c b/hw/arm/max78000fthr.c
index 290a14c8ad9..ed50bb91979 100644
--- a/hw/arm/max78000fthr.c
+++ b/hw/arm/max78000fthr.c
@@ -12,7 +12,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/core/qdev-clock.h"
#include "qemu/error-report.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/max78000_soc.h"
#include "hw/arm/boot.h"
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
index a3dafb20131..40071d2c7b9 100644
--- a/hw/arm/mcimx6ul-evk.c
+++ b/hw/arm/mcimx6ul-evk.c
@@ -14,7 +14,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6ul.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c
index cb4536faadd..db8a62e5f6c 100644
--- a/hw/arm/mcimx7d-sabre.c
+++ b/hw/arm/mcimx7d-sabre.c
@@ -16,7 +16,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx7.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index 85285861c5f..c1a3f6903fe 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -12,7 +12,6 @@
#include "qapi/error.h"
#include "hw/core/boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "system/system.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index 3a384d3cdb9..4e6744eddf4 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -60,7 +60,6 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/or-irq.h"
#include "hw/core/boards.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index b13b7bc55ec..35d867328a9 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -31,7 +31,6 @@
#include "qemu/error-report.h"
#include "hw/arm/boot.h"
#include "hw/arm/armv7m.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/or-irq.h"
#include "hw/core/boards.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c
index d6f4c1640ab..eedb877e4bc 100644
--- a/hw/arm/mps3r.c
+++ b/hw/arm/mps3r.c
@@ -37,7 +37,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/boot.h"
#include "hw/arm/bsa.h"
-#include "hw/arm/machines-qom.h"
#include "hw/char/cmsdk-apb-uart.h"
#include "hw/i2c/arm_sbcon_i2c.h"
#include "hw/intc/arm_gicv3.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index 8d00fef43b0..1372d7f628a 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -32,7 +32,6 @@
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/qdev-clock.h"
#include "system/address-spaces.h"
#include "hw/arm/msf2-soc.h"
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index 1b161487e7e..571bee1b72b 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -26,7 +26,6 @@
#include "system/system.h"
#include "hw/arm/boot.h"
#include "hw/arm/armsse.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/char/pl011.h"
#include "hw/core/split-irq.h"
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index 6a639264d61..0db8798b4bd 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -30,7 +30,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f205_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (120MHz) */
#define SYSCLK_FRQ 120000000ULL
diff --git a/hw/arm/netduinoplus2.c b/hw/arm/netduinoplus2.c
index d04ab8aeea4..5ac0eb81637 100644
--- a/hw/arm/netduinoplus2.c
+++ b/hw/arm/netduinoplus2.c
@@ -30,7 +30,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* Main SYSCLK frequency in Hz (168MHz) */
#define SYSCLK_FRQ 168000000ULL
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
index 025de42dac6..9c526a26839 100644
--- a/hw/arm/npcm7xx_boards.c
+++ b/hw/arm/npcm7xx_boards.c
@@ -17,7 +17,6 @@
#include "qemu/osdep.h"
#include "hw/arm/npcm7xx.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/i2c/i2c_mux_pca954x.h"
#include "hw/i2c/smbus_eeprom.h"
diff --git a/hw/arm/npcm8xx_boards.c b/hw/arm/npcm8xx_boards.c
index 2a04cf4f2c9..4b3af165034 100644
--- a/hw/arm/npcm8xx_boards.c
+++ b/hw/arm/npcm8xx_boards.c
@@ -19,7 +19,6 @@
#include "chardev/char.h"
#include "hw/core/boards.h"
#include "hw/arm/npcm8xx.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/cpu.h"
#include "hw/core/loader.h"
#include "hw/core/qdev.h"
diff --git a/hw/arm/olimex-stm32-h405.c b/hw/arm/olimex-stm32-h405.c
index 154501fc3c7..de9ac4978ce 100644
--- a/hw/arm/olimex-stm32-h405.c
+++ b/hw/arm/olimex-stm32-h405.c
@@ -31,7 +31,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f405_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* olimex-stm32-h405 implementation is derived from netduinoplus2 */
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index c3fe4187b8b..a7e469ea6a3 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -32,7 +32,6 @@
#include "hw/arm/omap.h"
#include "hw/core/boards.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "system/qtest.h"
#include "system/address-spaces.h"
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 3f06716c364..7a19732f5df 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -26,7 +26,6 @@
#include "hw/core/qdev-properties.h"
#include "hw/arm/allwinner-h3.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#define TYPE_ORANGEPI_MACHINE MACHINE_TYPE_NAME("orangepi-pc")
OBJECT_DECLARE_SIMPLE_TYPE(OrangePiMachineState, ORANGEPI_MACHINE)
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index 7ff3e8400e6..fadbacb2534 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -24,7 +24,6 @@
#include "qemu/error-report.h"
#include "hw/core/boards.h"
#include "hw/core/loader.h"
-#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#define TYPE_RASPI_MACHINE MACHINE_TYPE_NAME("raspi-common")
diff --git a/hw/arm/raspi4b.c b/hw/arm/raspi4b.c
index 08fcdf58c9f..7d3eed96304 100644
--- a/hw/arm/raspi4b.c
+++ b/hw/arm/raspi4b.c
@@ -11,7 +11,6 @@
#include "qemu/cutils.h"
#include "qapi/error.h"
#include "qapi/visitor.h"
-#include "hw/arm/machines-qom.h"
#include "hw/arm/raspi_platform.h"
#include "hw/display/bcm2835_fb.h"
#include "hw/core/registerfields.h"
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index aee7d05c3e6..ceba0331b08 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -12,7 +12,6 @@
#include "target/arm/cpu.h"
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/split-irq.h"
#include "hw/misc/arm_sysctl.h"
#include "hw/net/lan9118.h"
diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c
index ec307388f45..05dfabd9376 100644
--- a/hw/arm/sabrelite.c
+++ b/hw/arm/sabrelite.c
@@ -14,7 +14,6 @@
#include "qapi/error.h"
#include "hw/arm/fsl-imx6.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "hw/core/qdev-properties.h"
#include "qemu/error-report.h"
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 6ba353341a1..158b461eb48 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -35,7 +35,6 @@
#include "hw/arm/bsa.h"
#include "hw/arm/fdt.h"
#include "hw/arm/smmuv3.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/core/boards.h"
#include "hw/ide/ide-bus.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index f634918868b..f41315e1928 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -15,7 +15,6 @@
#include "hw/sd/sd.h"
#include "hw/ssi/ssi.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "qemu/timer.h"
#include "hw/i2c/i2c.h"
#include "net/net.h"
diff --git a/hw/arm/stm32vldiscovery.c b/hw/arm/stm32vldiscovery.c
index 0b39543c1ff..d899a134b38 100644
--- a/hw/arm/stm32vldiscovery.c
+++ b/hw/arm/stm32vldiscovery.c
@@ -31,7 +31,6 @@
#include "qemu/error-report.h"
#include "hw/arm/stm32f100_soc.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
/* stm32vldiscovery implementation is derived from netduinoplus2 */
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index 1db9bc1eb24..f94bf96599e 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -12,7 +12,6 @@
#include "hw/core/sysbus.h"
#include "migration/vmstate.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/net/smc91c111.h"
#include "net/net.h"
#include "system/system.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index 1e29fe0f09c..914cda66d20 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -26,7 +26,6 @@
#include "qemu/datadir.h"
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/misc/arm_sysctl.h"
#include "hw/net/lan9118.h"
#include "hw/i2c/i2c.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index eae4f0fe413..0871a35e11f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -37,7 +37,6 @@
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
#include "hw/arm/virt.h"
-#include "hw/arm/machines-qom.h"
#include "hw/block/flash.h"
#include "hw/display/ramfb.h"
#include "net/net.h"
diff --git a/hw/arm/xen-pvh.c b/hw/arm/xen-pvh.c
index b47dd9efd81..f05956c1662 100644
--- a/hw/arm/xen-pvh.c
+++ b/hw/arm/xen-pvh.c
@@ -10,7 +10,6 @@
#include "hw/core/boards.h"
#include "system/system.h"
#include "hw/xen/xen-pvh-common.h"
-#include "hw/arm/machines-qom.h"
#define TYPE_XEN_ARM MACHINE_TYPE_NAME("xenpvh")
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index 8ebd8e5ccd5..c1897ab1cf3 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -20,7 +20,6 @@
#include "qapi/error.h"
#include "hw/core/sysbus.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "net/net.h"
#include "system/system.h"
#include "hw/core/boards.h"
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
index e06a0c55549..4018f2bf7d1 100644
--- a/hw/arm/xlnx-versal-virt.c
+++ b/hw/arm/xlnx-versal-virt.c
@@ -21,7 +21,6 @@
#include "hw/arm/fdt.h"
#include "hw/arm/xlnx-versal.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "qom/object.h"
#include "target/arm/cpu.h"
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
index da8b3ede873..bb596218540 100644
--- a/hw/arm/xlnx-zcu102.c
+++ b/hw/arm/xlnx-zcu102.c
@@ -19,7 +19,6 @@
#include "qapi/error.h"
#include "hw/arm/xlnx-zynqmp.h"
#include "hw/arm/boot.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/boards.h"
#include "qemu/error-report.h"
#include "qemu/log.h"
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index c1ecf3214fd..2aa748233b3 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -16,7 +16,6 @@
#include "hw/core/boards.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
-#include "hw/arm/machines-qom.h"
#include "hw/riscv/machines-qom.h"
static void machine_none_init(MachineState *mch)
diff --git a/hw/nitro/machine.c b/hw/nitro/machine.c
index bb8878299bc..88d01960a01 100644
--- a/hw/nitro/machine.c
+++ b/hw/nitro/machine.c
@@ -31,7 +31,6 @@
#include "system/system.h"
#include "system/nitro-accel.h"
#include "qemu/accel.h"
-#include "hw/arm/machines-qom.h"
#include "hw/core/eif.h"
#include <zlib.h> /* for crc32 */
diff --git a/hw/remote/machine.c b/hw/remote/machine.c
index 6580e0d9683..ced782f6a9c 100644
--- a/hw/remote/machine.c
+++ b/hw/remote/machine.c
@@ -24,7 +24,6 @@
#include "hw/core/qdev.h"
#include "hw/remote/vfio-user-obj.h"
#include "hw/pci/msi.h"
-#include "hw/arm/machines-qom.h"
static void remote_machine_init(MachineState *machine)
{
diff --git a/target-info-qom.c b/target-info-qom.c
index eb9491338ca..7959853e0da 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -12,7 +12,6 @@
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
#include "qemu/target-info-qom.h"
-#include "hw/arm/machines-qom.h"
#include "hw/riscv/machines-qom.h"
static const TypeInfo target_info_types[] = {
diff --git a/target/arm/machine.c b/target/arm/machine.c
index 61106f9def6..7005f4e5d77 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -11,7 +11,6 @@
#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "target/arm/gtimer.h"
-#include "hw/arm/machines-qom.h"
static bool vfp_needed(void *opaque)
{
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 44/51] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (42 preceding siblings ...)
2026-09-03 10:39 ` [PULL 43/51] hw/arm: remove machines-qom.h Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 45/51] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces Philippe Mathieu-Daudé
` (7 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-12-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/riscv/machines-qom.h | 6 ------
hw/core/null-machine.c | 5 +----
hw/riscv/virt.c | 2 --
target-info-qom.c | 13 -------------
target/riscv/machine.c | 4 ----
5 files changed, 1 insertion(+), 29 deletions(-)
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index ee346227bb2..6c0bbdfc159 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -11,12 +11,6 @@
#include "hw/core/boards.h"
-#define TYPE_TARGET_RISCV32_MACHINE \
- "target-info-riscv32-machine"
-
-#define TYPE_TARGET_RISCV64_MACHINE \
- "target-info-riscv64-machine"
-
/*
* Interfaces specifying whether a given QOM object is available in
* qemu-system-riscv32, qemu-system-riscv64, or both.
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 2aa748233b3..2f008c4a702 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -56,7 +56,4 @@ static void machine_none_machine_init(MachineClass *mc)
mc->no_cdrom = 1;
}
-DEFINE_MACHINE_WITH_INTERFACES("none", machine_none_machine_init,
- { TYPE_TARGET_RISCV32_MACHINE },
- { TYPE_TARGET_RISCV64_MACHINE },
- { })
+DEFINE_MACHINE("none", machine_none_machine_init)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d58656f70d1..d2ae321a376 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1811,8 +1811,6 @@ static const TypeInfo virt_machine_typeinfo = {
.instance_size = sizeof(RISCVVirtState),
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
- { TYPE_TARGET_RISCV32_MACHINE },
- { TYPE_TARGET_RISCV64_MACHINE },
{ }
},
};
diff --git a/target-info-qom.c b/target-info-qom.c
index 7959853e0da..f98d3d7698e 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -14,19 +14,6 @@
#include "qemu/target-info-qom.h"
#include "hw/riscv/machines-qom.h"
-static const TypeInfo target_info_types[] = {
- {
- .name = TYPE_TARGET_RISCV32_MACHINE,
- .parent = TYPE_INTERFACE,
- },
- {
- .name = TYPE_TARGET_RISCV64_MACHINE,
- .parent = TYPE_INTERFACE,
- },
-};
-
-DEFINE_TYPES(target_info_types)
-
static void target_info_qom_class_init(ObjectClass *oc, const void * data)
{
TargetInfoQomClass *klass = TARGET_INFO_CLASS(oc);
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 31c49ca3e6a..59676c94470 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -582,17 +582,13 @@ const VMStateDescription vmstate_riscv_cpu = {
};
const InterfaceInfo riscv32_machine_interfaces[] = {
- { TYPE_TARGET_RISCV32_MACHINE },
{ }
};
const InterfaceInfo riscv64_machine_interfaces[] = {
- { TYPE_TARGET_RISCV64_MACHINE },
{ }
};
const InterfaceInfo riscv32_64_machine_interfaces[] = {
- { TYPE_TARGET_RISCV32_MACHINE },
- { TYPE_TARGET_RISCV64_MACHINE },
{ }
};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 45/51] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (43 preceding siblings ...)
2026-09-03 10:39 ` [PULL 44/51] hw/riscv: remove TYPE_TARGET_{RISCV32,RISCV64}_MACHINE Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 46/51] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64} Philippe Mathieu-Daudé
` (6 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-13-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/riscv/machines-qom.h | 15 +++------------
hw/riscv/k230.c | 1 -
hw/riscv/microchip_pfsoc.c | 1 -
hw/riscv/opentitan.c | 1 -
hw/riscv/shakti_c.c | 1 -
hw/riscv/sifive_e.c | 1 -
hw/riscv/sifive_u.c | 1 -
hw/riscv/spike.c | 1 -
hw/riscv/tt_atlantis.c | 1 -
hw/riscv/xiangshan_kmh.c | 1 -
target/riscv/machine.c | 12 ------------
11 files changed, 3 insertions(+), 33 deletions(-)
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index 6c0bbdfc159..e5f45b32e69 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -11,15 +11,6 @@
#include "hw/core/boards.h"
-/*
- * Interfaces specifying whether a given QOM object is available in
- * qemu-system-riscv32, qemu-system-riscv64, or both.
- */
-
-extern const InterfaceInfo riscv32_machine_interfaces[];
-extern const InterfaceInfo riscv64_machine_interfaces[];
-extern const InterfaceInfo riscv32_64_machine_interfaces[];
-
/*
* Helper macros for defining machines available in qemu-system-riscv32,
* qemu-system-riscv64, or both.
@@ -27,14 +18,14 @@ extern const InterfaceInfo riscv32_64_machine_interfaces[];
#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv32_machine_interfaces)
+ NULL)
#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv64_machine_interfaces)
+ NULL)
#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- riscv32_64_machine_interfaces)
+ NULL)
#endif
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 558f30b97e9..72d50d369a9 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -556,7 +556,6 @@ static const TypeInfo k230_machine_typeinfo = {
.class_init = k230_machine_class_init,
.instance_init = k230_machine_instance_init,
.instance_size = sizeof(K230MachineState),
- .interfaces = riscv64_machine_interfaces,
};
static void k230_machine_init_register_types(void)
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 4017129c830..42d4fc39734 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -756,7 +756,6 @@ static const TypeInfo microchip_icicle_kit_machine_typeinfo = {
.class_init = microchip_icicle_kit_machine_class_init,
.instance_init = microchip_icicle_kit_machine_instance_init,
.instance_size = sizeof(MicrochipIcicleKitState),
- .interfaces = riscv64_machine_interfaces,
};
static void microchip_icicle_kit_machine_init_register_types(void)
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index 5b2f33d5aca..c58d8993303 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -338,7 +338,6 @@ static const TypeInfo open_titan_types[] = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(OpenTitanState),
.class_init = opentitan_machine_class_init,
- .interfaces = riscv32_machine_interfaces,
}
};
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 835b1f879b7..9fd7856dc24 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -98,7 +98,6 @@ static const TypeInfo shakti_c_machine_type_info = {
.class_init = shakti_c_machine_class_init,
.instance_init = shakti_c_machine_instance_init,
.instance_size = sizeof(ShaktiCMachineState),
- .interfaces = riscv64_machine_interfaces,
};
static void shakti_c_machine_type_info_register(void)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 71925583bd9..ede7cb52f00 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -168,7 +168,6 @@ static const TypeInfo sifive_e_machine_typeinfo = {
.class_init = sifive_e_machine_class_init,
.instance_init = sifive_e_machine_instance_init,
.instance_size = sizeof(SiFiveEState),
- .interfaces = riscv32_64_machine_interfaces,
};
static void sifive_e_machine_init_register_types(void)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 57a57c96e16..08687cfc363 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -680,7 +680,6 @@ static const TypeInfo sifive_u_machine_typeinfo = {
.class_init = sifive_u_machine_class_init,
.instance_init = sifive_u_machine_instance_init,
.instance_size = sizeof(SiFiveUState),
- .interfaces = riscv32_64_machine_interfaces,
};
static void sifive_u_machine_init_register_types(void)
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 630b65f5697..3786de4b0b7 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -292,7 +292,6 @@ static const TypeInfo spike_machine_typeinfo = {
.class_init = spike_machine_class_init,
.instance_init = spike_machine_instance_init,
.instance_size = sizeof(SpikeState),
- .interfaces = riscv32_64_machine_interfaces,
};
static void spike_machine_init_register_types(void)
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index d808bcc11c3..5e155726abf 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -609,7 +609,6 @@ static const TypeInfo tt_atlantis_types[] = {
.parent = TYPE_MACHINE,
.class_init = tt_atlantis_machine_class_init,
.instance_size = sizeof(TTAtlantisState),
- .interfaces = riscv64_machine_interfaces,
},
};
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index 384624d69ad..e02624b62b4 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -216,7 +216,6 @@ static const TypeInfo xiangshan_kmh_machine_info = {
.parent = TYPE_MACHINE,
.instance_size = sizeof(XiangshanKmhState),
.class_init = xiangshan_kmh_machine_class_init,
- .interfaces = riscv64_machine_interfaces,
};
static void xiangshan_kmh_machine_register_types(void)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 59676c94470..22a918cec95 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -580,15 +580,3 @@ const VMStateDescription vmstate_riscv_cpu = {
NULL
}
};
-
-const InterfaceInfo riscv32_machine_interfaces[] = {
- { }
-};
-
-const InterfaceInfo riscv64_machine_interfaces[] = {
- { }
-};
-
-const InterfaceInfo riscv32_64_machine_interfaces[] = {
- { }
-};
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 46/51] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64}
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (44 preceding siblings ...)
2026-09-03 10:39 ` [PULL 45/51] hw/riscv: remove {riscv32, riscv32_64, riscv64}_machine_interfaces Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 47/51] hw/riscv: remove machines-qom.h Philippe Mathieu-Daudé
` (5 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-14-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/riscv/machines-qom.h | 17 -----------------
hw/riscv/boston-aia.c | 2 +-
hw/riscv/microblaze-v-generic.c | 2 +-
3 files changed, 2 insertions(+), 19 deletions(-)
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
index e5f45b32e69..79d212eeb7d 100644
--- a/include/hw/riscv/machines-qom.h
+++ b/include/hw/riscv/machines-qom.h
@@ -11,21 +11,4 @@
#include "hw/core/boards.h"
-/*
- * Helper macros for defining machines available in qemu-system-riscv32,
- * qemu-system-riscv64, or both.
- */
-
-#define DEFINE_MACHINE_RISCV32(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- NULL)
-
-#define DEFINE_MACHINE_RISCV64(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- NULL)
-
-#define DEFINE_MACHINE_RISCV32_64(namestr, machine_initfn) \
- DEFINE_MACHINE_WITH_INTERFACE_ARRAY(namestr, machine_initfn, \
- NULL)
-
#endif
diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index 965d0f5699e..30eff10bc5f 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston-aia.c
@@ -474,4 +474,4 @@ static void boston_mach_class_init(MachineClass *mc)
mc->default_cpu_type = TYPE_RISCV_CPU_MIPS_P8700;
}
-DEFINE_MACHINE_RISCV64("boston-aia", boston_mach_class_init)
+DEFINE_MACHINE("boston-aia", boston_mach_class_init)
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index d33ac39a68c..503e8e08992 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -187,4 +187,4 @@ static void mb_v_generic_machine_init(MachineClass *mc)
mc->default_cpus = 1;
}
-DEFINE_MACHINE_RISCV32_64("amd-microblaze-v-generic", mb_v_generic_machine_init)
+DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 47/51] hw/riscv: remove machines-qom.h
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (45 preceding siblings ...)
2026-09-03 10:39 ` [PULL 46/51] hw/riscv: remove DEFINE_MACHINE_{RISCV32,RISCV64} Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 48/51] rustfmt: disable wrap_comments Philippe Mathieu-Daudé
` (4 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260901202043.26532-15-pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
include/hw/riscv/machines-qom.h | 14 --------------
configs/targets/riscv32-softmmu.c | 1 -
configs/targets/riscv64-softmmu.c | 1 -
hw/core/null-machine.c | 1 -
hw/riscv/boston-aia.c | 1 -
hw/riscv/k230.c | 1 -
hw/riscv/microblaze-v-generic.c | 1 -
hw/riscv/microchip_pfsoc.c | 1 -
hw/riscv/opentitan.c | 1 -
hw/riscv/shakti_c.c | 1 -
hw/riscv/sifive_e.c | 1 -
hw/riscv/sifive_u.c | 1 -
hw/riscv/spike.c | 1 -
hw/riscv/tt_atlantis.c | 1 -
hw/riscv/virt.c | 1 -
hw/riscv/xiangshan_kmh.c | 1 -
target-info-qom.c | 1 -
target/riscv/machine.c | 1 -
18 files changed, 31 deletions(-)
delete mode 100644 include/hw/riscv/machines-qom.h
diff --git a/include/hw/riscv/machines-qom.h b/include/hw/riscv/machines-qom.h
deleted file mode 100644
index 79d212eeb7d..00000000000
--- a/include/hw/riscv/machines-qom.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * QOM type definitions for riscv32 / riscv64 machines
- *
- * Copyright (c) rev.ng Labs Srl.
- *
- * SPDX-License-Identifier: GPL-2.0-or-later
- */
-
-#ifndef HW_RISCV_MACHINES_QOM_H
-#define HW_RISCV_MACHINES_QOM_H
-
-#include "hw/core/boards.h"
-
-#endif
diff --git a/configs/targets/riscv32-softmmu.c b/configs/targets/riscv32-softmmu.c
index c1d94679c7e..0829ab84de5 100644
--- a/configs/targets/riscv32-softmmu.c
+++ b/configs/targets/riscv32-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
diff --git a/configs/targets/riscv64-softmmu.c b/configs/targets/riscv64-softmmu.c
index f648a5c8944..553bd1f75fe 100644
--- a/configs/targets/riscv64-softmmu.c
+++ b/configs/targets/riscv64-softmmu.c
@@ -9,7 +9,6 @@
#include "qemu/osdep.h"
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
-#include "hw/riscv/machines-qom.h"
#include "target/riscv/cpu-qom.h"
#include "target/riscv/cpu-param.h"
diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c
index 2f008c4a702..60254913019 100644
--- a/hw/core/null-machine.c
+++ b/hw/core/null-machine.c
@@ -16,7 +16,6 @@
#include "hw/core/boards.h"
#include "system/address-spaces.h"
#include "hw/core/cpu.h"
-#include "hw/riscv/machines-qom.h"
static void machine_none_init(MachineState *mch)
{
diff --git a/hw/riscv/boston-aia.c b/hw/riscv/boston-aia.c
index 30eff10bc5f..b90da096ea8 100644
--- a/hw/riscv/boston-aia.c
+++ b/hw/riscv/boston-aia.c
@@ -18,7 +18,6 @@
#include "hw/ide/ahci-pci.h"
#include "hw/core/loader.h"
#include "hw/riscv/cps.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/pci-host/xilinx-pcie.h"
#include "hw/core/qdev-properties.h"
#include "qapi/error.h"
diff --git a/hw/riscv/k230.c b/hw/riscv/k230.c
index 72d50d369a9..34905bb1702 100644
--- a/hw/riscv/k230.c
+++ b/hw/riscv/k230.c
@@ -26,7 +26,6 @@
#include "hw/core/sysbus.h"
#include "hw/riscv/k230.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
#include "hw/char/serial-mm.h"
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index 503e8e08992..b0494b1ac50 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -25,7 +25,6 @@
#include "system/address-spaces.h"
#include "hw/char/xilinx_uartlite.h"
#include "hw/misc/unimp.h"
-#include "hw/riscv/machines-qom.h"
#define LMB_BRAM_SIZE (128 * KiB)
#define MEMORY_BASEADDR 0x80000000
diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c
index 42d4fc39734..60bb96da016 100644
--- a/hw/riscv/microchip_pfsoc.c
+++ b/hw/riscv/microchip_pfsoc.c
@@ -49,7 +49,6 @@
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/microchip_pfsoc.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
index c58d8993303..8cd660dd415 100644
--- a/hw/riscv/opentitan.c
+++ b/hw/riscv/opentitan.c
@@ -26,7 +26,6 @@
#include "hw/core/boards.h"
#include "hw/misc/unimp.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "qemu/units.h"
#include "system/system.h"
#include "system/address-spaces.h"
diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c
index 9fd7856dc24..a205a213324 100644
--- a/hw/riscv/shakti_c.c
+++ b/hw/riscv/shakti_c.c
@@ -19,7 +19,6 @@
#include "qemu/osdep.h"
#include "hw/core/boards.h"
#include "hw/riscv/shakti_c.h"
-#include "hw/riscv/machines-qom.h"
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "hw/intc/sifive_plic.h"
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index ede7cb52f00..1acfea49668 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -40,7 +40,6 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_e.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/char/sifive_uart.h"
#include "hw/intc/riscv_aclint.h"
#include "hw/intc/sifive_plic.h"
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 08687cfc363..997ee91aa0e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -51,7 +51,6 @@
#include "hw/riscv/riscv_hart.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/fdt-common.h"
#include "hw/char/sifive_uart.h"
#include "hw/intc/riscv_aclint.h"
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 3786de4b0b7..e36fe996b09 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -34,7 +34,6 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/fdt-common.h"
#include "hw/riscv/numa.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/char/riscv_htif.h"
#include "hw/intc/riscv_aclint.h"
#include "chardev/char.h"
diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c
index 5e155726abf..7d02868b222 100644
--- a/hw/riscv/tt_atlantis.c
+++ b/hw/riscv/tt_atlantis.c
@@ -20,7 +20,6 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/fdt-common.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/riscv_hart.h"
#include "hw/char/serial-mm.h"
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index d2ae321a376..dd396410178 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -36,7 +36,6 @@
#include "hw/riscv/virt.h"
#include "hw/riscv/boot.h"
#include "hw/riscv/fdt-common.h"
-#include "hw/riscv/machines-qom.h"
#include "hw/riscv/numa.h"
#include "kvm/kvm_riscv.h"
#include "hw/firmware/smbios.h"
diff --git a/hw/riscv/xiangshan_kmh.c b/hw/riscv/xiangshan_kmh.c
index e02624b62b4..247a0b5d1f2 100644
--- a/hw/riscv/xiangshan_kmh.c
+++ b/hw/riscv/xiangshan_kmh.c
@@ -41,7 +41,6 @@
#include "hw/riscv/boot.h"
#include "hw/riscv/xiangshan_kmh.h"
#include "hw/riscv/riscv_hart.h"
-#include "hw/riscv/machines-qom.h"
#include "system/system.h"
static const MemMapEntry xiangshan_kmh_memmap[] = {
diff --git a/target-info-qom.c b/target-info-qom.c
index f98d3d7698e..6965e4d1169 100644
--- a/target-info-qom.c
+++ b/target-info-qom.c
@@ -12,7 +12,6 @@
#include "qemu/target-info-impl.h"
#include "qemu/target-info-init.h"
#include "qemu/target-info-qom.h"
-#include "hw/riscv/machines-qom.h"
static void target_info_qom_class_init(ObjectClass *oc, const void * data)
{
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 22a918cec95..c3f5a255099 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -24,7 +24,6 @@
#include "migration/cpu.h"
#include "exec/icount.h"
#include "target/riscv/tcg/debug.h"
-#include "hw/riscv/machines-qom.h"
#ifdef CONFIG_KVM
#include "kvm/kvm_riscv.h"
#endif
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 48/51] rustfmt: disable wrap_comments
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (46 preceding siblings ...)
2026-09-03 10:39 ` [PULL 47/51] hw/riscv: remove machines-qom.h Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 49/51] system: improve -mon deprecation warning Philippe Mathieu-Daudé
` (3 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Paolo Bonzini <pbonzini@redhat.com>
This was in practice not enabled until now, and now that it is
the results are not great. Disable it so that the CI job
check-rust-tools-nightly does not fail gratuitously.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <20260902083624.419157-1-pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
rust/rustfmt.toml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/rust/rustfmt.toml b/rust/rustfmt.toml
index ebecb99fe09..a7d610bce21 100644
--- a/rust/rustfmt.toml
+++ b/rust/rustfmt.toml
@@ -4,4 +4,4 @@ format_code_in_doc_comments = true
format_strings = true
imports_granularity = "Crate"
group_imports = "StdExternalCrate"
-wrap_comments = true
+wrap_comments = false
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 49/51] system: improve -mon deprecation warning
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (47 preceding siblings ...)
2026-09-03 10:39 ` [PULL 48/51] rustfmt: disable wrap_comments Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 50/51] MAINTAINERS: Stop reviewing meson-related patches Philippe Mathieu-Daudé
` (2 subsequent siblings)
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Daniel P. Berrangé <berrange@redhat.com>
Expand the text a bit to make the new syntax more explicit and point
users to the man page for further info.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20260902104753.1756783-1-berrange@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
system/vl.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/system/vl.c b/system/vl.c
index 1b22a358d23..9bd7664b85c 100644
--- a/system/vl.c
+++ b/system/vl.c
@@ -3238,8 +3238,13 @@ void qemu_init(int argc, char **argv)
default_monitor = 0;
break;
case QEMU_OPTION_mon:
- warn_report_once("'-mon' is deprecated, use '-object' with "
- "'monitor-hmp' or 'monitor-qmp' types instead");
+ warn_report_once(
+ "'-mon' is deprecated. Switch to either "
+ "'-object monitor-hmp,id=ID,chardev=CHR-ID' or "
+ "'-object monitor-qmp,id=ID,chardev=CHR-ID' instead. "
+ "See '-object' docs in the QEMU manual for further "
+ "configuration guidance: "
+ "https://www.qemu.org/docs/master/system/invocation.html");
if (!qemu_opts_parse_noisily(qemu_find_opts("mon"), optarg,
true)) {
exit(1);
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 50/51] MAINTAINERS: Stop reviewing meson-related patches
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (48 preceding siblings ...)
2026-09-03 10:39 ` [PULL 49/51] system: improve -mon deprecation warning Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 10:39 ` [PULL 51/51] MAINTAINERS: Update PhilMD's email address Philippe Mathieu-Daudé
2026-09-03 19:15 ` [PULL 00/51] Misc HW/accel patches for 2026-09-03 Peter Maydell
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@mailo.com>
With retrospective to commit 48fad83ff49 ("MAINTAINERS: add
entries for the key build bits") I think I only wanted to be
listed in the "Top Level Makefile and configure", not the
meson one (I'm not following meson changes closely enough).
Signed-off-by: Philippe Mathieu-Daudé <philmd@mailo.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260902155105.32165-1-philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
MAINTAINERS | 1 -
1 file changed, 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index e3f91ff1cab..2cff90141f7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4676,7 +4676,6 @@ Meson
M: Paolo Bonzini <pbonzini@redhat.com>
R: Marc-André Lureau <marcandre.lureau@redhat.com>
R: Daniel P. Berrange <berrange@redhat.com>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
R: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
S: Maintained
F: meson.build
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* [PULL 51/51] MAINTAINERS: Update PhilMD's email address
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (49 preceding siblings ...)
2026-09-03 10:39 ` [PULL 50/51] MAINTAINERS: Stop reviewing meson-related patches Philippe Mathieu-Daudé
@ 2026-09-03 10:39 ` Philippe Mathieu-Daudé
2026-09-03 19:15 ` [PULL 00/51] Misc HW/accel patches for 2026-09-03 Peter Maydell
51 siblings, 0 replies; 53+ messages in thread
From: Philippe Mathieu-Daudé @ 2026-09-03 10:39 UTC (permalink / raw)
To: qemu-devel
From: Philippe Mathieu-Daudé <philmd@mailo.com>
My personal email free service doesn't scale with qemu-devel@
mailing list traffic, returning distinct STMP errors. Dispatch
to work email instead. Update mailmap accordingly.
Signed-off-by: Philippe Mathieu-Daudé <philmd@mailo.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Message-Id: <20260902155211.32399-1-philmd@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
MAINTAINERS | 56 ++++++++++++++++++++++++++---------------------------
.mailmap | 9 +++++----
2 files changed, 33 insertions(+), 32 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2cff90141f7..f524d905236 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -68,7 +68,7 @@ Project policy and developer guides
R: Alex Bennée <alex.bennee@linaro.org>
R: Daniel P. Berrangé <berrange@redhat.com>
R: Markus Armbruster <armbru@redhat.com>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
W: https://www.qemu.org/docs/master/devel/index.html
S: Odd Fixes
F: docs/devel/build-environment.rst
@@ -132,7 +132,7 @@ T: git https://gitlab.com/cohuck/qemu.git s390-next
L: qemu-s390x@nongnu.org
MIPS general architecture support
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Odd Fixes
K: ^Subject:.*(?i)mips
@@ -315,7 +315,7 @@ F: tests/docker/dockerfiles/debian-microblaze-cross.d/build-toolchain.sh
F: tests/functional/microblaze/
MIPS TCG CPUs
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
R: Aleksandar Rikalo <arikalo@gmail.com>
@@ -545,7 +545,7 @@ Guest CPU Cores (other accelerators)
Overall CPUs other accelerators
M: Richard Henderson <richard.henderson@linaro.org>
R: Paolo Bonzini <pbonzini@redhat.com>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Maintained
F: include/exec/cpu*.h
F: include/exec/target_long.h
@@ -707,7 +707,7 @@ F: qemu.nsi
F: scripts/nsis.py
Darwin (macOS, iOS)
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Odd Fixes
F: .gitlab-ci.d/macos*
F: */*.m
@@ -1013,7 +1013,7 @@ F: tests/functional/arm/test_quanta_gsj.py
Raspberry Pi
M: Peter Maydell <peter.maydell@linaro.org>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
L: qemu-arm@nongnu.org
S: Odd Fixes
F: hw/arm/raspi*.c
@@ -1324,7 +1324,7 @@ F: include/hw/misc/avr_power.h
F: hw/misc/avr_power.c
Arduino
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Maintained
F: hw/avr/arduino.c
F: tests/functional/avr/test_uno.py
@@ -1473,7 +1473,7 @@ F: hw/microblaze/petalogix_ml605_mmu.c
MIPS Machines
-------------
Overall MIPS Machines
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Odd Fixes
F: configs/devices/mips*/*
F: hw/mips/
@@ -1490,7 +1490,7 @@ F: hw/dma/rc4030.c
F: hw/nvram/ds1225y.c
Malta
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Aurelien Jarno <aurelien@aurel32.net>
S: Odd Fixes
F: hw/isa/piix.c
@@ -1504,7 +1504,7 @@ F: tests/functional/mips*/test_tuxrun.py
Fuloong 2E
M: Huacai Chen <chenhuacai@kernel.org>
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Odd Fixes
F: hw/mips/fuloong2e.c
@@ -1528,7 +1528,7 @@ F: include/hw/intc/loongson_liointc.h
F: tests/functional/mips64el/test_loongson3v.py
Boston
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Aleksandar Rikalo <arikalo@gmail.com>
S: Odd Fixes
F: hw/core/loader-fit.c
@@ -2113,7 +2113,7 @@ F: include/hw/i386/nitro_enclave.h
F: docs/system/i386/nitro-enclave.rst
Machine core
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Zhao Liu <zhao1.liu@intel.com>
S: Maintained
F: hw/core/cpu-internal.h
@@ -2137,7 +2137,7 @@ F: tests/unit/test-smp-parse.c
TargetInfo API
M: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Supported
F: include/qemu/target-info*.h
F: target-info*.c
@@ -2373,7 +2373,7 @@ F: docs/system/virtio-net-failover.rst
T: git https://github.com/jasowang/qemu.git net
Parallel NOR Flash devices
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Maintained
F: hw/block/pflash_cfi*.c
F: include/hw/block/flash.h
@@ -2408,7 +2408,7 @@ S: Maintained
F: hw/ssi/xilinx_*
SD (Secure Card)
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
M: Bin Meng <bmeng.cn@gmail.com>
L: qemu-block@nongnu.org
S: Odd Fixes
@@ -2890,14 +2890,14 @@ F: tests/qtest/launchupdate-test.c
F: tests/data/igvm/*
LED
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Maintained
F: include/hw/misc/led.h
F: hw/misc/led.c
Unimplemented device
M: Peter Maydell <peter.maydell@linaro.org>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Ani Sinha <ani@anisinha.ca>
S: Maintained
F: include/hw/misc/unimp.h
@@ -2905,7 +2905,7 @@ F: hw/misc/unimp.c
Empty slot
M: Artyom Tarasenko <atar4qemu@gmail.com>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Ani Sinha <ani@anisinha.ca>
S: Maintained
F: include/hw/misc/empty_slot.h
@@ -2984,14 +2984,14 @@ F: hw/display/apple-gfx*
PIIX4 South Bridge (i82371AB)
M: Hervé Poussineau <hpoussin@reactos.org>
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Maintained
F: hw/isa/piix.c
F: include/hw/southbridge/piix.h
VIA South Bridges (VT82C686B, VT8231)
M: BALATON Zoltan <balaton@eik.bme.hu>
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Maintained
F: hw/isa/vt82c686.c
@@ -3056,13 +3056,13 @@ F: hw/intc/openpic.c
F: include/hw/ppc/openpic.h
MIPS CPS
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Odd Fixes
F: hw/misc/mips_*
F: include/hw/misc/mips_*
MIPS GIC
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Odd Fixes
F: hw/intc/mips_gic.c
F: hw/timer/mips_gictimer.c
@@ -3188,7 +3188,7 @@ F: audio/alsaaudio.c
Core Audio framework backend
M: Gerd Hoffmann <kraxel@redhat.com>
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Christian Schoenebeck <qemu_oss@crudebyte.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Odd Fixes
@@ -3426,7 +3426,7 @@ F: scripts/coccinelle/errp-guard.cocci
GDB stub
M: Alex Bennée <alex.bennee@linaro.org>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Maintained
F: docs/system/gdb.rst
F: gdbstub/*
@@ -3440,7 +3440,7 @@ T: git https://gitlab.com/stsquad/qemu gdbstub/next
Memory API
M: Paolo Bonzini <pbonzini@redhat.com>
M: Peter Xu <peterx@redhat.com>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Supported
F: include/system/ioport.h
F: include/exec/memop.h
@@ -3503,7 +3503,7 @@ F: tests/functional/generic/test_vnc.py
Cocoa graphics
M: Peter Maydell <peter.maydell@linaro.org>
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Akihiko Odaki <odaki@rsg.ci.i.u-tokyo.ac.jp>
S: Odd Fixes
F: ui/cocoa.m
@@ -4067,7 +4067,7 @@ S: Maintained
F: contrib/elf2dmp/
Overall sensors
-M: Philippe Mathieu-Daudé <philmd@mailo.com>
+M: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
S: Odd Fixes
F: hw/sensor
F: include/hw/sensor
@@ -4620,7 +4620,7 @@ F: tests/vm/freebsd
Functional testing framework
M: Thomas Huth <th.huth+qemu@posteo.eu>
-R: Philippe Mathieu-Daudé <philmd@mailo.com>
+R: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
R: Daniel P. Berrange <berrange@redhat.com>
S: Odd Fixes
F: docs/devel/testing/functional.rst
diff --git a/.mailmap b/.mailmap
index 08f0fa9e118..bd8bf07feb7 100644
--- a/.mailmap
+++ b/.mailmap
@@ -113,10 +113,11 @@ Paul Burton <paulburton@kernel.org> <paul.burton@mips.com>
Paul Burton <paulburton@kernel.org> <paul.burton@imgtec.com>
Paul Burton <paulburton@kernel.org> <paul@archlinuxmips.org>
Paul Burton <paulburton@kernel.org> <pburton@wavecomp.com>
-Philippe Mathieu-Daudé <philmd@mailo.com> <f4bug@amsat.org>
-Philippe Mathieu-Daudé <philmd@mailo.com> <philmd@redhat.com>
-Philippe Mathieu-Daudé <philmd@mailo.com> <philmd@fungible.com>
-Philippe Mathieu-Daudé <philmd@mailo.com> <philmd@linaro.org>
+Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> <f4bug@amsat.org>
+Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> <philmd@redhat.com>
+Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> <philmd@fungible.com>
+Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> <philmd@linaro.org>
+Philippe Mathieu-Daudé <philmd@oss.qualcomm.com> <philmd@mailo.com>
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> <pierrick.bouvier@linaro.org>
Roman Bolshakov <rbolshakov@ddn.com> <r.bolshakov@yadro.com>
Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
--
2.53.0
^ permalink raw reply related [flat|nested] 53+ messages in thread* Re: [PULL 00/51] Misc HW/accel patches for 2026-09-03
2026-09-03 10:38 [PULL 00/51] Misc HW/accel patches for 2026-09-03 Philippe Mathieu-Daudé
` (50 preceding siblings ...)
2026-09-03 10:39 ` [PULL 51/51] MAINTAINERS: Update PhilMD's email address Philippe Mathieu-Daudé
@ 2026-09-03 19:15 ` Peter Maydell
51 siblings, 0 replies; 53+ messages in thread
From: Peter Maydell @ 2026-09-03 19:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé; +Cc: qemu-devel
On Thu, 3 Sept 2026 at 11:40, Philippe Mathieu-Daudé
<philmd@oss.qualcomm.com> wrote:
>
> The following changes since commit c513597761d6fc06690b5b7cf10dfb7ab05815d0:
>
> Merge tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu into staging (2026-09-02 17:59:30 +0100)
>
> are available in the Git repository at:
>
> https://github.com/philmd/qemu.git tags/hw-misc-20260903
>
> for you to fetch changes up to 94651820173214b3e012cd7e0a69ccff0ab196db:
>
> MAINTAINERS: Update PhilMD's email address (2026-09-03 12:22:32 +0200)
>
> ----------------------------------------------------------------
> Misc HW and accel patch queue
>
> - MAINTAINERS updates
> - Add const qualifiers to CPU state accessors on various targets
> - Improve KVM/ARM error handling
> - Restrict TCG HALTED handling to system emulation
> - Introduce TypeInfo::is_available callback, remove arm/riscv machines filtering
> - Parallel NOR flash: Fix ROMD mode on Intel, add migrations support on AMD
> - SD/SDHCI Controller Fixes
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/11.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 53+ messages in thread