From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Zhao Liu" <zhao1.liu@intel.com>
Subject: [PATCH 09/27] target/i386: Implement and register CPUClass::exception_name()
Date: Wed, 7 Oct 2026 11:44:57 +0200 [thread overview]
Message-ID: <20261007094516.75732-10-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com>
Implement x86_exception_name() and register it as
the CPUClass::exception_name() handler, so the common
exception logging can resolve X86 exception codes to names.
Use the new helper in check_exception() and do_interrupt_all().
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/i386/cpu.h | 2 ++
target/i386/cpu.c | 33 +++++++++++++++++++++++++++++++++
target/i386/tcg/excp_helper.c | 5 +++--
target/i386/tcg/seg_helper.c | 6 ++++--
4 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 786957fadd0..4f5e4f56acc 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1515,6 +1515,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
#define EXCP_SYSCALL 0x101 /* only for user emulation */
#define EXCP_VSYSCALL 0x102 /* only for user emulation */
+const char *x86_exception_name(int excp);
+
/* i386-specific interrupt pending bits. */
#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index f3bc6911c10..885fd0ded16 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -9371,6 +9371,38 @@ static bool cpuid_has_xsave_feature(CPUX86State *env, const ExtSaveArea *esa)
return false;
}
+const char *x86_exception_name(int excp)
+{
+ static const char * const excp_names[] = {
+ [EXCP00_DIVZ] = "DIV#0",
+ [EXCP01_DB] = "DB",
+ [EXCP02_NMI] = "NMI",
+ [EXCP03_INT3] = "INT3",
+ [EXCP04_INTO] = "INTO",
+ [EXCP05_BOUND] = "BOUND",
+ [EXCP06_ILLOP] = "ILLOP",
+ [EXCP07_PREX] = "PREX",
+ [EXCP08_DBLE] = "DBLE",
+ [EXCP09_XERR] = "XERR",
+ [EXCP0A_TSS] = "TSS",
+ [EXCP0B_NOSEG] = "NOSEG",
+ [EXCP0C_STACK] = "STACK",
+ [EXCP0D_GPF] = "GPF",
+ [EXCP0E_PAGE] = "PAGE",
+ [EXCP10_COPR] = "COPR",
+ [EXCP11_ALGN] = "ALGN",
+ [EXCP12_MCHK] = "MCHK",
+ [EXCP_VMEXIT] = "VMEXIT",
+ [EXCP_SYSCALL] = "SYSCALL",
+ [EXCP_VSYSCALL] = "VSYSCALL",
+ };
+
+ if (excp < 0 || excp >= ARRAY_SIZE(excp_names) || !excp_names[excp]) {
+ return "unknown";
+ }
+ return excp_names[excp];
+}
+
static void x86_cpu_reset_hold(Object *obj, ResetType type)
{
CPUState *cs = CPU(obj);
@@ -10921,6 +10953,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, const void *data)
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->class_by_name = x86_cpu_class_by_name;
+ cc->exception_name = x86_exception_name;
cc->list_cpus = x86_cpu_list;
cc->parse_features = x86_cpu_parse_featurestr;
cc->dump_state = x86_cpu_dump_state;
diff --git a/target/i386/tcg/excp_helper.c b/target/i386/tcg/excp_helper.c
index 1eaa602c91d..34776de6a50 100644
--- a/target/i386/tcg/excp_helper.c
+++ b/target/i386/tcg/excp_helper.c
@@ -51,8 +51,9 @@ static int check_exception(CPUX86State *env, int intno, int *error_code,
int second_contributory = intno == 0 ||
(intno >= 10 && intno <= 13);
- qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x new 0x%x\n",
- env->old_exception, intno);
+ qemu_log_mask(CPU_LOG_INT, "check_exception old: 0x%x (%s) new 0x%x (%s)\n",
+ env->old_exception, x86_exception_name(env->old_exception),
+ intno, x86_exception_name(intno));
#if !defined(CONFIG_USER_ONLY)
if (env->old_exception == EXCP08_DBLE) {
diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c
index 138d2384b18..494898e5caa 100644
--- a/target/i386/tcg/seg_helper.c
+++ b/target/i386/tcg/seg_helper.c
@@ -1208,9 +1208,11 @@ void do_interrupt_all(X86CPU *cpu, int intno, int is_int,
if ((env->cr[0] & CR0_PE_MASK)) {
static int count;
- qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
+ qemu_log("%6d: v=%02x (%s) e=%04x i=%d"
+ " cpl=%d IP=%04x:" TARGET_FMT_lx
" pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx,
- count, intno, error_code, is_int,
+ count, intno, x86_exception_name(intno),
+ error_code, is_int,
env->hflags & HF_CPL_MASK,
env->segs[R_CS].selector, env->eip,
(int)env->segs[R_CS].base + env->eip,
--
2.55.0
next prev parent reply other threads:[~2026-10-07 9:50 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-07 9:44 [PATCH 00/27] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 01/27] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-07 10:47 ` Philippe Mathieu-Daudé
2026-10-07 11:00 ` Daniel P. Berrangé
2026-10-07 15:24 ` Yonggang Luo
2026-10-07 9:44 ` [PATCH 02/27] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 03/27] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 04/27] target/arm: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 05/27] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 06/27] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-09 1:34 ` Brian Cain
2026-10-07 9:44 ` [PATCH 07/27] target/hppa: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 08/27] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-07 9:44 ` Philippe Mathieu-Daudé [this message]
2026-10-07 9:44 ` [PATCH 10/27] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-08 1:31 ` Bibo Mao
2026-10-07 9:44 ` [PATCH 11/27] target/m68k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 12/27] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 13/27] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 14/27] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 15/27] target/or1k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 16/27] target/ppc: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 17/27] target/riscv: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 18/27] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 19/27] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 20/27] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 21/27] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 22/27] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 23/27] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 24/27] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 25/27] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 26/27] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 27/27] target/xtensa: " Philippe Mathieu-Daudé
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