From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Yoshinori Sato" <yoshinori.sato@nifty.com>
Subject: [PATCH 18/27] target/rx: Unify BRK and INT trap handling
Date: Wed, 7 Oct 2026 11:45:06 +0200 [thread overview]
Message-ID: <20261007094516.75732-19-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com>
BRK is equivalent to INT #0, so route both instructions
through the same trap helper.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Yoshinori Sato <yoshinori.sato@nifty.com>
---
target/rx/helper.h | 3 +--
target/rx/op_helper.c | 7 +------
target/rx/translate.c | 21 ++++++++++-----------
3 files changed, 12 insertions(+), 19 deletions(-)
diff --git a/target/rx/helper.h b/target/rx/helper.h
index 8cc38b0cb71..f3897ce7619 100644
--- a/target/rx/helper.h
+++ b/target/rx/helper.h
@@ -2,8 +2,7 @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
DEF_HELPER_1(raise_access_fault, noreturn, env)
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
DEF_HELPER_1(wait, noreturn, env)
-DEF_HELPER_2(rxint, noreturn, env, i32)
-DEF_HELPER_1(rxbrk, noreturn, env)
+DEF_HELPER_2(trap, noreturn, env, i32)
DEF_HELPER_3(fadd, f32, env, f32, f32)
DEF_HELPER_3(fsub, f32, env, f32, f32)
DEF_HELPER_3(fmul, f32, env, f32, f32)
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 36df7d377e5..6782912247e 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -455,12 +455,7 @@ G_NORETURN void helper_wait(CPURXState *env)
raise_exception(env, EXCP_HLT, 0);
}
-G_NORETURN void helper_rxint(CPURXState *env, uint32_t vec)
+G_NORETURN void helper_trap(CPURXState *env, uint32_t vec)
{
raise_exception(env, 0x100 + vec, 0);
}
-
-G_NORETURN void helper_rxbrk(CPURXState *env)
-{
- raise_exception(env, 0x100, 0);
-}
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 132d495710c..d0910fbf8e7 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2170,26 +2170,25 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
return true;
}
+static bool do_trap(DisasContext *ctx, uint8_t vec)
+{
+ tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
+ gen_helper_trap(tcg_env, tcg_constant_i32(vec));
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
+
/* brk */
static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
{
- tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
- gen_helper_rxbrk(tcg_env);
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
+ return do_trap(ctx, 0);
}
/* int #imm */
static bool trans_INT(DisasContext *ctx, arg_INT *a)
{
- TCGv_i32 vec;
-
tcg_debug_assert(a->imm < 0x100);
- vec = tcg_constant_i32(a->imm);
- tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
- gen_helper_rxint(tcg_env, vec);
- ctx->base.is_jmp = DISAS_NORETURN;
- return true;
+ return do_trap(ctx, a->imm);
}
/* wait */
--
2.55.0
next prev parent reply other threads:[~2026-10-07 9:53 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-07 9:44 [PATCH 00/27] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 01/27] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-07 10:47 ` Philippe Mathieu-Daudé
2026-10-07 11:00 ` Daniel P. Berrangé
2026-10-07 15:24 ` Yonggang Luo
2026-10-07 9:44 ` [PATCH 02/27] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 03/27] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 04/27] target/arm: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 05/27] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 06/27] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-09 1:34 ` Brian Cain
2026-10-07 9:44 ` [PATCH 07/27] target/hppa: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 08/27] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 09/27] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 10/27] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-08 1:31 ` Bibo Mao
2026-10-07 9:44 ` [PATCH 11/27] target/m68k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 12/27] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 13/27] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 14/27] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 15/27] target/or1k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 16/27] target/ppc: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 17/27] target/riscv: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` Philippe Mathieu-Daudé [this message]
2026-10-07 9:45 ` [PATCH 19/27] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 20/27] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 21/27] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 22/27] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 23/27] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 24/27] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 25/27] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 26/27] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 27/27] target/xtensa: " Philippe Mathieu-Daudé
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