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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
	"Zhao Liu" <zhao1.liu@intel.com>
Subject: [PATCH 02/27] cpus: Introduce CPUClass::exception_name() handler
Date: Wed,  7 Oct 2026 11:44:50 +0200	[thread overview]
Message-ID: <20261007094516.75732-3-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com>

Have targets register a helper to resolve their exceptions.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
 include/hw/core/cpu.h       | 2 ++
 accel/tcg/cpu-exec-common.c | 6 ++++++
 2 files changed, 8 insertions(+)

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index 328e30045ce..1d73cc69af8 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -105,6 +105,7 @@ struct SysemuCPUOps;
  * @list_cpus: list available CPU models and flags.
  * @parse_features: Callback to parse command line arguments.
  * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
+ * @exception_name: Callback for getting architecture exception name.
  * @memory_rw_debug: Callback for GDB memory access.
  * @dump_state: Callback for dumping state.
  * @query_cpu_fast:
@@ -175,6 +176,7 @@ struct CPUClass {
     const char * (*gdb_arch_name)(CPUState *cpu);
     const char * (*gdb_get_core_xml_file)(CPUState *cpu);
 
+    const char *(*exception_name)(int exception);
     void (*disas_set_info)(const CPUState *cpu, disassemble_info *info);
 
     const char *deprecation_note;
diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c
index 2ac8380d0bb..12cac8aec3c 100644
--- a/accel/tcg/cpu-exec-common.c
+++ b/accel/tcg/cpu-exec-common.c
@@ -117,6 +117,12 @@ static void log_raise_exception(const CPUState *cpu, int excp)
     if (excp >= EXCP_QEMU_INTERNAL) {
         qemu_log_mask(CPU_LOG_INT, "raise exception: 0x%x (internal: %s)\n",
                                    excp, qemu_excp_name(excp));
+    } else {
+        const CPUClass *cc = cpu->cc;
+        const char *name = cc->exception_name ? cc->exception_name(excp)
+                                              : "undocumented";
+
+        qemu_log_mask(CPU_LOG_INT, "raise exception: %d (%s)\n", excp, name);
     }
 }
 
-- 
2.55.0



  parent reply	other threads:[~2026-10-07  9:53 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-07  9:44 [PATCH 00/27] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 01/27] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-07 10:47   ` Philippe Mathieu-Daudé
2026-10-07 11:00     ` Daniel P. Berrangé
2026-10-07 15:24       ` Yonggang Luo
2026-10-07  9:44 ` Philippe Mathieu-Daudé [this message]
2026-10-07  9:44 ` [PATCH 03/27] target/alpha: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 04/27] target/arm: " Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 05/27] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 06/27] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-09  1:34   ` Brian Cain
2026-10-07  9:44 ` [PATCH 07/27] target/hppa: " Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 08/27] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 09/27] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07  9:44 ` [PATCH 10/27] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-08  1:31   ` Bibo Mao
2026-10-07  9:44 ` [PATCH 11/27] target/m68k: " Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 12/27] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 13/27] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 14/27] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 15/27] target/or1k: " Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 16/27] target/ppc: " Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 17/27] target/riscv: " Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 18/27] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 19/27] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 20/27] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 21/27] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 22/27] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 23/27] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 24/27] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 25/27] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 26/27] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07  9:45 ` [PATCH 27/27] target/xtensa: " Philippe Mathieu-Daudé

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