From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Yoshinori Sato" <yoshinori.sato@nifty.com>
Subject: [PATCH 23/27] target/sh4: Register CPUClass::exception_name() handler
Date: Wed, 7 Oct 2026 11:45:11 +0200 [thread overview]
Message-ID: <20261007094516.75732-24-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com>
Factor sh4_exception_name() out of superh_cpu_do_interrupt()
and register it as the CPUClass::exception_name() handler,
so the common exception logging can resolve SH-4 exception
codes to names.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/sh4/helper.c | 101 +++++++++++++++++++++++---------------------
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
index 0fbd613f333..66d6b612138 100644
--- a/target/sh4/helper.c
+++ b/target/sh4/helper.c
@@ -57,6 +57,58 @@ int cpu_sh4_is_cached(CPUSH4State *env, uint32_t addr)
#else /* !CONFIG_USER_ONLY */
+static const char *sh4_exception_name(int excp)
+{
+ const char *name;
+
+ switch (excp) {
+ case SH4_EXCP_ADDR_ERROR:
+ name = "addr_error";
+ break;
+ case SH4_EXCP_TLB_MISS:
+ name = "tlb_miss";
+ break;
+ case SH4_EXCP_TLB_VIOLATION:
+ name = "tlb_violation";
+ break;
+ case SH4_EXCP_ILLEGAL_INSTRUCTION:
+ name = "illegal_instruction";
+ break;
+ case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION:
+ name = "slot_illegal_instruction";
+ break;
+ case SH4_EXCP_FPU_DISABLE:
+ name = "fpu_disable";
+ break;
+ case SH4_EXCP_SLOT_FPU_DISABLE:
+ name = "slot_fpu";
+ break;
+ case SH4_EXCP_DATA_WRITE:
+ name = "data_write";
+ break;
+ case SH4_EXCP_DTLB_MISS_WRITE:
+ name = "dtlb_miss_write";
+ break;
+ case SH4_EXCP_DTLB_VIOLATION_WRITE:
+ name = "dtlb_violation_write";
+ break;
+ case SH4_EXCP_FPU:
+ name = "fpu_exception";
+ break;
+ case SH4_EXCP_INITIAL_PAGE_WRITE:
+ name = "initial_page_write";
+ break;
+ case SH4_EXCP_TRAPA:
+ name = "trapa";
+ break;
+ default:
+ name = "???";
+ break;
+ }
+
+ return name;
+}
+
void superh_cpu_do_interrupt(CPUState *cs)
{
CPUSH4State *env = cpu_env(cs);
@@ -95,53 +147,8 @@ void superh_cpu_do_interrupt(CPUState *cs)
}
if (qemu_loglevel_mask(CPU_LOG_INT)) {
- const char *expname;
- switch (cs->exception_index) {
- case SH4_EXCP_ADDR_ERROR:
- expname = "addr_error";
- break;
- case SH4_EXCP_TLB_MISS:
- expname = "tlb_miss";
- break;
- case SH4_EXCP_TLB_VIOLATION:
- expname = "tlb_violation";
- break;
- case SH4_EXCP_ILLEGAL_INSTRUCTION:
- expname = "illegal_instruction";
- break;
- case SH4_EXCP_SLOT_ILLEGAL_INSTRUCTION:
- expname = "slot_illegal_instruction";
- break;
- case SH4_EXCP_FPU_DISABLE:
- expname = "fpu_disable";
- break;
- case SH4_EXCP_SLOT_FPU_DISABLE:
- expname = "slot_fpu";
- break;
- case SH4_EXCP_DATA_WRITE:
- expname = "data_write";
- break;
- case SH4_EXCP_DTLB_MISS_WRITE:
- expname = "dtlb_miss_write";
- break;
- case SH4_EXCP_DTLB_VIOLATION_WRITE:
- expname = "dtlb_violation_write";
- break;
- case SH4_EXCP_FPU:
- expname = "fpu_exception";
- break;
- case SH4_EXCP_INITIAL_PAGE_WRITE:
- expname = "initial_page_write";
- break;
- case SH4_EXCP_TRAPA:
- expname = "trapa";
- break;
- default:
- expname = do_irq ? "interrupt" : "???";
- break;
- }
- qemu_log("exception 0x%03x [%s] raised\n",
- irq_vector, expname);
+ qemu_log("exception 0x%03x [%s] raised\n", irq_vector,
+ do_irq ? "interrupt" : sh4_exception_name(cs->exception_index));
log_cpu_state(cs, 0);
}
--
2.55.0
next prev parent reply other threads:[~2026-10-07 9:53 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-07 9:44 [PATCH 00/27] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 01/27] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-07 10:47 ` Philippe Mathieu-Daudé
2026-10-07 11:00 ` Daniel P. Berrangé
2026-10-07 15:24 ` Yonggang Luo
2026-10-07 9:44 ` [PATCH 02/27] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 03/27] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 04/27] target/arm: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 05/27] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 06/27] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-09 1:34 ` Brian Cain
2026-10-07 9:44 ` [PATCH 07/27] target/hppa: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 08/27] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 09/27] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 10/27] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-08 1:31 ` Bibo Mao
2026-10-07 9:44 ` [PATCH 11/27] target/m68k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 12/27] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 13/27] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 14/27] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 15/27] target/or1k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 16/27] target/ppc: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 17/27] target/riscv: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 18/27] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 19/27] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 20/27] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 21/27] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 22/27] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` Philippe Mathieu-Daudé [this message]
2026-10-07 9:45 ` [PATCH 24/27] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 25/27] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 26/27] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 27/27] target/xtensa: " Philippe Mathieu-Daudé
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