From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: "Richard Henderson" <richard.henderson@linaro.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Peter Maydell" <peter.maydell@linaro.org>,
"Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>,
"Helge Deller" <deller@gmx.de>
Subject: [PATCH 07/27] target/hppa: Register CPUClass::exception_name() handler
Date: Wed, 7 Oct 2026 11:44:55 +0200 [thread overview]
Message-ID: <20261007094516.75732-8-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261007094516.75732-1-philmd@oss.qualcomm.com>
Factor hppa_exception_name() out of hppa_cpu_do_interrupt()
and register it as the CPUClass::exception_name() handler,
so the common exception logging can resolve HPPA exception
codes to names.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/hppa/cpu.h | 2 +
target/hppa/int_helper.c | 91 ++++++++++++++++++++--------------------
2 files changed, 48 insertions(+), 45 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index f453444d7f9..3914b3285c5 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -98,6 +98,8 @@
/* Emulated hardware TOC button */
#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
+const char *hppa_exception_name(int excp);
+
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index 3e87b9a0011..ad240ab8b2e 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -90,6 +90,49 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val)
bql_unlock();
}
+const char *hppa_exception_name(int excp)
+{
+ static const char * const excp_names[] = {
+ [EXCP_HPMC] = "high priority machine check",
+ [EXCP_POWER_FAIL] = "power fail interrupt",
+ [EXCP_RC] = "recovery counter trap",
+ [EXCP_EXT_INTERRUPT] = "external interrupt",
+ [EXCP_LPMC] = "low priority machine check",
+ [EXCP_ITLB_MISS] = "instruction tlb miss fault",
+ [EXCP_IMP] = "instruction memory protection trap",
+ [EXCP_ILL] = "illegal instruction trap",
+ [EXCP_BREAK] = "break instruction trap",
+ [EXCP_PRIV_OPR] = "privileged operation trap",
+ [EXCP_PRIV_REG] = "privileged register trap",
+ [EXCP_OVERFLOW] = "overflow trap",
+ [EXCP_COND] = "conditional trap",
+ [EXCP_ASSIST] = "assist exception trap",
+ [EXCP_DTLB_MISS] = "data tlb miss fault",
+ [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
+ [EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
+ [EXCP_DMP] = "data memory protection trap",
+ [EXCP_DMB] = "data memory break trap",
+ [EXCP_TLB_DIRTY] = "tlb dirty bit trap",
+ [EXCP_PAGE_REF] = "page reference trap",
+ [EXCP_ASSIST_EMU] = "assist emulation trap",
+ [EXCP_HPT] = "high-privilege transfer trap",
+ [EXCP_LPT] = "low-privilege transfer trap",
+ [EXCP_TB] = "taken branch trap",
+ [EXCP_DMAR] = "data memory access rights trap",
+ [EXCP_DMPI] = "data memory protection id trap",
+ [EXCP_UNALIGN] = "unaligned data reference trap",
+ [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
+ [EXCP_SYSCALL] = "syscall",
+ [EXCP_SYSCALL_LWS] = "syscall-lws",
+ [EXCP_TOC] = "TOC (transfer of control)",
+ };
+
+ if (excp < 0 || excp >= ARRAY_SIZE(excp_names) || !excp_names[excp]) {
+ return "unknown";
+ }
+ return excp_names[excp];
+}
+
void hppa_cpu_do_interrupt(CPUState *cs)
{
HPPACPU *cpu = HPPA_CPU(cs);
@@ -235,53 +278,11 @@ void hppa_cpu_do_interrupt(CPUState *cs)
}
if (qemu_loglevel_mask(CPU_LOG_INT)) {
- static const char * const names[] = {
- [EXCP_HPMC] = "high priority machine check",
- [EXCP_POWER_FAIL] = "power fail interrupt",
- [EXCP_RC] = "recovery counter trap",
- [EXCP_EXT_INTERRUPT] = "external interrupt",
- [EXCP_LPMC] = "low priority machine check",
- [EXCP_ITLB_MISS] = "instruction tlb miss fault",
- [EXCP_IMP] = "instruction memory protection trap",
- [EXCP_ILL] = "illegal instruction trap",
- [EXCP_BREAK] = "break instruction trap",
- [EXCP_PRIV_OPR] = "privileged operation trap",
- [EXCP_PRIV_REG] = "privileged register trap",
- [EXCP_OVERFLOW] = "overflow trap",
- [EXCP_COND] = "conditional trap",
- [EXCP_ASSIST] = "assist exception trap",
- [EXCP_DTLB_MISS] = "data tlb miss fault",
- [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
- [EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
- [EXCP_DMP] = "data memory protection trap",
- [EXCP_DMB] = "data memory break trap",
- [EXCP_TLB_DIRTY] = "tlb dirty bit trap",
- [EXCP_PAGE_REF] = "page reference trap",
- [EXCP_ASSIST_EMU] = "assist emulation trap",
- [EXCP_HPT] = "high-privilege transfer trap",
- [EXCP_LPT] = "low-privilege transfer trap",
- [EXCP_TB] = "taken branch trap",
- [EXCP_DMAR] = "data memory access rights trap",
- [EXCP_DMPI] = "data memory protection id trap",
- [EXCP_UNALIGN] = "unaligned data reference trap",
- [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
- [EXCP_SYSCALL] = "syscall",
- [EXCP_SYSCALL_LWS] = "syscall-lws",
- [EXCP_TOC] = "TOC (transfer of control)",
- };
-
FILE *logfile = qemu_log_trylock();
if (logfile) {
- const char *name = NULL;
-
- if (i >= 0 && i < ARRAY_SIZE(names)) {
- name = names[i];
- }
- if (name) {
- fprintf(logfile, "INT: cpu %d %s\n", cs->cpu_index, name);
- } else {
- fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i);
- }
+ const char *name = hppa_exception_name(i);
+ fprintf(logfile, "INT: cpu %d excp %d (%s)\n",
+ cs->cpu_index, i, name);
hppa_cpu_dump_state(cs, logfile, 0);
qemu_log_unlock(logfile);
}
--
2.55.0
next prev parent reply other threads:[~2026-10-07 9:54 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-07 9:44 [PATCH 00/27] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 01/27] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-07 10:47 ` Philippe Mathieu-Daudé
2026-10-07 11:00 ` Daniel P. Berrangé
2026-10-07 15:24 ` Yonggang Luo
2026-10-07 9:44 ` [PATCH 02/27] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 03/27] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 04/27] target/arm: " Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 05/27] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 06/27] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-09 1:34 ` Brian Cain
2026-10-07 9:44 ` Philippe Mathieu-Daudé [this message]
2026-10-07 9:44 ` [PATCH 08/27] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 09/27] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:44 ` [PATCH 10/27] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-08 1:31 ` Bibo Mao
2026-10-07 9:44 ` [PATCH 11/27] target/m68k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 12/27] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 13/27] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 14/27] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 15/27] target/or1k: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 16/27] target/ppc: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 17/27] target/riscv: " Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 18/27] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 19/27] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 20/27] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 21/27] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 22/27] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 23/27] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 24/27] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 25/27] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 26/27] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-07 9:45 ` [PATCH 27/27] target/xtensa: " Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261007094516.75732-8-philmd@oss.qualcomm.com \
--to=philmd@oss.qualcomm.com \
--cc=deller@gmx.de \
--cc=pbonzini@redhat.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.