From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
qemu-s390x@nongnu.org,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH v2 09/33] target/hppa: Register CPUClass::exception_name() handler
Date: Wed, 21 Oct 2026 05:13:42 +0200 [thread overview]
Message-ID: <20261021031407.24862-10-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com>
Factor hppa_exception_name() out of hppa_cpu_do_interrupt()
and register it as the CPUClass::exception_name() handler,
so the common exception logging can resolve HPPA exception
codes to names.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
target/hppa/cpu.h | 2 +
target/hppa/cpu.c | 1 +
target/hppa/int_helper.c | 88 ++++++++++++++++++++--------------------
3 files changed, 46 insertions(+), 45 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index f453444d7f9..3914b3285c5 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -98,6 +98,8 @@
/* Emulated hardware TOC button */
#define EXCP_TOC 32 /* TOC = Transfer of control (NMI) */
+const char *hppa_exception_name(int excp);
+
#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 /* TOC */
/* Taken from Linux kernel: arch/parisc/include/asm/psw.h */
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
index 07b49e51326..81eef6a2fc7 100644
--- a/target/hppa/cpu.c
+++ b/target/hppa/cpu.c
@@ -305,6 +305,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, const void *data)
&acc->parent_phases);
cc->class_by_name = hppa_cpu_class_by_name;
+ cc->exception_name = hppa_exception_name;
cc->dump_state = hppa_cpu_dump_state;
cc->set_pc = hppa_cpu_set_pc;
cc->get_pc = hppa_cpu_get_pc;
diff --git a/target/hppa/int_helper.c b/target/hppa/int_helper.c
index 3e87b9a0011..e4297461d55 100644
--- a/target/hppa/int_helper.c
+++ b/target/hppa/int_helper.c
@@ -90,6 +90,46 @@ void HELPER(write_eirr)(CPUHPPAState *env, target_ulong val)
bql_unlock();
}
+const char *hppa_exception_name(int excp)
+{
+ static const char * const excp_names[] = {
+ [EXCP_HPMC] = "high priority machine check",
+ [EXCP_POWER_FAIL] = "power fail interrupt",
+ [EXCP_RC] = "recovery counter trap",
+ [EXCP_EXT_INTERRUPT] = "external interrupt",
+ [EXCP_LPMC] = "low priority machine check",
+ [EXCP_ITLB_MISS] = "instruction tlb miss fault",
+ [EXCP_IMP] = "instruction memory protection trap",
+ [EXCP_ILL] = "illegal instruction trap",
+ [EXCP_BREAK] = "break instruction trap",
+ [EXCP_PRIV_OPR] = "privileged operation trap",
+ [EXCP_PRIV_REG] = "privileged register trap",
+ [EXCP_OVERFLOW] = "overflow trap",
+ [EXCP_COND] = "conditional trap",
+ [EXCP_ASSIST] = "assist exception trap",
+ [EXCP_DTLB_MISS] = "data tlb miss fault",
+ [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
+ [EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
+ [EXCP_DMP] = "data memory protection trap",
+ [EXCP_DMB] = "data memory break trap",
+ [EXCP_TLB_DIRTY] = "tlb dirty bit trap",
+ [EXCP_PAGE_REF] = "page reference trap",
+ [EXCP_ASSIST_EMU] = "assist emulation trap",
+ [EXCP_HPT] = "high-privilege transfer trap",
+ [EXCP_LPT] = "low-privilege transfer trap",
+ [EXCP_TB] = "taken branch trap",
+ [EXCP_DMAR] = "data memory access rights trap",
+ [EXCP_DMPI] = "data memory protection id trap",
+ [EXCP_UNALIGN] = "unaligned data reference trap",
+ [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
+ [EXCP_SYSCALL] = "syscall",
+ [EXCP_SYSCALL_LWS] = "syscall-lws",
+ [EXCP_TOC] = "TOC (transfer of control)",
+ };
+
+ return ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown";
+}
+
void hppa_cpu_do_interrupt(CPUState *cs)
{
HPPACPU *cpu = HPPA_CPU(cs);
@@ -235,53 +275,11 @@ void hppa_cpu_do_interrupt(CPUState *cs)
}
if (qemu_loglevel_mask(CPU_LOG_INT)) {
- static const char * const names[] = {
- [EXCP_HPMC] = "high priority machine check",
- [EXCP_POWER_FAIL] = "power fail interrupt",
- [EXCP_RC] = "recovery counter trap",
- [EXCP_EXT_INTERRUPT] = "external interrupt",
- [EXCP_LPMC] = "low priority machine check",
- [EXCP_ITLB_MISS] = "instruction tlb miss fault",
- [EXCP_IMP] = "instruction memory protection trap",
- [EXCP_ILL] = "illegal instruction trap",
- [EXCP_BREAK] = "break instruction trap",
- [EXCP_PRIV_OPR] = "privileged operation trap",
- [EXCP_PRIV_REG] = "privileged register trap",
- [EXCP_OVERFLOW] = "overflow trap",
- [EXCP_COND] = "conditional trap",
- [EXCP_ASSIST] = "assist exception trap",
- [EXCP_DTLB_MISS] = "data tlb miss fault",
- [EXCP_NA_ITLB_MISS] = "non-access instruction tlb miss",
- [EXCP_NA_DTLB_MISS] = "non-access data tlb miss",
- [EXCP_DMP] = "data memory protection trap",
- [EXCP_DMB] = "data memory break trap",
- [EXCP_TLB_DIRTY] = "tlb dirty bit trap",
- [EXCP_PAGE_REF] = "page reference trap",
- [EXCP_ASSIST_EMU] = "assist emulation trap",
- [EXCP_HPT] = "high-privilege transfer trap",
- [EXCP_LPT] = "low-privilege transfer trap",
- [EXCP_TB] = "taken branch trap",
- [EXCP_DMAR] = "data memory access rights trap",
- [EXCP_DMPI] = "data memory protection id trap",
- [EXCP_UNALIGN] = "unaligned data reference trap",
- [EXCP_PER_INTERRUPT] = "performance monitor interrupt",
- [EXCP_SYSCALL] = "syscall",
- [EXCP_SYSCALL_LWS] = "syscall-lws",
- [EXCP_TOC] = "TOC (transfer of control)",
- };
-
FILE *logfile = qemu_log_trylock();
if (logfile) {
- const char *name = NULL;
-
- if (i >= 0 && i < ARRAY_SIZE(names)) {
- name = names[i];
- }
- if (name) {
- fprintf(logfile, "INT: cpu %d %s\n", cs->cpu_index, name);
- } else {
- fprintf(logfile, "INT: cpu %d unknown %d\n", cs->cpu_index, i);
- }
+ const char *name = hppa_exception_name(i);
+ fprintf(logfile, "INT: cpu %d excp %d (%s)\n",
+ cs->cpu_index, i, name);
hppa_cpu_dump_state(cs, logfile, 0);
qemu_log_unlock(logfile);
}
--
2.55.0
next prev parent reply other threads:[~2026-10-21 3:17 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 3:13 [PATCH v2 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 01/33] qemu/osdep: Add ARRAY_ELEM_OR_NULL() macro Philippe Mathieu-Daudé
2026-10-21 16:18 ` Pierrick Bouvier
2026-10-21 16:19 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 02/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-21 16:22 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 03/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 04/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 05/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:19 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 06/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 07/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 08/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` Philippe Mathieu-Daudé [this message]
2026-10-21 3:13 ` [PATCH v2 10/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 11/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 12/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 13/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 14/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:20 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 15/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 16/33] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 17/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 18/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 19/33] target/ppc: Dump EBB exceptions names Philippe Mathieu-Daudé
2026-10-21 16:22 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 20/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-21 16:21 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 22/33] target/riscv: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 23/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 24/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 25/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 26/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 27/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 28/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 29/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:21 ` Pierrick Bouvier
2026-10-21 3:14 ` [PATCH v2 30/33] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 31/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 32/33] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 33/33] target/xtensa: " Philippe Mathieu-Daudé
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261021031407.24862-10-philmd@oss.qualcomm.com \
--to=philmd@oss.qualcomm.com \
--cc=pierrick.bouvier@oss.qualcomm.com \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=qemu-s390x@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.