From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
qemu-s390x@nongnu.org,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH v2 14/33] target/m68k: Use a static table in m68k_exception_name()
Date: Wed, 21 Oct 2026 05:13:47 +0200 [thread overview]
Message-ID: <20261021031407.24862-15-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com>
Replace the switch statement with a static lookup table.
Suggested-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
---
target/m68k/op_helper.c | 152 ++++++++++++++--------------------------
1 file changed, 53 insertions(+), 99 deletions(-)
diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c
index c600f83ddbf..6a4eafddb31 100644
--- a/target/m68k/op_helper.c
+++ b/target/m68k/op_helper.c
@@ -84,107 +84,61 @@ throwaway:
const char *m68k_exception_name(int excp)
{
- switch (excp) {
- case EXCP_ACCESS:
- return "Access Fault";
- case EXCP_ADDRESS:
- return "Address Error";
- case EXCP_ILLEGAL:
- return "Illegal Instruction";
- case EXCP_DIV0:
- return "Divide by Zero";
- case EXCP_CHK:
- return "CHK/CHK2";
- case EXCP_TRAPCC:
- return "FTRAPcc, TRAPcc, TRAPV";
- case EXCP_PRIVILEGE:
- return "Privilege Violation";
- case EXCP_TRACE:
- return "Trace";
- case EXCP_LINEA:
- return "A-Line";
- case EXCP_LINEF:
- return "F-Line";
- case EXCP_DEBEGBP: /* 68020/030 only */
- return "Copro Protocol Violation";
- case EXCP_FORMAT:
- return "Format Error";
- case EXCP_UNINITIALIZED:
- return "Uninitialized Interrupt";
- case EXCP_SPURIOUS:
- return "Spurious Interrupt";
- case EXCP_INT_LEVEL_1:
- return "Level 1 Interrupt";
- case EXCP_INT_LEVEL_1 + 1:
- return "Level 2 Interrupt";
- case EXCP_INT_LEVEL_1 + 2:
- return "Level 3 Interrupt";
- case EXCP_INT_LEVEL_1 + 3:
- return "Level 4 Interrupt";
- case EXCP_INT_LEVEL_1 + 4:
- return "Level 5 Interrupt";
- case EXCP_INT_LEVEL_1 + 5:
- return "Level 6 Interrupt";
- case EXCP_INT_LEVEL_1 + 6:
- return "Level 7 Interrupt";
- case EXCP_TRAP0:
- return "TRAP #0";
- case EXCP_TRAP0 + 1:
- return "TRAP #1";
- case EXCP_TRAP0 + 2:
- return "TRAP #2";
- case EXCP_TRAP0 + 3:
- return "TRAP #3";
- case EXCP_TRAP0 + 4:
- return "TRAP #4";
- case EXCP_TRAP0 + 5:
- return "TRAP #5";
- case EXCP_TRAP0 + 6:
- return "TRAP #6";
- case EXCP_TRAP0 + 7:
- return "TRAP #7";
- case EXCP_TRAP0 + 8:
- return "TRAP #8";
- case EXCP_TRAP0 + 9:
- return "TRAP #9";
- case EXCP_TRAP0 + 10:
- return "TRAP #10";
- case EXCP_TRAP0 + 11:
- return "TRAP #11";
- case EXCP_TRAP0 + 12:
- return "TRAP #12";
- case EXCP_TRAP0 + 13:
- return "TRAP #13";
- case EXCP_TRAP0 + 14:
- return "TRAP #14";
- case EXCP_TRAP0 + 15:
- return "TRAP #15";
- case EXCP_FP_BSUN:
- return "FP Branch/Set on unordered condition";
- case EXCP_FP_INEX:
- return "FP Inexact Result";
- case EXCP_FP_DZ:
- return "FP Divide by Zero";
- case EXCP_FP_UNFL:
- return "FP Underflow";
- case EXCP_FP_OPERR:
- return "FP Operand Error";
- case EXCP_FP_OVFL:
- return "FP Overflow";
- case EXCP_FP_SNAN:
- return "FP Signaling NAN";
- case EXCP_FP_UNIMP:
- return "FP Unimplemented Data Type";
- case EXCP_MMU_CONF: /* 68030/68851 only */
- return "MMU Configuration Error";
- case EXCP_MMU_ILLEGAL: /* 68851 only */
- return "MMU Illegal Operation";
- case EXCP_MMU_ACCESS: /* 68851 only */
- return "MMU Access Level Violation";
- case 64 ... 255:
+ static const char * const excp_names[] = {
+ [EXCP_ACCESS] = "Access Fault",
+ [EXCP_ADDRESS] = "Address Error",
+ [EXCP_ILLEGAL] = "Illegal Instruction",
+ [EXCP_DIV0] = "Divide by Zero",
+ [EXCP_CHK] = "CHK/CHK2",
+ [EXCP_TRAPCC] = "FTRAPcc, TRAPcc, TRAPV",
+ [EXCP_PRIVILEGE] = "Privilege Violation",
+ [EXCP_TRACE] = "Trace",
+ [EXCP_LINEA] = "A-Line",
+ [EXCP_LINEF] = "F-Line",
+ [EXCP_DEBEGBP] = "Copro Protocol Violation", /* 68020/030 only */
+ [EXCP_FORMAT] = "Format Error",
+ [EXCP_UNINITIALIZED] = "Uninitialized Interrupt",
+ [EXCP_SPURIOUS] = "Spurious Interrupt",
+ [EXCP_INT_LEVEL_1] = "Level 1 Interrupt",
+ [EXCP_INT_LEVEL_1 + 1] = "Level 2 Interrupt",
+ [EXCP_INT_LEVEL_1 + 2] = "Level 3 Interrupt",
+ [EXCP_INT_LEVEL_1 + 3] = "Level 4 Interrupt",
+ [EXCP_INT_LEVEL_1 + 4] = "Level 5 Interrupt",
+ [EXCP_INT_LEVEL_1 + 5] = "Level 6 Interrupt",
+ [EXCP_INT_LEVEL_1 + 6] = "Level 7 Interrupt",
+ [EXCP_TRAP0] = "TRAP #0",
+ [EXCP_TRAP0 + 1] = "TRAP #1",
+ [EXCP_TRAP0 + 2] = "TRAP #2",
+ [EXCP_TRAP0 + 3] = "TRAP #3",
+ [EXCP_TRAP0 + 4] = "TRAP #4",
+ [EXCP_TRAP0 + 5] = "TRAP #5",
+ [EXCP_TRAP0 + 6] = "TRAP #6",
+ [EXCP_TRAP0 + 7] = "TRAP #7",
+ [EXCP_TRAP0 + 8] = "TRAP #8",
+ [EXCP_TRAP0 + 9] = "TRAP #9",
+ [EXCP_TRAP0 + 10] = "TRAP #10",
+ [EXCP_TRAP0 + 11] = "TRAP #11",
+ [EXCP_TRAP0 + 12] = "TRAP #12",
+ [EXCP_TRAP0 + 13] = "TRAP #13",
+ [EXCP_TRAP0 + 14] = "TRAP #14",
+ [EXCP_TRAP0 + 15] = "TRAP #15",
+ [EXCP_FP_BSUN] = "FP Branch/Set on unordered condition",
+ [EXCP_FP_INEX] = "FP Inexact Result",
+ [EXCP_FP_DZ] = "FP Divide by Zero",
+ [EXCP_FP_UNFL] = "FP Underflow",
+ [EXCP_FP_OPERR] = "FP Operand Error",
+ [EXCP_FP_OVFL] = "FP Overflow",
+ [EXCP_FP_SNAN] = "FP Signaling NAN",
+ [EXCP_FP_UNIMP] = "FP Unimplemented Data Type",
+ [EXCP_MMU_CONF] = "MMU Configuration Error", /* 68030/68851 only */
+ [EXCP_MMU_ILLEGAL] = "MMU Illegal Operation", /* 68851 only */
+ [EXCP_MMU_ACCESS] = "MMU Access Level Violation", /* 68851 only */
+ };
+
+ if (excp >= 64 && excp <= 255) {
return "User Defined Vector";
}
- return "Unassigned";
+ return ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "Unassigned";
}
#ifndef CONFIG_USER_ONLY
--
2.55.0
next prev parent reply other threads:[~2026-10-21 3:18 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 3:13 [PATCH v2 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 01/33] qemu/osdep: Add ARRAY_ELEM_OR_NULL() macro Philippe Mathieu-Daudé
2026-10-21 16:18 ` Pierrick Bouvier
2026-10-21 16:19 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 02/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-21 16:22 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 03/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 04/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 05/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:19 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 06/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 07/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 08/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 09/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 10/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 11/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 12/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 13/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` Philippe Mathieu-Daudé [this message]
2026-10-21 16:20 ` [PATCH v2 14/33] target/m68k: Use a static table in m68k_exception_name() Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 15/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 16/33] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 17/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 18/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 19/33] target/ppc: Dump EBB exceptions names Philippe Mathieu-Daudé
2026-10-21 16:22 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 20/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-21 16:21 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 22/33] target/riscv: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 23/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 24/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 25/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 26/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 27/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 28/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 29/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:21 ` Pierrick Bouvier
2026-10-21 3:14 ` [PATCH v2 30/33] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 31/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 32/33] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 33/33] target/xtensa: " Philippe Mathieu-Daudé
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