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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
	qemu-s390x@nongnu.org,
	Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH v2 23/33] target/rx: Unify BRK and INT trap handling
Date: Wed, 21 Oct 2026 05:13:56 +0200	[thread overview]
Message-ID: <20261021031407.24862-24-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com>

BRK is equivalent to INT #0, so route both instructions
through the same trap helper.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Yoshinori Sato <yoshinori.sato@nifty.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/rx/helper.h    |  3 +--
 target/rx/op_helper.c |  7 +------
 target/rx/translate.c | 21 ++++++++++-----------
 3 files changed, 12 insertions(+), 19 deletions(-)

diff --git a/target/rx/helper.h b/target/rx/helper.h
index b1ef843be1e..13f019ff81a 100644
--- a/target/rx/helper.h
+++ b/target/rx/helper.h
@@ -2,8 +2,7 @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
 DEF_HELPER_1(raise_access_fault, noreturn, env)
 DEF_HELPER_1(raise_privilege_violation, noreturn, env)
 DEF_HELPER_1(wait, noreturn, env)
-DEF_HELPER_2(rxint, noreturn, env, i32)
-DEF_HELPER_1(rxbrk, noreturn, env)
+DEF_HELPER_2(trap, noreturn, env, i32)
 DEF_HELPER_3(rx_fadd, f32, env, f32, f32)
 DEF_HELPER_3(rx_fsub, f32, env, f32, f32)
 DEF_HELPER_3(rx_fmul, f32, env, f32, f32)
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
index 5a7a87943fe..fb1fa4ffa69 100644
--- a/target/rx/op_helper.c
+++ b/target/rx/op_helper.c
@@ -455,12 +455,7 @@ G_NORETURN void helper_wait(CPURXState *env)
     raise_exception(env, EXCP_HLT, 0);
 }
 
-G_NORETURN void helper_rxint(CPURXState *env, uint32_t vec)
+G_NORETURN void helper_trap(CPURXState *env, uint32_t vec)
 {
     raise_exception(env, 0x100 + vec, 0);
 }
-
-G_NORETURN void helper_rxbrk(CPURXState *env)
-{
-    raise_exception(env, 0x100, 0);
-}
diff --git a/target/rx/translate.c b/target/rx/translate.c
index bd445bc0634..0672c5c5653 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2170,26 +2170,25 @@ static bool trans_RTE(DisasContext *ctx, arg_RTE *a)
     return true;
 }
 
+static bool do_trap(DisasContext *ctx, uint8_t vec)
+{
+    tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
+    gen_helper_trap(tcg_env, tcg_constant_i32(vec));
+    ctx->base.is_jmp = DISAS_NORETURN;
+    return true;
+}
+
 /* brk */
 static bool trans_BRK(DisasContext *ctx, arg_BRK *a)
 {
-    tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
-    gen_helper_rxbrk(tcg_env);
-    ctx->base.is_jmp = DISAS_NORETURN;
-    return true;
+    return do_trap(ctx, 0);
 }
 
 /* int #imm */
 static bool trans_INT(DisasContext *ctx, arg_INT *a)
 {
-    TCGv_i32 vec;
-
     tcg_debug_assert(a->imm < 0x100);
-    vec = tcg_constant_i32(a->imm);
-    tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
-    gen_helper_rxint(tcg_env, vec);
-    ctx->base.is_jmp = DISAS_NORETURN;
-    return true;
+    return do_trap(ctx, a->imm);
 }
 
 /* wait */
-- 
2.55.0



  parent reply	other threads:[~2026-10-21  3:20 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-21  3:13 [PATCH v2 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 01/33] qemu/osdep: Add ARRAY_ELEM_OR_NULL() macro Philippe Mathieu-Daudé
2026-10-21 16:18   ` Pierrick Bouvier
2026-10-21 16:19     ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 02/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-21 16:22   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 03/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 04/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 05/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:19   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 06/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 07/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 08/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 09/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 10/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 11/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 12/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 13/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 14/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:20   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 15/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 16/33] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 17/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 18/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 19/33] target/ppc: Dump EBB exceptions names Philippe Mathieu-Daudé
2026-10-21 16:22   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 20/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-21 16:21   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 22/33] target/riscv: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` Philippe Mathieu-Daudé [this message]
2026-10-21  3:13 ` [PATCH v2 24/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 25/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 26/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 27/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 28/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 29/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:21   ` Pierrick Bouvier
2026-10-21  3:14 ` [PATCH v2 30/33] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 31/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 32/33] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 33/33] target/xtensa: " Philippe Mathieu-Daudé

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