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From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
	qemu-s390x@nongnu.org,
	Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH v2 31/33] target/sparc: Register CPUClass::exception_name() handler
Date: Wed, 21 Oct 2026 05:14:04 +0200	[thread overview]
Message-ID: <20261021031407.24862-32-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com>

For each SPARC / SPARC64 target:
factor sparc_exception_name() out of sparc_cpu_do_interrupt()
and register it as the CPUClass::exception_name() handler, so
the common exception logging can resolve SPARC exception codes
to names.

Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
---
 target/sparc/cpu.h          |  1 +
 target/sparc/cpu.c          |  1 +
 target/sparc/int32_helper.c | 21 +++++++--------------
 target/sparc/int64_helper.c | 36 ++++++++++++++++++------------------
 4 files changed, 27 insertions(+), 32 deletions(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 31a16c2af03..3c1ba223eb2 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -583,6 +583,7 @@ extern const VMStateDescription vmstate_sparc_cpu;
 hwaddr sparc_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
 #endif
 
+const char *sparc_exception_name(int excp);
 void sparc_cpu_do_interrupt(CPUState *cpu);
 int sparc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
 int sparc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
index ae9bdca9df8..1f9a62a8c76 100644
--- a/target/sparc/cpu.c
+++ b/target/sparc/cpu.c
@@ -1098,6 +1098,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, const void *data)
                                        &scc->parent_phases);
 
     cc->class_by_name = sparc_cpu_class_by_name;
+    cc->exception_name = sparc_exception_name;
     cc->list_cpus = sparc_cpu_list,
     cc->parse_features = sparc_cpu_parse_features;
     cc->dump_state = sparc_cpu_dump_state;
diff --git a/target/sparc/int32_helper.c b/target/sparc/int32_helper.c
index d6bb3fa1e54..6db5aee81c5 100644
--- a/target/sparc/int32_helper.c
+++ b/target/sparc/int32_helper.c
@@ -58,12 +58,12 @@ static const char * const excp_names[0x80] = {
     [TT_NCP_INSN] = "Coprocessor Disabled",
 };
 
-static const char *excp_name_str(int32_t exception_index)
+const char *sparc_exception_name(int excp)
 {
-    if (exception_index < 0 || exception_index >= ARRAY_SIZE(excp_names)) {
-        return "Unknown";
+    if (excp >= 0x80 && excp < 0x100) {
+        return "Trap Instruction";
     }
-    return excp_names[exception_index];
+    return ARRAY_ELEM_OR_NULL(excp_names, excp) ?: "unknown";
 }
 
 #if !defined(CONFIG_USER_ONLY)
@@ -107,15 +107,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
 
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
         static int count;
-        const char *name;
-
-        if (intno < 0 || intno >= 0x100) {
-            name = "Unknown";
-        } else if (intno >= 0x80) {
-            name = "Trap Instruction";
-        } else {
-            name = excp_name_str(intno);
-        }
+        const char *name = sparc_exception_name(intno);
 
         qemu_log("%6d: %s (v=%02x)\n", count, name, intno);
         log_cpu_state(cs, 0);
@@ -129,7 +121,8 @@ void sparc_cpu_do_interrupt(CPUState *cs)
         } else {
             cpu_abort(cs, "Trap 0x%02x (%s) while interrupts disabled, "
                           "Error state",
-                      cs->exception_index, excp_name_str(cs->exception_index));
+                      cs->exception_index,
+                      sparc_exception_name(cs->exception_index));
         }
         return;
     }
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index 10341e0c282..aa4002e74da 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -60,6 +60,23 @@ static const char * const excp_names[0x80] = {
     [TT_EXTINT | 0xf] = "External Interrupt 15",
 };
 
+const char *sparc_exception_name(int excp)
+{
+    QEMU_BUILD_BUG_ON(ARRAY_SIZE(excp_names) > 0x200);
+    if (excp < 0 || excp >= 0x200) {
+        return "unknown";
+    } else if (excp >= 0x180) {
+        return "Hyperprivileged Trap Instruction";
+    } else if (excp >= 0x100) {
+        return "Trap Instruction";
+    } else if (excp >= 0xc0) {
+        return "Window Fill";
+    } else if (excp >= 0x80) {
+        return "Window Spill";
+    }
+    return excp_names[excp] ?: "unknown";
+}
+
 #if !defined(CONFIG_USER_ONLY)
 void cpu_check_irqs(CPUSPARCState *env)
 {
@@ -136,24 +153,7 @@ void sparc_cpu_do_interrupt(CPUState *cs)
 
     if (qemu_loglevel_mask(CPU_LOG_INT)) {
         static int count;
-        const char *name;
-
-        if (intno < 0 || intno >= 0x1ff) {
-            name = "Unknown";
-        } else if (intno >= 0x180) {
-            name = "Hyperprivileged Trap Instruction";
-        } else if (intno >= 0x100) {
-            name = "Trap Instruction";
-        } else if (intno >= 0xc0) {
-            name = "Window Fill";
-        } else if (intno >= 0x80) {
-            name = "Window Spill";
-        } else {
-            name = excp_names[intno];
-            if (!name) {
-                name = "Unknown";
-            }
-        }
+        const char *name = sparc_exception_name(intno);
 
         qemu_log("%6d: %s (v=%04x)\n", count, name, intno);
         log_cpu_state(cs, 0);
-- 
2.55.0



  parent reply	other threads:[~2026-10-21  3:21 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-21  3:13 [PATCH v2 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 01/33] qemu/osdep: Add ARRAY_ELEM_OR_NULL() macro Philippe Mathieu-Daudé
2026-10-21 16:18   ` Pierrick Bouvier
2026-10-21 16:19     ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 02/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-21 16:22   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 03/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 04/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 05/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:19   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 06/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 07/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 08/33] target/hexagon: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 09/33] target/hppa: " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 10/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 11/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 12/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 13/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 14/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:20   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 15/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 16/33] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 17/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 18/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 19/33] target/ppc: Dump EBB exceptions names Philippe Mathieu-Daudé
2026-10-21 16:22   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 20/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-21 16:21   ` Pierrick Bouvier
2026-10-21  3:13 ` [PATCH v2 22/33] target/riscv: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 23/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 24/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 25/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:13 ` [PATCH v2 26/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 27/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 28/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 29/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:21   ` Pierrick Bouvier
2026-10-21  3:14 ` [PATCH v2 30/33] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-21  3:14 ` Philippe Mathieu-Daudé [this message]
2026-10-21  3:14 ` [PATCH v2 32/33] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21  3:14 ` [PATCH v2 33/33] target/xtensa: " Philippe Mathieu-Daudé

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