From: "Philippe Mathieu-Daudé" <philmd@oss.qualcomm.com>
To: qemu-devel@nongnu.org
Cc: qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org,
qemu-s390x@nongnu.org,
Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Subject: [PATCH v2 08/33] target/hexagon: Register CPUClass::exception_name() handler
Date: Wed, 21 Oct 2026 05:13:41 +0200 [thread overview]
Message-ID: <20261021031407.24862-9-philmd@oss.qualcomm.com> (raw)
In-Reply-To: <20261021031407.24862-1-philmd@oss.qualcomm.com>
Expose the hexagon event_name[] array via a hexagon_event_name()
helper and register it as the CPUClass::exception_name() handler,
so the common exception logging can resolve Hexagon exception
codes to names.
Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
target/hexagon/cpu_bits.h | 2 ++
target/hexagon/cpu.c | 34 ++++++++++++++++++++++++++++++++++
target/hexagon/hexswi.c | 30 +-----------------------------
3 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h
index a8fba4aa188..7d1bdfcbc71 100644
--- a/target/hexagon/cpu_bits.h
+++ b/target/hexagon/cpu_bits.h
@@ -61,6 +61,8 @@ enum hex_event {
HEX_EVENT_INTF = 0x1f,
};
+const char *hexagon_event_name(int event);
+
enum hex_cause {
HEX_CAUSE_NONE = -1,
HEX_CAUSE_RESET = 0x000,
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index f20d6de6f63..962f00bc36c 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -318,6 +318,39 @@ void hexagon_debug(CPUHexagonState *env)
hexagon_dump(env, stdout, CPU_DUMP_FPU);
}
+const char *hexagon_event_name(int event)
+{
+ static const char *event_name[] = {
+ [HEX_EVENT_RESET] = "HEX_EVENT_RESET",
+ [HEX_EVENT_IMPRECISE] = "HEX_EVENT_IMPRECISE",
+ [HEX_EVENT_PRECISE] = "HEX_EVENT_PRECISE",
+ [HEX_EVENT_TLB_MISS_X] = "HEX_EVENT_TLB_MISS_X",
+ [HEX_EVENT_TLB_MISS_RW] = "HEX_EVENT_TLB_MISS_RW",
+ [HEX_EVENT_TRAP0] = "HEX_EVENT_TRAP0",
+ [HEX_EVENT_TRAP1] = "HEX_EVENT_TRAP1",
+ [HEX_EVENT_FPTRAP] = "HEX_EVENT_FPTRAP",
+ [HEX_EVENT_DEBUG] = "HEX_EVENT_DEBUG",
+ [HEX_EVENT_INT0] = "HEX_EVENT_INT0",
+ [HEX_EVENT_INT1] = "HEX_EVENT_INT1",
+ [HEX_EVENT_INT2] = "HEX_EVENT_INT2",
+ [HEX_EVENT_INT3] = "HEX_EVENT_INT3",
+ [HEX_EVENT_INT4] = "HEX_EVENT_INT4",
+ [HEX_EVENT_INT5] = "HEX_EVENT_INT5",
+ [HEX_EVENT_INT6] = "HEX_EVENT_INT6",
+ [HEX_EVENT_INT7] = "HEX_EVENT_INT7",
+ [HEX_EVENT_INT8] = "HEX_EVENT_INT8",
+ [HEX_EVENT_INT9] = "HEX_EVENT_INT9",
+ [HEX_EVENT_INTA] = "HEX_EVENT_INTA",
+ [HEX_EVENT_INTB] = "HEX_EVENT_INTB",
+ [HEX_EVENT_INTC] = "HEX_EVENT_INTC",
+ [HEX_EVENT_INTD] = "HEX_EVENT_INTD",
+ [HEX_EVENT_INTE] = "HEX_EVENT_INTE",
+ [HEX_EVENT_INTF] = "HEX_EVENT_INTF",
+ };
+
+ return ARRAY_ELEM_OR_NULL(event_name, event) ?: "unknown";
+}
+
static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
{
cpu_env(cs)->gpr[HEX_REG_PC] = value;
@@ -841,6 +874,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data)
&mcc->parent_phases);
cc->class_by_name = hexagon_cpu_class_by_name;
+ cc->exception_name = hexagon_event_name;
cc->dump_state = hexagon_dump_state;
cc->set_pc = hexagon_cpu_set_pc;
cc->get_pc = hexagon_cpu_get_pc;
diff --git a/target/hexagon/hexswi.c b/target/hexagon/hexswi.c
index e7362b56650..19439658392 100644
--- a/target/hexagon/hexswi.c
+++ b/target/hexagon/hexswi.c
@@ -735,34 +735,6 @@ static void set_addresses(CPUHexagonState *env, uint32_t pc_offset,
env->gpr[HEX_REG_PC] = evb | (exception_index << 2);
}
-static const char *event_name[] = {
- [HEX_EVENT_RESET] = "HEX_EVENT_RESET",
- [HEX_EVENT_IMPRECISE] = "HEX_EVENT_IMPRECISE",
- [HEX_EVENT_PRECISE] = "HEX_EVENT_PRECISE",
- [HEX_EVENT_TLB_MISS_X] = "HEX_EVENT_TLB_MISS_X",
- [HEX_EVENT_TLB_MISS_RW] = "HEX_EVENT_TLB_MISS_RW",
- [HEX_EVENT_TRAP0] = "HEX_EVENT_TRAP0",
- [HEX_EVENT_TRAP1] = "HEX_EVENT_TRAP1",
- [HEX_EVENT_FPTRAP] = "HEX_EVENT_FPTRAP",
- [HEX_EVENT_DEBUG] = "HEX_EVENT_DEBUG",
- [HEX_EVENT_INT0] = "HEX_EVENT_INT0",
- [HEX_EVENT_INT1] = "HEX_EVENT_INT1",
- [HEX_EVENT_INT2] = "HEX_EVENT_INT2",
- [HEX_EVENT_INT3] = "HEX_EVENT_INT3",
- [HEX_EVENT_INT4] = "HEX_EVENT_INT4",
- [HEX_EVENT_INT5] = "HEX_EVENT_INT5",
- [HEX_EVENT_INT6] = "HEX_EVENT_INT6",
- [HEX_EVENT_INT7] = "HEX_EVENT_INT7",
- [HEX_EVENT_INT8] = "HEX_EVENT_INT8",
- [HEX_EVENT_INT9] = "HEX_EVENT_INT9",
- [HEX_EVENT_INTA] = "HEX_EVENT_INTA",
- [HEX_EVENT_INTB] = "HEX_EVENT_INTB",
- [HEX_EVENT_INTC] = "HEX_EVENT_INTC",
- [HEX_EVENT_INTD] = "HEX_EVENT_INTD",
- [HEX_EVENT_INTE] = "HEX_EVENT_INTE",
- [HEX_EVENT_INTF] = "HEX_EVENT_INTF"
-};
-
void hexagon_cpu_do_interrupt(CPUState *cs)
{
@@ -775,7 +747,7 @@ void hexagon_cpu_do_interrupt(CPUState *cs)
qemu_log_mask(CPU_LOG_INT,
"\t%s: event 0x%02x:%s, cause 0x%" PRIx32 "(%" PRIu32 ")\n",
__func__, (unsigned)cs->exception_index,
- event_name[cs->exception_index], env->cause_code,
+ hexagon_event_name(cs->exception_index), env->cause_code,
env->cause_code);
env->llsc_addr = ~0;
--
2.55.0
next prev parent reply other threads:[~2026-10-21 3:16 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-21 3:13 [PATCH v2 00/33] cpus: Add common CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 01/33] qemu/osdep: Add ARRAY_ELEM_OR_NULL() macro Philippe Mathieu-Daudé
2026-10-21 16:18 ` Pierrick Bouvier
2026-10-21 16:19 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 02/33] cpus: Add helper to log raised exceptions with '-d int' Philippe Mathieu-Daudé
2026-10-21 16:22 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 03/33] cpus: Introduce CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 04/33] target/alpha: Register " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 05/33] target/alpha: Use a static table in alpha_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:19 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 06/33] target/arm: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 07/33] target/avr: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` Philippe Mathieu-Daudé [this message]
2026-10-21 3:13 ` [PATCH v2 09/33] target/hppa: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 10/33] target/i386: Replace magic value by proper EXCP0E_PAGE definition Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 11/33] target/i386: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 12/33] target/loongarch: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 13/33] target/m68k: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 14/33] target/m68k: Use a static table in m68k_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:20 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 15/33] target/microblaze: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 16/33] target/mips: Remove unuseful EXCP_LAST definition Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 17/33] target/mips: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 18/33] target/or1k: " Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 19/33] target/ppc: Dump EBB exceptions names Philippe Mathieu-Daudé
2026-10-21 16:22 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 20/33] target/ppc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 21/33] target/ppc: Use a static table in powerpc_excp_name() Philippe Mathieu-Daudé
2026-10-21 16:21 ` Pierrick Bouvier
2026-10-21 3:13 ` [PATCH v2 22/33] target/riscv: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 23/33] target/rx: Unify BRK and INT trap handling Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 24/33] target/rx: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 25/33] target/rx: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:13 ` [PATCH v2 26/33] target/s390x: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 27/33] target/sh4: Define exception vector constants Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 28/33] target/sh4: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 29/33] target/sh4: Use a static table in sh4_exception_name() Philippe Mathieu-Daudé
2026-10-21 16:21 ` Pierrick Bouvier
2026-10-21 3:14 ` [PATCH v2 30/33] target/sparc: Remove well tested DEBUG_PCALL definition Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 31/33] target/sparc: Register CPUClass::exception_name() handler Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 32/33] target/tricore: Implement and register CPUClass::exception_name() Philippe Mathieu-Daudé
2026-10-21 3:14 ` [PATCH v2 33/33] target/xtensa: " Philippe Mathieu-Daudé
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