[PATCH 0/8] drm/ast: Reorganize TX-chip detection and init

[PATCH 0/8] drm/ast: Reorganize TX-chip detection and init

[Thomas Zimmermann]

Detection and initialization of TX chips is mixed up with each other
and other device-probing code. Move it into one place and reorganize
branches by Aspeed Gen.

This series is another step towards separating the TX code from the
rest of the driver and making each hardware gen self-contained.

Tested on AST 1100, 2300, 2500 and 2600.

Thomas Zimmermann (8):
  drm/ast: Detect wide-screen support before creating modeset pipeline
  drm/ast: Detect DRAM before TX-chip
  drm/ast: Refactor ast_post_gpu() by Gen
  drm/ast: Initialize ASTDP in ast_post_gpu()
  drm/ast: Hide Gens 1 to 3 TX detection in branch
  drm/ast: Align Gen1 DVO detection to register manual
  drm/ast: Merge TX-chip detection code for Gen4 and later
  drm/ast: Only warn about unsupported TX chips on Gen4 and later

 drivers/gpu/drm/ast/ast_drv.c  |   6 +-
 drivers/gpu/drm/ast/ast_drv.h  |   2 +-
 drivers/gpu/drm/ast/ast_main.c | 113 +++++++++++++++++++--------------
 drivers/gpu/drm/ast/ast_post.c |  49 ++++++++++----
 drivers/gpu/drm/ast/ast_reg.h  |   1 +
 5 files changed, 107 insertions(+), 64 deletions(-)

-- 
2.47.1

[PATCH 1/8] drm/ast: Detect wide-screen support before creating modeset pipeline

[Thomas Zimmermann]

Wide-screen support is relevant for mode validation. Do not detect it
before setting up the mode-setting pipeline. Gets the function call out
of the way of other initialization code.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index bc37c65305d48..037d389ab630d 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -290,7 +290,6 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
 	ast->regs = regs;
 	ast->ioregs = ioregs;
 
-	ast_detect_widescreen(ast);
 	ast_detect_tx_chip(ast, need_post);
 
 	ret = ast_get_dram_info(ast);
@@ -315,6 +314,8 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
 			drm_info(dev, "failed to map reserved buffer!\n");
 	}
 
+	ast_detect_widescreen(ast);
+
 	ret = ast_mode_config_init(ast);
 	if (ret)
 		return ERR_PTR(ret);
-- 
2.47.1

Re: [PATCH 1/8] drm/ast: Detect wide-screen support before creating modeset pipeline

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Wide-screen support is relevant for mode validation. Do not detect it
> before setting up the mode-setting pipeline. Gets the function call out
> of the way of other initialization code.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_main.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index bc37c65305d48..037d389ab630d 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -290,7 +290,6 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
>   	ast->regs = regs;
>   	ast->ioregs = ioregs;
>   
> -	ast_detect_widescreen(ast);
>   	ast_detect_tx_chip(ast, need_post);
>   
>   	ret = ast_get_dram_info(ast);
> @@ -315,6 +314,8 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
>   			drm_info(dev, "failed to map reserved buffer!\n");
>   	}
>   
> +	ast_detect_widescreen(ast);
> +
>   	ret = ast_mode_config_init(ast);
>   	if (ret)
>   		return ERR_PTR(ret);

[PATCH 2/8] drm/ast: Detect DRAM before TX-chip

[Thomas Zimmermann]

Move DRAM detection before TX-chip detection. Both steps are independent
from each other. Detection of the TX-chip is now next to posting those
chips, which can be done in a single step.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 037d389ab630d..456230bef2736 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -290,15 +290,13 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
 	ast->regs = regs;
 	ast->ioregs = ioregs;
 
-	ast_detect_tx_chip(ast, need_post);
-
 	ret = ast_get_dram_info(ast);
 	if (ret)
 		return ERR_PTR(ret);
-
 	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
 		 ast->mclk, ast->dram_type, ast->dram_bus_width);
 
+	ast_detect_tx_chip(ast, need_post);
 	if (need_post)
 		ast_post_gpu(ast);
 
-- 
2.47.1

Re: [PATCH 2/8] drm/ast: Detect DRAM before TX-chip

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Move DRAM detection before TX-chip detection. Both steps are independent
> from each other. Detection of the TX-chip is now next to posting those
> chips, which can be done in a single step.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_main.c | 4 +---
>   1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index 037d389ab630d..456230bef2736 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -290,15 +290,13 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
>   	ast->regs = regs;
>   	ast->ioregs = ioregs;
>   
> -	ast_detect_tx_chip(ast, need_post);
> -
>   	ret = ast_get_dram_info(ast);
>   	if (ret)
>   		return ERR_PTR(ret);
> -
>   	drm_info(dev, "dram MCLK=%u Mhz type=%d bus_width=%d\n",
>   		 ast->mclk, ast->dram_type, ast->dram_bus_width);
>   
> +	ast_detect_tx_chip(ast, need_post);
>   	if (need_post)
>   		ast_post_gpu(ast);
>   

[PATCH 3/8] drm/ast: Refactor ast_post_gpu() by Gen

[Thomas Zimmermann]

Reorganize ast_post_gpu() so that it first branches by Gen and then
by config mode and TX chip. This will later make it possible to split
up the function by Gen.

The helper ast_init_3rdtx() only handles Gen4 and Gen5, so leave it
out from the other Gens.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_post.c | 36 ++++++++++++++++++++++++----------
 1 file changed, 26 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 364030f97571d..49f661760f9e5 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -344,21 +344,37 @@ void ast_post_gpu(struct ast_device *ast)
 {
 	ast_set_def_ext_reg(ast);
 
-	if (IS_AST_GEN7(ast)) {
+	if (AST_GEN(ast) >= 7) {
 		if (ast->tx_chip == AST_TX_ASTDP)
 			ast_dp_launch(ast);
-	} else if (ast->config_mode == ast_use_p2a) {
-		if (IS_AST_GEN6(ast))
+	} else if (AST_GEN(ast) >= 6) {
+		if (ast->config_mode == ast_use_p2a) {
 			ast_post_chip_2500(ast);
-		else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
+		} else {
+			if (ast->tx_chip == AST_TX_SIL164) {
+				/* Enable DVO */
+				ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
+			}
+		}
+	} else if (AST_GEN(ast) >= 4) {
+		if (ast->config_mode == ast_use_p2a) {
 			ast_post_chip_2300(ast);
-		else
+			ast_init_3rdtx(ast);
+		} else {
+			if (ast->tx_chip == AST_TX_SIL164) {
+				/* Enable DVO */
+				ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
+			}
+		}
+	} else  {
+		if (ast->config_mode == ast_use_p2a) {
 			ast_init_dram_reg(ast);
-
-		ast_init_3rdtx(ast);
-	} else {
-		if (ast->tx_chip == AST_TX_SIL164)
-			ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);	/* Enable DVO */
+		} else {
+			if (ast->tx_chip == AST_TX_SIL164) {
+				/* Enable DVO */
+				ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
+			}
+		}
 	}
 }
 
-- 
2.47.1

Re: [PATCH 3/8] drm/ast: Refactor ast_post_gpu() by Gen

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Reorganize ast_post_gpu() so that it first branches by Gen and then
> by config mode and TX chip. This will later make it possible to split
> up the function by Gen.
> 
> The helper ast_init_3rdtx() only handles Gen4 and Gen5, so leave it
> out from the other Gens.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_post.c | 36 ++++++++++++++++++++++++----------
>   1 file changed, 26 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
> index 364030f97571d..49f661760f9e5 100644
> --- a/drivers/gpu/drm/ast/ast_post.c
> +++ b/drivers/gpu/drm/ast/ast_post.c
> @@ -344,21 +344,37 @@ void ast_post_gpu(struct ast_device *ast)
>   {
>   	ast_set_def_ext_reg(ast);
>   
> -	if (IS_AST_GEN7(ast)) {
> +	if (AST_GEN(ast) >= 7) {
>   		if (ast->tx_chip == AST_TX_ASTDP)
>   			ast_dp_launch(ast);
> -	} else if (ast->config_mode == ast_use_p2a) {
> -		if (IS_AST_GEN6(ast))
> +	} else if (AST_GEN(ast) >= 6) {
> +		if (ast->config_mode == ast_use_p2a) {
>   			ast_post_chip_2500(ast);
> -		else if (IS_AST_GEN5(ast) || IS_AST_GEN4(ast))
> +		} else {
> +			if (ast->tx_chip == AST_TX_SIL164) {
> +				/* Enable DVO */
> +				ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
> +			}
> +		}
> +	} else if (AST_GEN(ast) >= 4) {
> +		if (ast->config_mode == ast_use_p2a) {
>   			ast_post_chip_2300(ast);
> -		else
> +			ast_init_3rdtx(ast);
> +		} else {
> +			if (ast->tx_chip == AST_TX_SIL164) {
> +				/* Enable DVO */
> +				ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
> +			}
> +		}
> +	} else  {
> +		if (ast->config_mode == ast_use_p2a) {
>   			ast_init_dram_reg(ast);
> -
> -		ast_init_3rdtx(ast);
> -	} else {
> -		if (ast->tx_chip == AST_TX_SIL164)
> -			ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);	/* Enable DVO */
> +		} else {
> +			if (ast->tx_chip == AST_TX_SIL164) {
> +				/* Enable DVO */
> +				ast_set_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xcf, 0x80);
> +			}
> +		}
>   	}
>   }
>   

[PATCH 4/8] drm/ast: Initialize ASTDP in ast_post_gpu()

[Thomas Zimmermann]

Remove the call to ast_dp_launch() from ast_detect_tx_chip() and
perform it unconditionally in ast_post_gpu().

Also add error handling: the detection code apparently used
ast_dp_launch() to test for a working ASTDP, falling back to VGA on
errors. As the VBIOS reports ASTDP, silently ignoring errors is
questionable behavior. With the refactoring, failing to initialize
the ASTDP will also fail probing the driver.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_drv.c  |  6 +++++-
 drivers/gpu/drm/ast/ast_drv.h  |  2 +-
 drivers/gpu/drm/ast/ast_main.c | 19 +++++++++++++------
 drivers/gpu/drm/ast/ast_post.c | 13 ++++++++++---
 4 files changed, 29 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
index ff3bcdd1cff2a..cddd69972e89d 100644
--- a/drivers/gpu/drm/ast/ast_drv.c
+++ b/drivers/gpu/drm/ast/ast_drv.c
@@ -393,11 +393,15 @@ static int ast_drm_freeze(struct drm_device *dev)
 static int ast_drm_thaw(struct drm_device *dev)
 {
 	struct ast_device *ast = to_ast_device(dev);
+	int ret;
 
 	ast_enable_vga(ast->ioregs);
 	ast_open_key(ast->ioregs);
 	ast_enable_mmio(dev->dev, ast->ioregs);
-	ast_post_gpu(ast);
+
+	ret = ast_post_gpu(ast);
+	if (ret)
+		return ret;
 
 	return drm_mode_config_helper_resume(dev);
 }
diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
index 6b4305ac07d4f..cf9edef8fca66 100644
--- a/drivers/gpu/drm/ast/ast_drv.h
+++ b/drivers/gpu/drm/ast/ast_drv.h
@@ -445,7 +445,7 @@ int ast_mode_config_init(struct ast_device *ast);
 int ast_mm_init(struct ast_device *ast);
 
 /* ast post */
-void ast_post_gpu(struct ast_device *ast);
+int ast_post_gpu(struct ast_device *ast);
 u32 ast_mindwm(struct ast_device *ast, u32 r);
 void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
 void ast_patch_ahb_2500(void __iomem *regs);
diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 456230bef2736..474eb255b325b 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -138,10 +138,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 	} else if (IS_AST_GEN7(ast)) {
 		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) ==
 		    AST_IO_VGACRD1_TX_ASTDP) {
-			int ret = ast_dp_launch(ast);
-
-			if (!ret)
-				ast->tx_chip = AST_TX_ASTDP;
+			ast->tx_chip = AST_TX_ASTDP;
 		}
 	}
 
@@ -297,8 +294,18 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
 		 ast->mclk, ast->dram_type, ast->dram_bus_width);
 
 	ast_detect_tx_chip(ast, need_post);
-	if (need_post)
-		ast_post_gpu(ast);
+	switch (ast->tx_chip) {
+	case AST_TX_ASTDP:
+		ret = ast_post_gpu(ast);
+		break;
+	default:
+		ret = 0;
+		if (need_post)
+			ret = ast_post_gpu(ast);
+		break;
+	}
+	if (ret)
+		return ERR_PTR(ret);
 
 	ret = ast_mm_init(ast);
 	if (ret)
diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
index 49f661760f9e5..0daa8e52a092a 100644
--- a/drivers/gpu/drm/ast/ast_post.c
+++ b/drivers/gpu/drm/ast/ast_post.c
@@ -340,13 +340,18 @@ static void ast_init_dram_reg(struct ast_device *ast)
 	} while ((j & 0x40) == 0);
 }
 
-void ast_post_gpu(struct ast_device *ast)
+int ast_post_gpu(struct ast_device *ast)
 {
+	int ret;
+
 	ast_set_def_ext_reg(ast);
 
 	if (AST_GEN(ast) >= 7) {
-		if (ast->tx_chip == AST_TX_ASTDP)
-			ast_dp_launch(ast);
+		if (ast->tx_chip == AST_TX_ASTDP) {
+			ret = ast_dp_launch(ast);
+			if (ret)
+				return ret;
+		}
 	} else if (AST_GEN(ast) >= 6) {
 		if (ast->config_mode == ast_use_p2a) {
 			ast_post_chip_2500(ast);
@@ -376,6 +381,8 @@ void ast_post_gpu(struct ast_device *ast)
 			}
 		}
 	}
+
+	return 0;
 }
 
 /* AST 2300 DRAM settings */
-- 
2.47.1

Re: [PATCH 4/8] drm/ast: Initialize ASTDP in ast_post_gpu()

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Remove the call to ast_dp_launch() from ast_detect_tx_chip() and
> perform it unconditionally in ast_post_gpu().
> 
> Also add error handling: the detection code apparently used
> ast_dp_launch() to test for a working ASTDP, falling back to VGA on
> errors. As the VBIOS reports ASTDP, silently ignoring errors is
> questionable behavior. With the refactoring, failing to initialize
> the ASTDP will also fail probing the driver.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_drv.c  |  6 +++++-
>   drivers/gpu/drm/ast/ast_drv.h  |  2 +-
>   drivers/gpu/drm/ast/ast_main.c | 19 +++++++++++++------
>   drivers/gpu/drm/ast/ast_post.c | 13 ++++++++++---
>   4 files changed, 29 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_drv.c b/drivers/gpu/drm/ast/ast_drv.c
> index ff3bcdd1cff2a..cddd69972e89d 100644
> --- a/drivers/gpu/drm/ast/ast_drv.c
> +++ b/drivers/gpu/drm/ast/ast_drv.c
> @@ -393,11 +393,15 @@ static int ast_drm_freeze(struct drm_device *dev)
>   static int ast_drm_thaw(struct drm_device *dev)
>   {
>   	struct ast_device *ast = to_ast_device(dev);
> +	int ret;
>   
>   	ast_enable_vga(ast->ioregs);
>   	ast_open_key(ast->ioregs);
>   	ast_enable_mmio(dev->dev, ast->ioregs);
> -	ast_post_gpu(ast);
> +
> +	ret = ast_post_gpu(ast);
> +	if (ret)
> +		return ret;
>   
>   	return drm_mode_config_helper_resume(dev);
>   }
> diff --git a/drivers/gpu/drm/ast/ast_drv.h b/drivers/gpu/drm/ast/ast_drv.h
> index 6b4305ac07d4f..cf9edef8fca66 100644
> --- a/drivers/gpu/drm/ast/ast_drv.h
> +++ b/drivers/gpu/drm/ast/ast_drv.h
> @@ -445,7 +445,7 @@ int ast_mode_config_init(struct ast_device *ast);
>   int ast_mm_init(struct ast_device *ast);
>   
>   /* ast post */
> -void ast_post_gpu(struct ast_device *ast);
> +int ast_post_gpu(struct ast_device *ast);
>   u32 ast_mindwm(struct ast_device *ast, u32 r);
>   void ast_moutdwm(struct ast_device *ast, u32 r, u32 v);
>   void ast_patch_ahb_2500(void __iomem *regs);
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index 456230bef2736..474eb255b325b 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -138,10 +138,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   	} else if (IS_AST_GEN7(ast)) {
>   		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) ==
>   		    AST_IO_VGACRD1_TX_ASTDP) {
> -			int ret = ast_dp_launch(ast);
> -
> -			if (!ret)
> -				ast->tx_chip = AST_TX_ASTDP;
> +			ast->tx_chip = AST_TX_ASTDP;
>   		}
>   	}
>   
> @@ -297,8 +294,18 @@ struct drm_device *ast_device_create(struct pci_dev *pdev,
>   		 ast->mclk, ast->dram_type, ast->dram_bus_width);
>   
>   	ast_detect_tx_chip(ast, need_post);
> -	if (need_post)
> -		ast_post_gpu(ast);
> +	switch (ast->tx_chip) {
> +	case AST_TX_ASTDP:
> +		ret = ast_post_gpu(ast);
> +		break;
> +	default:
> +		ret = 0;
> +		if (need_post)
> +			ret = ast_post_gpu(ast);
> +		break;
> +	}
> +	if (ret)
> +		return ERR_PTR(ret);
>   
>   	ret = ast_mm_init(ast);
>   	if (ret)
> diff --git a/drivers/gpu/drm/ast/ast_post.c b/drivers/gpu/drm/ast/ast_post.c
> index 49f661760f9e5..0daa8e52a092a 100644
> --- a/drivers/gpu/drm/ast/ast_post.c
> +++ b/drivers/gpu/drm/ast/ast_post.c
> @@ -340,13 +340,18 @@ static void ast_init_dram_reg(struct ast_device *ast)
>   	} while ((j & 0x40) == 0);
>   }
>   
> -void ast_post_gpu(struct ast_device *ast)
> +int ast_post_gpu(struct ast_device *ast)
>   {
> +	int ret;
> +
>   	ast_set_def_ext_reg(ast);
>   
>   	if (AST_GEN(ast) >= 7) {
> -		if (ast->tx_chip == AST_TX_ASTDP)
> -			ast_dp_launch(ast);
> +		if (ast->tx_chip == AST_TX_ASTDP) {
> +			ret = ast_dp_launch(ast);
> +			if (ret)
> +				return ret;
> +		}
>   	} else if (AST_GEN(ast) >= 6) {
>   		if (ast->config_mode == ast_use_p2a) {
>   			ast_post_chip_2500(ast);
> @@ -376,6 +381,8 @@ void ast_post_gpu(struct ast_device *ast)
>   			}
>   		}
>   	}
> +
> +	return 0;
>   }
>   
>   /* AST 2300 DRAM settings */

[PATCH 5/8] drm/ast: Hide Gens 1 to 3 TX detection in branch

[Thomas Zimmermann]

Gen7 only supports ASTDP. Gens 4 to 6 support various TX chips,
except ASTDP. These boards detect the TX chips by reading the SoC
scratch register as VGACRD1.

Gens 1 to 3 only support SIL164. These boards read the DVO bit from
VGACRA3. Hence move this test behind a branch, so that it does not
run on later generations.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 474eb255b325b..50b57bc15d53c 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -96,21 +96,21 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 	/* Check 3rd Tx option (digital output afaik) */
 	ast->tx_chip = AST_TX_NONE;
 
-	/*
-	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
-	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
-	 *
-	 * Don't make that assumption if we the chip wasn't enabled and
-	 * is at power-on reset, otherwise we'll incorrectly "detect" a
-	 * SIL164 when there is none.
-	 */
-	if (!need_post) {
-		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
-		if (jreg & 0x80)
-			ast->tx_chip = AST_TX_SIL164;
-	}
-
-	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
+	if (AST_GEN(ast) <= 3) {
+		/*
+		 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
+		 * enabled, in that case, assume we have a SIL164 TMDS transmitter
+		 *
+		 * Don't make that assumption if we the chip wasn't enabled and
+		 * is at power-on reset, otherwise we'll incorrectly "detect" a
+		 * SIL164 when there is none.
+		 */
+		if (!need_post) {
+			jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
+			if (jreg & 0x80)
+				ast->tx_chip = AST_TX_SIL164;
+		}
+	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
 		/*
 		 * On AST GEN4+, look the configuration set by the SoC in
 		 * the SOC scratch register #1 bits 11:8 (interestingly marked
-- 
2.47.1

Re: [PATCH 5/8] drm/ast: Hide Gens 1 to 3 TX detection in branch

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Gen7 only supports ASTDP. Gens 4 to 6 support various TX chips,
> except ASTDP. These boards detect the TX chips by reading the SoC
> scratch register as VGACRD1.
> 
> Gens 1 to 3 only support SIL164. These boards read the DVO bit from
> VGACRA3. Hence move this test behind a branch, so that it does not
> run on later generations.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_main.c | 30 +++++++++++++++---------------
>   1 file changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index 474eb255b325b..50b57bc15d53c 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -96,21 +96,21 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   	/* Check 3rd Tx option (digital output afaik) */
>   	ast->tx_chip = AST_TX_NONE;
>   
> -	/*
> -	 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
> -	 * enabled, in that case, assume we have a SIL164 TMDS transmitter
> -	 *
> -	 * Don't make that assumption if we the chip wasn't enabled and
> -	 * is at power-on reset, otherwise we'll incorrectly "detect" a
> -	 * SIL164 when there is none.
> -	 */
> -	if (!need_post) {
> -		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
> -		if (jreg & 0x80)
> -			ast->tx_chip = AST_TX_SIL164;
> -	}
> -
> -	if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
> +	if (AST_GEN(ast) <= 3) {
> +		/*
> +		 * VGACRA3 Enhanced Color Mode Register, check if DVO is already
> +		 * enabled, in that case, assume we have a SIL164 TMDS transmitter
> +		 *
> +		 * Don't make that assumption if we the chip wasn't enabled and
> +		 * is at power-on reset, otherwise we'll incorrectly "detect" a
> +		 * SIL164 when there is none.
> +		 */
> +		if (!need_post) {
> +			jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
> +			if (jreg & 0x80)
> +				ast->tx_chip = AST_TX_SIL164;
> +		}
> +	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
>   		/*
>   		 * On AST GEN4+, look the configuration set by the SoC in
>   		 * the SOC scratch register #1 bits 11:8 (interestingly marked

[PATCH 6/8] drm/ast: Align Gen1 DVO detection to register manual

[Thomas Zimmermann]

Align variable names and register constants for TX-chip detection
to the names in the register manual.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 6 +++---
 drivers/gpu/drm/ast/ast_reg.h  | 1 +
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 50b57bc15d53c..40d3b7770cf18 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -76,7 +76,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 	};
 
 	struct drm_device *dev = &ast->base;
-	u8 jreg, vgacrd1;
+	u8 vgacra3, vgacrd1;
 
 	/*
 	 * Several of the listed TX chips are not explicitly supported
@@ -106,8 +106,8 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 		 * SIL164 when there is none.
 		 */
 		if (!need_post) {
-			jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
-			if (jreg & 0x80)
+			vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
+			if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
 				ast->tx_chip = AST_TX_SIL164;
 		}
 	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
index 2aadf07d135af..0745d58e5b450 100644
--- a/drivers/gpu/drm/ast/ast_reg.h
+++ b/drivers/gpu/drm/ast/ast_reg.h
@@ -32,6 +32,7 @@
 #define AST_IO_VGACR80_PASSWORD		(0xa8)
 #define AST_IO_VGACRA1_VGAIO_DISABLED	BIT(1)
 #define AST_IO_VGACRA1_MMIO_ENABLED	BIT(2)
+#define AST_IO_VGACRA3_DVO_ENABLED	BIT(7)
 #define AST_IO_VGACRB6_HSYNC_OFF	BIT(0)
 #define AST_IO_VGACRB6_VSYNC_OFF	BIT(1)
 #define AST_IO_VGACRCB_HWC_16BPP	BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
-- 
2.47.1

Re: [PATCH 6/8] drm/ast: Align Gen1 DVO detection to register manual

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Align variable names and register constants for TX-chip detection
> to the names in the register manual.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_main.c | 6 +++---
>   drivers/gpu/drm/ast/ast_reg.h  | 1 +
>   2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index 50b57bc15d53c..40d3b7770cf18 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -76,7 +76,7 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   	};
>   
>   	struct drm_device *dev = &ast->base;
> -	u8 jreg, vgacrd1;
> +	u8 vgacra3, vgacrd1;
>   
>   	/*
>   	 * Several of the listed TX chips are not explicitly supported
> @@ -106,8 +106,8 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   		 * SIL164 when there is none.
>   		 */
>   		if (!need_post) {
> -			jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
> -			if (jreg & 0x80)
> +			vgacra3 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xa3, 0xff);
> +			if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
>   				ast->tx_chip = AST_TX_SIL164;
>   		}
>   	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
> diff --git a/drivers/gpu/drm/ast/ast_reg.h b/drivers/gpu/drm/ast/ast_reg.h
> index 2aadf07d135af..0745d58e5b450 100644
> --- a/drivers/gpu/drm/ast/ast_reg.h
> +++ b/drivers/gpu/drm/ast/ast_reg.h
> @@ -32,6 +32,7 @@
>   #define AST_IO_VGACR80_PASSWORD		(0xa8)
>   #define AST_IO_VGACRA1_VGAIO_DISABLED	BIT(1)
>   #define AST_IO_VGACRA1_MMIO_ENABLED	BIT(2)
> +#define AST_IO_VGACRA3_DVO_ENABLED	BIT(7)
>   #define AST_IO_VGACRB6_HSYNC_OFF	BIT(0)
>   #define AST_IO_VGACRB6_VSYNC_OFF	BIT(1)
>   #define AST_IO_VGACRCB_HWC_16BPP	BIT(0) /* set: ARGB4444, cleared: 2bpp palette */

[PATCH 7/8] drm/ast: Merge TX-chip detection code for Gen4 and later

[Thomas Zimmermann]

Gens 4 to 6 and Gen7 use the same pattern for detecting the installed
TX chips. Merge the code into a single branch.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 17 +++++++++++------
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index 40d3b7770cf18..b0d1b99ed532b 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -110,15 +110,18 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 			if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
 				ast->tx_chip = AST_TX_SIL164;
 		}
-	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
+	} else {
 		/*
-		 * On AST GEN4+, look the configuration set by the SoC in
+		 * On AST GEN4+, look at the configuration set by the SoC in
 		 * the SOC scratch register #1 bits 11:8 (interestingly marked
 		 * as "reserved" in the spec)
 		 */
 		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
 					      AST_IO_VGACRD1_TX_TYPE_MASK);
 		switch (jreg) {
+		/*
+		 * GEN4 to GEN6
+		 */
 		case AST_IO_VGACRD1_TX_SIL164_VBIOS:
 			ast->tx_chip = AST_TX_SIL164;
 			break;
@@ -134,11 +137,13 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 			fallthrough;
 		case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW:
 			ast->tx_chip = AST_TX_DP501;
-		}
-	} else if (IS_AST_GEN7(ast)) {
-		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) ==
-		    AST_IO_VGACRD1_TX_ASTDP) {
+			break;
+		/*
+		 * GEN7+
+		 */
+		case AST_IO_VGACRD1_TX_ASTDP:
 			ast->tx_chip = AST_TX_ASTDP;
+			break;
 		}
 	}
 
-- 
2.47.1

Re: [PATCH 7/8] drm/ast: Merge TX-chip detection code for Gen4 and later

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Gens 4 to 6 and Gen7 use the same pattern for detecting the installed
> TX chips. Merge the code into a single branch.
> 

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_main.c | 17 +++++++++++------
>   1 file changed, 11 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index 40d3b7770cf18..b0d1b99ed532b 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -110,15 +110,18 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   			if (vgacra3 & AST_IO_VGACRA3_DVO_ENABLED)
>   				ast->tx_chip = AST_TX_SIL164;
>   		}
> -	} else if (IS_AST_GEN4(ast) || IS_AST_GEN5(ast) || IS_AST_GEN6(ast)) {
> +	} else {
>   		/*
> -		 * On AST GEN4+, look the configuration set by the SoC in
> +		 * On AST GEN4+, look at the configuration set by the SoC in
>   		 * the SOC scratch register #1 bits 11:8 (interestingly marked
>   		 * as "reserved" in the spec)
>   		 */
>   		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
>   					      AST_IO_VGACRD1_TX_TYPE_MASK);
>   		switch (jreg) {
> +		/*
> +		 * GEN4 to GEN6
> +		 */
>   		case AST_IO_VGACRD1_TX_SIL164_VBIOS:
>   			ast->tx_chip = AST_TX_SIL164;
>   			break;
> @@ -134,11 +137,13 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   			fallthrough;
>   		case AST_IO_VGACRD1_TX_FW_EMBEDDED_FW:
>   			ast->tx_chip = AST_TX_DP501;
> -		}
> -	} else if (IS_AST_GEN7(ast)) {
> -		if (ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK) ==
> -		    AST_IO_VGACRD1_TX_ASTDP) {
> +			break;
> +		/*
> +		 * GEN7+
> +		 */
> +		case AST_IO_VGACRD1_TX_ASTDP:
>   			ast->tx_chip = AST_TX_ASTDP;
> +			break;
>   		}
>   	}
>   

[PATCH 8/8] drm/ast: Only warn about unsupported TX chips on Gen4 and later

[Thomas Zimmermann]

Only Gen4 and later read the installed TX chip from the SoC. So only
warn on those generations about unsupported chips.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
---
 drivers/gpu/drm/ast/ast_main.c | 40 +++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
index b0d1b99ed532b..ba69280b33e78 100644
--- a/drivers/gpu/drm/ast/ast_main.c
+++ b/drivers/gpu/drm/ast/ast_main.c
@@ -78,21 +78,6 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 	struct drm_device *dev = &ast->base;
 	u8 vgacra3, vgacrd1;
 
-	/*
-	 * Several of the listed TX chips are not explicitly supported
-	 * by the ast driver. If these exist in real-world devices, they
-	 * are most likely reported as VGA or SIL164 outputs. We warn here
-	 * to get bug reports for these devices. If none come in for some
-	 * time, we can begin to fail device probing on these values.
-	 */
-	vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK);
-	drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ITE66121_VBIOS,
-		 "ITE IT66121 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
-	drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_CH7003_VBIOS,
-		 "Chrontel CH7003 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
-	drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ANX9807_VBIOS,
-		 "Analogix ANX9807 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
-
 	/* Check 3rd Tx option (digital output afaik) */
 	ast->tx_chip = AST_TX_NONE;
 
@@ -116,9 +101,9 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 		 * the SOC scratch register #1 bits 11:8 (interestingly marked
 		 * as "reserved" in the spec)
 		 */
-		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
-					      AST_IO_VGACRD1_TX_TYPE_MASK);
-		switch (jreg) {
+		vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
+						 AST_IO_VGACRD1_TX_TYPE_MASK);
+		switch (vgacrd1) {
 		/*
 		 * GEN4 to GEN6
 		 */
@@ -144,6 +129,25 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
 		case AST_IO_VGACRD1_TX_ASTDP:
 			ast->tx_chip = AST_TX_ASTDP;
 			break;
+		/*
+		 * Several of the listed TX chips are not explicitly supported
+		 * by the ast driver. If these exist in real-world devices, they
+		 * are most likely reported as VGA or SIL164 outputs. We warn here
+		 * to get bug reports for these devices. If none come in for some
+		 * time, we can begin to fail device probing on these values.
+		 */
+		case AST_IO_VGACRD1_TX_ITE66121_VBIOS:
+			drm_warn(dev, "ITE IT66121 detected, 0x%x, Gen%lu\n",
+				 vgacrd1, AST_GEN(ast));
+			break;
+		case AST_IO_VGACRD1_TX_CH7003_VBIOS:
+			drm_warn(dev, "Chrontel CH7003 detected, 0x%x, Gen%lu\n",
+				 vgacrd1, AST_GEN(ast));
+			break;
+		case AST_IO_VGACRD1_TX_ANX9807_VBIOS:
+			drm_warn(dev, "Analogix ANX9807 detected, 0x%x, Gen%lu\n",
+				 vgacrd1, AST_GEN(ast));
+			break;
 		}
 	}
 
-- 
2.47.1

Re: [PATCH 8/8] drm/ast: Only warn about unsupported TX chips on Gen4 and later

[Jocelyn Falempe]

On 17/01/2025 11:29, Thomas Zimmermann wrote:
> Only Gen4 and later read the installed TX chip from the SoC. So only
> warn on those generations about unsupported chips.

Thanks, it looks good to me.

Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
> 
> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
> ---
>   drivers/gpu/drm/ast/ast_main.c | 40 +++++++++++++++++++---------------
>   1 file changed, 22 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/ast/ast_main.c b/drivers/gpu/drm/ast/ast_main.c
> index b0d1b99ed532b..ba69280b33e78 100644
> --- a/drivers/gpu/drm/ast/ast_main.c
> +++ b/drivers/gpu/drm/ast/ast_main.c
> @@ -78,21 +78,6 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   	struct drm_device *dev = &ast->base;
>   	u8 vgacra3, vgacrd1;
>   
> -	/*
> -	 * Several of the listed TX chips are not explicitly supported
> -	 * by the ast driver. If these exist in real-world devices, they
> -	 * are most likely reported as VGA or SIL164 outputs. We warn here
> -	 * to get bug reports for these devices. If none come in for some
> -	 * time, we can begin to fail device probing on these values.
> -	 */
> -	vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, AST_IO_VGACRD1_TX_TYPE_MASK);
> -	drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ITE66121_VBIOS,
> -		 "ITE IT66121 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
> -	drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_CH7003_VBIOS,
> -		 "Chrontel CH7003 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
> -	drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ANX9807_VBIOS,
> -		 "Analogix ANX9807 detected, 0x%x, Gen%lu\n", vgacrd1, AST_GEN(ast));
> -
>   	/* Check 3rd Tx option (digital output afaik) */
>   	ast->tx_chip = AST_TX_NONE;
>   
> @@ -116,9 +101,9 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   		 * the SOC scratch register #1 bits 11:8 (interestingly marked
>   		 * as "reserved" in the spec)
>   		 */
> -		jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
> -					      AST_IO_VGACRD1_TX_TYPE_MASK);
> -		switch (jreg) {
> +		vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
> +						 AST_IO_VGACRD1_TX_TYPE_MASK);
> +		switch (vgacrd1) {
>   		/*
>   		 * GEN4 to GEN6
>   		 */
> @@ -144,6 +129,25 @@ static void ast_detect_tx_chip(struct ast_device *ast, bool need_post)
>   		case AST_IO_VGACRD1_TX_ASTDP:
>   			ast->tx_chip = AST_TX_ASTDP;
>   			break;
> +		/*
> +		 * Several of the listed TX chips are not explicitly supported
> +		 * by the ast driver. If these exist in real-world devices, they
> +		 * are most likely reported as VGA or SIL164 outputs. We warn here
> +		 * to get bug reports for these devices. If none come in for some
> +		 * time, we can begin to fail device probing on these values.
> +		 */
> +		case AST_IO_VGACRD1_TX_ITE66121_VBIOS:
> +			drm_warn(dev, "ITE IT66121 detected, 0x%x, Gen%lu\n",
> +				 vgacrd1, AST_GEN(ast));
> +			break;
> +		case AST_IO_VGACRD1_TX_CH7003_VBIOS:
> +			drm_warn(dev, "Chrontel CH7003 detected, 0x%x, Gen%lu\n",
> +				 vgacrd1, AST_GEN(ast));
> +			break;
> +		case AST_IO_VGACRD1_TX_ANX9807_VBIOS:
> +			drm_warn(dev, "Analogix ANX9807 detected, 0x%x, Gen%lu\n",
> +				 vgacrd1, AST_GEN(ast));
> +			break;
>   		}
>   	}
>   

Re: [PATCH 8/8] drm/ast: Only warn about unsupported TX chips on Gen4 and later

[Thomas Zimmermann]

Hi


Am 20.01.25 um 11:37 schrieb Jocelyn Falempe:
> On 17/01/2025 11:29, Thomas Zimmermann wrote:
>> Only Gen4 and later read the installed TX chip from the SoC. So only
>> warn on those generations about unsupported chips.
>
> Thanks, it looks good to me.
>
> Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>

Thanks for reviewing. I'll merge the series by the end of the week if 
nothing else comes in.

Best regards
Thomas

>>
>> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
>> ---
>>   drivers/gpu/drm/ast/ast_main.c | 40 +++++++++++++++++++---------------
>>   1 file changed, 22 insertions(+), 18 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/ast/ast_main.c 
>> b/drivers/gpu/drm/ast/ast_main.c
>> index b0d1b99ed532b..ba69280b33e78 100644
>> --- a/drivers/gpu/drm/ast/ast_main.c
>> +++ b/drivers/gpu/drm/ast/ast_main.c
>> @@ -78,21 +78,6 @@ static void ast_detect_tx_chip(struct ast_device 
>> *ast, bool need_post)
>>       struct drm_device *dev = &ast->base;
>>       u8 vgacra3, vgacrd1;
>>   -    /*
>> -     * Several of the listed TX chips are not explicitly supported
>> -     * by the ast driver. If these exist in real-world devices, they
>> -     * are most likely reported as VGA or SIL164 outputs. We warn here
>> -     * to get bug reports for these devices. If none come in for some
>> -     * time, we can begin to fail device probing on these values.
>> -     */
>> -    vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1, 
>> AST_IO_VGACRD1_TX_TYPE_MASK);
>> -    drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ITE66121_VBIOS,
>> -         "ITE IT66121 detected, 0x%x, Gen%lu\n", vgacrd1, 
>> AST_GEN(ast));
>> -    drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_CH7003_VBIOS,
>> -         "Chrontel CH7003 detected, 0x%x, Gen%lu\n", vgacrd1, 
>> AST_GEN(ast));
>> -    drm_WARN(dev, vgacrd1 == AST_IO_VGACRD1_TX_ANX9807_VBIOS,
>> -         "Analogix ANX9807 detected, 0x%x, Gen%lu\n", vgacrd1, 
>> AST_GEN(ast));
>> -
>>       /* Check 3rd Tx option (digital output afaik) */
>>       ast->tx_chip = AST_TX_NONE;
>>   @@ -116,9 +101,9 @@ static void ast_detect_tx_chip(struct 
>> ast_device *ast, bool need_post)
>>            * the SOC scratch register #1 bits 11:8 (interestingly marked
>>            * as "reserved" in the spec)
>>            */
>> -        jreg = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
>> -                          AST_IO_VGACRD1_TX_TYPE_MASK);
>> -        switch (jreg) {
>> +        vgacrd1 = ast_get_index_reg_mask(ast, AST_IO_VGACRI, 0xd1,
>> +                         AST_IO_VGACRD1_TX_TYPE_MASK);
>> +        switch (vgacrd1) {
>>           /*
>>            * GEN4 to GEN6
>>            */
>> @@ -144,6 +129,25 @@ static void ast_detect_tx_chip(struct ast_device 
>> *ast, bool need_post)
>>           case AST_IO_VGACRD1_TX_ASTDP:
>>               ast->tx_chip = AST_TX_ASTDP;
>>               break;
>> +        /*
>> +         * Several of the listed TX chips are not explicitly supported
>> +         * by the ast driver. If these exist in real-world devices, 
>> they
>> +         * are most likely reported as VGA or SIL164 outputs. We 
>> warn here
>> +         * to get bug reports for these devices. If none come in for 
>> some
>> +         * time, we can begin to fail device probing on these values.
>> +         */
>> +        case AST_IO_VGACRD1_TX_ITE66121_VBIOS:
>> +            drm_warn(dev, "ITE IT66121 detected, 0x%x, Gen%lu\n",
>> +                 vgacrd1, AST_GEN(ast));
>> +            break;
>> +        case AST_IO_VGACRD1_TX_CH7003_VBIOS:
>> +            drm_warn(dev, "Chrontel CH7003 detected, 0x%x, Gen%lu\n",
>> +                 vgacrd1, AST_GEN(ast));
>> +            break;
>> +        case AST_IO_VGACRD1_TX_ANX9807_VBIOS:
>> +            drm_warn(dev, "Analogix ANX9807 detected, 0x%x, Gen%lu\n",
>> +                 vgacrd1, AST_GEN(ast));
>> +            break;
>>           }
>>       }
>

-- 
--
Thomas Zimmermann
Graphics Driver Developer
SUSE Software Solutions Germany GmbH
Frankenstrasse 146, 90461 Nuernberg, Germany
GF: Ivo Totev, Andrew Myers, Andrew McDonald, Boudien Moerman
HRB 36809 (AG Nuernberg)