* [PATCH] drm/i915: apply phase pointer override on SNB+ too
@ 2011-07-29 0:07 Jesse Barnes
2011-07-29 17:28 ` Keith Packard
0 siblings, 1 reply; 9+ messages in thread
From: Jesse Barnes @ 2011-07-29 0:07 UTC (permalink / raw)
To: intel-gfx
These bits moved around on SNB and above.
v2: again with the git send-email fail
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++-
2 files changed, 36 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..7261113 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,6 +3075,14 @@
#define TRANS_6BPC (2<<5)
#define TRANS_12BPC (3<<5)
+#define _TRANSA_CHICKEN2 0xf0064
+#define _TRANSB_CHICKEN2 0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_SHIFT 18
+#define FDI_PHASE_SYNC_OVR_EN (3)
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5609c06..65ead57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2086,6 +2086,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
FDI_FE_ERRC_ENABLE);
}
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags |= FDI_PHASE_SYNC_OVR_EN << (FDIA_PHASE_SYNC_SHIFT - (pipe * 2));
+
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
+
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
@@ -2133,7 +2145,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
FDI_RX_PHASE_SYNC_POINTER_EN);
- }
+ } else if (HAS_PCH_CPT(dev))
+ cpt_phase_pointer_enable(dev, pipe);
reg = FDI_RX_IIR(pipe);
for (tries = 0; tries < 5; tries++) {
@@ -2461,6 +2474,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
}
}
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags &= ~(FDI_PHASE_SYNC_OVR_EN << (FDIA_PHASE_SYNC_SHIFT -
+ (pipe * 2)));
+
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -2490,6 +2515,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe) &
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ cpt_phase_pointer_disable(dev, pipe);
}
/* still set train pattern 1 */
--
1.7.4.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* [PATCH] drm/i915: apply phase pointer override on SNB+ too
@ 2011-07-29 19:42 Jesse Barnes
2011-07-29 21:22 ` Keith Packard
0 siblings, 1 reply; 9+ messages in thread
From: Jesse Barnes @ 2011-07-29 19:42 UTC (permalink / raw)
To: intel-gfx
These bits moved around on SNB and above.
v2: again with the git send-email fail
v3: add macros for getting per-pipe override & enable bits
v4: enable phase sync pointer on SNB and IVB configs as well
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 30d8aae..a7f7a34 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3091,6 +3091,11 @@
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_SHIFT_OVR 19
+#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 32c8c95..67376e5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2110,6 +2110,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
FDI_FE_ERRC_ENABLE);
}
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags |= FDI_PHASE_SYNC_OVR(pipe);
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ flags |= FDI_PHASE_SYNC_EN(pipe);
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
+
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
@@ -2260,6 +2272,9 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
POSTING_READ(reg);
udelay(150);
+ if (HAS_PCH_CPT(dev))
+ cpt_phase_pointer_enable(dev, pipe);
+
for (i = 0; i < 4; i++ ) {
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
@@ -2376,6 +2391,9 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
POSTING_READ(reg);
udelay(150);
+ if (HAS_PCH_CPT(dev))
+ cpt_phase_pointer_enable(dev, pipe);
+
for (i = 0; i < 4; i++ ) {
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
@@ -2485,6 +2503,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
}
}
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags &= ~(FDI_PHASE_SYNC_EN(pipe));
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
+ flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -2514,6 +2543,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe) &
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ cpt_phase_pointer_disable(dev, pipe);
}
/* still set train pattern 1 */
--
1.7.4.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: apply phase pointer override on SNB+ too
2011-07-29 19:42 Jesse Barnes
@ 2011-07-29 21:22 ` Keith Packard
2011-07-29 21:55 ` Jesse Barnes
0 siblings, 1 reply; 9+ messages in thread
From: Keith Packard @ 2011-07-29 21:22 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 418 bytes --]
On Fri, 29 Jul 2011 12:42:37 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> v2: again with the git send-email fail
> v3: add macros for getting per-pipe override & enable bits
> v4: enable phase sync pointer on SNB and IVB configs as well
Yeah, this looks good -- a bit tricky in ironlake_fdi_disable -- it
works only because ILK was never supported with CPT, right?
--
keith.packard@intel.com
[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: apply phase pointer override on SNB+ too
2011-07-29 21:22 ` Keith Packard
@ 2011-07-29 21:55 ` Jesse Barnes
0 siblings, 0 replies; 9+ messages in thread
From: Jesse Barnes @ 2011-07-29 21:55 UTC (permalink / raw)
To: Keith Packard; +Cc: intel-gfx
On Fri, 29 Jul 2011 14:22:24 -0700
Keith Packard <keithp@keithp.com> wrote:
> On Fri, 29 Jul 2011 12:42:37 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
> > v2: again with the git send-email fail
> > v3: add macros for getting per-pipe override & enable bits
> > v4: enable phase sync pointer on SNB and IVB configs as well
>
> Yeah, this looks good -- a bit tricky in ironlake_fdi_disable -- it
> works only because ILK was never supported with CPT, right?
Right, I don't think we have any configs like that.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: apply phase pointer override on SNB+ too
@ 2011-07-29 17:50 Jesse Barnes
2011-07-29 18:47 ` Keith Packard
0 siblings, 1 reply; 9+ messages in thread
From: Jesse Barnes @ 2011-07-29 17:50 UTC (permalink / raw)
To: intel-gfx
These bits moved around on SNB and above.
v2: again with the git send-email fail
v3: add macros for getting per-pipe override & enable bits
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++++++++++++++++-
2 files changed, 32 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 00bd510..abab1f5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3077,6 +3077,11 @@
#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_SHIFT_OVR 19
+#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8f7ed73..6f1dfc3 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2110,6 +2110,18 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
FDI_FE_ERRC_ENABLE);
}
+static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags |= FDI_PHASE_SYNC_OVR(pipe);
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ flags |= FDI_PHASE_SYNC_EN(pipe);
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
+
/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
@@ -2157,7 +2169,8 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
FDI_RX_PHASE_SYNC_POINTER_EN);
- }
+ } else if (HAS_PCH_CPT(dev))
+ cpt_phase_pointer_enable(dev, pipe);
reg = FDI_RX_IIR(pipe);
for (tries = 0; tries < 5; tries++) {
@@ -2485,6 +2498,17 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
}
}
+static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 flags = I915_READ(SOUTH_CHICKEN1);
+
+ flags &= ~(FDI_PHASE_SYNC_EN(pipe));
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
+ flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
+ POSTING_READ(SOUTH_CHICKEN1);
+}
static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
@@ -2514,6 +2538,8 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe) &
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ cpt_phase_pointer_disable(dev, pipe);
}
/* still set train pattern 1 */
--
1.7.4.1
^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH] drm/i915: apply phase pointer override on SNB+ too
2011-07-29 17:50 Jesse Barnes
@ 2011-07-29 18:47 ` Keith Packard
2011-07-29 19:43 ` Jesse Barnes
0 siblings, 1 reply; 9+ messages in thread
From: Keith Packard @ 2011-07-29 18:47 UTC (permalink / raw)
To: Jesse Barnes, intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 677 bytes --]
On Fri, 29 Jul 2011 10:50:11 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
> + flags |= FDI_PHASE_SYNC_OVR(pipe);
> + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
> + flags |= FDI_PHASE_SYNC_EN(pipe);
> + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
> + POSTING_READ(SOUTH_CHICKEN1);
> +}
ooh, this even makes the sequence of two writes sound sensible.
Reviewed-by: Keith Packard <keithp@keithp.com>
You didn't happen to check the register values after doing this, did
you? Just to verify that all of the crazy math works, given that we
can't actually test whether this fixes anything.
--
keith.packard@intel.com
[-- Attachment #1.2: Type: application/pgp-signature, Size: 189 bytes --]
[-- Attachment #2: Type: text/plain, Size: 159 bytes --]
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH] drm/i915: apply phase pointer override on SNB+ too
2011-07-29 18:47 ` Keith Packard
@ 2011-07-29 19:43 ` Jesse Barnes
0 siblings, 0 replies; 9+ messages in thread
From: Jesse Barnes @ 2011-07-29 19:43 UTC (permalink / raw)
To: Keith Packard; +Cc: intel-gfx
On Fri, 29 Jul 2011 11:47:55 -0700
Keith Packard <keithp@keithp.com> wrote:
> On Fri, 29 Jul 2011 10:50:11 -0700, Jesse Barnes <jbarnes@virtuousgeek.org> wrote:
>
> > + flags |= FDI_PHASE_SYNC_OVR(pipe);
> > + I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
> > + flags |= FDI_PHASE_SYNC_EN(pipe);
> > + I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
> > + POSTING_READ(SOUTH_CHICKEN1);
> > +}
>
> ooh, this even makes the sequence of two writes sound sensible.
>
> Reviewed-by: Keith Packard <keithp@keithp.com>
>
> You didn't happen to check the register values after doing this, did
> you? Just to verify that all of the crazy math works, given that we
> can't actually test whether this fixes anything.
>
Tricky. I need to call this in the gen6 and ivb training routines
rather than the ilk one... Bits seem to be getting set correctly with
the last patch.
--
Jesse Barnes, Intel Open Source Technology Center
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH] drm/i915: apply phase pointer override on SNB+ too
@ 2011-07-29 0:06 Jesse Barnes
0 siblings, 0 replies; 9+ messages in thread
From: Jesse Barnes @ 2011-07-29 0:06 UTC (permalink / raw)
To: intel-gfx
These bits moved around on SNB and above.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
---
drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++++++
drivers/gpu/drm/i915/intel_display.c | 34 ++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+), 0 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5d5def7..d5a9812 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3075,6 +3075,18 @@
#define TRANS_6BPC (2<<5)
#define TRANS_12BPC (3<<5)
+#define _TRANSA_CHICKEN2 0xf0064
+#define _TRANSB_CHICKEN2 0xf1064
+#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
+
+#define SOUTH_CHICKEN1 0xc2000
+#define FDIA_PHASE_SYNC_OVR (1<<19)
+#define FDIA_PHASE_SYNC_EN (1<<18)
+#define FDIB_PHASE_SYNC_OVR (1<<17)
+#define FDIB_PHASE_SYNC_EN (1<<16)
+#define FDIC_PHASE_SYNC_OVR (1<<15)
+#define FDIC_PHASE_SYNC_EN (1<<14)
#define SOUTH_CHICKEN2 0xc2004
#define DPLS_EDP_PPS_FIX_DIS (1<<0)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5609c06..187b035 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2133,6 +2133,23 @@ static void ironlake_fdi_link_train(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
FDI_RX_PHASE_SYNC_POINTER_EN);
+ } else if (HAS_PCH_CPT(dev)) {
+ u32 flags;
+ switch (pipe) {
+ case 0:
+ flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+ break;
+ case 2:
+ flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+ break;
+ case 3:
+ flags = FDIA_PHASE_SYNC_OVR | FDIA_PHASE_SYNC_EN;
+ break;
+ default:
+ break;
+ }
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
}
reg = FDI_RX_IIR(pipe);
@@ -2490,6 +2507,23 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
I915_WRITE(FDI_RX_CHICKEN(pipe),
I915_READ(FDI_RX_CHICKEN(pipe) &
~FDI_RX_PHASE_SYNC_POINTER_EN));
+ } else if (HAS_PCH_CPT(dev)) {
+ u32 flags;
+ switch (pipe) {
+ case 0:
+ flags = FDIA_PHASE_SYNC_OVR;
+ break;
+ case 2:
+ flags = FDIA_PHASE_SYNC_OVR;
+ break;
+ case 3:
+ flags = FDIA_PHASE_SYNC_OVR;
+ break;
+ default:
+ break;
+ }
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
+ I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
}
/* still set train pattern 1 */
--
1.7.4.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
end of thread, other threads:[~2011-07-29 21:55 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-07-29 0:07 [PATCH] drm/i915: apply phase pointer override on SNB+ too Jesse Barnes
2011-07-29 17:28 ` Keith Packard
-- strict thread matches above, loose matches on Subject: below --
2011-07-29 19:42 Jesse Barnes
2011-07-29 21:22 ` Keith Packard
2011-07-29 21:55 ` Jesse Barnes
2011-07-29 17:50 Jesse Barnes
2011-07-29 18:47 ` Keith Packard
2011-07-29 19:43 ` Jesse Barnes
2011-07-29 0:06 Jesse Barnes
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