[PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 36f0300a21bfa..05178ee8e0e3a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 					      unsigned type,
 					      enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
 					      unsigned type,
 					      enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
@@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 					    unsigned type,
 					    enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (type) {
 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
 		gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
@@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 	return 0;
 }
 
-- 
2.52.0

[PATCH 02/12] drm/amdgpu/gmc9: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e35ed0cc2ec62..335163be45c1c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -468,6 +468,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 	struct amdgpu_vmhub *hub;
 	u32 tmp, reg, bits, i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 		VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
 		VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
@@ -536,6 +537,7 @@ static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 03/12] drm/amdgpu/gfx10: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 496121bdc1de1..31dd0aeef509d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -9141,6 +9141,7 @@ static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 					    unsigned int type,
 					    enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (type) {
 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
 		gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
@@ -9175,6 +9176,8 @@ static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
@@ -9226,6 +9229,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -9260,6 +9264,7 @@ static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -9272,6 +9277,7 @@ static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -9306,6 +9312,8 @@ static int gfx_v10_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
@@ -9317,6 +9325,7 @@ static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -9337,6 +9346,7 @@ static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -9410,6 +9420,7 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
 	uint32_t tmp, target;
 	struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	if (ring->me == 1)
 		target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
 	else
@@ -9444,6 +9455,8 @@ static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
 		BUG(); /* kiq only support GENERIC2_INT now */
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
-- 
2.52.0

[PATCH 04/12] drm/amdgpu/gmc9: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 2568eeaae9454..7a8e86efdfe40 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -64,6 +64,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 				   struct amdgpu_irq_src *src, unsigned int type,
 				   enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 		/* MM HUB */
@@ -92,6 +93,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 05/12] drm/amdgpu/sdma5: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index edb1e4d3f9292..c767429504e41 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1689,6 +1689,7 @@ static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
 {
 	u32 sdma_cntl;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	if (!amdgpu_sriov_vf(adev)) {
 		u32 reg_offset = (type == AMDGPU_SDMA_IRQ_INSTANCE0) ?
 			sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_CNTL) :
@@ -1699,6 +1700,7 @@ static int sdma_v5_0_set_trap_irq_state(struct amdgpu_device *adev,
 					  state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 		WREG32(reg_offset, sdma_cntl);
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 06/12] drm/amdgpu/sdma5.2: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index a57fe976cccaf..861d48b7fe9bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1607,12 +1607,14 @@ static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
 	u32 sdma_cntl;
 	u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	if (!amdgpu_sriov_vf(adev)) {
 		sdma_cntl = RREG32(reg_offset);
 		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
 			       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 		WREG32(reg_offset, sdma_cntl);
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 07/12] drm/amdgpu/gfx11: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 5ad2516a60240..ddbb92825fac3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -6421,6 +6421,7 @@ static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 					    unsigned type,
 					    enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (type) {
 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
 		gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
@@ -6443,6 +6444,8 @@ static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
@@ -6507,6 +6510,7 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -6541,6 +6545,7 @@ static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -6553,6 +6558,7 @@ static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -6587,6 +6593,8 @@ static int gfx_v11_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
@@ -6598,6 +6606,7 @@ static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -6618,6 +6627,7 @@ static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 08/12] drm/amdgpu/sdma6: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 210ea6ba6212f..1baad542db043 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1620,15 +1620,16 @@ static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev,
 					enum amdgpu_interrupt_state state)
 {
 	u32 sdma_cntl;
-
 	u32 reg_offset = sdma_v6_0_get_reg_offset(adev, type, regSDMA0_CNTL);
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	if (!amdgpu_sriov_vf(adev)) {
 		sdma_cntl = RREG32(reg_offset);
 		sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
 				state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 		WREG32(reg_offset, sdma_cntl);
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 09/12] drm/amdgpu/gfx12: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 4d5c6bdd8cad7..d5ca57b670cd0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -4787,6 +4787,7 @@ static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 					    unsigned type,
 					    enum amdgpu_interrupt_state state)
 {
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (type) {
 	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
 		gfx_v12_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
@@ -4809,6 +4810,8 @@ static int gfx_v12_0_set_eop_interrupt_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
@@ -4873,6 +4876,7 @@ static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -4907,6 +4911,7 @@ static int gfx_v12_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -4919,6 +4924,7 @@ static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -4953,6 +4959,8 @@ static int gfx_v12_0_set_bad_op_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
+
 	return 0;
 }
 
@@ -4964,6 +4972,7 @@ static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	u32 cp_int_cntl_reg, cp_int_cntl;
 	int i, j;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
 	case AMDGPU_IRQ_STATE_ENABLE:
@@ -4984,6 +4993,7 @@ static int gfx_v12_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 10/12] drm/amdgpu/gfx12.1: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 2519bdf4d109e..8116625c92d92 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -3575,6 +3575,7 @@ static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev,
 {
 	int i, num_xcc;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 	for (i = 0; i < num_xcc; i++) {
 		switch (type) {
@@ -3598,6 +3599,7 @@ static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev,
 			break;
 		}
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -3668,6 +3670,7 @@ static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev,
 {
 	int i, num_xcc;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
@@ -3680,6 +3683,7 @@ static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
@@ -3691,6 +3695,7 @@ static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev,
 {
 	int i, num_xcc;
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	num_xcc = NUM_XCC(adev->gfx.xcc_mask);
 	switch (state) {
 	case AMDGPU_IRQ_STATE_DISABLE:
@@ -3703,6 +3708,7 @@ static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev,
 	default:
 		break;
 	}
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 11/12] drm/amdgpu/sdma7: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 3b4417d19212e..90d5b017d9e14 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1545,13 +1545,14 @@ static int sdma_v7_0_set_trap_irq_state(struct amdgpu_device *adev,
 					enum amdgpu_interrupt_state state)
 {
 	u32 sdma_cntl;
-
 	u32 reg_offset = sdma_v7_0_get_reg_offset(adev, type, regSDMA0_CNTL);
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	sdma_cntl = RREG32(reg_offset);
 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 	WREG32(reg_offset, sdma_cntl);
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

[PATCH 12/12] drm/amdgpu/sdma7.1: handle gfxoff in interrupt set functions

[Alex Deucher]

Need to make sure gfxoff is disallowed when we touch GC
registers over MMIO.

Cc: Yifan Zhang <yifan1.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
index d8167ce18dbd8..38bc0e9edd86e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
@@ -1482,13 +1482,14 @@ static int sdma_v7_1_set_trap_irq_state(struct amdgpu_device *adev,
 					enum amdgpu_interrupt_state state)
 {
 	u32 sdma_cntl;
-
 	u32 reg_offset = sdma_v7_1_get_reg_offset(adev, type, regSDMA0_SDMA_CNTL);
 
+	amdgpu_gfx_off_ctrl(adev, false);
 	sdma_cntl = RREG32(reg_offset);
 	sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_SDMA_CNTL, TRAP_ENABLE,
 		       state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
 	WREG32(reg_offset, sdma_cntl);
+	amdgpu_gfx_off_ctrl(adev, true);
 
 	return 0;
 }
-- 
2.52.0

Re: [PATCH 04/12] drm/amdgpu/gmc9: handle gfxoff in interrupt set functions

[Alex Deucher]

On Mon, Jan 26, 2026 at 3:17 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>

Patch title should say gmc10.  Fixed locally.

Alex

> Need to make sure gfxoff is disallowed when we touch GC
> registers over MMIO.
>
> Cc: Yifan Zhang <yifan1.zhang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 2568eeaae9454..7a8e86efdfe40 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -64,6 +64,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>                                    struct amdgpu_irq_src *src, unsigned int type,
>                                    enum amdgpu_interrupt_state state)
>  {
> +       amdgpu_gfx_off_ctrl(adev, false);
>         switch (state) {
>         case AMDGPU_IRQ_STATE_DISABLE:
>                 /* MM HUB */
> @@ -92,6 +93,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>         default:
>                 break;
>         }
> +       amdgpu_gfx_off_ctrl(adev, true);
>
>         return 0;
>  }
> --
> 2.52.0
>

RE: [PATCH 04/12] drm/amdgpu/gmc9: handle gfxoff in interrupt set functions

[Zhang, Yifan]

[Public]

This series is :

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>

-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Tuesday, January 27, 2026 4:49 AM
To: Deucher, Alexander <Alexander.Deucher@amd.com>
Cc: amd-gfx@lists.freedesktop.org; Zhang, Yifan <Yifan1.Zhang@amd.com>
Subject: Re: [PATCH 04/12] drm/amdgpu/gmc9: handle gfxoff in interrupt set functions

On Mon, Jan 26, 2026 at 3:1 PM Alex Deucher <alexander.deucher@amd.com> wrote:
>

Patch title should say gmc10.  Fixed locally.

Alex

> Need to make sure gfxoff is disallowed when we touch GC registers over
> MMIO.
>
> Cc: Yifan Zhang <yifan1.zhang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> index 2568eeaae9454..7a8e86efdfe40 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
> @@ -64,6 +64,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>                                    struct amdgpu_irq_src *src, unsigned int type,
>                                    enum amdgpu_interrupt_state state)
> {
> +       amdgpu_gfx_off_ctrl(adev, false);
>         switch (state) {
>         case AMDGPU_IRQ_STATE_DISABLE:
>                 /* MM HUB */
> @@ -92,6 +93,7 @@ gmc_v10_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
>         default:
>                 break;
>         }
> +       amdgpu_gfx_off_ctrl(adev, true);
>
>         return 0;
>  }
> --
> 2.52.0
>

Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Lazar, Lijo]

On 27-Jan-26 1:37 AM, Alex Deucher wrote:
> Need to make sure gfxoff is disallowed when we touch GC
> registers over MMIO.
> 

I think interrupt enable/disable sequence is only supposed to be done 
under ip power/clock ungate sequence like in hw init/resume/suspend 
sequences. The fix probably should be in the higher level sequence which 
doesn't take care of that.

Thanks,
Lijo

> Cc: Yifan Zhang <yifan1.zhang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 36f0300a21bfa..05178ee8e0e3a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>   	u32 cp_int_cntl_reg, cp_int_cntl;
>   	int i, j;
>   
> +	amdgpu_gfx_off_ctrl(adev, false);
>   	switch (state) {
>   	case AMDGPU_IRQ_STATE_DISABLE:
>   	case AMDGPU_IRQ_STATE_ENABLE:
> @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>   	default:
>   		break;
>   	}
> +	amdgpu_gfx_off_ctrl(adev, true);
>   
>   	return 0;
>   }
> @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>   	u32 cp_int_cntl_reg, cp_int_cntl;
>   	int i, j;
>   
> +	amdgpu_gfx_off_ctrl(adev, false);
>   	switch (state) {
>   	case AMDGPU_IRQ_STATE_DISABLE:
>   	case AMDGPU_IRQ_STATE_ENABLE:
> @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>   	default:
>   		break;
>   	}
> +	amdgpu_gfx_off_ctrl(adev, true);
>   
>   	return 0;
>   }
> @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>   					      unsigned type,
>   					      enum amdgpu_interrupt_state state)
>   {
> +	amdgpu_gfx_off_ctrl(adev, false);
>   	switch (state) {
>   	case AMDGPU_IRQ_STATE_DISABLE:
>   	case AMDGPU_IRQ_STATE_ENABLE:
> @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>   	default:
>   		break;
>   	}
> +	amdgpu_gfx_off_ctrl(adev, true);
>   
>   	return 0;
>   }
> @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>   					      unsigned type,
>   					      enum amdgpu_interrupt_state state)
>   {
> +	amdgpu_gfx_off_ctrl(adev, false);
>   	switch (state) {
>   	case AMDGPU_IRQ_STATE_DISABLE:
>   		WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
> @@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>   	default:
>   		break;
>   	}
> +	amdgpu_gfx_off_ctrl(adev, true);
>   
>   	return 0;
>   }
> @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>   					    unsigned type,
>   					    enum amdgpu_interrupt_state state)
>   {
> +	amdgpu_gfx_off_ctrl(adev, false);
>   	switch (type) {
>   	case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
>   		gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
> @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>   	default:
>   		break;
>   	}
> +	amdgpu_gfx_off_ctrl(adev, true);
>   	return 0;
>   }
>   

Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Alex Deucher]

On Tue, Jan 27, 2026 at 12:02 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 27-Jan-26 1:37 AM, Alex Deucher wrote:
> > Need to make sure gfxoff is disallowed when we touch GC
> > registers over MMIO.
> >
>
> I think interrupt enable/disable sequence is only supposed to be done
> under ip power/clock ungate sequence like in hw init/resume/suspend
> sequences. The fix probably should be in the higher level sequence which
> doesn't take care of that.

In that case, Yifan's original patch is probably fine as is.  Someone
should still double check all of the call paths though.

Alex

>
> Thanks,
> Lijo
>
> > Cc: Yifan Zhang <yifan1.zhang@amd.com>
> > Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> > ---
> >   drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
> >   1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > index 36f0300a21bfa..05178ee8e0e3a 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
> >       u32 cp_int_cntl_reg, cp_int_cntl;
> >       int i, j;
> >
> > +     amdgpu_gfx_off_ctrl(adev, false);
> >       switch (state) {
> >       case AMDGPU_IRQ_STATE_DISABLE:
> >       case AMDGPU_IRQ_STATE_ENABLE:
> > @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
> >       default:
> >               break;
> >       }
> > +     amdgpu_gfx_off_ctrl(adev, true);
> >
> >       return 0;
> >   }
> > @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
> >       u32 cp_int_cntl_reg, cp_int_cntl;
> >       int i, j;
> >
> > +     amdgpu_gfx_off_ctrl(adev, false);
> >       switch (state) {
> >       case AMDGPU_IRQ_STATE_DISABLE:
> >       case AMDGPU_IRQ_STATE_ENABLE:
> > @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
> >       default:
> >               break;
> >       }
> > +     amdgpu_gfx_off_ctrl(adev, true);
> >
> >       return 0;
> >   }
> > @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
> >                                             unsigned type,
> >                                             enum amdgpu_interrupt_state state)
> >   {
> > +     amdgpu_gfx_off_ctrl(adev, false);
> >       switch (state) {
> >       case AMDGPU_IRQ_STATE_DISABLE:
> >       case AMDGPU_IRQ_STATE_ENABLE:
> > @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
> >       default:
> >               break;
> >       }
> > +     amdgpu_gfx_off_ctrl(adev, true);
> >
> >       return 0;
> >   }
> > @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
> >                                             unsigned type,
> >                                             enum amdgpu_interrupt_state state)
> >   {
> > +     amdgpu_gfx_off_ctrl(adev, false);
> >       switch (state) {
> >       case AMDGPU_IRQ_STATE_DISABLE:
> >               WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
> > @@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
> >       default:
> >               break;
> >       }
> > +     amdgpu_gfx_off_ctrl(adev, true);
> >
> >       return 0;
> >   }
> > @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
> >                                           unsigned type,
> >                                           enum amdgpu_interrupt_state state)
> >   {
> > +     amdgpu_gfx_off_ctrl(adev, false);
> >       switch (type) {
> >       case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
> >               gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
> > @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
> >       default:
> >               break;
> >       }
> > +     amdgpu_gfx_off_ctrl(adev, true);
> >       return 0;
> >   }
> >
>

Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Lazar, Lijo]

On 30-Jan-26 8:18 PM, Alex Deucher wrote:
> On Tue, Jan 27, 2026 at 12:02 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 27-Jan-26 1:37 AM, Alex Deucher wrote:
>>> Need to make sure gfxoff is disallowed when we touch GC
>>> registers over MMIO.
>>>
>>
>> I think interrupt enable/disable sequence is only supposed to be done
>> under ip power/clock ungate sequence like in hw init/resume/suspend
>> sequences. The fix probably should be in the higher level sequence which
>> doesn't take care of that.
> 
> In that case, Yifan's original patch is probably fine as is.  Someone
> should still double check all of the call paths though.
> 

Original one is also not correct. For example, if this is happening 
after reset re initialization, only that sequence needs to be modified 
to keep the affected IPs ungated during reinit.

Thanks,
Lijo

> Alex
> 
>>
>> Thanks,
>> Lijo
>>
>>> Cc: Yifan Zhang <yifan1.zhang@amd.com>
>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>> ---
>>>    drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
>>>    1 file changed, 10 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> index 36f0300a21bfa..05178ee8e0e3a 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>> @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>>>        u32 cp_int_cntl_reg, cp_int_cntl;
>>>        int i, j;
>>>
>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>        switch (state) {
>>>        case AMDGPU_IRQ_STATE_DISABLE:
>>>        case AMDGPU_IRQ_STATE_ENABLE:
>>> @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>>>        default:
>>>                break;
>>>        }
>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>
>>>        return 0;
>>>    }
>>> @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>>>        u32 cp_int_cntl_reg, cp_int_cntl;
>>>        int i, j;
>>>
>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>        switch (state) {
>>>        case AMDGPU_IRQ_STATE_DISABLE:
>>>        case AMDGPU_IRQ_STATE_ENABLE:
>>> @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>>>        default:
>>>                break;
>>>        }
>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>
>>>        return 0;
>>>    }
>>> @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>>>                                              unsigned type,
>>>                                              enum amdgpu_interrupt_state state)
>>>    {
>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>        switch (state) {
>>>        case AMDGPU_IRQ_STATE_DISABLE:
>>>        case AMDGPU_IRQ_STATE_ENABLE:
>>> @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>>>        default:
>>>                break;
>>>        }
>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>
>>>        return 0;
>>>    }
>>> @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>>>                                              unsigned type,
>>>                                              enum amdgpu_interrupt_state state)
>>>    {
>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>        switch (state) {
>>>        case AMDGPU_IRQ_STATE_DISABLE:
>>>                WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
>>> @@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>>>        default:
>>>                break;
>>>        }
>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>
>>>        return 0;
>>>    }
>>> @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>>>                                            unsigned type,
>>>                                            enum amdgpu_interrupt_state state)
>>>    {
>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>        switch (type) {
>>>        case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
>>>                gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
>>> @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>>>        default:
>>>                break;
>>>        }
>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>        return 0;
>>>    }
>>>
>>

Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Alex Deucher]

On Fri, Jan 30, 2026 at 10:05 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>
>
>
> On 30-Jan-26 8:18 PM, Alex Deucher wrote:
> > On Tue, Jan 27, 2026 at 12:02 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
> >>
> >>
> >>
> >> On 27-Jan-26 1:37 AM, Alex Deucher wrote:
> >>> Need to make sure gfxoff is disallowed when we touch GC
> >>> registers over MMIO.
> >>>
> >>
> >> I think interrupt enable/disable sequence is only supposed to be done
> >> under ip power/clock ungate sequence like in hw init/resume/suspend
> >> sequences. The fix probably should be in the higher level sequence which
> >> doesn't take care of that.
> >
> > In that case, Yifan's original patch is probably fine as is.  Someone
> > should still double check all of the call paths though.
> >
>
> Original one is also not correct. For example, if this is happening
> after reset re initialization, only that sequence needs to be modified
> to keep the affected IPs ungated during reinit.

It also gets called in amdgpu_device_fini_hw().

Alex

>
> Thanks,
> Lijo
>
> > Alex
> >
> >>
> >> Thanks,
> >> Lijo
> >>
> >>> Cc: Yifan Zhang <yifan1.zhang@amd.com>
> >>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> >>> ---
> >>>    drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
> >>>    1 file changed, 10 insertions(+)
> >>>
> >>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> index 36f0300a21bfa..05178ee8e0e3a 100644
> >>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> >>> @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
> >>>        u32 cp_int_cntl_reg, cp_int_cntl;
> >>>        int i, j;
> >>>
> >>> +     amdgpu_gfx_off_ctrl(adev, false);
> >>>        switch (state) {
> >>>        case AMDGPU_IRQ_STATE_DISABLE:
> >>>        case AMDGPU_IRQ_STATE_ENABLE:
> >>> @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
> >>>        default:
> >>>                break;
> >>>        }
> >>> +     amdgpu_gfx_off_ctrl(adev, true);
> >>>
> >>>        return 0;
> >>>    }
> >>> @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
> >>>        u32 cp_int_cntl_reg, cp_int_cntl;
> >>>        int i, j;
> >>>
> >>> +     amdgpu_gfx_off_ctrl(adev, false);
> >>>        switch (state) {
> >>>        case AMDGPU_IRQ_STATE_DISABLE:
> >>>        case AMDGPU_IRQ_STATE_ENABLE:
> >>> @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
> >>>        default:
> >>>                break;
> >>>        }
> >>> +     amdgpu_gfx_off_ctrl(adev, true);
> >>>
> >>>        return 0;
> >>>    }
> >>> @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
> >>>                                              unsigned type,
> >>>                                              enum amdgpu_interrupt_state state)
> >>>    {
> >>> +     amdgpu_gfx_off_ctrl(adev, false);
> >>>        switch (state) {
> >>>        case AMDGPU_IRQ_STATE_DISABLE:
> >>>        case AMDGPU_IRQ_STATE_ENABLE:
> >>> @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
> >>>        default:
> >>>                break;
> >>>        }
> >>> +     amdgpu_gfx_off_ctrl(adev, true);
> >>>
> >>>        return 0;
> >>>    }
> >>> @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
> >>>                                              unsigned type,
> >>>                                              enum amdgpu_interrupt_state state)
> >>>    {
> >>> +     amdgpu_gfx_off_ctrl(adev, false);
> >>>        switch (state) {
> >>>        case AMDGPU_IRQ_STATE_DISABLE:
> >>>                WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
> >>> @@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
> >>>        default:
> >>>                break;
> >>>        }
> >>> +     amdgpu_gfx_off_ctrl(adev, true);
> >>>
> >>>        return 0;
> >>>    }
> >>> @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
> >>>                                            unsigned type,
> >>>                                            enum amdgpu_interrupt_state state)
> >>>    {
> >>> +     amdgpu_gfx_off_ctrl(adev, false);
> >>>        switch (type) {
> >>>        case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
> >>>                gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
> >>> @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
> >>>        default:
> >>>                break;
> >>>        }
> >>> +     amdgpu_gfx_off_ctrl(adev, true);
> >>>        return 0;
> >>>    }
> >>>
> >>
>

Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Lazar, Lijo]

On 30-Jan-26 9:19 PM, Alex Deucher wrote:
> On Fri, Jan 30, 2026 at 10:05 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 30-Jan-26 8:18 PM, Alex Deucher wrote:
>>> On Tue, Jan 27, 2026 at 12:02 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>>>
>>>>
>>>>
>>>> On 27-Jan-26 1:37 AM, Alex Deucher wrote:
>>>>> Need to make sure gfxoff is disallowed when we touch GC
>>>>> registers over MMIO.
>>>>>
>>>>
>>>> I think interrupt enable/disable sequence is only supposed to be done
>>>> under ip power/clock ungate sequence like in hw init/resume/suspend
>>>> sequences. The fix probably should be in the higher level sequence which
>>>> doesn't take care of that.
>>>
>>> In that case, Yifan's original patch is probably fine as is.  Someone
>>> should still double check all of the call paths though.
>>>
>>
>> Original one is also not correct. For example, if this is happening
>> after reset re initialization, only that sequence needs to be modified
>> to keep the affected IPs ungated during reinit.
> 
> It also gets called in amdgpu_device_fini_hw().
> 

Checked now. What I meant is - we should call ip cg/pg ungate insid 
amdgpu_device_fini_hw() to protect all other accesses within that 
sequence and not restricted to irq_disable/enable all. Now that happens 
a while later in amdgpu_device_ip_fini_early.

Basically, the high level sequence needs IP pg ungate protection.

Thanks,
Lijo

> Alex
> 
>>
>> Thanks,
>> Lijo
>>
>>> Alex
>>>
>>>>
>>>> Thanks,
>>>> Lijo
>>>>
>>>>> Cc: Yifan Zhang <yifan1.zhang@amd.com>
>>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>>>> ---
>>>>>     drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
>>>>>     1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> index 36f0300a21bfa..05178ee8e0e3a 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>>>>>         u32 cp_int_cntl_reg, cp_int_cntl;
>>>>>         int i, j;
>>>>>
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>         case AMDGPU_IRQ_STATE_ENABLE:
>>>>> @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>>>>>         u32 cp_int_cntl_reg, cp_int_cntl;
>>>>>         int i, j;
>>>>>
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>         case AMDGPU_IRQ_STATE_ENABLE:
>>>>> @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>>>>>                                               unsigned type,
>>>>>                                               enum amdgpu_interrupt_state state)
>>>>>     {
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>         case AMDGPU_IRQ_STATE_ENABLE:
>>>>> @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>>>>>                                               unsigned type,
>>>>>                                               enum amdgpu_interrupt_state state)
>>>>>     {
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
>>>>> @@ -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>>>>>                                             unsigned type,
>>>>>                                             enum amdgpu_interrupt_state state)
>>>>>     {
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (type) {
>>>>>         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
>>>>>                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
>>>>> @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>         return 0;
>>>>>     }
>>>>>
>>>>
>>

RE: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions

[Zhang, Yifan]

[Public]

Hi Alex and Lijo,

Revised the patch based on your  comments. Please review [PATCH] drm/amdgpu: Put GPU CG/PG ungate in device_fini_hw and device_halt

Best Regards,
Yifan

-----Original Message-----
From: Lazar, Lijo <Lijo.Lazar@amd.com>
Sent: Saturday, January 31, 2026 2:05 PM
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; amd-gfx@lists.freedesktop.org; Zhang, Yifan <Yifan1.Zhang@amd.com>
Subject: Re: [PATCH 01/12] drm/amdgpu/gfx9: handle gfxoff in interrupt set functions



On 30-Jan-26 9:19 PM, Alex Deucher wrote:
> On Fri, Jan 30, 2026 at 10:05 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>
>>
>>
>> On 30-Jan-26 8:18 PM, Alex Deucher wrote:
>>> On Tue, Jan 27, 2026 at 12:02 AM Lazar, Lijo <lijo.lazar@amd.com> wrote:
>>>>
>>>>
>>>>
>>>> On 27-Jan-26 1:37 AM, Alex Deucher wrote:
>>>>> Need to make sure gfxoff is disallowed when we touch GC registers
>>>>> over MMIO.
>>>>>
>>>>
>>>> I think interrupt enable/disable sequence is only supposed to be
>>>> done under ip power/clock ungate sequence like in hw
>>>> init/resume/suspend sequences. The fix probably should be in the
>>>> higher level sequence which doesn't take care of that.
>>>
>>> In that case, Yifan's original patch is probably fine as is.
>>> Someone should still double check all of the call paths though.
>>>
>>
>> Original one is also not correct. For example, if this is happening
>> after reset re initialization, only that sequence needs to be
>> modified to keep the affected IPs ungated during reinit.
>
> It also gets called in amdgpu_device_fini_hw().
>

Checked now. What I meant is - we should call ip cg/pg ungate insid
amdgpu_device_fini_hw() to protect all other accesses within that sequence and not restricted to irq_disable/enable all. Now that happens a while later in amdgpu_device_ip_fini_early.

Basically, the high level sequence needs IP pg ungate protection.

Thanks,
Lijo

> Alex
>
>>
>> Thanks,
>> Lijo
>>
>>> Alex
>>>
>>>>
>>>> Thanks,
>>>> Lijo
>>>>
>>>>> Cc: Yifan Zhang <yifan1.zhang@amd.com>
>>>>> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
>>>>> ---
>>>>>     drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 ++++++++++
>>>>>     1 file changed, 10 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> index 36f0300a21bfa..05178ee8e0e3a 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>>>>> @@ -6056,6 +6056,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>>>>>         u32 cp_int_cntl_reg, cp_int_cntl;
>>>>>         int i, j;
>>>>>
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>         case AMDGPU_IRQ_STATE_ENABLE:
>>>>> @@ -6080,6 +6081,7 @@ static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6092,6 +6094,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>>>>>         u32 cp_int_cntl_reg, cp_int_cntl;
>>>>>         int i, j;
>>>>>
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>         case AMDGPU_IRQ_STATE_ENABLE:
>>>>> @@ -6116,6 +6119,7 @@ static int gfx_v9_0_set_bad_op_fault_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6125,6 +6129,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>>>>>                                               unsigned type,
>>>>>                                               enum amdgpu_interrupt_state state)
>>>>>     {
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>         case AMDGPU_IRQ_STATE_ENABLE:
>>>>> @@ -6135,6 +6140,7 @@ static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6152,6 +6158,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>>>>>                                               unsigned type,
>>>>>                                               enum amdgpu_interrupt_state state)
>>>>>     {
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (state) {
>>>>>         case AMDGPU_IRQ_STATE_DISABLE:
>>>>>                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, @@
>>>>> -6173,6 +6180,7 @@ static int gfx_v9_0_set_cp_ecc_error_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>
>>>>>         return 0;
>>>>>     }
>>>>> @@ -6183,6 +6191,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>>>>>                                             unsigned type,
>>>>>                                             enum amdgpu_interrupt_state state)
>>>>>     {
>>>>> +     amdgpu_gfx_off_ctrl(adev, false);
>>>>>         switch (type) {
>>>>>         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
>>>>>                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
>>>>> @@ -6214,6 +6223,7 @@ static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
>>>>>         default:
>>>>>                 break;
>>>>>         }
>>>>> +     amdgpu_gfx_off_ctrl(adev, true);
>>>>>         return 0;
>>>>>     }
>>>>>
>>>>
>>