[PATCH 12/21] drm/i915/bdw: posting read the full 64b PTE

[Ben Widawsky <benjamin.widawsky@intel.com>]

For our posting read we were reading only 32b on BDW. There was a FIXME
already - the warning is annoying.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 638fd09..3620a1b 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -899,12 +899,9 @@ static void gen8_ggtt_insert_entries(struct i915_address_space *vm,
 	 * registers and PTEs are within the same BAR that they are potentially
 	 * of NUMA access patterns. Therefore, even with the way we assume
 	 * hardware should work, we must keep this posting read for paranoia.
-	 *
-	 * FIXME(BDW): The check is bogus - we read 32bit but the ptes are
-	 * 64bit.
 	 */
 	if (i != 0)
-		WARN_ON(readl(&gtt_entries[i-1])
+		WARN_ON(readq(&gtt_entries[i-1])
 			!= gen8_pte_encode(addr, level, true));
 
 #if 0 /* TODO: Still needed on GEN8? */
-- 
1.8.4.2