[PATCH 0/5] drm/i915: Gen2 PLL fixes

[PATCH 0/5] drm/i915: Gen2 PLL fixes

[ville.syrjala]

There appear to be some gen2 machines that don't really like the current PLL
limits we have. We also have some accuracy problems with the PLL calculations.
This series aims to eliminate those problems, and at least my 855 machine
seems happier with these patches.

Ville Syrjälä (5):
      drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
      drm/i915: Change N divider minimum from 3 to 2 for gen2
      drm/i915: Increase gen2 vco frequency limit to 1512 MHz
      drm/i915: Fix 66 MHz LVDS SSC freq for gen2
      drm/i915: Decrease gen2 vco frequency minimum to 908 MHz

 drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
 drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
 2 files changed, 23 insertions(+), 19 deletions(-)
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[PATCH 1/5] drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In order to determine the correct p2 divider for LVDS on gen2,
we need to check the CLKB mode from the LVDS port register to
determine if we're dealing with single or dual channel LVDS.

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index af3717a..0d63f57 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7939,12 +7939,17 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
 		else
 			i9xx_clock(refclk, &clock);
 	} else {
-		bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
+		u32 lvds = I915_READ(LVDS);
+		bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
 
 		if (is_lvds) {
 			clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
 				       DPLL_FPA01_P1_POST_DIV_SHIFT);
-			clock.p2 = 14;
+
+			if (lvds & LVDS_CLKB_POWER_UP)
+				clock.p2 = 7;
+			else
+				clock.p2 = 14;
 		} else {
 			if (dpll & PLL_P1_DIVIDE_BY_TWO)
 				clock.p1 = 2;
-- 
1.8.3.2

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[PATCH 2/5] drm/i915: Change N divider minimum from 3 to 2 for gen2

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen.

The VBT mode is as follows:
0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa

The BIOS uses the following DPLL settings:
DPLL = 0x90020000
FP0 = 0x2140e
FP1 = 0x21207

We can't generate that pixel clock currently as we're limiting the N
divider to at least 3, whereas the BIOS uses a value of 2.

Let's reduce the N minimum to 2 and see what happens.

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 0d63f57..f1d3a8f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -91,7 +91,7 @@ intel_fdi_link_freq(struct drm_device *dev)
 static const intel_limit_t intel_limits_i8xx_dac = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
-	.n = { .min = 3, .max = 16 },
+	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
@@ -104,7 +104,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
 static const intel_limit_t intel_limits_i8xx_dvo = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
-	.n = { .min = 3, .max = 16 },
+	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
@@ -117,7 +117,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
 static const intel_limit_t intel_limits_i8xx_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
 	.vco = { .min = 930000, .max = 1400000 },
-	.n = { .min = 3, .max = 16 },
+	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
 	.m2 = { .min = 6, .max = 16 },
-- 
1.8.3.2

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[PATCH 3/5] drm/i915: Increase gen2 vco frequency limit to 1512 MHz

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Bruno Prémont has a 855 machine with a 1400x1050 LVDS screen.

The VBT mode is as follows:
0:"1400x1050" 0 108000 1400 1416 1528 1688 1050 1051 1054 1066 0x8 0xa

The BIOS uses the following DPLL settings:
DPLL = 0x90020000
FP0 = 0x2140e
FP1 = 0x21207

That puts the BIOS generated VCO frequency at 1512 MHz, which is
higher than the 1400 MHz limit we have currently.

Let's bump the VCO limit to 1512 MHz and see what happens.

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f1d3a8f..434cdde 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -90,7 +90,7 @@ intel_fdi_link_freq(struct drm_device *dev)
 
 static const intel_limit_t intel_limits_i8xx_dac = {
 	.dot = { .min = 25000, .max = 350000 },
-	.vco = { .min = 930000, .max = 1400000 },
+	.vco = { .min = 930000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
@@ -103,7 +103,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
 
 static const intel_limit_t intel_limits_i8xx_dvo = {
 	.dot = { .min = 25000, .max = 350000 },
-	.vco = { .min = 930000, .max = 1400000 },
+	.vco = { .min = 930000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
@@ -116,7 +116,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
 
 static const intel_limit_t intel_limits_i8xx_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
-	.vco = { .min = 930000, .max = 1400000 },
+	.vco = { .min = 930000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
-- 
1.8.3.2

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[PATCH 4/5] drm/i915: Fix 66 MHz LVDS SSC freq for gen2

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Store the SSC refclock frequency in kHz to get more accuracy. Currently
we're pretending that 66 MHz is ~66000 kHz, when in fact it is actually
~66667 kHz. By storing the less rounded kHz value we get a much better
accuracy for out pixel clock calculations.

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
 drivers/gpu/drm/i915/intel_display.c | 13 ++++++-------
 2 files changed, 10 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index e4fba39..f88e507 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -327,12 +327,12 @@ static int intel_bios_ssc_frequency(struct drm_device *dev,
 {
 	switch (INTEL_INFO(dev)->gen) {
 	case 2:
-		return alternate ? 66 : 48;
+		return alternate ? 66667 : 48000;
 	case 3:
 	case 4:
-		return alternate ? 100 : 96;
+		return alternate ? 100000 : 96000;
 	default:
-		return alternate ? 100 : 120;
+		return alternate ? 100000 : 120000;
 	}
 }
 
@@ -796,7 +796,7 @@ init_vbt_defaults(struct drm_i915_private *dev_priv)
 	 */
 	dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev,
 			!HAS_PCH_SPLIT(dev));
-	DRM_DEBUG_KMS("Set default to SSC at %dMHz\n", dev_priv->vbt.lvds_ssc_freq);
+	DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq);
 
 	for (port = PORT_A; port < I915_MAX_PORTS; port++) {
 		struct ddi_vbt_port_info *info =
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 434cdde..9ff03ce 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4757,9 +4757,8 @@ static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
 		refclk = 100000;
 	} else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 	    intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
-		refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
-		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
-			      refclk / 1000);
+		refclk = dev_priv->vbt.lvds_ssc_freq;
+		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
 	} else if (!IS_GEN2(dev)) {
 		refclk = 96000;
 	} else {
@@ -5905,9 +5904,9 @@ static int ironlake_get_refclk(struct drm_crtc *crtc)
 	}
 
 	if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
-		DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
+		DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
 			      dev_priv->vbt.lvds_ssc_freq);
-		return dev_priv->vbt.lvds_ssc_freq * 1000;
+		return dev_priv->vbt.lvds_ssc_freq;
 	}
 
 	return 120000;
@@ -6169,7 +6168,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
 	factor = 21;
 	if (is_lvds) {
 		if ((intel_panel_use_ssc(dev_priv) &&
-		     dev_priv->vbt.lvds_ssc_freq == 100) ||
+		     dev_priv->vbt.lvds_ssc_freq == 100000) ||
 		    (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
 			factor = 25;
 	} else if (intel_crtc->config.sdvo_tv_clock)
@@ -7876,7 +7875,7 @@ static int i9xx_pll_refclk(struct drm_device *dev,
 	u32 dpll = pipe_config->dpll_hw_state.dpll;
 
 	if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
-		return dev_priv->vbt.lvds_ssc_freq * 1000;
+		return dev_priv->vbt.lvds_ssc_freq;
 	else if (HAS_PCH_SPLIT(dev))
 		return 120000;
 	else if (!IS_GEN2(dev))
-- 
1.8.3.2

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[PATCH 5/5] drm/i915: Decrease gen2 vco frequency minimum to 908 MHz

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

On my 855 machine the BIOS uses the following DPLL settings:
DPLL 0x90016000
FP0 = 0x61207
FP1 = 0x21207

With the 66MHz SSC refclock, that puts the BIOS generated VCO
frequency at ~908 MHz, which is lower than the 930 MHz limit
we have currently. This also results in the pixel clock coming
out significantly higher than the requested 65 MHz when we try
to recompute it.

Reduce the the VCO limit to 908 MHz. Combined with the earlier
SSC reference clock accuracy fix, this results in the pixel clock
coming out as 65.08 MHz which is quite close to the target. For
some reason the BIOS uses 64.881 MHz, which isn't quite as close.

This makes kms_flip wf_vblank-ts-check pass for the first time
on this machine \o/

Cc: Bruno Prémont <bonbons@linux-vserver.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9ff03ce..3bf34a4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -90,7 +90,7 @@ intel_fdi_link_freq(struct drm_device *dev)
 
 static const intel_limit_t intel_limits_i8xx_dac = {
 	.dot = { .min = 25000, .max = 350000 },
-	.vco = { .min = 930000, .max = 1512000 },
+	.vco = { .min = 908000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
@@ -103,7 +103,7 @@ static const intel_limit_t intel_limits_i8xx_dac = {
 
 static const intel_limit_t intel_limits_i8xx_dvo = {
 	.dot = { .min = 25000, .max = 350000 },
-	.vco = { .min = 930000, .max = 1512000 },
+	.vco = { .min = 908000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
@@ -116,7 +116,7 @@ static const intel_limit_t intel_limits_i8xx_dvo = {
 
 static const intel_limit_t intel_limits_i8xx_lvds = {
 	.dot = { .min = 25000, .max = 350000 },
-	.vco = { .min = 930000, .max = 1512000 },
+	.vco = { .min = 908000, .max = 1512000 },
 	.n = { .min = 2, .max = 16 },
 	.m = { .min = 96, .max = 140 },
 	.m1 = { .min = 18, .max = 26 },
-- 
1.8.3.2

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Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes

[Bruno Prémont]

[-- Attachment #1: Type: text/plain, Size: 3448 bytes --]

Hi Ville,

On Mon, 09 December 2013 ville.syrjala@linux.intel.com wrote:
> There appear to be some gen2 machines that don't really like the current PLL
> limits we have. We also have some accuracy problems with the PLL calculations.
> This series aims to eliminate those problems, and at least my 855 machine
> seems happier with these patches.
> 
> Ville Syrjälä (5):
>       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
>       drm/i915: Change N divider minimum from 3 to 2 for gen2
>       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
>       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
>       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> 
>  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
>  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
>  2 files changed, 23 insertions(+), 19 deletions(-)

Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
the PLL debug patch).

The WARN() are not hit anymore.

[    0.782919] [drm:intel_shared_dpll_init], 0 shared PLLs initialized
[    0.782925] vgaarb: device changed decodes: PCI:0000:00:02.0,olddecodes=io+mem,decodes=io+mem:owns=io+mem
[    0.870218] [drm] GMBUS [i915 gmbus panel] timed out, falling back to bit banging on pin 3
...
[    0.966313] [drm:intel_dump_pipe_config], DPLL = 0x808b0000
[    0.966316] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    0.966318] [drm:intel_dump_pipe_config], FP0 = 0x21207
[    0.966320] [drm:intel_dump_pipe_config], FP1 = 0x21207
...
[    0.966369] [drm:intel_dump_pipe_config], DPLL = 0x90020000
[    0.966371] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    0.966373] [drm:intel_dump_pipe_config], FP0 = 0x2140e
[    0.966375] [drm:intel_dump_pipe_config], FP1 = 0x21207
...
[    1.020672] [drm:intel_dump_pipe_config], DPLL = 0x0
[    1.020674] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    1.020677] [drm:intel_dump_pipe_config], FP0 = 0x0
[    1.020679] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[    1.121981] fbcon: inteldrmfb (fb0) is primary device
[    1.122810] [drm:intel_crtc_set_config], [CRTC:3] [NOFB]
[    1.122817] [drm:intel_set_config_compute_mode_changes], computed changes for [CRTC:3], mode_changed=0, fb_changed=0
...
[    1.122907] [drm:intel_dump_pipe_config], DPLL = 0x0
[    1.122908] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[    1.122910] [drm:intel_dump_pipe_config], FP0 = 0x0
[    1.122911] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[    1.646702] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
[    1.646765] i915 0000:00:02.0: registered panic notifier
[    1.646831] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
...
[   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
[   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
[   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[   69.216340] [drm:intel_dump_pipe_config], DPLL = 0x0
[   69.216342] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[   69.216345] [drm:intel_dump_pipe_config], FP0 = 0x0
[   69.216347] [drm:intel_dump_pipe_config], FP1 = 0x0
...
[   69.329866] [drm:intel_dump_pipe_config], DPLL = 0x0
[   69.329870] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
[   69.329874] [drm:intel_dump_pipe_config], FP0 = 0x0
[   69.329878] [drm:intel_dump_pipe_config], FP1 = 0x0

Bruno

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Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes

[Ville Syrjälä]

On Tue, Dec 10, 2013 at 12:52:27PM +0100, Bruno Prémont wrote:
> Hi Ville,
> 
> On Mon, 09 December 2013 ville.syrjala@linux.intel.com wrote:
> > There appear to be some gen2 machines that don't really like the current PLL
> > limits we have. We also have some accuracy problems with the PLL calculations.
> > This series aims to eliminate those problems, and at least my 855 machine
> > seems happier with these patches.
> > 
> > Ville Syrjälä (5):
> >       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
> >       drm/i915: Change N divider minimum from 3 to 2 for gen2
> >       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
> >       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
> >       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> > 
> >  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
> >  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
> >  2 files changed, 23 insertions(+), 19 deletions(-)
> 
> Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
> the PLL debug patch).
> 
> The WARN() are not hit anymore.
> 
<snip>
> [   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
> [   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
> [   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
> [   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0

OK, so I think the problem got fixed, but my debug patch wasn't
all that good since it doesn't dump the values we computed unless
the clock is off.

Can you still run this (as root) when the LVDS output is active:
# intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c

intel_reg_read is part of intel-gpu-tools.

I just want to confirm we calculated the DPLL registers correctly.
I know we at least got close since ther WARN is gone, but by my
calculations we should get exactly the same as what the BIOS used.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes

[Bruno Prémont]

Hi Ville,

On Tue, 10 December 2013 Ville Syrjälä wrote:
> On Tue, Dec 10, 2013 at 12:52:27PM +0100, Bruno Prémont wrote:
> > On Mon, 09 December 2013 Ville Syrjälä wrote:
> > > There appear to be some gen2 machines that don't really like the current PLL
> > > limits we have. We also have some accuracy problems with the PLL calculations.
> > > This series aims to eliminate those problems, and at least my 855 machine
> > > seems happier with these patches.
> > > 
> > > Ville Syrjälä (5):
> > >       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
> > >       drm/i915: Change N divider minimum from 3 to 2 for gen2
> > >       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
> > >       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
> > >       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> > > 
> > >  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
> > >  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
> > >  2 files changed, 23 insertions(+), 19 deletions(-)
> > 
> > Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
> > the PLL debug patch).
> > 
> > The WARN() are not hit anymore.
> > 
> <snip>
> > [   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
> > [   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
> > [   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
> > [   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0
> 
> OK, so I think the problem got fixed, but my debug patch wasn't
> all that good since it doesn't dump the values we computed unless
> the clock is off.
> 
> Can you still run this (as root) when the LVDS output is active:
> # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> 
> intel_reg_read is part of intel-gpu-tools.

Here are the results (when already running under X since previous
my mail):

# intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
0x6014 : 0x0
0x6018 : 0x90020000
0x6040 : 0x2140E
0x6044 : 0x2140E
0x6048 : 0x2140E
0x604C : 0x2140E

> I just want to confirm we calculated the DPLL registers correctly.
> I know we at least got close since ther WARN is gone, but by my
> calculations we should get exactly the same as what the BIOS used.

Bruno
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Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes

[Ville Syrjälä]

On Tue, Dec 10, 2013 at 01:33:01PM +0100, Bruno Prémont wrote:
> Hi Ville,
> 
> On Tue, 10 December 2013 Ville Syrjälä wrote:
> > On Tue, Dec 10, 2013 at 12:52:27PM +0100, Bruno Prémont wrote:
> > > On Mon, 09 December 2013 Ville Syrjälä wrote:
> > > > There appear to be some gen2 machines that don't really like the current PLL
> > > > limits we have. We also have some accuracy problems with the PLL calculations.
> > > > This series aims to eliminate those problems, and at least my 855 machine
> > > > seems happier with these patches.
> > > > 
> > > > Ville Syrjälä (5):
> > > >       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
> > > >       drm/i915: Change N divider minimum from 3 to 2 for gen2
> > > >       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
> > > >       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
> > > >       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> > > > 
> > > >  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
> > > >  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
> > > >  2 files changed, 23 insertions(+), 19 deletions(-)
> > > 
> > > Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
> > > the PLL debug patch).
> > > 
> > > The WARN() are not hit anymore.
> > > 
> > <snip>
> > > [   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
> > > [   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
> > > [   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
> > > [   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0
> > 
> > OK, so I think the problem got fixed, but my debug patch wasn't
> > all that good since it doesn't dump the values we computed unless
> > the clock is off.
> > 
> > Can you still run this (as root) when the LVDS output is active:
> > # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> > 
> > intel_reg_read is part of intel-gpu-tools.
> 
> Here are the results (when already running under X since previous
> my mail):
> 
> # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> 0x6014 : 0x0
> 0x6018 : 0x90020000
> 0x6040 : 0x2140E
> 0x6044 : 0x2140E
> 0x6048 : 0x2140E
> 0x604C : 0x2140E

Thanks. That's what the BIOS had, so it seems we're good. Now I suppose
we just need to figure out if we dare change the PLL limits for all gen2,
or if we should limit the changes to a more narrow set of platforms.

-- 
Ville Syrjälä
Intel OTC

Re: [PATCH 0/5] drm/i915: Gen2 PLL fixes

[Daniel Vetter]

On Tue, Dec 10, 2013 at 02:47:07PM +0200, Ville Syrjälä wrote:
> On Tue, Dec 10, 2013 at 01:33:01PM +0100, Bruno Prémont wrote:
> > Hi Ville,
> > 
> > On Tue, 10 December 2013 Ville Syrjälä wrote:
> > > On Tue, Dec 10, 2013 at 12:52:27PM +0100, Bruno Prémont wrote:
> > > > On Mon, 09 December 2013 Ville Syrjälä wrote:
> > > > > There appear to be some gen2 machines that don't really like the current PLL
> > > > > limits we have. We also have some accuracy problems with the PLL calculations.
> > > > > This series aims to eliminate those problems, and at least my 855 machine
> > > > > seems happier with these patches.
> > > > > 
> > > > > Ville Syrjälä (5):
> > > > >       drm/i915: Extract p2 divider correctly for gen2 LVDS dual channel
> > > > >       drm/i915: Change N divider minimum from 3 to 2 for gen2
> > > > >       drm/i915: Increase gen2 vco frequency limit to 1512 MHz
> > > > >       drm/i915: Fix 66 MHz LVDS SSC freq for gen2
> > > > >       drm/i915: Decrease gen2 vco frequency minimum to 908 MHz
> > > > > 
> > > > >  drivers/gpu/drm/i915/intel_bios.c    |  8 ++++----
> > > > >  drivers/gpu/drm/i915/intel_display.c | 34 +++++++++++++++++++---------------
> > > > >  2 files changed, 23 insertions(+), 19 deletions(-)
> > > > 
> > > > Here is my dmesg with the 5 patches applied (on top of 3.13-rc3 and
> > > > the PLL debug patch).
> > > > 
> > > > The WARN() are not hit anymore.
> > > > 
> > > <snip>
> > > > [   46.584578] [drm:intel_dump_pipe_config], DPLL = 0x0
> > > > [   46.584581] [drm:intel_dump_pipe_config], DPLL_MD = 0x0
> > > > [   46.584583] [drm:intel_dump_pipe_config], FP0 = 0x0
> > > > [   46.584586] [drm:intel_dump_pipe_config], FP1 = 0x0
> > > 
> > > OK, so I think the problem got fixed, but my debug patch wasn't
> > > all that good since it doesn't dump the values we computed unless
> > > the clock is off.
> > > 
> > > Can you still run this (as root) when the LVDS output is active:
> > > # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> > > 
> > > intel_reg_read is part of intel-gpu-tools.
> > 
> > Here are the results (when already running under X since previous
> > my mail):
> > 
> > # intel_reg_read 0x6014 0x6018 0x6040 0x6044 0x6048 0x604c
> > 0x6014 : 0x0
> > 0x6018 : 0x90020000
> > 0x6040 : 0x2140E
> > 0x6044 : 0x2140E
> > 0x6048 : 0x2140E
> > 0x604C : 0x2140E
> 
> Thanks. That's what the BIOS had, so it seems we're good. Now I suppose
> we just need to figure out if we dare change the PLL limits for all gen2,
> or if we should limit the changes to a more narrow set of platforms.

Ok, I've pulled them all into dinq, let's see what happens.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch