From: Manasi Navare <manasi.d.navare@intel.com>
To: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org
Cc: Manasi Navare <manasi.d.navare@intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: [PATCH v8 12/19] drm/i915/dsc: Add a power domain for VDSC on eDP/MIPI DSI
Date: Fri, 2 Nov 2018 14:31:31 -0700 [thread overview]
Message-ID: <20181102213138.301-13-manasi.d.navare@intel.com> (raw)
In-Reply-To: <20181102213138.301-1-manasi.d.navare@intel.com>
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI error (Ville)
* Rename as VDSC_PIPE_A (Imre)
* Fix a whitespace (Anusha)
* Fix Comments (Imre)
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Ville Syrjala <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.h | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index b0b23e1e9392..4e6b824ccc8c 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -226,6 +226,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
POWER_DOMAIN_TRANSCODER_EDP,
+ POWER_DOMAIN_TRANSCODER_EDP_VDSC,
POWER_DOMAIN_TRANSCODER_DSI_A,
POWER_DOMAIN_TRANSCODER_DSI_C,
POWER_DOMAIN_PORT_DDI_A_LANES,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6c453366cd24..acbe52adbf16 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -76,6 +76,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_C";
case POWER_DOMAIN_TRANSCODER_EDP:
return "TRANSCODER_EDP";
+ case POWER_DOMAIN_TRANSCODER_EDP_VDSC:
+ return "TRANSCODER_EDP_VDSC";
case POWER_DOMAIN_TRANSCODER_DSI_A:
return "TRANSCODER_DSI_A";
case POWER_DOMAIN_TRANSCODER_DSI_C:
@@ -2006,9 +2008,9 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
*/
#define ICL_PW_2_POWER_DOMAINS ( \
ICL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
- * - eDP/DSI VDSC
* - KVMR (HW control)
*/
#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
--
2.18.0
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next prev parent reply other threads:[~2018-11-02 21:31 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-02 21:31 [PATCH v8 00/19] DSC enabling remaining patches respin Manasi Navare
2018-11-02 21:31 ` [PATCH v8 01/19] drm/dsc: Define Display Stream Compression PPS infoframe Manasi Navare
2018-11-02 21:31 ` [PATCH v8 02/19] drm/dsc: Define VESA Display Stream Compression Capabilities Manasi Navare
2018-11-02 21:31 ` [PATCH v8 03/19] drm/dsc: Define Rate Control values that do not change over configurations Manasi Navare
2018-11-02 21:31 ` [PATCH v8 04/19] drm/dsc: Add helpers for DSC picture parameter set infoframes Manasi Navare
2018-11-06 1:38 ` Srivatsa, Anusha
2018-11-06 20:17 ` Manasi Navare
2018-11-02 21:31 ` [PATCH v8 05/19] drm/dsc: Define the DSC 1.1 and 1.2 Line Buffer depth constants Manasi Navare
2018-11-02 21:31 ` [PATCH v8 06/19] drm/i915/dp: Add DSC params and DSC config to intel_crtc_state Manasi Navare
2018-11-02 21:31 ` [PATCH v8 07/19] drm/i915/dp: Compute DSC pipe config in atomic check Manasi Navare
2018-11-03 2:09 ` Manasi Navare
2018-11-06 14:42 ` Ville Syrjälä
2018-11-06 20:37 ` Manasi Navare
2018-11-07 22:31 ` Manasi Navare
2018-11-06 22:41 ` Srivatsa, Anusha
2018-11-06 22:48 ` Manasi Navare
2018-11-02 21:31 ` [PATCH v8 08/19] drm/i915/dp: Do not enable PSR2 if DSC is enabled Manasi Navare
2018-11-02 21:31 ` [PATCH v8 09/19] drm/i915/dsc: Define & Compute VESA DSC params Manasi Navare
2018-11-02 21:31 ` [PATCH v8 10/19] drm/i915/dsc: Compute Rate Control parameters for DSC Manasi Navare
2018-11-06 14:33 ` Ville Syrjälä
2018-11-06 16:52 ` Manasi Navare
2018-11-06 17:00 ` Ville Syrjälä
2018-11-06 20:14 ` Manasi Navare
2018-11-06 20:30 ` Ville Syrjälä
2018-11-02 21:31 ` [PATCH v8 11/19] drm/i915/dp: Enable/Disable DSC in DP Sink Manasi Navare
2018-11-02 21:31 ` Manasi Navare [this message]
2018-11-02 21:31 ` [PATCH v8 13/19] drm/i915/dp: Configure i915 Picture parameter Set registers during DSC enabling Manasi Navare
2018-11-06 14:36 ` Ville Syrjälä
2018-11-06 16:50 ` Manasi Navare
2018-11-02 21:31 ` [PATCH v8 14/19] drm/i915/dp: Use the existing write_infoframe() for DSC PPS SDPs Manasi Navare
2018-11-02 21:31 ` [PATCH v8 15/19] drm/i915/dp: Populate DSC PPS SDP and send PPS infoframes Manasi Navare
2018-11-02 21:31 ` [PATCH v8 16/19] drm/i915/dp: Configure Display stream splitter registers during DSC enable Manasi Navare
2018-11-02 21:31 ` [PATCH v8 17/19] drm/i915/dp: Disable DSC in source by disabling DSS CTL bits Manasi Navare
2018-11-02 21:31 ` [PATCH v8 18/19] drm/i915/dsc: Enable and disable appropriate power wells for VDSC Manasi Navare
2018-11-02 21:31 ` [PATCH v8 19/19] drm/i915/dsc: Add Per connector debugfs node for DSC support/enable Manasi Navare
2018-11-03 2:40 ` Manasi Navare
2018-11-02 21:51 ` ✗ Fi.CI.CHECKPATCH: warning for DSC enabling remaining patches respin Patchwork
2018-11-02 21:57 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-11-02 22:30 ` ✗ Fi.CI.BAT: failure " Patchwork
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