[PATCH 00/10] DC3CO Support for TGL.

[PATCH 00/10] DC3CO Support for TGL.

[Anshuman Gupta]

Addressed few review comment provided by Imre on internal mailing
list.

This series requires Tigerlake platform enablement patches and
TGL PSR patches to be merged first, so few patches has commented 
out original code, which has commented out in order to build the
series. 

DC3CO DMC f/w entry/exit sequence:
HSD: https://hsdes.intel.com/appstore/article/#/1405906487
has attached a DC3CO HAS document, HAS document page no.8 has
described the DC3CO DMC entry and exit sequence.

I am able to validate that DC3CO counter increments on pipe2d emulator.
DC5 counter also increment post DC3CO.

DC3CO requirements:

*Audio codec idle and disabled.
*External displays disabled. WD transcoders and DP/HDMI transcoders must be disabled.
*Backlight cannot be driven from the display utility pin. It can be driven from the south display.
*This feature should be enabled only in Display Video playback on eDP.
*DC5 and DC6 not allowed when this feature is enabled.
*PSR2 deep sleep disabled (PSR2_CTL Idle Frames = 0000b)
*Disable DC3co before mode set, or other Aux, PLL, and DBUF programming,
 and do not re-enable until after that programming is completed.
*DC3co must not be enabled until after PSR2 is enabled.
*DC3co must be disabled before PSR2 is disabled.

B.Specs: https://gfxspecs.intel.com/Predator/Home/Index/49196


Anshuman Gupta (10):
  drm/i915/tgl:Added DC3CO required register and bits.
  i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.
  i915:Added DC3CO power well.
  drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6.
  drm/i915/tgl:Added helper function to prefer dc3co over dc5.
  drm/i915/tgl:Added VIDEO power domain.
  drm/i915/tgl:DC3CO PSR2 helper.
  drm/i915/tgl:switch between dc3co and dc5 based on display idleness.
  drm/i915/tgl:Added DC3CO counter in i915_dmc_info.
  drm/i915/tgl: Added new DC5/DC6 counter.

 drivers/gpu/drm/i915/i915_debugfs.c     |  23 ++-
 drivers/gpu/drm/i915/i915_drv.h         |   8 +
 drivers/gpu/drm/i915/i915_params.c      |   3 +-
 drivers/gpu/drm/i915/i915_reg.h         |  13 ++
 drivers/gpu/drm/i915/intel_display.c    |  45 ++++-
 drivers/gpu/drm/i915/intel_display.h    |   1 +
 drivers/gpu/drm/i915/intel_pm.c         |   2 +-
 drivers/gpu/drm/i915/intel_pm.h         |   1 +
 drivers/gpu/drm/i915/intel_psr.c        |  55 ++++++
 drivers/gpu/drm/i915/intel_psr.h        |   2 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 228 +++++++++++++++++++++++-
 drivers/gpu/drm/i915/intel_runtime_pm.h |   7 +
 12 files changed, 378 insertions(+), 10 deletions(-)

-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 01/10] drm/i915/tgl:Added DC3CO required register and bits.

[Anshuman Gupta]

This patch adds following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.

v2: Commit log typo fixing.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e97c47fca645..bf59ff40719f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4161,6 +4161,7 @@ enum {
 #define _VTOTAL_A	0x6000c
 #define _VBLANK_A	0x60010
 #define _VSYNC_A	0x60014
+#define _EXITLINE_A	0x60018
 #define _PIPEASRC	0x6001c
 #define _BCLRPAT_A	0x60020
 #define _VSYNCSHIFT_A	0x60028
@@ -4206,11 +4207,16 @@ enum {
 #define VTOTAL(trans)		_MMIO_TRANS2(trans, _VTOTAL_A)
 #define VBLANK(trans)		_MMIO_TRANS2(trans, _VBLANK_A)
 #define VSYNC(trans)		_MMIO_TRANS2(trans, _VSYNC_A)
+#define EXITLINE(trans)		_MMIO_TRANS2(trans, _EXITLINE_A)
 #define BCLRPAT(trans)		_MMIO_TRANS2(trans, _BCLRPAT_A)
 #define VSYNCSHIFT(trans)	_MMIO_TRANS2(trans, _VSYNCSHIFT_A)
 #define PIPESRC(trans)		_MMIO_TRANS2(trans, _PIPEASRC)
 #define PIPE_MULT(trans)	_MMIO_TRANS2(trans, _PIPE_MULT_A)
 
+#define  EXITLINE_ENABLE	(1 << 31)
+#define  EXITLINE_MASK		(0x1fff)
+#define  EXITLINE_SHIFT		0
+
 /* HSW+ eDP PSR registers */
 #define HSW_EDP_PSR_BASE	0x64800
 #define BDW_EDP_PSR_BASE	0x6f800
@@ -9873,6 +9879,8 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
+#define  DC_STATE_EN_DC3CO		(1 << 30)
+#define  DC_STATE_DC3CO_STATUS		(1 << 29)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 02/10] i915:Added DC3CO mask to allowed_dc_mask and gen9_dc_mask.

[Anshuman Gupta]

This patch enables dc3co state in enable_dc module param
and adds dc3co enable mask to allowed_dc_mask and gen9_dc_mask.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_params.c      |  3 ++-
 drivers/gpu/drm/i915/intel_runtime_pm.c | 13 +++++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index b5be0abbba35..eed19ce3c18a 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -46,7 +46,8 @@ i915_param_named(modeset, int, 0400,
 
 i915_param_named_unsafe(enable_dc, int, 0400,
 	"Enable power-saving display C-states. "
-	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6)");
+	"(-1=auto [default]; 0=disable; 1=up to DC5; 2=up to DC6; "
+	"3=up to DC6 with DC3CO)");
 
 i915_param_named_unsafe(enable_fbc, int, 0600,
 	"Enable frame buffer compression for power savings "
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b4abababdf6c..c860c1107c82 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -948,6 +948,10 @@ static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
 	u32 mask;
 
 	mask = DC_STATE_EN_UPTO_DC5;
+
+	if (INTEL_GEN(dev_priv) == 12)
+		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+					  | DC_STATE_EN_DC9;
 	if (INTEL_GEN(dev_priv) >= 11)
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
 	else if (IS_GEN9_LP(dev_priv))
@@ -3754,7 +3758,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 	int requested_dc;
 	int max_dc;
 
-	if (INTEL_GEN(dev_priv) >= 11) {
+	if (INTEL_GEN(dev_priv) == 12) {
+		max_dc = 3;
+		mask = DC_STATE_EN_DC9;
+	} else if (INTEL_GEN(dev_priv) >= 11) {
 		max_dc = 2;
 		/*
 		 * DC9 has a separate HW flow from the rest of the DC states,
@@ -3780,7 +3787,7 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		requested_dc = enable_dc;
 	} else if (enable_dc == -1) {
 		requested_dc = max_dc;
-	} else if (enable_dc > max_dc && enable_dc <= 2) {
+	} else if (enable_dc > max_dc && enable_dc <= 3) {
 		DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
 			      enable_dc, max_dc);
 		requested_dc = max_dc;
@@ -3789,6 +3796,8 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
 		requested_dc = max_dc;
 	}
 
+	if (requested_dc > 2)
+		mask |= DC_STATE_EN_DC3CO;
 	if (requested_dc > 1)
 		mask |= DC_STATE_EN_UPTO_DC6;
 	if (requested_dc > 0)
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 03/10] i915:Added DC3CO power well.

[Anshuman Gupta]

This patch adds a new "DC3CO Off" power well and adds
its power domain which are inherits from "DC Off" power well.
These power domains will disallow DC3CO when any external
display are connected and at time of modeset and aux
programming.
This patch also changes "DC Off" power well to "DC5 Off" power well.

v2: commit log improvement.
v3: Used intel_wait_for_register to wait for DC3CO exit. [Imre]
    Used gen9_set_dc_state() to allow/disallow DC3CO. [Imre]
    Moved transcoder psr2 exit line enablement from tgl_allow_dc3co()
    to a appropriate place haswell_crtc_enable(). [Imre]
    Changed the DC3CO power well enabled call back logic as
    recommended in review comments. [Imre]
Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: rodrigo.vivi@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 72 ++++++++++++++++++++++++-
 1 file changed, 71 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index c860c1107c82..b29761b4f55e 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1022,6 +1022,31 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 	dev_priv->csr.dc_state = val & mask;
 }
 
+static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
+{
+	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disallow_dc3co(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+
+	val = I915_READ(DC_STATE_EN);
+	val &= ~DC_STATE_DC3CO_STATUS;
+	I915_WRITE(DC_STATE_EN, val);
+	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+	/*
+	 * Delay of 200us DC3CO Exit time B.Spec 49196
+	 * It is not necessary that DC3CO exit will completed
+	 * every time, when we disallow DC3CO.
+	 * it might not get chance to enter DC3CO earlier.
+	 */
+	if (intel_wait_for_register(&dev_priv->uncore, DC_STATE_EN,
+				    DC_STATE_DC3CO_STATUS,
+				    DC_STATE_DC3CO_STATUS, 1))
+		DRM_DEBUG_KMS("Timed out waiting for dc3co exit\n");
+}
+
 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 {
 	assert_can_enable_dc9(dev_priv);
@@ -1238,6 +1263,33 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 		gen9_enable_dc5(dev_priv);
 }
 
+static void tgl_dc3co_power_well_enable(struct drm_i915_private *dev_priv,
+					struct i915_power_well *power_well)
+{
+	tgl_disallow_dc3co(dev_priv);
+}
+
+static void tgl_dc3co_power_well_disable(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
+{
+	if (WARN_ON(!dev_priv->psr.sink_psr2_support))
+		return;
+
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_allow_dc3co(dev_priv);
+}
+
+static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
+					 struct i915_power_well *power_well)
+{
+	/*
+	 * Checking alone DC_STATE_EN is not enough as DC5 power well also
+	 * allow/disallow DC3CO to make sure both are not enabled at same time
+	 */
+	return ((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+		(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
 					 struct i915_power_well *power_well)
 {
@@ -2740,6 +2792,11 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	ICL_PW_3_POWER_DOMAINS |			\
 	BIT_ULL(POWER_DOMAIN_TRANSCODER_EDP_VDSC) |		\
 	BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS (		\
+	ICL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_MODESET) |			\
+	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
+	BIT_ULL(POWER_DOMAIN_INIT))
 	/*
 	 * - KVMR (HW control)
 	 */
@@ -2852,6 +2909,13 @@ static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
 	.is_enabled = gen9_dc_off_power_well_enabled,
 };
 
+static const struct i915_power_well_ops tgl_dc3co_power_well_ops = {
+	.sync_hw = i9xx_power_well_sync_hw_noop,
+	.enable = tgl_dc3co_power_well_enable,
+	.disable = tgl_dc3co_power_well_disable,
+	.is_enabled = tgl_dc3co_power_well_enabled,
+};
+
 static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
 	.sync_hw = i9xx_power_well_sync_hw_noop,
 	.enable = bxt_dpio_cmn_power_well_enable,
@@ -3530,11 +3594,17 @@ static const struct i915_power_well_desc icl_power_wells[] = {
 		},
 	},
 	{
-		.name = "DC off",
+		.name = "DC5 off",
 		.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
 		.ops = &gen9_dc_off_power_well_ops,
 		.id = DISP_PW_ID_NONE,
 	},
+	{
+		.name = "DC3CO off",
+		.domains = TGL_DISPLAY_DC3CO_OFF_POWER_DOMAINS,
+		.ops = &tgl_dc3co_power_well_ops,
+		.id = DISP_PW_ID_NONE,
+	},
 	{
 		.name = "power well 2",
 		.domains = ICL_PW_2_POWER_DOMAINS,
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 04/10] drm/i915/tgl:Added mutual exclusive handling for DC3CO and DC5/6.

[Anshuman Gupta]

As per B.Spces DC5 and DC6 not allowed when DC3CO is enabled.
and DC3CO should be enabled only during VIDEO playback.
Which essentially means both can DC5 and DC3CO can not be
enabled at same time.
This patch makes DC3CO and DC5 mutual exclusive.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: rodrigo.vivi@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/intel_runtime_pm.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index b29761b4f55e..3f87e9bb9f94 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1233,6 +1233,10 @@ static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 
 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 
+	/* DC3CO and DC5/6 are mutually exclusive */
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_allow_dc3co(dev_priv);
+
 	dev_priv->display.get_cdclk(dev_priv, &cdclk_state);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
@@ -1257,6 +1261,10 @@ static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 	if (!dev_priv->csr.dmc_payload)
 		return;
 
+	/* DC3CO and DC5/6 are mutually exclusive */
+	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_DC3CO)
+		tgl_disallow_dc3co(dev_priv);
+
 	if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 		skl_enable_dc6(dev_priv);
 	else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 05/10] drm/i915/tgl:Added helper function to prefer dc3co over dc5.

[Anshuman Gupta]

This patch check if it is only edp display connected and
crtc has psr2 capability, then it sets the prefer_dc3co flag to
true. It also enable DC3CO PSR2 transcoder early exitline event
in haswell_crtc_enable() function.

TODO: B. Specs says dc3co should be allow only in video playback
case, currently driver doesn't differentiate between video playback
and a normal flip.
User space will be the best to judge if it is VPB case
otherwise we need to have that intelligence in driver.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_display.c    | 12 +++-
 drivers/gpu/drm/i915/intel_pm.c         |  2 +-
 drivers/gpu/drm/i915/intel_pm.h         |  1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 95 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.h |  3 +
 6 files changed, 112 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5801f5407589..acc1bc963b06 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -359,6 +359,7 @@ struct intel_csr {
 	u32 dc_state;
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
+	bool prefer_dc3co;
 };
 
 enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 90cd1f51eda6..1b9ab9bf4daa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6030,6 +6030,9 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 
 	if (WARN_ON(intel_crtc->active))
 		return;
+	/* Enable PSR2 transcoder exit line */
+	if (pipe_config->has_psr2 && dev_priv->csr.prefer_dc3co)
+		tgl_enable_psr2_transcoder_exitline(pipe_config);
 
 	intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
 
@@ -13119,7 +13122,14 @@ static int intel_atomic_check(struct drm_device *dev,
 		return ret;
 
 	intel_fbc_choose_crtc(dev_priv, intel_state);
-	return calc_watermark_data(intel_state);
+
+	ret = calc_watermark_data(intel_state);
+	if (ret)
+		return ret;
+
+	tgl_prefer_dc3co_over_dc5_check(dev_priv, state);
+
+	return 0;
 }
 
 static int intel_atomic_prepare_commit(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index decdd79c3805..8db0236ad99a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4594,7 +4594,7 @@ skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency,
 	return ret;
 }
 
-static uint_fixed_16_16_t
+uint_fixed_16_16_t
 intel_get_linetime_us(const struct intel_crtc_state *cstate)
 {
 	u32 pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 17339c99440c..4c18e20b50c1 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -76,6 +76,7 @@ u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, i915_reg_t reg);
 u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, i915_reg_t reg);
 
 u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1);
+uint_fixed_16_16_t intel_get_linetime_us(const struct intel_crtc_state *cstate);
 
 
 #endif /* __INTEL_PM_H__ */
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3f87e9bb9f94..056b02c1ab6b 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -42,6 +42,7 @@
 #include "intel_drv.h"
 #include "intel_hotplug.h"
 #include "intel_sideband.h"
+#include "intel_pm.h"
 
 /**
  * DOC: runtime pm
@@ -1022,6 +1023,100 @@ static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
 	dev_priv->csr.dc_state = val & mask;
 }
 
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate)
+{
+	u32 linetime_us, val, exit_scanlines;
+	u32 crtc_vdisplay = cstate->base.adjusted_mode.crtc_vdisplay;
+	struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
+
+	if (WARN_ON(cstate->cpu_transcoder != TRANSCODER_A))
+		return;
+
+	linetime_us = fixed16_to_u32_round_up(intel_get_linetime_us(cstate));
+	if (WARN_ON(!linetime_us))
+		return;
+	/*
+	 * DC3CO Exit time 200us B.Spec 49196
+	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
+	 * Exit line event need to program above calculated scan lines before
+	 * next VBLANK.
+	 */
+	exit_scanlines = DIV_ROUND_UP(200, linetime_us) + 1;
+	if (WARN_ON(exit_scanlines > crtc_vdisplay))
+		return;
+
+	exit_scanlines = crtc_vdisplay - exit_scanlines;
+	exit_scanlines <<= EXITLINE_SHIFT;
+	val = I915_READ(EXITLINE(cstate->cpu_transcoder));
+	val &= ~(EXITLINE_MASK | EXITLINE_ENABLE);
+	val |= exit_scanlines;
+	val |= EXITLINE_ENABLE;
+	I915_WRITE(EXITLINE(cstate->cpu_transcoder), val);
+}
+
+static bool tgl_is_only_edp_connected(struct intel_crtc_state  *crtc_state)
+{
+	struct drm_atomic_state *state = crtc_state->base.state;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+	struct drm_connector *connector, *edp_connector = NULL;
+	struct drm_connector_state *connector_state;
+	int i;
+
+	for_each_new_connector_in_state(state, connector, connector_state, i) {
+		if (connector_state->crtc != &crtc->base)
+			continue;
+
+		if (connector->status == connector_status_connected &&
+		    connector->connector_type != DRM_MODE_CONNECTOR_eDP)
+			return false;
+		else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP &&
+			 connector->status == connector_status_connected)
+			edp_connector = connector;
+	}
+
+	if (edp_connector)
+		return true;
+
+	return false;
+}
+
+/*
+ * tgl_prefer_dc3co_over_dc5_check check whether it is worth to choose
+ * DC3CO over DC5. Currently it just check crtc psr2 capebilty and only
+ * edp display should be connected.
+ * TODO: Prefer DC3CO over DC5 only in video playback.
+ */
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+				     struct drm_atomic_state *state)
+{
+	struct drm_crtc_state *crtc_state_drm;
+	struct drm_crtc *crtc;
+	int i;
+
+	dev_priv->csr.prefer_dc3co = false;
+
+	if (INTEL_GEN(dev_priv) < 12)
+		return;
+
+	for_each_new_crtc_in_state(state, crtc, crtc_state_drm, i) {
+		struct intel_crtc_state *crtc_state =
+			to_intel_crtc_state(crtc_state_drm);
+		if (!crtc_state->has_psr2 && crtc_state->base.active) {
+			dev_priv->csr.prefer_dc3co = false;
+			return;
+		} else if (crtc_state->has_psr2) {
+			if (tgl_is_only_edp_connected(crtc_state) &&
+			    crtc_state->base.active) {
+				dev_priv->csr.prefer_dc3co = true;
+				continue;
+			} else {
+				dev_priv->csr.prefer_dc3co = false;
+				return;
+			}
+		}
+	}
+}
+
 static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index b964ca7af9c8..d74dc0251402 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -44,6 +44,9 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_disable(struct drm_i915_private *dev_priv);
 void intel_runtime_pm_cleanup(struct drm_i915_private *dev_priv);
+void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
+				     struct drm_atomic_state *state);
+void tgl_enable_psr2_transcoder_exitline(struct intel_crtc_state  *cstate);
 
 const char *
 intel_display_power_domain_str(enum intel_display_power_domain domain);
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 06/10] drm/i915/tgl:Added VIDEO power domain.

[Anshuman Gupta]

Added POWER_DOMAIN_VIDEO power domain and added its helper stuff.
POWER_DOMAIN_VIDEO is a hook to "DC5 Off" power well.
which can disallow DC5/6 in order to allow dc3co.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         | 6 ++++++
 drivers/gpu/drm/i915/intel_display.h    | 1 +
 drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index acc1bc963b06..af4eb223afa2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -360,6 +360,12 @@ struct intel_csr {
 	u32 allowed_dc_mask;
 	intel_wakeref_t wakeref;
 	bool prefer_dc3co;
+	intel_wakeref_t dc5_wakeref;
+	/*
+	 * Mutex to protect dc5_wakeref which make maintain proper
+	 * power domain reference count of POWER_DOMAIN_VIDEO
+	 */
+	struct mutex dc5_mutex;
 };
 
 enum i915_cache_level {
diff --git a/drivers/gpu/drm/i915/intel_display.h b/drivers/gpu/drm/i915/intel_display.h
index 41f2aa966abc..2789c590ed59 100644
--- a/drivers/gpu/drm/i915/intel_display.h
+++ b/drivers/gpu/drm/i915/intel_display.h
@@ -251,6 +251,7 @@ enum intel_display_power_domain {
 	POWER_DOMAIN_PORT_OTHER,
 	POWER_DOMAIN_VGA,
 	POWER_DOMAIN_AUDIO,
+	POWER_DOMAIN_VIDEO,
 	POWER_DOMAIN_AUX_A,
 	POWER_DOMAIN_AUX_B,
 	POWER_DOMAIN_AUX_C,
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 056b02c1ab6b..a9714c8ef21a 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -472,6 +472,8 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
 		return "VGA";
 	case POWER_DOMAIN_AUDIO:
 		return "AUDIO";
+	case POWER_DOMAIN_VIDEO:
+		return "VIDEO";
 	case POWER_DOMAIN_AUX_A:
 		return "AUX_A";
 	case POWER_DOMAIN_AUX_B:
@@ -2905,6 +2907,7 @@ void intel_display_power_put(struct drm_i915_private *dev_priv,
 	 */
 #define ICL_DISPLAY_DC_OFF_POWER_DOMAINS (		\
 	ICL_PW_2_POWER_DOMAINS |			\
+	BIT_ULL(POWER_DOMAIN_VIDEO) |			\
 	BIT_ULL(POWER_DOMAIN_MODESET) |			\
 	BIT_ULL(POWER_DOMAIN_AUX_A) |			\
 	BIT_ULL(POWER_DOMAIN_INIT))
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 07/10] drm/i915/tgl:DC3CO PSR2 helper.

[Anshuman Gupta]

This patch adds dc3co helper function to enable/disable
psr2 deep sleep.
This patch make sure DC3CO disallowed before PSR2 exit,
it does that essentially by putting a reference to
POWER_DOMAIN_VIDEO before PSR2 exit.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: jose.souza@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/intel_psr.c | 55 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_psr.h |  2 ++
 2 files changed, 57 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 963663ba0edf..1c0cbfd50ad4 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -542,6 +542,60 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	I915_WRITE(EDP_PSR2_CTL, val);
 }
 
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	int idle_frames = 0;
+
+	idle_frames <<= EDP_PSR2_IDLE_FRAME_SHIFT;
+	/*
+	 * PSR registers are moved to each transcoder, it requires
+	 * https://patchwork.freedesktop.org/series/62416/ series
+	 * to be merged in order to use new PSR macro, as of now
+	 * using old PSR register macro to avoid compilation error.
+	 * similar logic on other places using the PSR2_CTL reg.
+	 */
+	//val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+	val = I915_READ(EDP_PSR2_CTL);
+	val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+	val |= idle_frames;
+	//I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+	I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv)
+{
+	u32 val;
+	int idle_frames;
+
+	/*
+	 * Let's use 6 as the minimum to cover all known cases including the
+	 * off-by-one issue that HW has in some cases.
+	 */
+	idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
+	idle_frames = max(idle_frames, dev_priv->psr.sink_sync_latency + 1);
+	idle_frames <<=  EDP_PSR2_IDLE_FRAME_SHIFT;
+	//val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
+	val = I915_READ(EDP_PSR2_CTL);
+	val &= ~EDP_PSR2_IDLE_FRAME_MASK;
+	val |= idle_frames;
+	//I915_WRITE(EDP_PSR2_CTL(dev_priv->psr.transcoder), val);
+	I915_WRITE(EDP_PSR2_CTL, val);
+}
+
+void tgl_disallow_dc3co_on_psr2_exit(struct drm_i915_private *dev_priv)
+{
+	intel_wakeref_t wakeref __maybe_unused;
+
+	/* Before PSR2 exit disallow dc3co*/
+	mutex_lock(&dev_priv->csr.dc5_mutex);
+	wakeref	= fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+	if (wakeref)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO,
+					dev_priv->csr.dc5_wakeref);
+	mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
 static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
@@ -798,6 +852,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
 	}
 
 	if (dev_priv->psr.psr2_enabled) {
+		tgl_disallow_dc3co_on_psr2_exit(dev_priv);
 		val = I915_READ(EDP_PSR2_CTL);
 		WARN_ON(!(val & EDP_PSR2_ENABLE));
 		I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE);
diff --git a/drivers/gpu/drm/i915/intel_psr.h b/drivers/gpu/drm/i915/intel_psr.h
index dc818826f36d..6fb4c385489c 100644
--- a/drivers/gpu/drm/i915/intel_psr.h
+++ b/drivers/gpu/drm/i915/intel_psr.h
@@ -36,5 +36,7 @@ void intel_psr_short_pulse(struct intel_dp *intel_dp);
 int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state,
 			    u32 *out_value);
 bool intel_psr_enabled(struct intel_dp *intel_dp);
+void tgl_psr2_deep_sleep_disable(struct drm_i915_private *dev_priv);
+void tgl_psr2_deep_sleep_enable(struct drm_i915_private *dev_priv);
 
 #endif /* __INTEL_PSR_H__ */
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 08/10] drm/i915/tgl:switch between dc3co and dc5 based on display idleness.

[Anshuman Gupta]

DC5 and DC6 not allowed when DC3CO feature is enabled.

DC5 and DC6 saves more power, but cannot be entered during video
playback because there are not enough idle frames in a row to meet.
Most PSR2 panel deep sleep entry requirements typically 4 frames.

This patch switch to DC3CO when there is an update to display and it
switch to DC5 when display is idle.
It is safer to allow DC5 after 6 idle frame, as PSR2 required minimum
6 idle frame.

v2: calculated s/w state to switch over dc3co when there is an
    update. [Imre]
    used cancel_delayed_work_sync() in order to avoid any race
    with already scheduled delayed work. [Imre]

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h         |  1 +
 drivers/gpu/drm/i915/intel_display.c    | 33 ++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 37 +++++++++++++++++++++++++
 drivers/gpu/drm/i915/intel_runtime_pm.h |  4 +++
 4 files changed, 75 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index af4eb223afa2..4829e3f9afaf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -358,6 +358,7 @@ struct intel_csr {
 	u32 mmiodata[8];
 	u32 dc_state;
 	u32 allowed_dc_mask;
+	struct delayed_work idle_work;
 	intel_wakeref_t wakeref;
 	bool prefer_dc3co;
 	intel_wakeref_t dc5_wakeref;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1b9ab9bf4daa..abb9407eb03a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13595,6 +13595,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
 	struct drm_i915_private *dev_priv = to_i915(dev);
 	int ret = 0;
+	u32 delay;
 
 	drm_atomic_state_get(state);
 	i915_sw_fence_init(&intel_state->commit_ready,
@@ -13675,6 +13676,36 @@ static int intel_atomic_commit(struct drm_device *dev,
 			flush_workqueue(dev_priv->modeset_wq);
 		intel_atomic_commit_tail(state);
 	}
+	/* PSR2 is enabled and only edp is connected */
+	if (dev_priv->csr.prefer_dc3co && dev_priv->psr.psr2_enabled &&
+	    dev_priv->psr.enabled) {
+		struct intel_crtc *crtc;
+		struct intel_crtc_state *cstate;
+
+		/*
+		 * As every flip go through intel_atomic_commit, so tracking a
+		 * atomic commit will be a hint for idle frames.
+		 * Delayed work for 6 idle frames will be enough to allow dc6
+		 * over dc3co for deepest power savings.
+		 * At every atomic commit cancel the delayed work first,
+		 * when delayed scheduled that means display has been idle
+		 * for the 6 idle frame.
+		 */
+		cancel_delayed_work_sync(&dev_priv->csr.idle_work);
+
+		if (!dev_priv->csr.dc5_wakeref) {
+			dev_priv->csr.dc5_wakeref =
+			intel_display_power_get(dev_priv, POWER_DOMAIN_VIDEO);
+			tgl_psr2_deep_sleep_disable(dev_priv);
+		}
+		crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+		cstate = to_intel_crtc_state(crtc->base.state);
+
+		delay = DC5_REQ_IDLE_FRAMES * intel_get_frame_time_us(cstate);
+		schedule_delayed_work(&dev_priv->csr.idle_work,
+				      usecs_to_jiffies(delay));
+	}
+
 
 	return 0;
 }
@@ -15542,6 +15573,7 @@ int intel_modeset_init(struct drm_device *dev)
 	init_llist_head(&dev_priv->atomic_helper.free_list);
 	INIT_WORK(&dev_priv->atomic_helper.free_work,
 		  intel_atomic_helper_free_state_worker);
+	INIT_DELAYED_WORK(&dev_priv->csr.idle_work, intel_dc5_idle_thread);
 
 	intel_init_quirks(dev_priv);
 
@@ -16444,6 +16476,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
 	flush_workqueue(dev_priv->modeset_wq);
 
 	flush_work(&dev_priv->atomic_helper.free_work);
+	flush_delayed_work(&dev_priv->csr.idle_work);
 	WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
 
 	/*
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a9714c8ef21a..93f70cac3c38 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -43,6 +43,7 @@
 #include "intel_hotplug.h"
 #include "intel_sideband.h"
 #include "intel_pm.h"
+#include "intel_psr.h"
 
 /**
  * DOC: runtime pm
@@ -1119,6 +1120,20 @@ void tgl_prefer_dc3co_over_dc5_check(struct drm_i915_private *dev_priv,
 	}
 }
 
+void intel_dc5_idle_thread(struct work_struct *work)
+{
+	intel_wakeref_t wakeref __maybe_unused;
+	struct drm_i915_private *dev_priv =
+		container_of(work, typeof(*dev_priv), csr.idle_work.work);
+
+	mutex_lock(&dev_priv->csr.dc5_mutex);
+	wakeref	= fetch_and_zero(&dev_priv->csr.dc5_wakeref);
+	if (wakeref)
+		intel_display_power_put(dev_priv, POWER_DOMAIN_VIDEO, wakeref);
+	tgl_psr2_deep_sleep_enable(dev_priv);
+	mutex_unlock(&dev_priv->csr.dc5_mutex);
+}
+
 static void tgl_allow_dc3co(struct drm_i915_private *dev_priv)
 {
 	gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
@@ -1395,6 +1410,27 @@ static bool tgl_dc3co_power_well_enabled(struct drm_i915_private *dev_priv,
 		(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
 }
 
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate)
+{
+	u32 pixel_rate, crtc_htotal, crtc_vtotal;
+	uint_fixed_16_16_t frametime_us;
+
+	if (!cstate || !cstate->base.active)
+		return 0;
+
+	pixel_rate = cstate->pixel_rate;
+
+	if (WARN_ON(pixel_rate == 0))
+		return 0;
+
+	crtc_htotal = cstate->base.adjusted_mode.crtc_htotal;
+	crtc_vtotal = cstate->base.adjusted_mode.crtc_vtotal;
+	frametime_us = div_fixed16(crtc_htotal * crtc_vtotal * 1000,
+				   pixel_rate);
+
+	return fixed16_to_u32_round_up(frametime_us);
+}
+
 static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
 					 struct i915_power_well *power_well)
 {
@@ -4041,6 +4077,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
 	BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
 
 	mutex_init(&power_domains->lock);
+	mutex_init(&dev_priv->csr.dc5_mutex);
 
 	INIT_DELAYED_WORK(&power_domains->async_put_work,
 			  intel_display_power_put_async_work);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.h b/drivers/gpu/drm/i915/intel_runtime_pm.h
index d74dc0251402..fcfdbed95daf 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.h
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.h
@@ -9,6 +9,8 @@
 #include <linux/stackdepot.h>
 #include <linux/types.h>
 
+#define DC5_REQ_IDLE_FRAMES	6
+
 struct drm_i915_private;
 
 typedef depot_stack_handle_t intel_wakeref_t;
@@ -21,6 +23,8 @@ enum i915_drm_suspend_mode {
 
 void skl_enable_dc6(struct drm_i915_private *dev_priv);
 void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
+void intel_dc5_idle_thread(struct work_struct *work);
+u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate);
 void bxt_enable_dc9(struct drm_i915_private *dev_priv);
 void bxt_disable_dc9(struct drm_i915_private *dev_priv);
 void gen9_enable_dc5(struct drm_i915_private *dev_priv);
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 09/10] drm/i915/tgl:Added DC3CO counter in i915_dmc_info.

[Anshuman Gupta]

This patch exposes DC3CO counter in i915_dmc_info debugfs.
Which will be useful for DC3CO validation.
DMC firmware is using DMC_DEBUG3 register as DC3CO counter.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 15 ++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h     |  3 +++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 072464a18050..76e425cc19c2 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2719,9 +2719,22 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
 		   CSR_VERSION_MINOR(csr->version));
 
-	if (WARN_ON(INTEL_GEN(dev_priv) > 11))
+	if (WARN_ON(INTEL_GEN(dev_priv) > 12))
 		goto out;
 
+	/*
+	 * B.Spes specify that DMC_DEBUG3 is general debug register
+	 * DMC folks uses this register for DC3CO counter for TGL
+	 */
+	/*
+	 * It requires TGL plaform enabling pacthes to be merged in order to use
+	 * IS_TIGERLAKE() macro. Using INTEL_GEN instead of IS_TIGERLAKE in
+	 * order to avoid compilation errors.
+	 */
+	//if (IS_TIGERLAKE(dev_priv))
+	if (INTEL_GEN(dev_priv) == 12)
+		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
+
 	seq_printf(m, "DC3 -> DC5 count: %d\n",
 		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
 						    SKL_CSR_DC3_DC5_COUNT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf59ff40719f..3febd29df5d3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7221,6 +7221,9 @@ enum {
 #define SKL_CSR_DC5_DC6_COUNT	_MMIO(0x8002C)
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 
+/* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG3		_MMIO(0x101090) /*DC3CO debug counter*/
+
 /* interrupts */
 #define DE_MASTER_IRQ_CONTROL   (1 << 31)
 #define DE_SPRITEB_FLIP_DONE    (1 << 29)
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 10/10] drm/i915/tgl: Added new DC5/DC6 counter.

[Anshuman Gupta]

TGL onwards we have new DC5 and DC6 counter
DMC_DEBUG1 and DMC_DEBUG2 these counter will retain
there values upon DMC reset.
Currently using IS_GEN() macro instead of IS_TIGERLAKE()
to avoid compilation error and flot the pacthes.
Will be using IS_TIGERLAKE() once TGL platform
enabling pacthes merged to drm-tip.

Cc: jani.nikula@intel.com
Cc: imre.deak@intel.com
Cc: animesh.manna@intel.com
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 8 +++++---
 drivers/gpu/drm/i915/i915_reg.h     | 2 ++
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 76e425cc19c2..3c0aa0cb74fa 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2736,11 +2736,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		seq_printf(m, "DC3CO count: %d\n", I915_READ(DMC_DEBUG3));
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n",
-		   I915_READ(IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
-						    SKL_CSR_DC3_DC5_COUNT));
+		   I915_READ((INTEL_GEN(dev_priv) == 12) ? DMC_DEBUG1 :
+			     (IS_BROXTON(dev_priv) ? BXT_CSR_DC3_DC5_COUNT :
+						    SKL_CSR_DC3_DC5_COUNT)));
 	if (!IS_GEN9_LP(dev_priv))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   I915_READ(SKL_CSR_DC5_DC6_COUNT));
+			   I915_READ((INTEL_GEN(dev_priv) == 12) ? DMC_DEBUG2 :
+				     SKL_CSR_DC5_DC6_COUNT));
 
 out:
 	seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3febd29df5d3..cdeff113d712 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7222,6 +7222,8 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 
 /* DMC DEBUG COUNTERS for TGL*/
+#define DMC_DEBUG1		_MMIO(0x101084)
+#define DMC_DEBUG2		_MMIO(0x101088)
 #define DMC_DEBUG3		_MMIO(0x101090) /*DC3CO debug counter*/
 
 /* interrupts */
-- 
2.21.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx