[PATCH v3 00/23] Tiger Lake batch 3

[Lucas De Marchi <lucas.demarchi@intel.com>]

v3 of https://patchwork.freedesktop.org/series/65290/

Note that some patches were handled outside of the "batch series for
Tiger Lake". Compared to v2 several patches were merged. Anothe great
portion received comments and reviews. Unfortunately some people
commented/reviewed the wrong revision of the patch, making it difficult
to follow up on adding the R-b. Also, patchwork got pretty confused with
the patches sent by José to cover the review feedback. So, if I didn't
handle your comment, I will double check for the next version. If you
reviewed a patch and it does not show here, then please add your r-b
again.

2 patches to add perf support are dropped: one of them was missing
a userspace component and the other one depends on the first.

Patches that still need to handle the comments from previous versions
are prefixed with FIXME and are not meant to be merged.

For the patches that already have a r-b tag: I was planning to merge
them and remove from this series, but in the end I felt more confortable
doing it in steps: add them here again and merge them later.

Lucas De Marchi

Dhinakaran Pandiyan (5):
  drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 render
    compression
  drm/i915/tgl: Gen-12 render decompression
  drm/framebuffer/tgl: Format modifier for Intel Gen-12 media
    compression
  drm/i915/tgl: Gen-12 media compression

José Roberto de Souza (12):
  drm/i915/psr: Only handle interruptions of the transcoder in use
  drm/i915/bdw+: Enable PSR in any eDP port
  drm/i915: Guard and warn if more than one eDP panel is present
  drm/i915: Do not read PSR2 register in transcoders without PSR2
  drm/i915/tgl: PSR link standby is not supported anymore
  drm/i915/tgl: Access the right register when handling PSR
    interruptions
  drm/i915/tgl: Add maximum resolution supported by PSR2 HW
  drm/i915: Add for_each_new_intel_connector_in_state()
  drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
  drm/i915: Disable pipes in reverse order
  FIXME: drm/i915/tgl: Select master transcoder in DP MST
  drm/i915/tgl: Implement TGL DisplayPort training sequence

Lucas De Marchi (1):
  drm/i915/tgl: move DP_TP_* to transcoder

Michel Thierry (5):
  drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
  drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
  drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12
    onwards
  FIXME: drm/i915/tgl: Register state context definition for Gen12
  drm/i915/tgl/perf: use the same oa ctx_id format as icl

 drivers/gpu/drm/i915/display/intel_crt.c      |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      | 199 +++++++++++++++--
 drivers/gpu/drm/i915/display/intel_display.c  | 105 ++++++++-
 drivers/gpu/drm/i915/display/intel_display.h  |  20 ++
 .../drm/i915/display/intel_display_types.h    |   4 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  74 ++++++-
 drivers/gpu/drm/i915/display/intel_dp.h       |   9 +
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 179 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dp_mst.h   |   2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 200 +++++++++---------
 drivers/gpu/drm/i915/display/intel_psr.h      |   1 +
 drivers/gpu/drm/i915/display/intel_sprite.c   |  96 ++++++++-
 drivers/gpu/drm/i915/gt/intel_lrc.c           | 156 ++++++++++----
 drivers/gpu/drm/i915/gt/intel_lrc.h           |   2 +
 drivers/gpu/drm/i915/gt/intel_lrc_reg.h       |  30 ++-
 drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h    |   3 +
 drivers/gpu/drm/i915/i915_gem_gtt.c           |  10 +-
 drivers/gpu/drm/i915/i915_irq.c               |  52 ++++-
 drivers/gpu/drm/i915/i915_perf.c              |   3 +-
 drivers/gpu/drm/i915/i915_reg.h               |  35 ++-
 drivers/gpu/drm/i915/intel_pm.c               |  18 +-
 include/uapi/drm/drm_fourcc.h                 |  20 ++
 22 files changed, 1011 insertions(+), 209 deletions(-)

-- 
2.23.0

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