public inbox for intel-gfx@lists.freedesktop.org
 help / color / mirror / Atom feed
From: Patchwork <patchwork@emeril.freedesktop.org>
To: "Souza, Jose" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev5)
Date: Fri, 23 Aug 2019 13:24:51 -0000	[thread overview]
Message-ID: <20190823132451.27175.74457@emeril.freedesktop.org> (raw)
In-Reply-To: <20190823082055.5992-1-lucas.demarchi@intel.com>

== Series Details ==

Series: Tiger Lake batch 3 (rev5)
URL   : https://patchwork.freedesktop.org/series/65290/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
385d0cea263f drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap
-:28: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#28: FILE: drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h:87:
+#define   GEN12_GUC_TLB_INV_CR_INVALIDATE	(1<<0)
                                          	  ^

total: 0 errors, 0 warnings, 1 checks, 25 lines checked
2f4032c673ce drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating
01ce36bb2bfa drm/i915/psr: Only handle interruptions of the transcoder in use
-:230: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'trans' - possible side-effects?
#230: FILE: drivers/gpu/drm/i915/i915_reg.h:4228:
+#define   _EDP_PSR_TRANS_SHIFT(trans)		((trans) == TRANSCODER_EDP ? \
+						 0 : ((trans) + 1) * 8)

total: 0 errors, 0 warnings, 1 checks, 204 lines checked
a2bf1ac1f4f0 drm/i915/bdw+: Enable PSR in any eDP port
2c444eefb88f drm/i915: Guard and warn if more than one eDP panel is present
04f3d0338d3f drm/i915: Do not read PSR2 register in transcoders without PSR2
c7a7a115467e drm/i915/tgl: PSR link standby is not supported anymore
6c29d1d87d2d drm/i915/tgl: Access the right register when handling PSR interruptions
4962b6d88797 drm/i915/tgl: Add maximum resolution supported by PSR2 HW
04c9257c9791 drm/i915: Add for_each_new_intel_connector_in_state()
-:24: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:24: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#24: FILE: drivers/gpu/drm/i915/display/intel_display.h:414:
+#define for_each_new_intel_connector_in_state(__state, connector, new_connector_state, __i) \
+	for ((__i) = 0; \
+	     (__i) < (__state)->base.num_connector; \
+	     (__i)++) \
+		for_each_if ((__state)->base.connectors[__i].ptr && \
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

-:28: WARNING:SPACING: space prohibited between function name and open parenthesis '('
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:418:
+		for_each_if ((__state)->base.connectors[__i].ptr && \

-:29: WARNING:LONG_LINE: line over 100 characters
#29: FILE: drivers/gpu/drm/i915/display/intel_display.h:419:
+			     ((connector) = to_intel_connector((__state)->base.connectors[__i].ptr), \

-:30: WARNING:LONG_LINE: line over 100 characters
#30: FILE: drivers/gpu/drm/i915/display/intel_display.h:420:
+			     (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))

total: 1 errors, 3 warnings, 2 checks, 14 lines checked
8ff0f4dfd8d7 drm: Add for_each_oldnew_intel_crtc_in_state_reverse()
-:28: WARNING:LONG_LINE: line over 100 characters
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__state' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'crtc' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

-:28: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__i' - possible side-effects?
#28: FILE: drivers/gpu/drm/i915/display/intel_display.h:422:
+#define for_each_oldnew_intel_crtc_in_state_reverse(__state, crtc, old_crtc_state, new_crtc_state, __i) \
+	for ((__i) = (__state)->base.dev->mode_config.num_crtc - 1; \
+	     (__i) >= 0  && \
+	     ((crtc) = to_intel_crtc((__state)->base.crtcs[__i].ptr), \
+	      (old_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].old_state), \
+	      (new_crtc_state) = to_intel_crtc_state((__state)->base.crtcs[__i].new_state), 1); \
+	     (__i)--) \
+		for_each_if(crtc)

total: 0 errors, 1 warnings, 3 checks, 15 lines checked
ac6110ed3d55 drm/i915: Disable pipes in reverse order
4e72fd9a7b1a FIXME: drm/i915/tgl: Select master transcoder in DP MST
-:26: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#26: 
    Add FIXME. From Jani: double check PIPE_CONF_CHECK_I(mst_master_trans) - it's

total: 0 errors, 1 warnings, 0 checks, 325 lines checked
2732c013a2e5 drm/i915/tgl: move DP_TP_* to transcoder
82a4ff669aa6 drm/i915/tgl: Implement TGL DisplayPort training sequence
e44fa908a435 drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards
5a65c5bddfa6 FIXME: drm/i915/tgl: Register state context definition for Gen12
53d10786309a drm/i915/tgl/perf: use the same oa ctx_id format as icl
6fd7e43b7477 drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support
32f171b41ca7 drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression
fca4dac975ee drm/i915/tgl: Gen-12 render decompression
fc2223c91ae2 drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression
62b7125d235e drm/i915/tgl: Gen-12 media compression
-:74: WARNING:MISSING_BREAK: Possible switch case/default not preceded by break or fallthrough comment
#74: FILE: drivers/gpu/drm/i915/display/intel_display.c:2523:
+	case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:

total: 0 errors, 1 warnings, 0 checks, 134 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2019-08-23 13:24 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-23  8:20 [PATCH v3 00/23] Tiger Lake batch 3 Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 01/23] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-09-13  7:06   ` Chris Wilson
2019-08-23  8:20 ` [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-26 17:28   ` Imre Deak
2019-08-27 16:50     ` Lucas De Marchi
2019-08-28 16:29       ` Imre Deak
2019-08-28 22:16         ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-26 13:41   ` Imre Deak
2019-08-26 17:43     ` Runyan, Arthur J
2019-08-27 16:36       ` Lucas De Marchi
2019-08-27 17:55         ` Souza, Jose
2019-08-23  8:20 ` [PATCH v3 05/23] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-26  6:41   ` Anshuman Gupta
2019-08-23  8:20 ` [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-26 14:21   ` Imre Deak
2019-08-26 16:32     ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 07/23] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-26  9:53   ` Anshuman Gupta
2019-08-26 16:56     ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-24 11:06   ` Anshuman Gupta
2019-08-26 17:10     ` Lucas De Marchi
2019-08-26 17:17       ` Souza, Jose
2019-08-26 17:29         ` Lucas De Marchi
2019-08-26 17:33       ` Gupta, Anshuman
2019-08-23  8:20 ` [PATCH v3 10/23] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 11/23] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 12/23] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-23 13:02   ` Ville Syrjälä
2019-08-23  8:20 ` [PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-23 12:25   ` Ville Syrjälä
2019-08-23 12:39     ` Ville Syrjälä
2019-08-23  8:20 ` [PATCH v3 15/23] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 16/23] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 17/23] FIXME: drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-23  8:30   ` Lionel Landwerlin
2019-08-23 18:16   ` Umesh Nerlige Ramappa
2019-08-23  8:20 ` [PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-28 23:04   ` Matt Roper
2019-08-28 23:59     ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 20/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-29  0:33   ` Matt Roper
2019-09-13  0:31   ` Sripada, Radhakrishna
2019-08-23  8:20 ` [PATCH v3 22/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 23/23] drm/i915/tgl: " Lucas De Marchi
2019-08-23 13:24 ` Patchwork [this message]
2019-08-23 13:28 ` ✗ Fi.CI.SPARSE: warning for Tiger Lake batch 3 (rev5) Patchwork
2019-08-23 13:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-24 11:50 ` ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20190823132451.27175.74457@emeril.freedesktop.org \
    --to=patchwork@emeril.freedesktop.org \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=jose.souza@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox