From: "Gupta, Anshuman" <anshuman.gupta@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW
Date: Mon, 26 Aug 2019 23:03:51 +0530 [thread overview]
Message-ID: <6bfd609d-cbfa-48c1-adc0-49f3b97d0c02@intel.com> (raw)
In-Reply-To: <20190826171050.ay7sa3yvc5cdgznb@ldmartin-desk1>
Validated with respect to B.Specs:49199 and 50422.
On 8/26/2019 10:40 PM, Lucas De Marchi wrote:
> On Sat, Aug 24, 2019 at 04:36:52PM +0530, Anshuman Gupta wrote:
>> On 2019-08-23 at 01:20:41 -0700, Lucas De Marchi wrote:
>>> From: José Roberto de Souza <jose.souza@intel.com>
>>>
>>> TGL PSR2 HW supports a bigger resolution, so lets add it
>>>
>>> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
>>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_psr.c | 5 ++++-
>>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
>>> b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index c33aa16ed038..5d24f1c47a2b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -570,7 +570,10 @@ static bool intel_psr2_config_valid(struct
>>> intel_dp *intel_dp,
>>> return false;
>>> }
>>>
>>> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>> + if (INTEL_GEN(dev_priv) >= 12) {
>> As per B.Specs:28692 on few Gen11 platform, PSR2 supports max
>> resolution of 5120X3200.
>> Do we need to handle those Gen11 platform here?
>
> the only thing I see there for gen11 is:
>
> "PSR2 maximum pipe horizontal active size 4096 pixels."
>
> Lucas De Marchi
>
>>> + psr_max_h = 5120;
>>> + psr_max_v = 3200;
>>> + } else if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) {
>>> psr_max_h = 4096;
>>> psr_max_v = 2304;
>>> } else if (IS_GEN(dev_priv, 9)) {
>>> --
>>> 2.23.0
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-08-26 17:33 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 8:20 [PATCH v3 00/23] Tiger Lake batch 3 Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 01/23] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-09-13 7:06 ` Chris Wilson
2019-08-23 8:20 ` [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-26 17:28 ` Imre Deak
2019-08-27 16:50 ` Lucas De Marchi
2019-08-28 16:29 ` Imre Deak
2019-08-28 22:16 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-26 13:41 ` Imre Deak
2019-08-26 17:43 ` Runyan, Arthur J
2019-08-27 16:36 ` Lucas De Marchi
2019-08-27 17:55 ` Souza, Jose
2019-08-23 8:20 ` [PATCH v3 05/23] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-26 6:41 ` Anshuman Gupta
2019-08-23 8:20 ` [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-26 14:21 ` Imre Deak
2019-08-26 16:32 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 07/23] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-26 9:53 ` Anshuman Gupta
2019-08-26 16:56 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-24 11:06 ` Anshuman Gupta
2019-08-26 17:10 ` Lucas De Marchi
2019-08-26 17:17 ` Souza, Jose
2019-08-26 17:29 ` Lucas De Marchi
2019-08-26 17:33 ` Gupta, Anshuman [this message]
2019-08-23 8:20 ` [PATCH v3 10/23] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 11/23] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 12/23] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-23 13:02 ` Ville Syrjälä
2019-08-23 8:20 ` [PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-23 12:25 ` Ville Syrjälä
2019-08-23 12:39 ` Ville Syrjälä
2019-08-23 8:20 ` [PATCH v3 15/23] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 16/23] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 17/23] FIXME: drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-23 8:30 ` Lionel Landwerlin
2019-08-23 18:16 ` Umesh Nerlige Ramappa
2019-08-23 8:20 ` [PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-28 23:04 ` Matt Roper
2019-08-28 23:59 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 20/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-29 0:33 ` Matt Roper
2019-09-13 0:31 ` Sripada, Radhakrishna
2019-08-23 8:20 ` [PATCH v3 22/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 23/23] drm/i915/tgl: " Lucas De Marchi
2019-08-23 13:24 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev5) Patchwork
2019-08-23 13:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-23 13:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-24 11:50 ` ✓ Fi.CI.IGT: " Patchwork
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