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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Michel Thierry <michel.thierry@intel.com>
Subject: [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl
Date: Fri, 23 Aug 2019 01:20:50 -0700	[thread overview]
Message-ID: <20190823082055.5992-19-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20190823082055.5992-1-lucas.demarchi@intel.com>

From: Michel Thierry <michel.thierry@intel.com>

Compared to Icelake, Tigerlake's MAX_CONTEXT_HW_ID is smaller by one, but
since we just use the upper 32 bits of the lrc_desc, it's guaranteed OA
will use the correct one.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_perf.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index e42b86827d6b..2c9f46e12622 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1299,7 +1299,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
 		}
 		break;
 
-	case 11: {
+	case 11:
+	case 12: {
 		stream->specific_ctx_id_mask =
 			((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
 			((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
-- 
2.23.0

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  parent reply	other threads:[~2019-08-23  8:54 UTC|newest]

Thread overview: 56+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-23  8:20 [PATCH v3 00/23] Tiger Lake batch 3 Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 01/23] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-09-13  7:06   ` Chris Wilson
2019-08-23  8:20 ` [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-26 17:28   ` Imre Deak
2019-08-27 16:50     ` Lucas De Marchi
2019-08-28 16:29       ` Imre Deak
2019-08-28 22:16         ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-26 13:41   ` Imre Deak
2019-08-26 17:43     ` Runyan, Arthur J
2019-08-27 16:36       ` Lucas De Marchi
2019-08-27 17:55         ` Souza, Jose
2019-08-23  8:20 ` [PATCH v3 05/23] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-26  6:41   ` Anshuman Gupta
2019-08-23  8:20 ` [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-26 14:21   ` Imre Deak
2019-08-26 16:32     ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 07/23] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-26  9:53   ` Anshuman Gupta
2019-08-26 16:56     ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-24 11:06   ` Anshuman Gupta
2019-08-26 17:10     ` Lucas De Marchi
2019-08-26 17:17       ` Souza, Jose
2019-08-26 17:29         ` Lucas De Marchi
2019-08-26 17:33       ` Gupta, Anshuman
2019-08-23  8:20 ` [PATCH v3 10/23] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 11/23] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 12/23] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-23 13:02   ` Ville Syrjälä
2019-08-23  8:20 ` [PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-23 12:25   ` Ville Syrjälä
2019-08-23 12:39     ` Ville Syrjälä
2019-08-23  8:20 ` [PATCH v3 15/23] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 16/23] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 17/23] FIXME: drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-23  8:20 ` Lucas De Marchi [this message]
2019-08-23  8:30   ` [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lionel Landwerlin
2019-08-23 18:16   ` Umesh Nerlige Ramappa
2019-08-23  8:20 ` [PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-28 23:04   ` Matt Roper
2019-08-28 23:59     ` Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 20/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-29  0:33   ` Matt Roper
2019-09-13  0:31   ` Sripada, Radhakrishna
2019-08-23  8:20 ` [PATCH v3 22/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-23  8:20 ` [PATCH v3 23/23] drm/i915/tgl: " Lucas De Marchi
2019-08-23 13:24 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev5) Patchwork
2019-08-23 13:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-23 13:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-24 11:50 ` ✓ Fi.CI.IGT: " Patchwork

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