From: Imre Deak <imre.deak@intel.com>
To: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2
Date: Mon, 26 Aug 2019 17:21:56 +0300 [thread overview]
Message-ID: <20190826142156.GB27192@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20190823082055.5992-7-lucas.demarchi@intel.com>
On Fri, Aug 23, 2019 at 01:20:38AM -0700, Lucas De Marchi wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> This fix unclaimed access warnings:
>
> [ 245.525788] ------------[ cut here ]------------
> [ 245.525884] Unclaimed read from register 0x62900
> [ 245.526154] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
> [ 245.526160] Modules linked in: i915 x86_pkg_temp_thermal ax88179_178a coretemp usbnet crct10dif_pclmul mii crc32_pclmul ghash_clmulni_intel e1000e [last unloaded: i915]
> [ 245.526191] CPU: 0 PID: 1234 Comm: kms_fullmodeset Not tainted 5.1.0-rc6+ #915
> [ 245.526197] Hardware name: Intel Corporation Tiger Lake Client Platform/TigerLake U DDR4 SODIMM RVP, BIOS TGLSFWR1.D00.2081.A10.1904182155 04/18/2019
> [ 245.526273] RIP: 0010:__unclaimed_reg_debug+0x40/0x50 [i915]
> [ 245.526281] Code: 74 05 5b 5d 41 5c c3 45 84 e4 48 c7 c0 76 97 21 a0 48 c7 c6 6c 97 21 a0 89 ea 48 0f 44 f0 48 c7 c7 7f 97 21 a0 e8 4f 1e fe e0 <0f> 0b 83 2d 6f d9 1c 00 01 5b 5d 41 5c c3 66 90 41 57 41 56 41 55
> [ 245.526288] RSP: 0018:ffffc900006bf7d8 EFLAGS: 00010086
> [ 245.526297] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000
> [ 245.526304] RDX: 0000000000000007 RSI: 0000000000000000 RDI: 00000000ffffffff
> [ 245.526310] RBP: 0000000000061900 R08: 0000000000000000 R09: 0000000000000001
> [ 245.526317] R10: 0000000000000006 R11: 0000000000000000 R12: 0000000000000001
> [ 245.526324] R13: 0000000000000000 R14: ffff8882914f0d58 R15: 0000000000000206
> [ 245.526332] FS: 00007fed2a3c39c0(0000) GS:ffff8882a8600000(0000) knlGS:0000000000000000
> [ 245.526340] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 245.526347] CR2: 00007fed28dff000 CR3: 00000002a086c006 CR4: 0000000000760ef0
> [ 245.526354] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
> [ 245.526361] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
> [ 245.526367] PKRU: 55555554
> [ 245.526373] Call Trace:
> [ 245.526454] gen11_fwtable_read32+0x219/0x250 [i915]
> [ 245.526576] intel_psr_activate+0x57/0x400 [i915]
> [ 245.526697] intel_psr_enable_locked+0x367/0x4b0 [i915]
> [ 245.526828] intel_psr_enable+0xa4/0xd0 [i915]
> [ 245.526946] intel_enable_ddi+0x127/0x2f0 [i915]
> [ 245.527075] intel_encoders_enable.isra.79+0x62/0x90 [i915]
> [ 245.527202] haswell_crtc_enable+0x2a2/0x850 [i915]
> [ 245.527337] intel_update_crtc+0x51/0x360 [i915]
> [ 245.527466] skl_update_crtcs+0x26c/0x300 [i915]
> [ 245.527603] intel_atomic_commit_tail+0x3e5/0x13c0 [i915]
> [ 245.527757] intel_atomic_commit+0x24d/0x2d0 [i915]
> [ 245.527782] drm_atomic_helper_set_config+0x7b/0x90
> [ 245.527799] drm_mode_setcrtc+0x1b4/0x6f0
> [ 245.527856] ? drm_mode_getcrtc+0x180/0x180
> [ 245.527867] drm_ioctl_kernel+0xad/0xf0
> [ 245.527886] drm_ioctl+0x2f4/0x3b0
> [ 245.527902] ? drm_mode_getcrtc+0x180/0x180
> [ 245.527935] ? rcu_read_lock_sched_held+0x6f/0x80
> [ 245.527956] do_vfs_ioctl+0xa0/0x6d0
> [ 245.527970] ? __task_pid_nr_ns+0xb6/0x200
> [ 245.527991] ksys_ioctl+0x35/0x70
> [ 245.528009] __x64_sys_ioctl+0x11/0x20
> [ 245.528020] do_syscall_64+0x55/0x180
> [ 245.528034] entry_SYSCALL_64_after_hwframe+0x49/0xbe
> [ 245.528042] RIP: 0033:0x7fed2cc7c3c7
> [ 245.528050] Code: 00 00 90 48 8b 05 c9 3a 0d 00 64 c7 00 26 00 00 00 48 c7 c0 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 b8 10 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 99 3a 0d 00 f7 d8 64 89 01 48
> [ 245.528057] RSP: 002b:00007ffe36944378 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
> [ 245.528067] RAX: ffffffffffffffda RBX: 00007ffe369443b0 RCX: 00007fed2cc7c3c7
> [ 245.528074] RDX: 00007ffe369443b0 RSI: 00000000c06864a2 RDI: 0000000000000003
> [ 245.528081] RBP: 00007ffe369443b0 R08: 0000000000000000 R09: 0000564c0173ae98
> [ 245.528088] R10: 0000564c0173aeb8 R11: 0000000000000246 R12: 00000000c06864a2
> [ 245.528095] R13: 0000000000000003 R14: 0000000000000000 R15: 0000000000000000
> [ 245.528128] irq event stamp: 140866
> [ 245.528138] hardirqs last enabled at (140865): [<ffffffff819a63dc>] _raw_spin_unlock_irqrestore+0x4c/0x60
> [ 245.528148] hardirqs last disabled at (140866): [<ffffffff819a624d>] _raw_spin_lock_irqsave+0xd/0x50
> [ 245.528158] softirqs last enabled at (140860): [<ffffffff81c0038c>] __do_softirq+0x38c/0x499
> [ 245.528170] softirqs last disabled at (140853): [<ffffffff810b4a09>] irq_exit+0xa9/0xc0
> [ 245.528247] WARNING: CPU: 0 PID: 1234 at drivers/gpu/drm/i915/intel_uncore.c:1100 __unclaimed_reg_debug+0x40/0x50 [i915]
> [ 245.528254] ---[ end trace 366069676e98a410 ]---
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index cf07ab3d9280..4e6b3ae8a872 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -631,7 +631,8 @@ static void intel_psr_activate(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> - if (INTEL_GEN(dev_priv) >= 9)
> + if (INTEL_GEN(dev_priv) >= 9 &&
> + psr2_supported(dev_priv, dev_priv->psr.transcoder))
^transcoder_has_psr2()
nit: Move the GEN check to transcoder_has_psr2()?
Either way:
Reviewed-by: Imre Deak <imre.deak@intel.com>
> WARN_ON(I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder)) & EDP_PSR2_ENABLE);
> WARN_ON(I915_READ(EDP_PSR_CTL(dev_priv->psr.transcoder)) & EDP_PSR_ENABLE);
> WARN_ON(dev_priv->psr.active);
> @@ -785,7 +786,8 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv)
> u32 val;
>
> if (!dev_priv->psr.active) {
> - if (INTEL_GEN(dev_priv) >= 9) {
> + if (INTEL_GEN(dev_priv) >= 9 &&
> + psr2_supported(dev_priv, dev_priv->psr.transcoder)) {
> val = I915_READ(EDP_PSR2_CTL(dev_priv->psr.transcoder));
> WARN_ON(val & EDP_PSR2_ENABLE);
> }
> --
> 2.23.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2019-08-26 14:23 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-23 8:20 [PATCH v3 00/23] Tiger Lake batch 3 Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 01/23] drm/i915/tgl: Move GTCR register to cope with GAM MMIO address remap Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 02/23] drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating Lucas De Marchi
2019-09-13 7:06 ` Chris Wilson
2019-08-23 8:20 ` [PATCH v3 03/23] drm/i915/psr: Only handle interruptions of the transcoder in use Lucas De Marchi
2019-08-26 17:28 ` Imre Deak
2019-08-27 16:50 ` Lucas De Marchi
2019-08-28 16:29 ` Imre Deak
2019-08-28 22:16 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 04/23] drm/i915/bdw+: Enable PSR in any eDP port Lucas De Marchi
2019-08-26 13:41 ` Imre Deak
2019-08-26 17:43 ` Runyan, Arthur J
2019-08-27 16:36 ` Lucas De Marchi
2019-08-27 17:55 ` Souza, Jose
2019-08-23 8:20 ` [PATCH v3 05/23] drm/i915: Guard and warn if more than one eDP panel is present Lucas De Marchi
2019-08-26 6:41 ` Anshuman Gupta
2019-08-23 8:20 ` [PATCH v3 06/23] drm/i915: Do not read PSR2 register in transcoders without PSR2 Lucas De Marchi
2019-08-26 14:21 ` Imre Deak [this message]
2019-08-26 16:32 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 07/23] drm/i915/tgl: PSR link standby is not supported anymore Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 08/23] drm/i915/tgl: Access the right register when handling PSR interruptions Lucas De Marchi
2019-08-26 9:53 ` Anshuman Gupta
2019-08-26 16:56 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 09/23] drm/i915/tgl: Add maximum resolution supported by PSR2 HW Lucas De Marchi
2019-08-24 11:06 ` Anshuman Gupta
2019-08-26 17:10 ` Lucas De Marchi
2019-08-26 17:17 ` Souza, Jose
2019-08-26 17:29 ` Lucas De Marchi
2019-08-26 17:33 ` Gupta, Anshuman
2019-08-23 8:20 ` [PATCH v3 10/23] drm/i915: Add for_each_new_intel_connector_in_state() Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 11/23] drm: Add for_each_oldnew_intel_crtc_in_state_reverse() Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 12/23] drm/i915: Disable pipes in reverse order Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 13/23] FIXME: drm/i915/tgl: Select master transcoder in DP MST Lucas De Marchi
2019-08-23 13:02 ` Ville Syrjälä
2019-08-23 8:20 ` [PATCH v3 14/23] drm/i915/tgl: move DP_TP_* to transcoder Lucas De Marchi
2019-08-23 12:25 ` Ville Syrjälä
2019-08-23 12:39 ` Ville Syrjälä
2019-08-23 8:20 ` [PATCH v3 15/23] drm/i915/tgl: Implement TGL DisplayPort training sequence Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 16/23] drm/i915/tgl: Do not apply WaIncreaseDefaultTLBEntries from GEN12 onwards Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 17/23] FIXME: drm/i915/tgl: Register state context definition for Gen12 Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 18/23] drm/i915/tgl/perf: use the same oa ctx_id format as icl Lucas De Marchi
2019-08-23 8:30 ` Lionel Landwerlin
2019-08-23 18:16 ` Umesh Nerlige Ramappa
2019-08-23 8:20 ` [PATCH v3 19/23] drm/i915/tgl: Gen-12 display loses Yf tiling and legacy CCS support Lucas De Marchi
2019-08-28 23:04 ` Matt Roper
2019-08-28 23:59 ` Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 20/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 render compression Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 21/23] drm/i915/tgl: Gen-12 render decompression Lucas De Marchi
2019-08-29 0:33 ` Matt Roper
2019-09-13 0:31 ` Sripada, Radhakrishna
2019-08-23 8:20 ` [PATCH v3 22/23] drm/framebuffer/tgl: Format modifier for Intel Gen-12 media compression Lucas De Marchi
2019-08-23 8:20 ` [PATCH v3 23/23] drm/i915/tgl: " Lucas De Marchi
2019-08-23 13:24 ` ✗ Fi.CI.CHECKPATCH: warning for Tiger Lake batch 3 (rev5) Patchwork
2019-08-23 13:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-08-23 13:53 ` ✓ Fi.CI.BAT: success " Patchwork
2019-08-24 11:50 ` ✓ Fi.CI.IGT: " Patchwork
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