Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v7 11/15] drm/i915/dg1: Load DMC
Date: Mon, 12 Oct 2020 14:29:55 -0700	[thread overview]
Message-ID: <20201012212959.871513-12-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201012212959.871513-1-lucas.demarchi@intel.com>

From: Matt Atwood <matthew.s.atwood@intel.com>

Add support to load DMC v2.0.2 on DG1

While we're at it, make TGL use the same GEN12 firmware size definition
and remove obsolete comment.

Bpec: 49230

v2: do not replace GEN12_CSR_MAX_FW_SIZE (from José)
    and replace stale comment

Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_csr.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_csr.c b/drivers/gpu/drm/i915/display/intel_csr.c
index d5db16764619..67dc64df78a5 100644
--- a/drivers/gpu/drm/i915/display/intel_csr.c
+++ b/drivers/gpu/drm/i915/display/intel_csr.c
@@ -40,13 +40,16 @@
 
 #define GEN12_CSR_MAX_FW_SIZE		ICL_CSR_MAX_FW_SIZE
 
+#define DG1_CSR_PATH			"i915/dg1_dmc_ver2_02.bin"
+#define DG1_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
+MODULE_FIRMWARE(DG1_CSR_PATH);
+
 #define RKL_CSR_PATH			"i915/rkl_dmc_ver2_02.bin"
 #define RKL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 2)
 MODULE_FIRMWARE(RKL_CSR_PATH);
 
 #define TGL_CSR_PATH			"i915/tgl_dmc_ver2_08.bin"
 #define TGL_CSR_VERSION_REQUIRED	CSR_VERSION(2, 8)
-#define TGL_CSR_MAX_FW_SIZE		0x6000
 MODULE_FIRMWARE(TGL_CSR_PATH);
 
 #define ICL_CSR_PATH			"i915/icl_dmc_ver1_09.bin"
@@ -686,14 +689,17 @@ void intel_csr_ucode_init(struct drm_i915_private *dev_priv)
 	 */
 	intel_csr_runtime_pm_get(dev_priv);
 
-	if (IS_ROCKETLAKE(dev_priv)) {
+	if (IS_DG1(dev_priv)) {
+		csr->fw_path = DG1_CSR_PATH;
+		csr->required_version = DG1_CSR_VERSION_REQUIRED;
+		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
+	} else if (IS_ROCKETLAKE(dev_priv)) {
 		csr->fw_path = RKL_CSR_PATH;
 		csr->required_version = RKL_CSR_VERSION_REQUIRED;
 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 	} else if (INTEL_GEN(dev_priv) >= 12) {
 		csr->fw_path = TGL_CSR_PATH;
 		csr->required_version = TGL_CSR_VERSION_REQUIRED;
-		/* Allow to load fw via parameter using the last known size */
 		csr->max_fw_size = GEN12_CSR_MAX_FW_SIZE;
 	} else if (IS_GEN(dev_priv, 11)) {
 		csr->fw_path = ICL_CSR_PATH;
-- 
2.28.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2020-10-12 21:31 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] Introduce DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 01/15] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-12 22:02   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 02/15] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-12 22:04   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 03/15] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-10-12 22:05   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 04/15] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 05/15] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 17:24   ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 06/15] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-10-12 22:40   ` Aditya Swarup
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 07/15] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-10-12 22:51   ` Aditya Swarup
2020-10-13  0:29     ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 08/15] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 09/15] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 10/15] drm/i915/dg1: Enable ports Lucas De Marchi
2020-10-12 21:29 ` Lucas De Marchi [this message]
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 12/15] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 13/15] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 14/15] drm/i915/dg1: Update DMC_DEBUG register Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 15/15] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-10-12 21:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-12 22:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-13  4:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20201012212959.871513-12-lucas.demarchi@intel.com \
    --to=lucas.demarchi@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox