From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v7 03/15] drm/i915/dg1: Add DG1 power wells
Date: Mon, 12 Oct 2020 14:29:47 -0700 [thread overview]
Message-ID: <20201012212959.871513-4-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201012212959.871513-1-lucas.demarchi@intel.com>
TGL power wells can be re-used for DG1 with the exception of the fake
power well for TC_COLD.
v2: use logic to skip power wells while copying instead of duplicating
the definition of TGL power wells (Matt Roper)
Bspec: 49182
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 7 +++++--
drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7437c7a79e5f..4934c89882b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4150,7 +4150,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "TC cold off",
.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
.ops = &tgl_tc_cold_off_ops,
- .id = DISP_PW_ID_NONE,
+ .id = TGL_DISP_PW_TC_COLD_OFF,
},
{
.name = "AUX A",
@@ -4634,7 +4634,10 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
* The enabling order will be from lower to higher indexed wells,
* the disabling order is reversed.
*/
- if (IS_ROCKETLAKE(dev_priv)) {
+ if (IS_DG1(dev_priv)) {
+ err = set_power_wells_mask(power_domains, tgl_power_wells,
+ BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+ } else if (IS_ROCKETLAKE(dev_priv)) {
err = set_power_wells(power_domains, rkl_power_wells);
} else if (IS_GEN(dev_priv, 12)) {
err = set_power_wells(power_domains, tgl_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 824590c5401f..4aa0a09cf14f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -105,6 +105,7 @@ enum i915_power_well_id {
CNL_DISP_PW_DDI_F_AUX,
ICL_DISP_PW_3,
SKL_DISP_DC_OFF,
+ TGL_DISP_PW_TC_COLD_OFF,
};
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
--
2.28.0
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next prev parent reply other threads:[~2020-10-12 21:30 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] Introduce DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 01/15] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-12 22:02 ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 02/15] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-12 22:04 ` Matt Roper
2020-10-12 21:29 ` Lucas De Marchi [this message]
2020-10-12 22:05 ` [Intel-gfx] [PATCH v7 03/15] drm/i915/dg1: Add DG1 power wells Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 04/15] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 05/15] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 17:24 ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 06/15] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-10-12 22:40 ` Aditya Swarup
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 07/15] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-10-12 22:51 ` Aditya Swarup
2020-10-13 0:29 ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 08/15] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 09/15] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 10/15] drm/i915/dg1: Enable ports Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 11/15] drm/i915/dg1: Load DMC Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 12/15] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 13/15] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 14/15] drm/i915/dg1: Update DMC_DEBUG register Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 15/15] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-10-12 21:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-12 22:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-13 4:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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