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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v7 14/15] drm/i915/dg1: Update DMC_DEBUG register
Date: Mon, 12 Oct 2020 14:29:58 -0700	[thread overview]
Message-ID: <20201012212959.871513-15-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201012212959.871513-1-lucas.demarchi@intel.com>

From: Anshuman Gupta <anshuman.gupta@intel.com>

Update the DMC_DEBUG_DC5 register to its new location and do not try
reading the DC6 counter since DG1 doesn't support DC6.

v2: Use IS_DGFX() instead of IS_DG1(). Even if not having DC6 is not
directly related to DGFX, the register move to a new location is. So in
future, if there is one supporting DC6, it would just need to add the
other register rather than fixing the case of a wrong register being
read (Matt)

Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_debugfs.c | 9 +++++++--
 drivers/gpu/drm/i915/i915_reg.h                      | 1 +
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index 0bf31f9a8af5..cfb4c1474982 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -518,8 +518,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
 		   CSR_VERSION_MINOR(csr->version));
 
 	if (INTEL_GEN(dev_priv) >= 12) {
-		dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
-		dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		if (IS_DGFX(dev_priv)) {
+			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+		} else {
+			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
+			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
+		}
+
 		/*
 		 * NOTE: DMC_DEBUG3 is a general purpose reg.
 		 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d7d902bb640..dead4bcf717f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7538,6 +7538,7 @@ enum {
 #define BXT_CSR_DC3_DC5_COUNT	_MMIO(0x80038)
 #define TGL_DMC_DEBUG_DC5_COUNT	_MMIO(0x101084)
 #define TGL_DMC_DEBUG_DC6_COUNT	_MMIO(0x101088)
+#define DG1_DMC_DEBUG_DC5_COUNT	_MMIO(0x134154)
 
 #define DMC_DEBUG3		_MMIO(0x101090)
 
-- 
2.28.0

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  parent reply	other threads:[~2020-10-12 21:31 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] Introduce DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 01/15] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-12 22:02   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 02/15] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-12 22:04   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 03/15] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-10-12 22:05   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 04/15] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 05/15] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 17:24   ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 06/15] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-10-12 22:40   ` Aditya Swarup
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 07/15] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-10-12 22:51   ` Aditya Swarup
2020-10-13  0:29     ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 08/15] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 09/15] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 10/15] drm/i915/dg1: Enable ports Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 11/15] drm/i915/dg1: Load DMC Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 12/15] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 13/15] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-10-12 21:29 ` Lucas De Marchi [this message]
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 15/15] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-10-12 21:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-12 22:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-13  4:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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