From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v7 13/15] drm/i915/dg1: DG1 does not support DC6
Date: Mon, 12 Oct 2020 14:29:57 -0700 [thread overview]
Message-ID: <20201012212959.871513-14-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201012212959.871513-1-lucas.demarchi@intel.com>
From: Anshuman Gupta <anshuman.gupta@intel.com>
DC6 is not supported on DG1, so change the allowed DC mask for DG1.
This is not yet on bspec, but it has been confirmed by HW engineers.
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 18af078c208b..45806cfc679a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4492,7 +4492,10 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
int max_dc;
if (INTEL_GEN(dev_priv) >= 12) {
- max_dc = 4;
+ if (IS_DG1(dev_priv))
+ max_dc = 3;
+ else
+ max_dc = 4;
/*
* DC9 has a separate HW flow from the rest of the DC states,
* not depending on the DMC firmware. It's needed by system
--
2.28.0
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next prev parent reply other threads:[~2020-10-12 21:31 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] Introduce DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 01/15] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-12 22:02 ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 02/15] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-12 22:04 ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 03/15] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-10-12 22:05 ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 04/15] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 05/15] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 17:24 ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 06/15] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-10-12 22:40 ` Aditya Swarup
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 07/15] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-10-12 22:51 ` Aditya Swarup
2020-10-13 0:29 ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 08/15] drm/i915/dg1: invert HPD pins Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 09/15] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 10/15] drm/i915/dg1: Enable ports Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 11/15] drm/i915/dg1: Load DMC Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 12/15] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-12 21:29 ` Lucas De Marchi [this message]
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 14/15] drm/i915/dg1: Update DMC_DEBUG register Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 15/15] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-10-12 21:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-12 22:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-13 4:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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