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From: Lucas De Marchi <lucas.demarchi@intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH v7 08/15] drm/i915/dg1: invert HPD pins
Date: Mon, 12 Oct 2020 14:29:52 -0700	[thread overview]
Message-ID: <20201012212959.871513-9-lucas.demarchi@intel.com> (raw)
In-Reply-To: <20201012212959.871513-1-lucas.demarchi@intel.com>

From: Clinton A Taylor <clinton.a.taylor@intel.com>

HPD pins are inverted for DG1 platform.

Bspec: 49956
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Clinton A Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/i915_irq.c | 9 +++++++++
 drivers/gpu/drm/i915/i915_reg.h | 4 ++++
 2 files changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 0d6e4894b505..d76974d957b3 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3288,6 +3288,15 @@ static void jsp_hpd_irq_setup(struct drm_i915_private *dev_priv)
 
 static void dg1_hpd_irq_setup(struct drm_i915_private *dev_priv)
 {
+	u32 val;
+
+	val = I915_READ(SOUTH_CHICKEN1);
+	val |= (INVERT_DDIA_HPD |
+		INVERT_DDIB_HPD |
+		INVERT_DDIC_HPD |
+		INVERT_DDID_HPD);
+	I915_WRITE(SOUTH_CHICKEN1, val);
+
 	icp_hpd_irq_setup(dev_priv,
 			  DG1_DDI_HPD_ENABLE_MASK, 0);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e7f1aac553d0..a943f36819eb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8697,6 +8697,10 @@ enum {
 #define SOUTH_CHICKEN1		_MMIO(0xc2000)
 #define  FDIA_PHASE_SYNC_SHIFT_OVR	19
 #define  FDIA_PHASE_SYNC_SHIFT_EN	18
+#define  INVERT_DDID_HPD			(1 << 18)
+#define  INVERT_DDIC_HPD			(1 << 17)
+#define  INVERT_DDIB_HPD			(1 << 16)
+#define  INVERT_DDIA_HPD			(1 << 15)
 #define  FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
 #define  FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
 #define  FDI_BC_BIFURCATION_SELECT	(1 << 12)
-- 
2.28.0

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  parent reply	other threads:[~2020-10-12 21:30 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-12 21:29 [Intel-gfx] [PATCH v7 00/15] Introduce DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 01/15] drm/i915/display: allow to skip certain power wells Lucas De Marchi
2020-10-12 22:02   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 02/15] drm/i915/cnl: skip PW_DDI_F on certain skus Lucas De Marchi
2020-10-12 22:04   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 03/15] drm/i915/dg1: Add DG1 power wells Lucas De Marchi
2020-10-12 22:05   ` Matt Roper
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 04/15] drm/i915/dg1: Add DPLL macros for DG1 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 05/15] drm/i915/dg1: Add and setup DPLLs " Lucas De Marchi
2020-10-14 17:24   ` Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 06/15] drm/i915/dg1: Enable DPLL " Lucas De Marchi
2020-10-12 22:40   ` Aditya Swarup
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 07/15] drm/i915/dg1: add hpd interrupt handling Lucas De Marchi
2020-10-12 22:51   ` Aditya Swarup
2020-10-13  0:29     ` Lucas De Marchi
2020-10-12 21:29 ` Lucas De Marchi [this message]
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 09/15] drm/i915/dg1: map/unmap pll clocks Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 10/15] drm/i915/dg1: Enable ports Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 11/15] drm/i915/dg1: Load DMC Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 12/15] drm/i915/dg1: Add initial DG1 workarounds Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 13/15] drm/i915/dg1: DG1 does not support DC6 Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 14/15] drm/i915/dg1: Update DMC_DEBUG register Lucas De Marchi
2020-10-12 21:29 ` [Intel-gfx] [PATCH v7 15/15] drm/i915/dgfx: define llc and snooping behaviour Lucas De Marchi
2020-10-12 21:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce DG1 Patchwork
2020-10-12 21:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-12 22:17 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-13  4:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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