* [Intel-gfx] [PATCH 01/10] drm/i915: s/USHRT_MAX/U16_MAX/
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 02/10] drm/i915: Shrink ilk-bdw wm storage by using u16 Ville Syrjala
` (12 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We use u16 for the watermarks so let's switch from
USHRT_MAX to U16_MAX for consistency.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 44 ++++++++++++++++-----------------
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f54375b11964..75d2322cd456 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1141,7 +1141,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
unsigned int clock, htotal, cpp, width, wm;
if (latency == 0)
- return USHRT_MAX;
+ return U16_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -1187,7 +1187,7 @@ static u16 g4x_compute_wm(const struct intel_crtc_state *crtc_state,
wm = DIV_ROUND_UP(wm, 64) + 2;
- return min_t(unsigned int, wm, USHRT_MAX);
+ return min_t(unsigned int, wm, U16_MAX);
}
static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state,
@@ -1272,17 +1272,17 @@ static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
* can always just disable its use.
*/
if (wm > max_wm)
- wm = USHRT_MAX;
+ wm = U16_MAX;
dirty |= raw->fbc != wm;
raw->fbc = wm;
}
/* mark watermarks as invalid */
- dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
+ dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, U16_MAX);
if (plane_id == PLANE_PRIMARY)
- dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
+ dirty |= g4x_raw_fbc_wm_set(crtc_state, level, U16_MAX);
out:
if (dirty) {
@@ -1332,21 +1332,21 @@ static void g4x_invalidate_wms(struct intel_crtc *crtc,
enum plane_id plane_id;
for_each_plane_id_on_crtc(crtc, plane_id)
- wm_state->wm.plane[plane_id] = USHRT_MAX;
+ wm_state->wm.plane[plane_id] = U16_MAX;
}
if (level <= G4X_WM_LEVEL_SR) {
wm_state->cxsr = false;
- wm_state->sr.cursor = USHRT_MAX;
- wm_state->sr.plane = USHRT_MAX;
- wm_state->sr.fbc = USHRT_MAX;
+ wm_state->sr.cursor = U16_MAX;
+ wm_state->sr.plane = U16_MAX;
+ wm_state->sr.fbc = U16_MAX;
}
if (level <= G4X_WM_LEVEL_HPLL) {
wm_state->hpll_en = false;
- wm_state->hpll.cursor = USHRT_MAX;
- wm_state->hpll.plane = USHRT_MAX;
- wm_state->hpll.fbc = USHRT_MAX;
+ wm_state->hpll.cursor = U16_MAX;
+ wm_state->hpll.plane = U16_MAX;
+ wm_state->hpll.fbc = U16_MAX;
}
}
@@ -1665,7 +1665,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
unsigned int clock, htotal, cpp, width, wm;
if (dev_priv->wm.pri_latency[level] == 0)
- return USHRT_MAX;
+ return U16_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -1688,7 +1688,7 @@ static u16 vlv_compute_wm_level(const struct intel_crtc_state *crtc_state,
dev_priv->wm.pri_latency[level] * 10);
}
- return min_t(unsigned int, wm, USHRT_MAX);
+ return min_t(unsigned int, wm, U16_MAX);
}
static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes)
@@ -1790,17 +1790,17 @@ static void vlv_invalidate_wms(struct intel_crtc *crtc,
enum plane_id plane_id;
for_each_plane_id_on_crtc(crtc, plane_id)
- wm_state->wm[level].plane[plane_id] = USHRT_MAX;
+ wm_state->wm[level].plane[plane_id] = U16_MAX;
- wm_state->sr[level].cursor = USHRT_MAX;
- wm_state->sr[level].plane = USHRT_MAX;
+ wm_state->sr[level].cursor = U16_MAX;
+ wm_state->sr[level].plane = U16_MAX;
}
}
static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
{
if (wm > fifo_size)
- return USHRT_MAX;
+ return U16_MAX;
else
return fifo_size - wm;
}
@@ -1854,7 +1854,7 @@ static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
}
/* mark all higher levels as invalid */
- dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX);
+ dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, U16_MAX);
out:
if (dirty)
@@ -6492,8 +6492,8 @@ void g4x_wm_get_hw_state(struct drm_i915_private *dev_priv)
out:
for_each_plane_id_on_crtc(crtc, plane_id)
g4x_raw_plane_wm_set(crtc_state, level,
- plane_id, USHRT_MAX);
- g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX);
+ plane_id, U16_MAX);
+ g4x_raw_fbc_wm_set(crtc_state, level, U16_MAX);
crtc_state->wm.g4x.optimal = *active;
crtc_state->wm.g4x.intermediate = *active;
@@ -6652,7 +6652,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
for_each_plane_id_on_crtc(crtc, plane_id)
vlv_raw_plane_wm_set(crtc_state, level,
- plane_id, USHRT_MAX);
+ plane_id, U16_MAX);
vlv_invalidate_wms(crtc, active, level);
crtc_state->wm.vlv.optimal = *active;
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 02/10] drm/i915: Shrink ilk-bdw wm storage by using u16
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 01/10] drm/i915: s/USHRT_MAX/U16_MAX/ Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 03/10] drm/i915: Rename ilk watermark structs/enums Ville Syrjala
` (11 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The maximum watermark value we can ever have on ilk-bdw is
11 bits. Thus we can safely store all of these values in
u16.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 74 +++++++++----------
2 files changed, 40 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f6f0626649e0..4c25e2e4f4ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -666,10 +666,10 @@ struct intel_crtc_scaler_state {
struct intel_wm_level {
bool enable;
- u32 pri_val;
- u32 spr_val;
- u32 cur_val;
- u32 fbc_val;
+ u16 pri_val;
+ u16 spr_val;
+ u16 cur_val;
+ u16 fbc_val;
};
struct intel_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 75d2322cd456..a82fb812b8c7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1225,9 +1225,9 @@ static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state,
return dirty;
}
-static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
+static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- u32 pri_val);
+ u16 pri_val);
static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
@@ -2506,7 +2506,7 @@ static unsigned int ilk_wm_method1(unsigned int pixel_rate,
ret = intel_wm_method1(pixel_rate, cpp, latency);
ret = DIV_ROUND_UP(ret, 64) + 2;
- return ret;
+ return min_t(unsigned int, ret, U16_MAX);
}
/* latency must be in 0.1us units. */
@@ -2522,10 +2522,11 @@ static unsigned int ilk_wm_method2(unsigned int pixel_rate,
width, cpp, latency);
ret = DIV_ROUND_UP(ret, 64) + 2;
- return ret;
+ return min_t(unsigned int, ret, U16_MAX);
}
-static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
+static u16 ilk_wm_fbc(u16 pri_val, unsigned int horiz_pixels,
+ unsigned int cpp)
{
/*
* Neither of these should be possible since this function shouldn't be
@@ -2552,15 +2553,15 @@ struct ilk_wm_maximums {
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
+static u16 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- u32 mem_value, bool is_lp)
+ unsigned int mem_value, bool is_lp)
{
- u32 method1, method2;
+ u16 method1, method2;
int cpp;
if (mem_value == 0)
- return U32_MAX;
+ return U16_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -2584,15 +2585,15 @@ static u32 ilk_compute_pri_wm(const struct intel_crtc_state *crtc_state,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
+static u16 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- u32 mem_value)
+ unsigned int mem_value)
{
- u32 method1, method2;
+ u16 method1, method2;
int cpp;
if (mem_value == 0)
- return U32_MAX;
+ return U16_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -2611,14 +2612,14 @@ static u32 ilk_compute_spr_wm(const struct intel_crtc_state *crtc_state,
* For both WM_PIPE and WM_LP.
* mem_value must be in 0.1us units.
*/
-static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
+static u16 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- u32 mem_value)
+ unsigned int mem_value)
{
int cpp;
if (mem_value == 0)
- return U32_MAX;
+ return U16_MAX;
if (!intel_wm_plane_visible(crtc_state, plane_state))
return 0;
@@ -2632,9 +2633,9 @@ static u32 ilk_compute_cur_wm(const struct intel_crtc_state *crtc_state,
}
/* Only for WM_LP. */
-static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
+static u16 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
- u32 pri_val)
+ u16 pri_val)
{
int cpp;
@@ -2647,8 +2648,7 @@ static u32 ilk_compute_fbc_wm(const struct intel_crtc_state *crtc_state,
cpp);
}
-static unsigned int
-ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
+static u16 ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) >= 8)
return 3072;
@@ -2658,9 +2658,8 @@ ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
return 512;
}
-static unsigned int
-ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
- int level, bool is_sprite)
+static u16 ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
+ int level, bool is_sprite)
{
if (INTEL_GEN(dev_priv) >= 8)
/* BDW primary/sprite plane watermarks */
@@ -2676,8 +2675,7 @@ ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
return level == 0 ? 63 : 255;
}
-static unsigned int
-ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
+static u16 ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
{
if (INTEL_GEN(dev_priv) >= 7)
return level == 0 ? 63 : 255;
@@ -2685,7 +2683,7 @@ ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
return level == 0 ? 31 : 63;
}
-static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
+static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
{
if (INTEL_GEN(dev_priv) >= 8)
return 31;
@@ -2694,13 +2692,13 @@ static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
}
/* Calculate the maximum primary/sprite plane watermark */
-static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
- int level,
- const struct intel_wm_config *config,
- enum intel_ddb_partitioning ddb_partitioning,
- bool is_sprite)
+static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
+ int level,
+ const struct intel_wm_config *config,
+ enum intel_ddb_partitioning ddb_partitioning,
+ bool is_sprite)
{
- unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
+ u16 fifo_size = ilk_display_fifo_size(dev_priv);
/* if sprites aren't enabled, sprites get nothing */
if (is_sprite && !config->sprites_enabled)
@@ -2735,9 +2733,9 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
}
/* Calculate the maximum cursor plane watermark */
-static unsigned int ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
- int level,
- const struct intel_wm_config *config)
+static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
+ int level,
+ const struct intel_wm_config *config)
{
/* HSW LP1+ watermarks w/ multiple pipes */
if (level > 0 && config->num_pipes_active > 1)
@@ -2801,9 +2799,9 @@ static bool ilk_validate_wm_level(int level,
DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
level, result->cur_val, max->cur);
- result->pri_val = min_t(u32, result->pri_val, max->pri);
- result->spr_val = min_t(u32, result->spr_val, max->spr);
- result->cur_val = min_t(u32, result->cur_val, max->cur);
+ result->pri_val = min(result->pri_val, max->pri);
+ result->spr_val = min(result->spr_val, max->spr);
+ result->cur_val = min(result->cur_val, max->cur);
result->enable = true;
}
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 03/10] drm/i915: Rename ilk watermark structs/enums
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 01/10] drm/i915: s/USHRT_MAX/U16_MAX/ Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 02/10] drm/i915: Shrink ilk-bdw wm storage by using u16 Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 04/10] drm/i915: s/dev_priv->wm.hw/&dev_priv->wm.ilk/ Ville Syrjala
` (10 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename all the watermark related structs/enums specific to ilk-bdw
to have an ilk_ prefix rather than an intel_ prefix. Should make it
less confusing for everyone when it's clear where these things
get used.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 12 +--
drivers/gpu/drm/i915/i915_drv.h | 8 +-
drivers/gpu/drm/i915/intel_pm.c | 102 +++++++++---------
3 files changed, 60 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 4c25e2e4f4ee..6b31af60d24d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -664,7 +664,7 @@ struct intel_crtc_scaler_state {
/* Flag to indicate mipi dsi periodic command mode where we do not get TE */
#define I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE (1<<5)
-struct intel_wm_level {
+struct ilk_wm_level {
bool enable;
u16 pri_val;
u16 spr_val;
@@ -672,8 +672,8 @@ struct intel_wm_level {
u16 fbc_val;
};
-struct intel_pipe_wm {
- struct intel_wm_level wm[5];
+struct ilk_pipe_wm {
+ struct ilk_wm_level wm[5];
bool fbc_wm_enabled;
bool pipe_enabled;
bool sprites_enabled;
@@ -745,13 +745,13 @@ struct intel_crtc_wm_state {
* switching away from and the new
* configuration we're switching to.
*/
- struct intel_pipe_wm intermediate;
+ struct ilk_pipe_wm intermediate;
/*
* Optimal watermarks, programmed post-vblank
* when this state is committed.
*/
- struct intel_pipe_wm optimal;
+ struct ilk_pipe_wm optimal;
} ilk;
struct {
@@ -1147,7 +1147,7 @@ struct intel_crtc {
struct {
/* watermarks currently being used */
union {
- struct intel_pipe_wm ilk;
+ struct ilk_pipe_wm ilk;
struct vlv_wm_state vlv;
struct g4x_wm_state g4x;
} active;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bcd8650603d8..3a1b37c560e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -723,9 +723,9 @@ struct intel_vbt_data {
struct sdvo_device_mapping sdvo_mappings[2];
};
-enum intel_ddb_partitioning {
- INTEL_DDB_PART_1_2,
- INTEL_DDB_PART_5_6, /* IVB+ */
+enum ilk_ddb_partitioning {
+ ILK_DDB_PART_1_2,
+ ILK_DDB_PART_5_6, /* IVB+ */
};
struct ilk_wm_values {
@@ -733,7 +733,7 @@ struct ilk_wm_values {
u32 wm_lp[3];
u32 wm_lp_spr[3];
bool enable_fbc_wm;
- enum intel_ddb_partitioning partitioning;
+ enum ilk_ddb_partitioning partitioning;
};
struct g4x_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index a82fb812b8c7..536420327c66 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -65,7 +65,7 @@ struct skl_wm_params {
};
/* used in computing the new watermarks state */
-struct intel_wm_config {
+struct ilk_wm_config {
unsigned int num_pipes_active;
bool sprites_enabled;
bool sprites_scaled;
@@ -2694,8 +2694,8 @@ static u16 ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
/* Calculate the maximum primary/sprite plane watermark */
static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
int level,
- const struct intel_wm_config *config,
- enum intel_ddb_partitioning ddb_partitioning,
+ const struct ilk_wm_config *config,
+ enum ilk_ddb_partitioning ddb_partitioning,
bool is_sprite)
{
u16 fifo_size = ilk_display_fifo_size(dev_priv);
@@ -2719,7 +2719,7 @@ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
if (config->sprites_enabled) {
/* level 0 is always calculated with 1:1 split */
- if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
+ if (level > 0 && ddb_partitioning == ILK_DDB_PART_5_6) {
if (is_sprite)
fifo_size *= 5;
fifo_size /= 6;
@@ -2735,7 +2735,7 @@ static u16 ilk_plane_wm_max(const struct drm_i915_private *dev_priv,
/* Calculate the maximum cursor plane watermark */
static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
int level,
- const struct intel_wm_config *config)
+ const struct ilk_wm_config *config)
{
/* HSW LP1+ watermarks w/ multiple pipes */
if (level > 0 && config->num_pipes_active > 1)
@@ -2747,8 +2747,8 @@ static u16 ilk_cursor_wm_max(const struct drm_i915_private *dev_priv,
static void ilk_compute_wm_maximums(const struct drm_i915_private *dev_priv,
int level,
- const struct intel_wm_config *config,
- enum intel_ddb_partitioning ddb_partitioning,
+ const struct ilk_wm_config *config,
+ enum ilk_ddb_partitioning ddb_partitioning,
struct ilk_wm_maximums *max)
{
max->pri = ilk_plane_wm_max(dev_priv, level, config, ddb_partitioning, false);
@@ -2769,7 +2769,7 @@ static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
static bool ilk_validate_wm_level(int level,
const struct ilk_wm_maximums *max,
- struct intel_wm_level *result)
+ struct ilk_wm_level *result)
{
bool ret;
@@ -2815,7 +2815,7 @@ static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
const struct intel_plane_state *pristate,
const struct intel_plane_state *sprstate,
const struct intel_plane_state *curstate,
- struct intel_wm_level *result)
+ struct ilk_wm_level *result)
{
u16 pri_latency = dev_priv->wm.pri_latency[level];
u16 spr_latency = dev_priv->wm.spr_latency[level];
@@ -3114,10 +3114,10 @@ static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
}
static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
- struct intel_pipe_wm *pipe_wm)
+ struct ilk_pipe_wm *pipe_wm)
{
/* LP0 watermark maximums depend on this pipe alone */
- const struct intel_wm_config config = {
+ const struct ilk_wm_config config = {
.num_pipes_active = 1,
.sprites_enabled = pipe_wm->sprites_enabled,
.sprites_scaled = pipe_wm->sprites_scaled,
@@ -3125,7 +3125,7 @@ static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
struct ilk_wm_maximums max;
/* LP0 watermarks always use 1/2 DDB partitioning */
- ilk_compute_wm_maximums(dev_priv, 0, &config, INTEL_DDB_PART_1_2, &max);
+ ilk_compute_wm_maximums(dev_priv, 0, &config, ILK_DDB_PART_1_2, &max);
/* At least LP0 must be valid */
if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
@@ -3141,7 +3141,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct intel_pipe_wm *pipe_wm;
+ struct ilk_pipe_wm *pipe_wm;
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
const struct intel_plane_state *pristate = NULL;
@@ -3189,7 +3189,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
for (level = 1; level <= usable_level; level++) {
- struct intel_wm_level *wm = &pipe_wm->wm[level];
+ struct ilk_wm_level *wm = &pipe_wm->wm[level];
ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
pristate, sprstate, curstate, wm);
@@ -3217,12 +3217,12 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
{
struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
+ struct ilk_pipe_wm *a = &newstate->wm.ilk.intermediate;
struct intel_atomic_state *intel_state =
to_intel_atomic_state(newstate->uapi.state);
const struct intel_crtc_state *oldstate =
intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
- const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
+ const struct ilk_pipe_wm *b = &oldstate->wm.ilk.optimal;
int level, max_level = ilk_wm_max_level(dev_priv);
/*
@@ -3240,8 +3240,8 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
a->sprites_scaled |= b->sprites_scaled;
for (level = 0; level <= max_level; level++) {
- struct intel_wm_level *a_wm = &a->wm[level];
- const struct intel_wm_level *b_wm = &b->wm[level];
+ struct ilk_wm_level *a_wm = &a->wm[level];
+ const struct ilk_wm_level *b_wm = &b->wm[level];
a_wm->enable &= b_wm->enable;
a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
@@ -3274,15 +3274,15 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
*/
static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
int level,
- struct intel_wm_level *ret_wm)
+ struct ilk_wm_level *ret_wm)
{
const struct intel_crtc *intel_crtc;
ret_wm->enable = true;
for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
- const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
- const struct intel_wm_level *wm = &active->wm[level];
+ const struct ilk_pipe_wm *active = &intel_crtc->wm.active.ilk;
+ const struct ilk_wm_level *wm = &active->wm[level];
if (!active->pipe_enabled)
continue;
@@ -3306,9 +3306,9 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
* Merge all low power watermarks for all active pipes.
*/
static void ilk_wm_merge(struct drm_i915_private *dev_priv,
- const struct intel_wm_config *config,
+ const struct ilk_wm_config *config,
const struct ilk_wm_maximums *max,
- struct intel_pipe_wm *merged)
+ struct ilk_pipe_wm *merged)
{
int level, max_level = ilk_wm_max_level(dev_priv);
int last_enabled_level = max_level;
@@ -3323,7 +3323,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
/* merge each WM1+ level */
for (level = 1; level <= max_level; level++) {
- struct intel_wm_level *wm = &merged->wm[level];
+ struct ilk_wm_level *wm = &merged->wm[level];
ilk_merge_wm_level(dev_priv, level, wm);
@@ -3353,14 +3353,14 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
if (IS_GEN(dev_priv, 5) && !merged->fbc_wm_enabled &&
intel_fbc_is_active(dev_priv)) {
for (level = 2; level <= max_level; level++) {
- struct intel_wm_level *wm = &merged->wm[level];
+ struct ilk_wm_level *wm = &merged->wm[level];
wm->enable = false;
}
}
}
-static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
+static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm)
{
/* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
@@ -3377,11 +3377,11 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
}
static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
- const struct intel_pipe_wm *merged,
- enum intel_ddb_partitioning partitioning,
+ const struct ilk_pipe_wm *merged,
+ enum ilk_ddb_partitioning partitioning,
struct ilk_wm_values *results)
{
- struct intel_crtc *intel_crtc;
+ struct intel_crtc *crtc;
int level, wm_lp;
results->enable_fbc_wm = merged->fbc_wm_enabled;
@@ -3389,7 +3389,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
/* LP1+ register values */
for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
- const struct intel_wm_level *r;
+ const struct ilk_wm_level *r;
level = ilk_wm_lp_to_level(wm_lp, merged);
@@ -3426,10 +3426,9 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
}
/* LP0 register values */
- for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
- enum pipe pipe = intel_crtc->pipe;
- const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
- const struct intel_wm_level *r = &pipe_wm->wm[0];
+ for_each_intel_crtc(&dev_priv->drm, crtc) {
+ const struct ilk_wm_level *r = &crtc->wm.active.ilk.wm[0];
+ enum pipe pipe = crtc->pipe;
if (drm_WARN_ON(&dev_priv->drm, !r->enable))
continue;
@@ -3443,10 +3442,10 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
/* Find the result with the highest level enabled. Check for enable_fbc_wm in
* case both are at the same level. Prefer r1 in case they're the same. */
-static struct intel_pipe_wm *
+static struct ilk_pipe_wm *
ilk_find_best_result(struct drm_i915_private *dev_priv,
- struct intel_pipe_wm *r1,
- struct intel_pipe_wm *r2)
+ struct ilk_pipe_wm *r1,
+ struct ilk_pipe_wm *r2)
{
int level, max_level = ilk_wm_max_level(dev_priv);
int level1 = 0, level2 = 0;
@@ -3580,14 +3579,14 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_DDB) {
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
val = I915_READ(WM_MISC);
- if (results->partitioning == INTEL_DDB_PART_1_2)
+ if (results->partitioning == ILK_DDB_PART_1_2)
val &= ~WM_MISC_DATA_PARTITION_5_6;
else
val |= WM_MISC_DATA_PARTITION_5_6;
I915_WRITE(WM_MISC, val);
} else {
val = I915_READ(DISP_ARB_CTL2);
- if (results->partitioning == INTEL_DDB_PART_1_2)
+ if (results->partitioning == ILK_DDB_PART_1_2)
val &= ~DISP_DATA_PARTITION_5_6;
else
val |= DISP_DATA_PARTITION_5_6;
@@ -6135,13 +6134,13 @@ skl_compute_wm(struct intel_atomic_state *state)
}
static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
- struct intel_wm_config *config)
+ struct ilk_wm_config *config)
{
struct intel_crtc *crtc;
/* Compute the currently _active_ config */
for_each_intel_crtc(&dev_priv->drm, crtc) {
- const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
+ const struct ilk_pipe_wm *wm = &crtc->wm.active.ilk;
if (!wm->pipe_enabled)
continue;
@@ -6154,21 +6153,21 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
+ struct ilk_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
- struct intel_wm_config config = {};
+ struct ilk_wm_config config = {};
struct ilk_wm_values results = {};
- enum intel_ddb_partitioning partitioning;
+ enum ilk_ddb_partitioning partitioning;
ilk_compute_wm_config(dev_priv, &config);
- ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_1_2, &max);
+ ilk_compute_wm_maximums(dev_priv, 1, &config, ILK_DDB_PART_1_2, &max);
ilk_wm_merge(dev_priv, &config, &max, &lp_wm_1_2);
/* 5/6 split only in single pipe config on IVB+ */
if (INTEL_GEN(dev_priv) >= 7 &&
config.num_pipes_active == 1 && config.sprites_enabled) {
- ilk_compute_wm_maximums(dev_priv, 1, &config, INTEL_DDB_PART_5_6, &max);
+ ilk_compute_wm_maximums(dev_priv, 1, &config, ILK_DDB_PART_5_6, &max);
ilk_wm_merge(dev_priv, &config, &max, &lp_wm_5_6);
best_lp_wm = ilk_find_best_result(dev_priv, &lp_wm_1_2, &lp_wm_5_6);
@@ -6177,7 +6176,7 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
}
partitioning = (best_lp_wm == &lp_wm_1_2) ?
- INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
+ ILK_DDB_PART_1_2 : ILK_DDB_PART_5_6;
ilk_compute_wm_results(dev_priv, best_lp_wm, partitioning, &results);
@@ -6279,11 +6278,10 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct ilk_wm_values *hw = &dev_priv->wm.hw;
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
- struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
+ struct ilk_pipe_wm *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
@@ -6757,10 +6755,10 @@ void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
- INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
+ ILK_DDB_PART_5_6 : ILK_DDB_PART_1_2;
else if (IS_IVYBRIDGE(dev_priv))
hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
- INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
+ ILK_DDB_PART_5_6 : ILK_DDB_PART_1_2;
hw->enable_fbc_wm =
!(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 04/10] drm/i915: s/dev_priv->wm.hw/&dev_priv->wm.ilk/
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (2 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 03/10] drm/i915: Rename ilk watermark structs/enums Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 05/10] drm/i915: s/ilk_pipe_wm/ilk_wm_state/ Ville Syrjala
` (9 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the 'hw' thing to 'ilk' to make sure it's specific
to ilk+. We already have 'g4x' and 'vlv' next to it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 2 +-
drivers/gpu/drm/i915/intel_pm.c | 10 +++++-----
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3a1b37c560e5..0d05f7586e19 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1113,7 +1113,7 @@ struct drm_i915_private {
/* current hardware state */
union {
- struct ilk_wm_values hw;
+ struct ilk_wm_values ilk;
struct vlv_wm_values vlv;
struct g4x_wm_values g4x;
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 536420327c66..871d374fb93f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3525,7 +3525,7 @@ static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
unsigned int dirty)
{
- struct ilk_wm_values *previous = &dev_priv->wm.hw;
+ struct ilk_wm_values *previous = &dev_priv->wm.ilk;
bool changed = false;
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
@@ -3559,7 +3559,7 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
struct ilk_wm_values *results)
{
- struct ilk_wm_values *previous = &dev_priv->wm.hw;
+ struct ilk_wm_values *previous = &dev_priv->wm.ilk;
unsigned int dirty;
u32 val;
@@ -3621,7 +3621,7 @@ static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
- dev_priv->wm.hw = *results;
+ dev_priv->wm.ilk = *results;
}
bool ilk_disable_lp_wm(struct drm_i915_private *dev_priv)
@@ -6279,7 +6279,7 @@ void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- struct ilk_wm_values *hw = &dev_priv->wm.hw;
+ struct ilk_wm_values *hw = &dev_priv->wm.ilk;
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
struct ilk_pipe_wm *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
@@ -6735,7 +6735,7 @@ static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
void ilk_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
- struct ilk_wm_values *hw = &dev_priv->wm.hw;
+ struct ilk_wm_values *hw = &dev_priv->wm.ilk;
struct intel_crtc *crtc;
ilk_init_lp_watermarks(dev_priv);
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 05/10] drm/i915: s/ilk_pipe_wm/ilk_wm_state/
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (3 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 04/10] drm/i915: s/dev_priv->wm.hw/&dev_priv->wm.ilk/ Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 06/10] drm/i915: Stash away the original SSKPD latency values Ville Syrjala
` (8 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename ilk_pipe_wm to ilk_wm_state to match how things are
named for g4x/vlv.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_types.h | 8 +++---
drivers/gpu/drm/i915/intel_pm.c | 28 +++++++++----------
2 files changed, 18 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6b31af60d24d..9b4be062a7ef 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -672,7 +672,7 @@ struct ilk_wm_level {
u16 fbc_val;
};
-struct ilk_pipe_wm {
+struct ilk_wm_state {
struct ilk_wm_level wm[5];
bool fbc_wm_enabled;
bool pipe_enabled;
@@ -745,13 +745,13 @@ struct intel_crtc_wm_state {
* switching away from and the new
* configuration we're switching to.
*/
- struct ilk_pipe_wm intermediate;
+ struct ilk_wm_state intermediate;
/*
* Optimal watermarks, programmed post-vblank
* when this state is committed.
*/
- struct ilk_pipe_wm optimal;
+ struct ilk_wm_state optimal;
} ilk;
struct {
@@ -1147,7 +1147,7 @@ struct intel_crtc {
struct {
/* watermarks currently being used */
union {
- struct ilk_pipe_wm ilk;
+ struct ilk_wm_state ilk;
struct vlv_wm_state vlv;
struct g4x_wm_state g4x;
} active;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 871d374fb93f..61bb36239930 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3114,7 +3114,7 @@ static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
}
static bool ilk_validate_pipe_wm(const struct drm_i915_private *dev_priv,
- struct ilk_pipe_wm *pipe_wm)
+ struct ilk_wm_state *pipe_wm)
{
/* LP0 watermark maximums depend on this pipe alone */
const struct ilk_wm_config config = {
@@ -3141,7 +3141,7 @@ static int ilk_compute_pipe_wm(struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct ilk_pipe_wm *pipe_wm;
+ struct ilk_wm_state *pipe_wm;
struct intel_plane *plane;
const struct intel_plane_state *plane_state;
const struct intel_plane_state *pristate = NULL;
@@ -3217,12 +3217,12 @@ static int ilk_compute_intermediate_wm(struct intel_crtc_state *newstate)
{
struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
- struct ilk_pipe_wm *a = &newstate->wm.ilk.intermediate;
+ struct ilk_wm_state *a = &newstate->wm.ilk.intermediate;
struct intel_atomic_state *intel_state =
to_intel_atomic_state(newstate->uapi.state);
const struct intel_crtc_state *oldstate =
intel_atomic_get_old_crtc_state(intel_state, intel_crtc);
- const struct ilk_pipe_wm *b = &oldstate->wm.ilk.optimal;
+ const struct ilk_wm_state *b = &oldstate->wm.ilk.optimal;
int level, max_level = ilk_wm_max_level(dev_priv);
/*
@@ -3281,7 +3281,7 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
ret_wm->enable = true;
for_each_intel_crtc(&dev_priv->drm, intel_crtc) {
- const struct ilk_pipe_wm *active = &intel_crtc->wm.active.ilk;
+ const struct ilk_wm_state *active = &intel_crtc->wm.active.ilk;
const struct ilk_wm_level *wm = &active->wm[level];
if (!active->pipe_enabled)
@@ -3308,7 +3308,7 @@ static void ilk_merge_wm_level(struct drm_i915_private *dev_priv,
static void ilk_wm_merge(struct drm_i915_private *dev_priv,
const struct ilk_wm_config *config,
const struct ilk_wm_maximums *max,
- struct ilk_pipe_wm *merged)
+ struct ilk_wm_state *merged)
{
int level, max_level = ilk_wm_max_level(dev_priv);
int last_enabled_level = max_level;
@@ -3360,7 +3360,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv,
}
}
-static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_pipe_wm *pipe_wm)
+static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_wm_state *pipe_wm)
{
/* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
@@ -3377,7 +3377,7 @@ static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
}
static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
- const struct ilk_pipe_wm *merged,
+ const struct ilk_wm_state *merged,
enum ilk_ddb_partitioning partitioning,
struct ilk_wm_values *results)
{
@@ -3442,10 +3442,10 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
/* Find the result with the highest level enabled. Check for enable_fbc_wm in
* case both are at the same level. Prefer r1 in case they're the same. */
-static struct ilk_pipe_wm *
+static struct ilk_wm_state *
ilk_find_best_result(struct drm_i915_private *dev_priv,
- struct ilk_pipe_wm *r1,
- struct ilk_pipe_wm *r2)
+ struct ilk_wm_state *r1,
+ struct ilk_wm_state *r2)
{
int level, max_level = ilk_wm_max_level(dev_priv);
int level1 = 0, level2 = 0;
@@ -6140,7 +6140,7 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
/* Compute the currently _active_ config */
for_each_intel_crtc(&dev_priv->drm, crtc) {
- const struct ilk_pipe_wm *wm = &crtc->wm.active.ilk;
+ const struct ilk_wm_state *wm = &crtc->wm.active.ilk;
if (!wm->pipe_enabled)
continue;
@@ -6153,7 +6153,7 @@ static void ilk_compute_wm_config(struct drm_i915_private *dev_priv,
static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
{
- struct ilk_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
+ struct ilk_wm_state lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
struct ilk_wm_maximums max;
struct ilk_wm_config config = {};
struct ilk_wm_values results = {};
@@ -6281,7 +6281,7 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct ilk_wm_values *hw = &dev_priv->wm.ilk;
struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
- struct ilk_pipe_wm *active = &crtc_state->wm.ilk.optimal;
+ struct ilk_wm_state *active = &crtc_state->wm.ilk.optimal;
enum pipe pipe = crtc->pipe;
hw->wm_pipe[pipe] = I915_READ(WM0_PIPE_ILK(pipe));
--
2.26.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 06/10] drm/i915: Stash away the original SSKPD latency values
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (4 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 05/10] drm/i915: s/ilk_pipe_wm/ilk_wm_state/ Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 07/10] drm/i915: Remove gen6_check_mch_setup() Ville Syrjala
` (7 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
On ILK-IVB we must write the latency value read from SSKPD into
the latency field in the WM_LP registers. While bspec was never
clear on how the punit (or whatever) interprets these values
empirical evidence has shown that these are treated as a cookie
rather than as a literal latency value. That is, if we write a
value that we didn't get from SSKPD (just off by one is sufficient)
the system no longer appears to enter the corresponding power
saving state.
This was made much more obvious on HSW/BDW since there we longer
write the latency value into the WM_LP registers, and rather we
write the desired watermark level number (well, 2x the level
number).
Since we allow the user to adjust the latency values via debugfs,
and since we have some quirks where we adjust the values automagically,
we must stash away the originals read from SSKPD for later use
in the WM_LP registers.
v2: s/latency/cookie/ to make it clear what it is
s/u16/u8/ since the reg can only hold 7 bits
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 6 ++++++
drivers/gpu/drm/i915/intel_pm.c | 37 +++++++++++++++++++++++----------
2 files changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0d05f7586e19..533afb4da3c0 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1135,6 +1135,12 @@ struct drm_i915_private {
* FIXME get rid of this.
*/
bool distrust_bios_wm;
+
+ /*
+ * The values we must write to the LP watermark
+ * registers' latency field on ILK-BDW.
+ */
+ u8 ilk_wm_lp_cookie[5];
} wm;
struct dram_info {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 61bb36239930..5db20bf36302 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3085,10 +3085,35 @@ static void snb_wm_lp3_irq_quirk(struct drm_i915_private *dev_priv)
intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
}
+/* The value we need to program into the WM_LPx latency field */
+static u16 ilk_wm_lp_cookie(struct drm_i915_private *dev_priv, int level)
+{
+ if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
+ return 2 * level;
+ else
+ return dev_priv->wm.pri_latency[level];
+}
+
+static void ilk_setup_wm_lp_cookie(struct drm_i915_private *dev_priv)
+{
+ int level, max_level = ilk_wm_max_level(dev_priv);
+
+ for (level = 1; level <= max_level; level++)
+ dev_priv->wm.ilk_wm_lp_cookie[level] =
+ ilk_wm_lp_cookie(dev_priv, level);
+}
+
static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
{
intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
+ /*
+ * On ILK-IVB the values written to the LP watermark register
+ * latency field must match SSKPD 100%. So do this before any
+ * adjustments are made to the latency values we got from SSKPD.
+ */
+ ilk_setup_wm_lp_cookie(dev_priv);
+
memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
sizeof(dev_priv->wm.pri_latency));
memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
@@ -3366,16 +3391,6 @@ static int ilk_wm_lp_to_level(int wm_lp, const struct ilk_wm_state *pipe_wm)
return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
}
-/* The value we need to program into the WM_LPx latency field */
-static unsigned int ilk_wm_lp_latency(struct drm_i915_private *dev_priv,
- int level)
-{
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- return 2 * level;
- else
- return dev_priv->wm.pri_latency[level];
-}
-
static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
const struct ilk_wm_state *merged,
enum ilk_ddb_partitioning partitioning,
@@ -3400,7 +3415,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* disabled. Doing otherwise could cause underruns.
*/
results->wm_lp[wm_lp - 1] =
- (ilk_wm_lp_latency(dev_priv, level) << WM1_LP_LATENCY_SHIFT) |
+ (dev_priv->wm.ilk_wm_lp_cookie[level] << WM1_LP_LATENCY_SHIFT) |
(r->pri_val << WM1_LP_SR_SHIFT) |
r->cur_val;
--
2.26.2
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 07/10] drm/i915: Remove gen6_check_mch_setup()
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (5 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 06/10] drm/i915: Stash away the original SSKPD latency values Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 08/10] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64() Ville Syrjala
` (6 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
snb_wm_latency_quirk() already boosts up the latency values
so the extra warning about the SSKPD value being insufficient
is now redundant. Drop it.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 2 --
drivers/gpu/drm/i915/intel_pm.c | 15 ---------------
2 files changed, 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bb0656875697..89f5204508fb 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3791,8 +3791,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
-#define MCH_SSKPD_WM0_MASK 0x3f
-#define MCH_SSKPD_WM0_VAL 0xc
/* Clocking configuration register */
#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5db20bf36302..d4cbc16441d7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6982,17 +6982,6 @@ static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
}
}
-static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
-{
- u32 tmp;
-
- tmp = I915_READ(MCH_SSKPD);
- if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
- drm_dbg_kms(&dev_priv->drm,
- "Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
- tmp);
-}
-
static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
{
u32 dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
@@ -7050,8 +7039,6 @@ static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
g4x_disable_trickle_feed(dev_priv);
cpt_init_clock_gating(dev_priv);
-
- gen6_check_mch_setup(dev_priv);
}
static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -7420,8 +7407,6 @@ static void ivb_init_clock_gating(struct drm_i915_private *dev_priv)
if (!HAS_PCH_NOP(dev_priv))
cpt_init_clock_gating(dev_priv);
-
- gen6_check_mch_setup(dev_priv);
}
static void vlv_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.26.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 08/10] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (6 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 07/10] drm/i915: Remove gen6_check_mch_setup() Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 16:50 ` [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
` (5 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We treat SSKPD as a 64 bit register. Add the support macros
to define/extract bits in such registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 57 +++++++++++++++++++++++++--------
1 file changed, 43 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 89f5204508fb..d8bf85db633d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -129,20 +129,35 @@
BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
((__n) < 0 || (__n) > 31))))
-/**
- * REG_GENMASK() - Prepare a continuous u32 bitmask
- * @__high: 0-based high bit
- * @__low: 0-based low bit
- *
- * Local wrapper for GENMASK() to force u32, with compile time checks.
- *
- * @return: Continuous bitmask from @__high to @__low, inclusive.
- */
-#define REG_GENMASK(__high, __low) \
- ((u32)(GENMASK(__high, __low) + \
- BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+#define _REG_GENMASK(__type, __high, __low) \
+ ((__type)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
__is_constexpr(__low) && \
- ((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
+ ((__low) < 0 || \
+ (__high) >= BITS_PER_TYPE(__type) || \
+ (__low) > (__high)))))
+
+/**
+ * REG_GENMASK() - Prepare a continuous u32 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK(__high, __low) _REG_GENMASK(u32, __high, __low)
+
+/**
+ * REG_GENMASK64() - Prepare a continuous u64 bitmask
+ * @__high: 0-based high bit
+ * @__low: 0-based low bit
+ *
+ * Local wrapper for GENMASK() to force u32, with compile time checks.
+ *
+ * @return: Continuous bitmask from @__high to @__low, inclusive.
+ */
+#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
/*
* Local integer constant expression version of is_power_of_2().
@@ -166,6 +181,8 @@
BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
+#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
+
/**
* REG_FIELD_GET() - Extract a u32 bitfield value
* @__mask: shifted mask defining the field's length and position
@@ -176,7 +193,19 @@
*
* @return: Masked and shifted value of the field defined by @__mask in @__val.
*/
-#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
+#define REG_FIELD_GET(__mask, __val) _REG_FIELD_GET(u32, __mask, __val)
+
+/**
+ * REG_FIELD_GET64() - Extract a u64 bitfield value
+ * @__mask: shifted mask defining the field's length and position
+ * @__val: value to extract the bitfield value from
+ *
+ * Local wrapper for FIELD_GET() to force u64 and for consistency with
+ * REG_GENMASK64().
+ *
+ * @return: Masked and shifted value of the field defined by @__mask in @__val.
+ */
+#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
typedef struct {
u32 reg;
--
2.26.2
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^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (7 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 08/10] drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64() Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 20:52 ` kernel test robot
2020-11-15 10:54 ` kernel test robot
2020-10-30 16:50 ` [Intel-gfx] [PATCH 10/10] drm/i915: Polish ilk+ wm regidster bits Ville Syrjala
` (4 subsequent siblings)
13 siblings, 2 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Give names to the SSKPD/MLTR fields, and use the
REG_GENMASK* and REG_FIELD_GET*.
Also drop the bogus non-mirrored SSKP register define.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 25 ++++++++++++-------------
drivers/gpu/drm/i915/intel_pm.c | 24 ++++++++++++------------
2 files changed, 24 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index d8bf85db633d..249bf17bcf9b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3818,8 +3818,17 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define MAD_DIMM_A_SIZE_SHIFT 0
#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
-/* snb MCH registers for priority tuning */
#define MCH_SSKPD _MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5d10)
+#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
+#define SSKPD_WM4_MASK_HSW REG_GENMASK64(40, 32)
+#define SSKPD_WM3_MASK_HSW REG_GENMASK64(28, 20)
+#define SSKPD_WM2_MASK_HSW REG_GENMASK64(19, 12)
+#define SSKPD_WM1_MASK_HSW REG_GENMASK64(11, 4)
+#define SSKPD_OLD_WM0_MASK_HSW REG_GENMASK64(3, 0)
+#define SSKPD_WM3_MASK_SNB REG_GENMASK(29, 24)
+#define SSKPD_WM2_MASK_SNB REG_GENMASK(21, 16)
+#define SSKPD_WM1_MASK_SNB REG_GENMASK(13, 8)
+#define SSKPD_WM0_MASK_SNB REG_GENMASK(5, 0)
/* Clocking configuration register */
#define CLKCFG _MMIO(MCHBAR_MIRROR_BASE + 0xc00)
@@ -6496,19 +6505,9 @@ enum {
/* Memory latency timer register */
#define MLTR_ILK _MMIO(0x11222)
-#define MLTR_WM1_SHIFT 0
-#define MLTR_WM2_SHIFT 8
/* the unit of memory self-refresh latency time is 0.5us */
-#define ILK_SRLT_MASK 0x3f
-
-
-/* the address where we get all kinds of latency value */
-#define SSKPD _MMIO(0x5d10)
-#define SSKPD_WM_MASK 0x3f
-#define SSKPD_WM0_SHIFT 0
-#define SSKPD_WM1_SHIFT 8
-#define SSKPD_WM2_SHIFT 16
-#define SSKPD_WM3_SHIFT 24
+#define MLTR_WM2_MASK REG_GENMASK(13, 8)
+#define MLTR_WM1_MASK REG_GENMASK(5, 0)
/*
* The two pipe frame counter registers are not synchronized, so
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d4cbc16441d7..f29fac94c935 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2933,27 +2933,27 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
u64 sskpd = intel_uncore_read64(uncore, MCH_SSKPD);
- wm[0] = (sskpd >> 56) & 0xFF;
+ wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
if (wm[0] == 0)
- wm[0] = sskpd & 0xF;
- wm[1] = (sskpd >> 4) & 0xFF;
- wm[2] = (sskpd >> 12) & 0xFF;
- wm[3] = (sskpd >> 20) & 0x1FF;
- wm[4] = (sskpd >> 32) & 0x1FF;
+ wm[0] = REG_FIELD_GET64(SSKPD_OLD_WM0_MASK_HSW, sskpd);
+ wm[1] = REG_FIELD_GET64(SSKPD_WM1_MASK_HSW, sskpd);
+ wm[2] = REG_FIELD_GET64(SSKPD_WM2_MASK_HSW, sskpd);
+ wm[3] = REG_FIELD_GET64(SSKPD_WM3_MASK_HSW, sskpd);
+ wm[4] = REG_FIELD_GET64(SSKPD_WM4_MASK_HSW, sskpd);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 sskpd = intel_uncore_read(uncore, MCH_SSKPD);
- wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
- wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
- wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
- wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
+ wm[0] = REG_FIELD_GET(SSKPD_WM0_MASK_SNB, sskpd);
+ wm[1] = REG_FIELD_GET(SSKPD_WM1_MASK_SNB, sskpd);
+ wm[2] = REG_FIELD_GET(SSKPD_WM2_MASK_SNB, sskpd);
+ wm[3] = REG_FIELD_GET(SSKPD_WM3_MASK_SNB, sskpd);
} else if (INTEL_GEN(dev_priv) >= 5) {
u32 mltr = intel_uncore_read(uncore, MLTR_ILK);
/* ILK primary LP0 latency is 700 ns */
wm[0] = 7;
- wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
- wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
+ wm[1] = REG_FIELD_GET(MLTR_WM1_MASK, mltr);
+ wm[2] = REG_FIELD_GET(MLTR_WM2_MASK, mltr);
} else {
MISSING_CASE(INTEL_DEVID(dev_priv));
}
--
2.26.2
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines
2020-10-30 16:50 ` [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
@ 2020-10-30 20:52 ` kernel test robot
2020-11-15 10:54 ` kernel test robot
1 sibling, 0 replies; 17+ messages in thread
From: kernel test robot @ 2020-10-30 20:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 29354 bytes --]
Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.10-rc1 next-20201030]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-ilk-wm-cleanups/20201031-005212
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-r002-20201030 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/85b64f8c6a46ef8a0a7f4969c508d4272a940a83
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-ilk-wm-cleanups/20201031-005212
git checkout 85b64f8c6a46ef8a0a7f4969c508d4272a940a83
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All error/warnings (new ones prefixed by >>):
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:50:19: note: in expansion of macro '__bf_shf'
50 | ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:50:19: note: in expansion of macro '__bf_shf'
50 | ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:50:16: warning: right shift count is negative [-Wshift-count-negative]
50 | ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:52:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
52 | BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:52:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
52 | BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
--
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:21: note: in expansion of macro '__bf_shf'
55 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:21: note: in expansion of macro '__bf_shf'
55 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:55:18: warning: left shift count is negative [-Wshift-count-negative]
55 | (1ULL << __bf_shf(_mask))); \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:35:22: warning: left shift count >= width of type [-Wshift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/bits.h:36:11: warning: right shift count is negative [-Wshift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
..
vim +/__compiletime_assert_615 +319 include/linux/compiler_types.h
eb5c2d4b45e3d2d Will Deacon 2020-07-21 305
eb5c2d4b45e3d2d Will Deacon 2020-07-21 306 #define _compiletime_assert(condition, msg, prefix, suffix) \
eb5c2d4b45e3d2d Will Deacon 2020-07-21 307 __compiletime_assert(condition, msg, prefix, suffix)
eb5c2d4b45e3d2d Will Deacon 2020-07-21 308
eb5c2d4b45e3d2d Will Deacon 2020-07-21 309 /**
eb5c2d4b45e3d2d Will Deacon 2020-07-21 310 * compiletime_assert - break build and emit msg if condition is false
eb5c2d4b45e3d2d Will Deacon 2020-07-21 311 * @condition: a compile-time constant condition to check
eb5c2d4b45e3d2d Will Deacon 2020-07-21 312 * @msg: a message to emit if condition is false
eb5c2d4b45e3d2d Will Deacon 2020-07-21 313 *
eb5c2d4b45e3d2d Will Deacon 2020-07-21 314 * In tradition of POSIX assert, this macro will break the build if the
eb5c2d4b45e3d2d Will Deacon 2020-07-21 315 * supplied condition is *false*, emitting the supplied error message if the
eb5c2d4b45e3d2d Will Deacon 2020-07-21 316 * compiler has support to do so.
eb5c2d4b45e3d2d Will Deacon 2020-07-21 317 */
eb5c2d4b45e3d2d Will Deacon 2020-07-21 318 #define compiletime_assert(condition, msg) \
eb5c2d4b45e3d2d Will Deacon 2020-07-21 @319 _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
eb5c2d4b45e3d2d Will Deacon 2020-07-21 320
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
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_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines
2020-10-30 16:50 ` [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
2020-10-30 20:52 ` kernel test robot
@ 2020-11-15 10:54 ` kernel test robot
1 sibling, 0 replies; 17+ messages in thread
From: kernel test robot @ 2020-11-15 10:54 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: kbuild-all
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Hi Ville,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm-intel/for-linux-next]
[also build test ERROR on drm-tip/drm-tip v5.10-rc3 next-20201113]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-ilk-wm-cleanups/20201031-222959
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-randconfig-a003-20201031 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
reproduce (this is a W=1 build):
# https://github.com/0day-ci/linux/commit/c5a60152af62d42e7f7ab2525073c7d7f74a8e7c
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Ville-Syrjala/drm-i915-ilk-wm-cleanups/20201031-222959
git checkout c5a60152af62d42e7f7ab2525073c7d7f74a8e7c
# save the attached .config to linux build tree
make W=1 ARCH=i386
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
In file included from <command-line>:
drivers/gpu/drm/i915/intel_pm.c: In function 'intel_read_wm_latency':
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:46:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
46 | BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:46:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
46 | BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:48:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
48 | BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:48:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
48 | BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:50:19: note: in expansion of macro '__bf_shf'
50 | ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:50:19: note: in expansion of macro '__bf_shf'
50 | ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:50:16: error: right shift count is negative [-Werror=shift-count-negative]
50 | ~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:49:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
49 | BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:52:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
52 | BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:52:3: note: in expansion of macro 'BUILD_BUG_ON_MSG'
52 | BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
| ^~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:21: note: in expansion of macro '__bf_shf'
55 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:21: note: in expansion of macro '__bf_shf'
55 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bitfield.h:55:18: error: left shift count is negative [-Werror=shift-count-negative]
55 | (1ULL << __bf_shf(_mask))); \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:21: note: in expansion of macro '__bf_shf'
55 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
>> include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
36 | (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:21: note: in expansion of macro '__bf_shf'
55 | (1ULL << __bf_shf(_mask))); \
| ^~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
include/linux/bits.h:38:31: note: in expansion of macro '__GENMASK'
38 | (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro 'GENMASK'
133 | ((__type)(GENMASK(__high, __low) + \
| ^~~~~~~
drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro '_REG_GENMASK'
160 | #define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
| ^~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro 'REG_GENMASK64'
3822 | #define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
| ^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro 'SSKPD_NEW_WM0_MASK_HSW'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:55:18: error: left shift count is negative [-Werror=shift-count-negative]
55 | (1ULL << __bf_shf(_mask))); \
| ^~
include/linux/compiler_types.h:299:9: note: in definition of macro '__compiletime_assert'
299 | if (!(condition)) \
| ^~~~~~~~~
include/linux/compiler_types.h:319:2: note: in expansion of macro '_compiletime_assert'
319 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
| ^~~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:39:37: note: in expansion of macro 'compiletime_assert'
39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
| ^~~~~~~~~~~~~~~~~~
include/linux/build_bug.h:50:2: note: in expansion of macro 'BUILD_BUG_ON_MSG'
50 | BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
| ^~~~~~~~~~~~~~~~
include/linux/build_bug.h:21:2: note: in expansion of macro 'BUILD_BUG_ON'
21 | BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
| ^~~~~~~~~~~~
include/linux/bitfield.h:54:3: note: in expansion of macro '__BUILD_BUG_ON_NOT_POWER_OF_2'
54 | __BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/bitfield.h:108:3: note: in expansion of macro '__BF_FIELD_CHECK'
108 | __BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
| ^~~~~~~~~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro 'FIELD_GET'
184 | #define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
| ^~~~~~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
In file included from drivers/gpu/drm/i915/intel_wakeref.h:11,
from drivers/gpu/drm/i915/intel_runtime_pm.h:13,
from drivers/gpu/drm/i915/display/intel_display_power.h:10,
from drivers/gpu/drm/i915/display/intel_bw.h:12,
from drivers/gpu/drm/i915/intel_pm.c:36:
include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
35 | (((~UL(0)) - (UL(1) << (l)) + 1) & \
| ^~
include/linux/bitfield.h:109:30: note: in definition of macro 'FIELD_GET'
109 | (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \
| ^~~~~
drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro '_REG_FIELD_GET'
208 | #define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
| ^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro 'REG_FIELD_GET64'
2936 | wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
| ^~~~~~~~~~~~~~~
vim +35 include/linux/bits.h
295bcca84916cb5 Rikard Falkeborn 2020-04-06 33
295bcca84916cb5 Rikard Falkeborn 2020-04-06 34 #define __GENMASK(h, l) \
95b980d62d52c4c Masahiro Yamada 2019-07-16 @35 (((~UL(0)) - (UL(1) << (l)) + 1) & \
95b980d62d52c4c Masahiro Yamada 2019-07-16 @36 (~UL(0) >> (BITS_PER_LONG - 1 - (h))))
295bcca84916cb5 Rikard Falkeborn 2020-04-06 37 #define GENMASK(h, l) \
295bcca84916cb5 Rikard Falkeborn 2020-04-06 38 (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
8bd9cb51daac893 Will Deacon 2018-06-19 39
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
[-- Attachment #2: .config.gz --]
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_______________________________________________
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH 10/10] drm/i915: Polish ilk+ wm regidster bits
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (8 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 09/10] drm/i915: Clean up SSKPD/MLTR defines Ville Syrjala
@ 2020-10-30 16:50 ` Ville Syrjala
2020-10-30 17:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ilk+ wm cleanups Patchwork
` (3 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjala @ 2020-10-30 16:50 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Use REG_GENMASK() & co. for ilk+ watermarm registers.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../drm/i915/display/intel_display_debugfs.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 41 +++++++------
drivers/gpu/drm/i915/intel_pm.c | 59 +++++++++----------
3 files changed, 50 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index cfb4c1474982..3ee29a77eeba 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -152,7 +152,7 @@ static int i915_sr_status(struct seq_file *m, void *unused)
if (INTEL_GEN(dev_priv) >= 9)
/* no global SR status; inspect per-plane WM */;
else if (HAS_PCH_SPLIT(dev_priv))
- sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM1_LP_SR_EN;
+ sr_enabled = intel_de_read(dev_priv, WM1_LP_ILK) & WM_LP_ENABLE;
else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
IS_I945G(dev_priv) || IS_I945GM(dev_priv))
sr_enabled = intel_de_read(dev_priv, FW_BLC_SELF) & FW_BLC_SELF_EN;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 249bf17bcf9b..cdcc57452828 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6475,33 +6475,32 @@ enum {
#define _WM0_PIPEC_IVB 0x45200
#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \
_WM0_PIPEB_ILK, _WM0_PIPEC_IVB)
-#define WM0_PIPE_PLANE_MASK (0xffff << 16)
-#define WM0_PIPE_PLANE_SHIFT 16
-#define WM0_PIPE_SPRITE_MASK (0xff << 8)
-#define WM0_PIPE_SPRITE_SHIFT 8
-#define WM0_PIPE_CURSOR_MASK (0xff)
+#define WM0_PIPE_PRIMARY_MASK REG_GENMASK(23, 16)
+#define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8)
+#define WM0_PIPE_CURSOR_MASK REG_GENMASK(5, 0)
+#define WM0_PIPE_PRIMARY(x) REG_FIELD_PREP(WM0_PIPE_PRIMARY_MASK, (x))
+#define WM0_PIPE_SPRITE(x) REG_FIELD_PREP(WM0_PIPE_SPRITE_MASK, (x))
+#define WM0_PIPE_CURSOR(x) REG_FIELD_PREP(WM0_PIPE_CURSOR_MASK, (x))
#define WM1_LP_ILK _MMIO(0x45108)
-#define WM1_LP_SR_EN (1 << 31)
-#define WM1_LP_LATENCY_SHIFT 24
-#define WM1_LP_LATENCY_MASK (0x7f << 24)
-#define WM1_LP_FBC_MASK (0xf << 20)
-#define WM1_LP_FBC_SHIFT 20
-#define WM1_LP_FBC_SHIFT_BDW 19
-#define WM1_LP_SR_MASK (0x7ff << 8)
-#define WM1_LP_SR_SHIFT 8
-#define WM1_LP_CURSOR_MASK (0xff)
#define WM2_LP_ILK _MMIO(0x4510c)
-#define WM2_LP_EN (1 << 31)
#define WM3_LP_ILK _MMIO(0x45110)
-#define WM3_LP_EN (1 << 31)
+#define WM_LP_ENABLE REG_BIT(31)
+#define WM_LP_LATENCY_MASK REG_GENMASK(30, 24)
+#define WM_LP_FBC_MASK_BDW REG_GENMASK(23, 19)
+#define WM_LP_FBC_MASK_ILK REG_GENMASK(23, 20)
+#define WM_LP_PRIMARY_MASK REG_GENMASK(18, 8)
+#define WM_LP_CURSOR_MASK REG_GENMASK(7, 0)
+#define WM_LP_LATENCY(x) REG_FIELD_PREP(WM_LP_LATENCY_MASK, (x))
+#define WM_LP_FBC_BDW(x) REG_FIELD_PREP(WM_LP_FBC_MASK_BDW, (x))
+#define WM_LP_FBC_ILK(x) REG_FIELD_PREP(WM_LP_FBC_MASK_ILK, (x))
+#define WM_LP_PRIMARY(x) REG_FIELD_PREP(WM_LP_PRIMARY_MASK, (x))
+#define WM_LP_CURSOR(x) REG_FIELD_PREP(WM_LP_CURSOR_MASK, (x))
#define WM1S_LP_ILK _MMIO(0x45120)
#define WM2S_LP_IVB _MMIO(0x45124)
#define WM3S_LP_IVB _MMIO(0x45128)
-#define WM1S_LP_EN (1 << 31)
-
-#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
- (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
- ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
+#define WM_LP_SPRITE_ENABLE REG_BIT(31) /* ilk/snb WM1 only */
+#define WM_LP_SPRITE_MASK REG_GENMASK(10, 0)
+#define WM_LP_SPRITE(x) REG_FIELD_PREP(WM_LP_SPRITE_MASK, (x))
/* Memory latency timer register */
#define MLTR_ILK _MMIO(0x11222)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index f29fac94c935..b2bfe66da82d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3415,29 +3415,28 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
* disabled. Doing otherwise could cause underruns.
*/
results->wm_lp[wm_lp - 1] =
- (dev_priv->wm.ilk_wm_lp_cookie[level] << WM1_LP_LATENCY_SHIFT) |
- (r->pri_val << WM1_LP_SR_SHIFT) |
- r->cur_val;
+ WM_LP_LATENCY(dev_priv->wm.ilk_wm_lp_cookie[level]) |
+ WM_LP_PRIMARY(r->pri_val) |
+ WM_LP_CURSOR(r->cur_val);
if (r->enable)
- results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
+ results->wm_lp[wm_lp - 1] |= WM_LP_ENABLE;
if (INTEL_GEN(dev_priv) >= 8)
- results->wm_lp[wm_lp - 1] |=
- r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
+ results->wm_lp[wm_lp - 1] |= WM_LP_FBC_BDW(r->fbc_val);
else
- results->wm_lp[wm_lp - 1] |=
- r->fbc_val << WM1_LP_FBC_SHIFT;
+ results->wm_lp[wm_lp - 1] |= WM_LP_FBC_ILK(r->fbc_val);
+
+ results->wm_lp_spr[wm_lp - 1] = WM_LP_SPRITE(r->spr_val);
/*
- * Always set WM1S_LP_EN when spr_val != 0, even if the
+ * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the
* level is disabled. Doing otherwise could cause underruns.
*/
- if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
+ if (INTEL_GEN(dev_priv) < 7 && r->spr_val) {
drm_WARN_ON(&dev_priv->drm, wm_lp != 1);
- results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
- } else
- results->wm_lp_spr[wm_lp - 1] = r->spr_val;
+ results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;
+ }
}
/* LP0 register values */
@@ -3449,9 +3448,9 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv,
continue;
results->wm_pipe[pipe] =
- (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
- (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
- r->cur_val;
+ WM0_PIPE_PRIMARY(r->pri_val) |
+ WM0_PIPE_SPRITE(r->spr_val) |
+ WM0_PIPE_CURSOR(r->cur_val);
}
}
@@ -3543,24 +3542,24 @@ static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
struct ilk_wm_values *previous = &dev_priv->wm.ilk;
bool changed = false;
- if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
- previous->wm_lp[2] &= ~WM1_LP_SR_EN;
+ if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM_LP_ENABLE) {
+ previous->wm_lp[2] &= ~WM_LP_ENABLE;
I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
changed = true;
}
- if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
- previous->wm_lp[1] &= ~WM1_LP_SR_EN;
+ if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM_LP_ENABLE) {
+ previous->wm_lp[1] &= ~WM_LP_ENABLE;
I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
changed = true;
}
- if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
- previous->wm_lp[0] &= ~WM1_LP_SR_EN;
+ if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM_LP_ENABLE) {
+ previous->wm_lp[0] &= ~WM_LP_ENABLE;
I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
changed = true;
}
/*
- * Don't touch WM1S_LP_EN here.
+ * Don't touch WM_LP_SPRITE_EN here.
* Doing so could cause underruns.
*/
@@ -6315,9 +6314,9 @@ static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
* multiple pipes are active.
*/
active->wm[0].enable = true;
- active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
- active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
- active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
+ active->wm[0].pri_val = REG_FIELD_GET(WM0_PIPE_PRIMARY_MASK, tmp);
+ active->wm[0].spr_val = REG_FIELD_GET(WM0_PIPE_SPRITE_MASK, tmp);
+ active->wm[0].cur_val = REG_FIELD_GET(WM0_PIPE_CURSOR_MASK, tmp);
} else {
int level, max_level = ilk_wm_max_level(dev_priv);
@@ -6738,12 +6737,12 @@ void vlv_wm_sanitize(struct drm_i915_private *dev_priv)
*/
static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
{
- I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
- I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
- I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
+ I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM_LP_ENABLE);
+ I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM_LP_ENABLE);
+ I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM_LP_ENABLE);
/*
- * Don't touch WM1S_LP_EN here.
+ * Don't touch WM_LP_SPRITE_ENABLE here.
* Doing so could cause underruns.
*/
}
--
2.26.2
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ilk+ wm cleanups
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (9 preceding siblings ...)
2020-10-30 16:50 ` [Intel-gfx] [PATCH 10/10] drm/i915: Polish ilk+ wm regidster bits Ville Syrjala
@ 2020-10-30 17:43 ` Patchwork
2020-10-30 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-10-30 17:43 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: ilk+ wm cleanups
URL : https://patchwork.freedesktop.org/series/83289/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3a6a0cd6f2b drm/i915: s/USHRT_MAX/U16_MAX/
0a33e58a3709 drm/i915: Shrink ilk-bdw wm storage by using u16
2fd87c0096c8 drm/i915: Rename ilk watermark structs/enums
4dfe713bb6f6 drm/i915: s/dev_priv->wm.hw/&dev_priv->wm.ilk/
e2474971c9a4 drm/i915: s/ilk_pipe_wm/ilk_wm_state/
8b27740a8cff drm/i915: Stash away the original SSKPD latency values
75df3bb251fb drm/i915: Remove gen6_check_mch_setup()
cd66098043f8 drm/i915: Add REG_GENMASK64() and REG_FIELD_GET64()
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__type' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_reg.h:132:
+#define _REG_GENMASK(__type, __high, __low) \
+ ((__type)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || \
+ (__high) >= BITS_PER_TYPE(__type) || \
+ (__low) > (__high)))))
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__high' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_reg.h:132:
+#define _REG_GENMASK(__type, __high, __low) \
+ ((__type)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || \
+ (__high) >= BITS_PER_TYPE(__type) || \
+ (__low) > (__high)))))
-:22: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__low' - possible side-effects?
#22: FILE: drivers/gpu/drm/i915/i915_reg.h:132:
+#define _REG_GENMASK(__type, __high, __low) \
+ ((__type)(GENMASK(__high, __low) + \
+ BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
+ __is_constexpr(__low) && \
+ ((__low) < 0 || \
+ (__high) >= BITS_PER_TYPE(__type) || \
+ (__low) > (__high)))))
total: 0 errors, 0 warnings, 3 checks, 65 lines checked
b4636d40be70 drm/i915: Clean up SSKPD/MLTR defines
edaa7edda21c drm/i915: Polish ilk+ wm regidster bits
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: ilk+ wm cleanups
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (10 preceding siblings ...)
2020-10-30 17:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ilk+ wm cleanups Patchwork
@ 2020-10-30 18:11 ` Patchwork
2020-10-30 18:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
2020-10-30 22:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-10-30 18:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 30753 bytes --]
== Series Details ==
Series: drm/i915: ilk+ wm cleanups
URL : https://patchwork.freedesktop.org/series/83289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9229 -> Patchwork_18817
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/index.html
New tests
---------
New tests have been introduced between CI_DRM_9229 and Patchwork_18817:
### New CI tests (1) ###
* boot:
- Statuses : 40 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18817 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@core_hotunplug@unbind-rebind:
- fi-tgl-u2: [PASS][1] -> [DMESG-WARN][2] ([i915#1982])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-tgl-u2/igt@core_hotunplug@unbind-rebind.html
* igt@i915_module_load@reload:
- fi-bxt-dsi: [PASS][3] -> [DMESG-WARN][4] ([i915#1635] / [i915#1982])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-bxt-dsi/igt@i915_module_load@reload.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-bxt-dsi/igt@i915_module_load@reload.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-byt-j1900: [PASS][5] -> [DMESG-WARN][6] ([i915#1982])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-byt-j1900/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-atomic:
- fi-icl-u2: [PASS][7] -> [DMESG-WARN][8] ([i915#1982])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-icl-u2/igt@kms_cursor_legacy@basic-flip-before-cursor-atomic.html
* igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1:
- fi-kbl-soraka: [PASS][9] -> [FAIL][10] ([i915#2122])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-kbl-soraka/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-kbl-soraka/igt@kms_flip@basic-flip-vs-wf_vblank@a-edp1.html
#### Possible fixes ####
* igt@i915_module_load@reload:
- fi-byt-j1900: [DMESG-WARN][11] ([i915#1982]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-byt-j1900/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-byt-j1900/igt@i915_module_load@reload.html
* igt@i915_selftest@live@active:
- {fi-ehl-1}: [INCOMPLETE][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-ehl-1/igt@i915_selftest@live@active.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-ehl-1/igt@i915_selftest@live@active.html
* igt@i915_selftest@live@execlists:
- fi-kbl-x1275: [INCOMPLETE][15] ([i915#794]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-kbl-x1275/igt@i915_selftest@live@execlists.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-kbl-x1275/igt@i915_selftest@live@execlists.html
* igt@kms_busy@basic@flip:
- {fi-kbl-7560u}: [DMESG-WARN][17] ([i915#1982]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-kbl-7560u/igt@kms_busy@basic@flip.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-kbl-7560u/igt@kms_busy@basic@flip.html
#### Warnings ####
* igt@core_hotunplug@unbind-rebind:
- fi-icl-u2: [DMESG-WARN][19] ([i915#1982] / [i915#289]) -> [DMESG-WARN][20] ([i915#289])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/fi-icl-u2/igt@core_hotunplug@unbind-rebind.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
[i915#794]: https://gitlab.freedesktop.org/drm/intel/issues/794
Participating hosts (45 -> 40)
------------------------------
Missing (5): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_9229 -> Patchwork_18817
CI-20190529: 20190529
CI_DRM_9229: 4abde8e3625d7249799c3e1cdeac1b2aa3ad3edb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18817: edaa7edda21c8d60b7772330048faddea456f26b @ git://anongit.freedesktop.org/gfx-ci/linux
== Kernel 32bit build ==
Warning: Kernel 32bit buildtest failed:
https://intel-gfx-ci.01.org/Patchwork_18817/build_32bit.log
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_pm.o
In file included from <command-line>:
drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_read_wm_latency’:
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:46:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:46:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:48:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:48:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:50:19: note: in expansion of macro ‘__bf_shf’
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
^~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:50:19: note: in expansion of macro ‘__bf_shf’
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
^~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:50:16: error: right shift count is negative [-Werror=shift-count-negative]
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:52:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/index.html
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^ permalink raw reply [flat|nested] 17+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915: ilk+ wm cleanups
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (11 preceding siblings ...)
2020-10-30 18:11 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-10-30 18:11 ` Patchwork
2020-10-30 22:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-10-30 18:11 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: ilk+ wm cleanups
URL : https://patchwork.freedesktop.org/series/83289/
State : warning
== Summary ==
CALL scripts/checksyscalls.sh
CALL scripts/atomic/check-atomics.sh
CHK include/generated/compile.h
CC [M] drivers/gpu/drm/i915/intel_pm.o
In file included from <command-line>:
drivers/gpu/drm/i915/intel_pm.c: In function ‘intel_read_wm_latency’:
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:46:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:46:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(!__builtin_constant_p(_mask), \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:48:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:48:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) == 0, _pfx "mask is zero"); \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:50:19: note: in expansion of macro ‘__bf_shf’
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
^~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:50:19: note: in expansion of macro ‘__bf_shf’
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
^~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:50:16: error: right shift count is negative [-Werror=shift-count-negative]
~((_mask) >> __bf_shf(_mask)) & (_val) : 0, \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:49:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(__builtin_constant_p(_val) ? \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:52:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:36:11: error: right shift count is negative [-Werror=shift-count-negative]
(~UL(0) >> (BITS_PER_LONG - 1 - (h))))
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:52:3: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG((_mask) > (typeof(_reg))~0ull, \
^~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:3822:34: note: in expansion of macro ‘REG_GENMASK64’
#define SSKPD_NEW_WM0_MASK_HSW REG_GENMASK64(63, 56)
^~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:27: note: in expansion of macro ‘SSKPD_NEW_WM0_MASK_HSW’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~~~~~~~~
./include/linux/bits.h:35:22: error: left shift count >= width of type [-Werror=shift-count-overflow]
(((~UL(0)) - (UL(1) << (l)) + 1) & \
^~
././include/linux/compiler_types.h:299:9: note: in definition of macro ‘__compiletime_assert’
if (!(condition)) \
^~~~~~~~~
././include/linux/compiler_types.h:319:2: note: in expansion of macro ‘_compiletime_assert’
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
^~~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
#define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
^~~~~~~~~~~~~~~~~~
./include/linux/build_bug.h:50:2: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
BUILD_BUG_ON_MSG(condition, "BUILD_BUG_ON failed: " #condition)
^~~~~~~~~~~~~~~~
./include/linux/build_bug.h:21:2: note: in expansion of macro ‘BUILD_BUG_ON’
BUILD_BUG_ON(((n) & ((n) - 1)) != 0)
^~~~~~~~~~~~
./include/linux/bitfield.h:54:3: note: in expansion of macro ‘__BUILD_BUG_ON_NOT_POWER_OF_2’
__BUILD_BUG_ON_NOT_POWER_OF_2((_mask) + \
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/bitfield.h:108:3: note: in expansion of macro ‘__BF_FIELD_CHECK’
__BF_FIELD_CHECK(_mask, _reg, 0U, "FIELD_GET: "); \
^~~~~~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:184:56: note: in expansion of macro ‘FIELD_GET’
#define _REG_FIELD_GET(__type, __mask, __val) ((__type)FIELD_GET(__mask, __val))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:208:40: note: in expansion of macro ‘_REG_FIELD_GET’
#define REG_FIELD_GET64(__mask, __val) _REG_FIELD_GET(u64, __mask, __val)
^~~~~~~~~~~~~~
drivers/gpu/drm/i915/intel_pm.c:2936:11: note: in expansion of macro ‘REG_FIELD_GET64’
wm[0] = REG_FIELD_GET64(SSKPD_NEW_WM0_MASK_HSW, sskpd);
^~~~~~~~~~~~~~~
./include/linux/bits.h:38:31: note: in expansion of macro ‘__GENMASK’
(GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l))
^~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:133:12: note: in expansion of macro ‘GENMASK’
((__type)(GENMASK(__high, __low) + \
^~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:160:38: note: in expansion of macro ‘_REG_GENMASK’
#define REG_GENMASK64(__high, __low) _REG_GENMASK(u64, __high, __low)
^~~~~~~~~~~~
./drivers/gpu/drm/i915/i915_reg.h:
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/build_32bit.log
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: ilk+ wm cleanups
2020-10-30 16:50 [Intel-gfx] [PATCH 00/10] drm/i915: ilk+ wm cleanups Ville Syrjala
` (12 preceding siblings ...)
2020-10-30 18:11 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
@ 2020-10-30 22:21 ` Patchwork
13 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-10-30 22:21 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1.1: Type: text/plain, Size: 17900 bytes --]
== Series Details ==
Series: drm/i915: ilk+ wm cleanups
URL : https://patchwork.freedesktop.org/series/83289/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_9229_full -> Patchwork_18817_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_18817_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_18817_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_18817_full:
### IGT changes ###
#### Warnings ####
* igt@core_hotunplug@hotrebind-lateclose:
- shard-hsw: [WARN][1] ([i915#2283]) -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-hsw4/igt@core_hotunplug@hotrebind-lateclose.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-hsw2/igt@core_hotunplug@hotrebind-lateclose.html
New tests
---------
New tests have been introduced between CI_DRM_9229_full and Patchwork_18817_full:
### New CI tests (1) ###
* boot:
- Statuses : 200 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_18817_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_create@forked:
- shard-glk: [PASS][3] -> [DMESG-WARN][4] ([i915#118] / [i915#95])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-glk3/igt@gem_exec_create@forked.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-glk7/igt@gem_exec_create@forked.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][5] -> [DMESG-WARN][6] ([i915#1436] / [i915#716])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl6/igt@gen9_exec_parse@allowed-single.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl9/igt@gen9_exec_parse@allowed-single.html
* igt@kms_cursor_crc@pipe-b-cursor-128x128-random:
- shard-skl: [PASS][7] -> [FAIL][8] ([i915#54]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl10/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl8/igt@kms_cursor_crc@pipe-b-cursor-128x128-random.html
* igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge:
- shard-glk: [PASS][9] -> [DMESG-WARN][10] ([i915#1982])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-glk7/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-glk5/igt@kms_cursor_edge_walk@pipe-c-256x256-right-edge.html
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-skl: [PASS][11] -> [DMESG-WARN][12] ([i915#1982]) +6 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl8/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#52] / [i915#54])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-untiled.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#1635] / [i915#1982]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-apl6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-apl4/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-gtt-untiled.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][17] -> [FAIL][18] ([i915#79]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl6/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate@b-edp1:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#2122]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl4/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl2/igt@kms_flip@plain-flip-fb-recreate@b-edp1.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render:
- shard-tglb: [PASS][21] -> [DMESG-WARN][22] ([i915#1982]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-render.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl7/igt@kms_hdr@bpc-switch-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][25] -> [SKIP][26] ([fdo#109441]) +3 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-iclb8/igt@kms_psr@psr2_cursor_render.html
* igt@perf@polling-parameterized:
- shard-glk: [PASS][27] -> [FAIL][28] ([i915#1542])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-glk9/igt@perf@polling-parameterized.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-glk7/igt@perf@polling-parameterized.html
- shard-skl: [PASS][29] -> [FAIL][30] ([i915#1542])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl1/igt@perf@polling-parameterized.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl10/igt@perf@polling-parameterized.html
#### Possible fixes ####
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-hsw: [FAIL][31] -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-hsw4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-hsw2/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* {igt@kms_async_flips@async-flip-with-page-flip-events}:
- shard-apl: [FAIL][33] ([i915#1635] / [i915#2521]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-apl4/igt@kms_async_flips@async-flip-with-page-flip-events.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-apl2/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@edp-1-pipe-b:
- shard-skl: [DMESG-WARN][35] ([i915#1982]) -> [PASS][36] +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl8/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@edp-1-pipe-b.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels@edp-1-pipe-b.html
* igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding:
- shard-skl: [FAIL][37] ([i915#54]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl7/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl1/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html
* igt@kms_cursor_edge_walk@pipe-d-128x128-bottom-edge:
- shard-tglb: [DMESG-WARN][39] ([i915#1982]) -> [PASS][40] +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-tglb5/igt@kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-tglb1/igt@kms_cursor_edge_walk@pipe-d-128x128-bottom-edge.html
* igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy:
- shard-hsw: [FAIL][41] ([i915#96]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-hsw6/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-hsw1/igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
- shard-glk: [DMESG-WARN][43] ([i915#1982]) -> [PASS][44] +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-glk3/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-glk8/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][45] ([i915#2346]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@blocking-wf_vblank@a-dp1:
- shard-kbl: [DMESG-WARN][47] ([i915#1982]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-kbl4/igt@kms_flip@blocking-wf_vblank@a-dp1.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-kbl7/igt@kms_flip@blocking-wf_vblank@a-dp1.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-kbl: [DMESG-WARN][49] ([i915#180]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-kbl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1:
- shard-skl: [FAIL][51] ([i915#2122]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl10/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@c-edp1.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-skl: [FAIL][53] ([i915#1188]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl4/igt@kms_hdr@bpc-switch-dpms.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence:
- shard-apl: [DMESG-WARN][55] ([i915#1635] / [i915#1982]) -> [PASS][56] +4 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-apl8/igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-apl6/igt@kms_pipe_crc_basic@read-crc-pipe-b-frame-sequence.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][57] ([fdo#108145] / [i915#265]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][59] ([fdo#109441]) -> [PASS][60] +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@perf@non-system-wide-paranoid:
- shard-hsw: [SKIP][61] ([fdo#109271]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-hsw4/igt@perf@non-system-wide-paranoid.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-hsw2/igt@perf@non-system-wide-paranoid.html
* igt@perf@polling-parameterized:
- shard-tglb: [FAIL][63] ([i915#1542]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-tglb5/igt@perf@polling-parameterized.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-tglb1/igt@perf@polling-parameterized.html
#### Warnings ####
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [DMESG-WARN][65] ([i915#1982]) -> [DMESG-FAIL][66] ([i915#1982])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl9/igt@kms_color@pipe-a-ctm-red-to-blue.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl7/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_flip@flip-vs-suspend-interruptible@a-edp1:
- shard-tglb: [DMESG-WARN][67] ([i915#2411]) -> [INCOMPLETE][68] ([i915#1436] / [i915#456])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-tglb7/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-tglb2/igt@kms_flip@flip-vs-suspend-interruptible@a-edp1.html
* igt@kms_flip_tiling@flip-x-tiled:
- shard-skl: [DMESG-WARN][69] ([i915#1982]) -> [DMESG-FAIL][70] ([fdo#108145] / [i915#1982])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-skl9/igt@kms_flip_tiling@flip-x-tiled.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-skl7/igt@kms_flip_tiling@flip-x-tiled.html
* igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
- shard-apl: [FAIL][71] ([fdo#108145] / [i915#1635] / [i915#265]) -> [DMESG-FAIL][72] ([fdo#108145] / [i915#1635] / [i915#1982])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-apl4/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html
* igt@runner@aborted:
- shard-tglb: [FAIL][73] ([i915#2439]) -> ([FAIL][74], [FAIL][75]) ([i915#2248] / [i915#2439])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_9229/shard-tglb1/igt@runner@aborted.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-tglb2/igt@runner@aborted.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/shard-tglb7/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2248]: https://gitlab.freedesktop.org/drm/intel/issues/2248
[i915#2283]: https://gitlab.freedesktop.org/drm/intel/issues/2283
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2411]: https://gitlab.freedesktop.org/drm/intel/issues/2411
[i915#2439]: https://gitlab.freedesktop.org/drm/intel/issues/2439
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
[i915#96]: https://gitlab.freedesktop.org/drm/intel/issues/96
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_9229 -> Patchwork_18817
CI-20190529: 20190529
CI_DRM_9229: 4abde8e3625d7249799c3e1cdeac1b2aa3ad3edb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5830: 12d370cb57e0cfcb781c87ad9e15e68b17a1f41f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_18817: edaa7edda21c8d60b7772330048faddea456f26b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_18817/index.html
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