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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 09/15] drm/i915: Use intel_de_rmw() for DDI clock routing
Date: Mon,  1 Feb 2021 20:33:37 +0200	[thread overview]
Message-ID: <20210201183343.15292-10-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210201183343.15292-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DDI clock routing programming is riddled with shared
registers, forcing us to do a lot of RMW. Switch over to
intel_de_rmw() to make that a bit less obnoxious.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 78 +++++++++---------------
 1 file changed, 28 insertions(+), 50 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index aac85e86d776..7137929f58bd 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3164,7 +3164,6 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
-	u32 val;
 
 	/*
 	 * If we fail this, something went very wrong: first 2 PLLs should be
@@ -3177,17 +3176,12 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)) == 0);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy));
 
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
-	val |= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
-	intel_de_posting_read(dev_priv, DG1_DPCLKA_CFGCR0(phy));
-
-	val &= ~DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
-	intel_de_write(dev_priv, DG1_DPCLKA_CFGCR0(phy), val);
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3199,8 +3193,8 @@ static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy), 0,
-		     DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
+	intel_de_rmw(dev_priv, DG1_DPCLKA_CFGCR0(phy),
+		     0, DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3212,14 +3206,9 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
-	u32 val;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, reg);
-	drm_WARN_ON(&dev_priv->drm,
-		    (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
-
 	/*
 	 * Even though this register references DDIs, note that we
 	 * want to pass the PHY rather than the port (DDI).  For
@@ -3230,13 +3219,12 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
 	 *   Clock Select chooses the PLL for both DDIA and DDID and
 	 *   drives port A in all cases."
 	 */
-	val &= ~icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy);
-	val |= icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy);
-	intel_de_write(dev_priv, reg, val);
-	intel_de_posting_read(dev_priv, reg);
+	intel_de_rmw(dev_priv, reg,
+		     icl_dpclka_cfgcr0_clk_sel_mask(dev_priv, phy),
+		     icl_dpclka_cfgcr0_clk_sel(dev_priv, pll->info->id, phy));
 
-	val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     icl_dpclka_cfgcr0_clk_off(dev_priv, phy), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3246,14 +3234,11 @@ static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 	i915_reg_t reg = icl_dpclka_cfgcr0_reg(dev_priv, phy);
-	u32 val;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, reg);
-	val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
-
-	intel_de_write(dev_priv, reg, val);
+	intel_de_rmw(dev_priv, reg,
+		     0, icl_dpclka_cfgcr0_clk_off(dev_priv, phy));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3453,25 +3438,22 @@ static void cnl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
-	val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
-	intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
+	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port),
+		     DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port));
 
 	/*
 	 * "This step and the step before must be
 	 *  done with separate register writes."
 	 */
-	val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
-	val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
-	intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
+	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
+		     DPCLKA_CFGCR0_DDI_CLK_OFF(port), 0);
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3481,8 +3463,8 @@ static void cnl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(dev_priv, DPCLKA_CFGCR0,
-		       intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
+	intel_de_rmw(dev_priv, DPCLKA_CFGCR0,
+		     0, DPCLKA_CFGCR0_DDI_CLK_OFF(port));
 }
 
 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
@@ -3491,21 +3473,17 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder,
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 	enum port port = encoder->port;
-	u32 val;
 
 	if (drm_WARN_ON(&dev_priv->drm, !pll))
 		return;
 
 	mutex_lock(&dev_priv->dpll.lock);
 
-	val = intel_de_read(dev_priv, DPLL_CTRL2);
-
-	val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
-		 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
-	val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
-		DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
-
-	intel_de_write(dev_priv, DPLL_CTRL2, val);
+	intel_de_rmw(dev_priv, DPLL_CTRL2,
+		     DPLL_CTRL2_DDI_CLK_OFF(port) |
+		     DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
+		     DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
+		     DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
 
 	mutex_unlock(&dev_priv->dpll.lock);
 }
@@ -3515,8 +3493,8 @@ static void skl_ddi_disable_clock(struct intel_encoder *encoder)
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	enum port port = encoder->port;
 
-	intel_de_write(dev_priv, DPLL_CTRL2,
-		       intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
+	intel_de_rmw(dev_priv, DPLL_CTRL2,
+		     0, DPLL_CTRL2_DDI_CLK_OFF(port));
 }
 
 static void hsw_ddi_enable_clock(struct intel_encoder *encoder,
-- 
2.26.2

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  parent reply	other threads:[~2021-02-01 18:34 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-01 18:33 [Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 01/15] drm/i915: Extract icl_dpclka_cfgcr0_reg() Ville Syrjala
2021-02-01 18:55   ` Lucas De Marchi
2021-02-01 18:33 ` [Intel-gfx] [PATCH 02/15] drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*() Ville Syrjala
2021-02-01 18:59   ` Lucas De Marchi
2021-02-01 18:33 ` [Intel-gfx] [PATCH 03/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs Ville Syrjala
2021-02-01 19:04   ` Lucas De Marchi
2021-02-01 19:09     ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 04/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 19:07   ` Lucas De Marchi
2021-02-01 19:16     ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 05/15] drm/i915: Extract skl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 06/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 07/15] drm/i915: Convert DG1 over to .{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 08/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs Ville Syrjala
2021-02-01 18:33 ` Ville Syrjala [this message]
2021-02-01 18:33 ` [Intel-gfx] [PATCH 10/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers Ville Syrjala
2021-02-01 19:15   ` Lucas De Marchi
2021-02-01 19:21     ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 11/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() Ville Syrjala
2021-02-01 19:15   ` Lucas De Marchi
2021-02-01 18:33 ` [Intel-gfx] [PATCH 12/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 13/15] drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock() Ville Syrjala
2021-02-01 19:22   ` Lucas De Marchi
2021-02-01 19:31     ` Ville Syrjälä
2021-02-01 19:38       ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use .disable_clock() for pll sanitation Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 15/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() Ville Syrjala
2021-02-01 19:28 ` [Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess Lucas De Marchi
2021-02-01 19:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-02-01 19:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-01 20:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-02-01 20:34   ` Ville Syrjälä
2021-02-01 21:08     ` Vudum, Lakshminarayana
2021-02-02  6:05     ` Nautiyal, Ankit K
2021-02-01 21:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-02  2:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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