From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 03/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs
Date: Mon, 1 Feb 2021 20:33:31 +0200 [thread overview]
Message-ID: <20210201183343.15292-4-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20210201183343.15292-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The current code dealing with the clock routing for DDI encoders
is a maintenance nightmare. Let's start cleaning it up by allowing
the encoder to provide vfuncs for enablign/disabling the clock.
We leave them initially unimplemented, falling back to the old
if-else approach.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 29 +++++++++++++++----
.../drm/i915/display/intel_display_types.h | 6 ++++
2 files changed, 29 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 23fbb9013e09..da8bb9a2de0b 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3464,6 +3464,23 @@ static void intel_ddi_clk_disable(struct intel_encoder *encoder)
}
}
+static void intel_ddi_enable_clock(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (encoder->enable_clock)
+ encoder->enable_clock(encoder, crtc_state);
+ else
+ intel_ddi_clk_select(encoder, crtc_state);
+}
+
+static void intel_ddi_disable_clock(struct intel_encoder *encoder)
+{
+ if (encoder->disable_clock)
+ encoder->disable_clock(encoder);
+ else
+ intel_ddi_clk_disable(encoder);
+}
+
static void
icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
const struct intel_crtc_state *crtc_state)
@@ -3708,7 +3725,7 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
* hsw_crtc_enable()->intel_enable_shared_dpll(). We need only
* configure the PLL to port mapping here.
*/
- intel_ddi_clk_select(encoder, crtc_state);
+ intel_ddi_enable_clock(encoder, crtc_state);
/* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
if (!intel_phy_is_tc(dev_priv, phy) ||
@@ -3829,7 +3846,7 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_pps_on(intel_dp);
- intel_ddi_clk_select(encoder, crtc_state);
+ intel_ddi_enable_clock(encoder, crtc_state);
if (!intel_phy_is_tc(dev_priv, phy) ||
dig_port->tc_mode != TC_PORT_TBT_ALT) {
@@ -3904,7 +3921,7 @@ static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
- intel_ddi_clk_select(encoder, crtc_state);
+ intel_ddi_enable_clock(encoder, crtc_state);
drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
@@ -4056,7 +4073,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
dig_port->ddi_io_power_domain,
fetch_and_zero(&dig_port->ddi_io_wakeref));
- intel_ddi_clk_disable(encoder);
+ intel_ddi_disable_clock(encoder);
}
static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
@@ -4079,7 +4096,7 @@ static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
dig_port->ddi_io_power_domain,
fetch_and_zero(&dig_port->ddi_io_wakeref));
- intel_ddi_clk_disable(encoder);
+ intel_ddi_disable_clock(encoder);
intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
}
@@ -4179,7 +4196,7 @@ void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
intel_disable_ddi_buf(encoder, old_crtc_state);
- intel_ddi_clk_disable(encoder);
+ intel_ddi_disable_clock(encoder);
val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 39397748b4b0..085162616112 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -219,6 +219,12 @@ struct intel_encoder {
* encoders have been disabled and suspended.
*/
void (*shutdown)(struct intel_encoder *encoder);
+ /*
+ * Enable/disable the clock to the port.
+ */
+ void (*enable_clock)(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
+ void (*disable_clock)(struct intel_encoder *encoder);
enum hpd_pin hpd_pin;
enum intel_display_power_domain power_domain;
/* for communication with audio component; protected by av_mutex */
--
2.26.2
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next prev parent reply other threads:[~2021-02-01 18:33 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-01 18:33 [Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 01/15] drm/i915: Extract icl_dpclka_cfgcr0_reg() Ville Syrjala
2021-02-01 18:55 ` Lucas De Marchi
2021-02-01 18:33 ` [Intel-gfx] [PATCH 02/15] drm/i915: Extract icl_dpclka_cfgcr0_clk_sel*() Ville Syrjala
2021-02-01 18:59 ` Lucas De Marchi
2021-02-01 18:33 ` Ville Syrjala [this message]
2021-02-01 19:04 ` [Intel-gfx] [PATCH 03/15] drm/i915: Introduce .{enable, disable}_clock() encoder vfuncs Lucas De Marchi
2021-02-01 19:09 ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 04/15] drm/i915: Extract hsw_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 19:07 ` Lucas De Marchi
2021-02-01 19:16 ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 05/15] drm/i915: Extract skl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 06/15] drm/i195: Extract cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 07/15] drm/i915: Convert DG1 over to .{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 08/15] drm/i915: Extract icl+ .{enable, disable}_clock() vfuncs Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 09/15] drm/i915: Use intel_de_rmw() for DDI clock routing Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 10/15] drm/i915: Sprinkle a few missing locks around shared DDI clock registers Ville Syrjala
2021-02-01 19:15 ` Lucas De Marchi
2021-02-01 19:21 ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 11/15] drm/i915: Sprinkle WARN(!pll) into icl/dg1 .clock_enable() Ville Syrjala
2021-02-01 19:15 ` Lucas De Marchi
2021-02-01 18:33 ` [Intel-gfx] [PATCH 12/15] drm/i915: Extract _cnl_ddi_{enable, disable}_clock() Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 13/15] drm/i915: Split alds/rkl from icl_ddi_combo_{enable, disable}_clock() Ville Syrjala
2021-02-01 19:22 ` Lucas De Marchi
2021-02-01 19:31 ` Ville Syrjälä
2021-02-01 19:38 ` Ville Syrjälä
2021-02-01 18:33 ` [Intel-gfx] [PATCH 14/15] drm/i915: Use .disable_clock() for pll sanitation Ville Syrjala
2021-02-01 18:33 ` [Intel-gfx] [PATCH 15/15] drm/i915: Relocate icl_sanitize_encoder_pll_mapping() Ville Syrjala
2021-02-01 19:28 ` [Intel-gfx] [PATCH 00/15] drm/i915: Clean up the DDI clock routing mess Lucas De Marchi
2021-02-01 19:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2021-02-01 19:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-02-01 20:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2021-02-01 20:34 ` Ville Syrjälä
2021-02-01 21:08 ` Vudum, Lakshminarayana
2021-02-02 6:05 ` Nautiyal, Ankit K
2021-02-01 21:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-02-02 2:12 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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