[Intel-gfx] [PATCH v2 47/50] drm/i915/display/adl_p: Implement Wa_22011320316

[Matt Roper <matthew.d.roper@intel.com>]

From: José Roberto de Souza <jose.souza@intel.com>

Implementation details are in the HSD 22011320316, requiring CD clock
to be at least 307MHz to make DC states to work.

Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 21 ++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h            |  7 +++++++
 2 files changed, 27 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4c441b359d7f..a1fafd3573e8 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1257,6 +1257,21 @@ static const struct intel_cdclk_vals rkl_cdclk_table[] = {
 	{}
 };
 
+static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
+	{ .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
+	{ .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
+	{ .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
+
+	{ .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
+	{ .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
+	{ .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+
+	{ .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
+	{ .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
+	{ .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
+	{}
+};
+
 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
 	{ .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
 	{ .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
@@ -2836,7 +2851,11 @@ void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
 		dev_priv->display.modeset_calc_cdclk = bxt_modeset_calc_cdclk;
 		dev_priv->display.calc_voltage_level = tgl_calc_voltage_level;
-		dev_priv->cdclk.table = adlp_cdclk_table;
+		/* Wa_22011320316:adlp[a0] */
+		if (IS_ADLP_REVID(dev_priv, ADLP_REVID_A0, ADLP_REVID_A0))
+			dev_priv->cdclk.table = adlp_a_step_cdclk_table;
+		else
+			dev_priv->cdclk.table = adlp_cdclk_table;
 	} else if (IS_ROCKETLAKE(dev_priv)) {
 		dev_priv->display.set_cdclk = bxt_set_cdclk;
 		dev_priv->display.bw_calc_min_cdclk = skl_bw_calc_min_cdclk;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 68e216f5e0bb..b89b27b94e22 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1598,6 +1598,13 @@ tgl_stepping_get(struct drm_i915_private *dev_priv)
 	 tgl_stepping_get(p)->gt_stepping >= (since) && \
 	 tgl_stepping_get(p)->gt_stepping <= (until))
 
+#define ADLP_REVID_A0		0x0
+#define ADLP_REVID_B0		0x4
+#define ADLP_REVID_C0		0x8
+
+#define IS_ADLP_REVID(p, since, until) \
+	(IS_ALDERLAKE_P(p) && IS_REVID(p, since, until))
+
 #define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
 #define IS_GEN9_LP(dev_priv)	(IS_GEN(dev_priv, 9) && IS_LP(dev_priv))
 #define IS_GEN9_BC(dev_priv)	(IS_GEN(dev_priv, 9) && !IS_LP(dev_priv))
-- 
2.25.4

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