From: Matt Roper <matthew.d.roper@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: me@freedesktop.org
Subject: [Intel-gfx] [PATCH v2 06/50] drm/i915/xelpd: Handle new location of outputs D and E
Date: Thu, 25 Mar 2021 11:06:36 -0700 [thread overview]
Message-ID: <20210325180720.401410-7-matthew.d.roper@intel.com> (raw)
In-Reply-To: <20210325180720.401410-1-matthew.d.roper@intel.com>
The DDI naming template for display version 12 went A-C, TC1-TC6. With
XE_LPD, that naming scheme for DDI's has now changed to A-E, TC1-TC4.
The XE_LPD design keeps the register offsets and bitfields relating to
the TC outputs in the same location they were previously. The new "D"
and "E" outputs now take the locations that were previously used by TC5
and TC6 outputs, or what we would have considered to be outputs "H" and
"I" under the legacy lettering scheme.
For the most part everything will just work as long as we initialize the
output with the proper 'enum port' value. However we do need to take
care to pick the correct AUX channel when parsing the VBT (e.g., a
reference to 'AUX D' is actually asking us to use the 8th aux channel,
not the fourth). We should also make sure that our encoders and aux
channels are named appropriately so that it's easier to correlate driver
debug messages with the bspec instructions.
v2:
- Update handling of TGL_TRANS_CLK_SEL_PORT. (Jose)
Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 8 +++++--
drivers/gpu/drm/i915/display/intel_ddi.c | 25 +++++++++++++-------
drivers/gpu/drm/i915/display/intel_display.c | 6 ++++-
drivers/gpu/drm/i915/display/intel_display.h | 8 +++++++
drivers/gpu/drm/i915/display/intel_dp_aux.c | 14 +++++++----
5 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 3d0c035b5e38..6847fb5aff4d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2852,7 +2852,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
aux_ch = AUX_CH_C;
break;
case DP_AUX_D:
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) >= 13)
+ aux_ch = AUX_CH_D_XELPD;
+ else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC3;
else if (IS_DG1(i915) || IS_ROCKETLAKE(i915))
aux_ch = AUX_CH_USBC2;
@@ -2860,7 +2862,9 @@ enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *i915,
aux_ch = AUX_CH_D;
break;
case DP_AUX_E:
- if (IS_ALDERLAKE_S(i915))
+ if (DISPLAY_VER(i915) >= 13)
+ aux_ch = AUX_CH_E_XELPD;
+ else if (IS_ALDERLAKE_S(i915))
aux_ch = AUX_CH_USBC4;
else
aux_ch = AUX_CH_E;
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 953de42e277c..933af861253e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -850,18 +850,19 @@ void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- enum port port = encoder->port;
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
+ u32 val;
if (cpu_transcoder != TRANSCODER_EDP) {
- if (DISPLAY_VER(dev_priv) >= 12)
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TGL_TRANS_CLK_SEL_PORT(port));
+ if (DISPLAY_VER(dev_priv) >= 13)
+ val = TGL_TRANS_CLK_SEL_PORT(phy);
+ else if (DISPLAY_VER(dev_priv) >= 12)
+ val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
else
- intel_de_write(dev_priv,
- TRANS_CLK_SEL(cpu_transcoder),
- TRANS_CLK_SEL_PORT(port));
+ val = TRANS_CLK_SEL_PORT(encoder->port);
+
+ intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
}
}
@@ -4489,7 +4490,13 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder = &dig_port->base;
encoder->devdata = devdata;
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
+ drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
+ DRM_MODE_ENCODER_TMDS,
+ "DDI %c/PHY %c",
+ port_name(port - PORT_D_XELPD + PORT_D),
+ phy_name(phy));
+ } else if (DISPLAY_VER(dev_priv) >= 12) {
enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 17490d29dc13..03d1e0eedaa8 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4206,7 +4206,11 @@ bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
{
- if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
+ if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
+ return PHY_D + port - PORT_D_XELPD;
+ else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
+ return PHY_F + port - PORT_TC1;
+ else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
return PHY_B + port - PORT_TC1;
else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
return PHY_C + port - PORT_TC1;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index f056e19cf559..5b19953840aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -217,6 +217,10 @@ enum port {
PORT_TC5,
PORT_TC6,
+ /* XE_LPD repositions D/E offsets and bitfields */
+ PORT_D_XELPD = PORT_TC5,
+ PORT_E_XELPD,
+
I915_MAX_PORTS
};
@@ -300,6 +304,10 @@ enum aux_ch {
AUX_CH_USBC4,
AUX_CH_USBC5,
AUX_CH_USBC6,
+
+ /* XE_LPD repositions D/E offsets and bitfields */
+ AUX_CH_D_XELPD = AUX_CH_USBC5,
+ AUX_CH_E_XELPD,
};
#define aux_ch_name(a) ((a) + 'A')
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 7e83bc2cc34a..8937561329b1 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -607,8 +607,8 @@ static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
+ case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
+ case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
return DP_AUX_CH_CTL(aux_ch);
default:
MISSING_CASE(aux_ch);
@@ -630,8 +630,8 @@ static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- case AUX_CH_USBC5:
- case AUX_CH_USBC6:
+ case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */
+ case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */
return DP_AUX_CH_DATA(aux_ch, index);
default:
MISSING_CASE(aux_ch);
@@ -685,7 +685,11 @@ void intel_dp_aux_init(struct intel_dp *intel_dp)
drm_dp_aux_init(&intel_dp->aux);
/* Failure to allocate our preferred name is not critical */
- if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
+ if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD)
+ intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s",
+ aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D),
+ encoder->base.name);
+ else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1)
intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s",
aux_ch - AUX_CH_USBC1 + '1',
encoder->base.name);
--
2.25.4
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next prev parent reply other threads:[~2021-03-25 18:07 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 18:06 [Intel-gfx] [PATCH v2 00/50] Introduce Alder Lake-P Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 01/50] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 02/50] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 03/50] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 04/50] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 05/50] drm/i915/xelpd: Support 128k plane stride Matt Roper
2021-03-25 18:06 ` Matt Roper [this message]
2021-03-26 16:45 ` [Intel-gfx] [PATCH v2 06/50] drm/i915/xelpd: Handle new location of outputs D and E Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 07/50] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 08/50] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 09/50] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 10/50] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 11/50] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-03-25 21:06 ` Souza, Jose
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 12/50] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 13/50] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 14/50] drm/i915: Get slice height before computing rc params Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 15/50] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 16/50] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-04-07 12:58 ` Jani Nikula
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 17/50] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 18/50] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 19/50] drm/i915/adl_p: ADL_P device info enabling Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 20/50] drm/i915/adl_p: Add PCH support Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 21/50] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 22/50] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 23/50] drm/i915/adl_p: Load DMC Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 24/50] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 25/50] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 26/50] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-03-26 16:31 ` Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 27/50] drm/i915/adl_p: Handle TC cold Matt Roper
2021-03-26 16:30 ` Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 28/50] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-03-26 16:03 ` Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 29/50] drm/i915/adl_p: Enable modular fia Matt Roper
2021-03-26 16:31 ` Imre Deak
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 30/50] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 31/50] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 32/50] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 33/50] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 34/50] drm/i915/adl_p: MBUS programming Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 35/50] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 36/50] drm/i915/adl_p: Add initial ADL_P Workarounds Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 37/50] drm/i915/adlp: Define GuC/HuC for Alderlake_P Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 38/50] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 39/50] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-03-26 16:18 ` Imre Deak
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 40/50] drm/i915/adl_p: Add PLL Support Matt Roper
2021-03-26 16:25 ` Imre Deak
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 41/50] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 42/50] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 43/50] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 44/50] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 45/50] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 46/50] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 47/50] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 48/50] drm/i915/display/adl_p: Remove CCS support Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 49/50] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 50/50] drm/i915/display/adl_p: Implement PSR changes Matt Roper
2021-03-25 22:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P (rev2) Patchwork
2021-03-25 22:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-25 22:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-03-25 23:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-26 4:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-04-21 11:03 ` [Intel-gfx] [PATCH v2 00/50] Introduce Alder Lake-P Jani Nikula
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