From: Imre Deak <imre.deak@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org, me@freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 26/50] drm/i915/display/tc: Rename safe_mode functions ownership
Date: Fri, 26 Mar 2021 18:31:48 +0200 [thread overview]
Message-ID: <20210326163148.GO2237616@ideak-desk.fi.intel.com> (raw)
In-Reply-To: <20210325180720.401410-27-matthew.d.roper@intel.com>
On Thu, Mar 25, 2021 at 11:06:56AM -0700, Matt Roper wrote:
> From: José Roberto de Souza <jose.souza@intel.com>
>
> When DP_PHY_MODE_STATUS_NOT_SAFE is set, it means that display
> has the control over the TC phy.
> The "not safe" naming is confusing using ownership make it easier
> to read also future platforms will have a new register that does the
> same job as DP_PHY_MODE_STATUS_NOT_SAFE but with the onwership name.
>
> BSpec: 49294
> Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Clinton Taylor <Clinton.A.Taylor@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_tc.c | 35 ++++++++++++-------------
> 1 file changed, 17 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 71b8edafb1c3..c007803cfd30 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -256,8 +256,8 @@ static bool icl_tc_phy_status_complete(struct intel_digital_port *dig_port)
> return val & DP_PHY_MODE_STATUS_COMPLETED(dig_port->tc_phy_fia_idx);
> }
>
> -static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> - bool enable)
> +static bool icl_tc_phy_take_ownership(struct intel_digital_port *dig_port,
> + bool take)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> struct intel_uncore *uncore = &i915->uncore;
> @@ -267,20 +267,20 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia));
> if (val == 0xffffffff) {
> drm_dbg_kms(&i915->drm,
> - "Port %s: PHY in TCCOLD, can't set safe-mode to %s\n",
> - dig_port->tc_port_name, enableddisabled(enable));
> + "Port %s: PHY in TCCOLD, can't %s ownership\n",
> + dig_port->tc_port_name, take ? "take" : "release");
>
> return false;
> }
>
> val &= ~DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
> - if (!enable)
> + if (take)
> val |= DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
>
> intel_uncore_write(uncore,
> PORT_TX_DFLEXDPCSSS(dig_port->tc_phy_fia), val);
>
> - if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
> + if (!take && wait_for(!icl_tc_phy_status_complete(dig_port), 10))
> drm_dbg_kms(&i915->drm,
> "Port %s: PHY complete clear timed out\n",
> dig_port->tc_port_name);
> @@ -288,7 +288,7 @@ static bool icl_tc_phy_set_safe_mode(struct intel_digital_port *dig_port,
> return true;
> }
>
> -static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
> +static bool icl_tc_phy_is_owned(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> struct intel_uncore *uncore = &i915->uncore;
> @@ -303,7 +303,7 @@ static bool icl_tc_phy_is_in_safe_mode(struct intel_digital_port *dig_port)
> return true;
> }
>
> - return !(val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx));
> + return val & DP_PHY_MODE_STATUS_NOT_SAFE(dig_port->tc_phy_fia_idx);
> }
>
> /*
> @@ -329,7 +329,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
> goto out_set_tbt_alt_mode;
> }
>
> - if (!icl_tc_phy_set_safe_mode(dig_port, false) &&
> + if (!icl_tc_phy_take_ownership(dig_port, true) &&
> !drm_WARN_ON(&i915->drm, dig_port->tc_legacy_port))
> goto out_set_tbt_alt_mode;
>
> @@ -348,7 +348,7 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
> if (!(tc_port_live_status_mask(dig_port) & BIT(TC_PORT_DP_ALT))) {
> drm_dbg_kms(&i915->drm, "Port %s: PHY sudden disconnect\n",
> dig_port->tc_port_name);
> - goto out_set_safe_mode;
> + goto out_release_phy;
> }
>
> if (max_lanes < required_lanes) {
> @@ -356,15 +356,15 @@ static void icl_tc_phy_connect(struct intel_digital_port *dig_port,
> "Port %s: PHY max lanes %d < required lanes %d\n",
> dig_port->tc_port_name,
> max_lanes, required_lanes);
> - goto out_set_safe_mode;
> + goto out_release_phy;
> }
>
> dig_port->tc_mode = TC_PORT_DP_ALT;
>
> return;
>
> -out_set_safe_mode:
> - icl_tc_phy_set_safe_mode(dig_port, true);
> +out_release_phy:
> + icl_tc_phy_take_ownership(dig_port, false);
> out_set_tbt_alt_mode:
> dig_port->tc_mode = TC_PORT_TBT_ALT;
> }
> @@ -380,7 +380,7 @@ static void icl_tc_phy_disconnect(struct intel_digital_port *dig_port)
> /* Nothing to do, we never disconnect from legacy mode */
> break;
> case TC_PORT_DP_ALT:
> - icl_tc_phy_set_safe_mode(dig_port, true);
> + icl_tc_phy_take_ownership(dig_port, false);
> dig_port->tc_mode = TC_PORT_TBT_ALT;
> break;
> case TC_PORT_TBT_ALT:
> @@ -401,8 +401,8 @@ static bool icl_tc_phy_is_connected(struct intel_digital_port *dig_port)
> return dig_port->tc_mode == TC_PORT_TBT_ALT;
> }
>
> - if (icl_tc_phy_is_in_safe_mode(dig_port)) {
> - drm_dbg_kms(&i915->drm, "Port %s: PHY still in safe mode\n",
> + if (!icl_tc_phy_is_owned(dig_port)) {
> + drm_dbg_kms(&i915->drm, "Port %s: PHY not owned\n",
> dig_port->tc_port_name);
>
> return false;
> @@ -417,10 +417,9 @@ intel_tc_port_get_current_mode(struct intel_digital_port *dig_port)
> {
> struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> u32 live_status_mask = tc_port_live_status_mask(dig_port);
> - bool in_safe_mode = icl_tc_phy_is_in_safe_mode(dig_port);
> enum tc_port_mode mode;
>
> - if (in_safe_mode ||
> + if (!icl_tc_phy_is_owned(dig_port) ||
> drm_WARN_ON(&i915->drm, !icl_tc_phy_status_complete(dig_port)))
> return TC_PORT_TBT_ALT;
>
> --
> 2.25.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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next prev parent reply other threads:[~2021-03-26 16:31 UTC|newest]
Thread overview: 66+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-25 18:06 [Intel-gfx] [PATCH v2 00/50] Introduce Alder Lake-P Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 01/50] drm/i915/xelpd: add XE_LPD display characteristics Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 02/50] drm/i915/xelpd: Handle proper AUX interrupt bits Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 03/50] drm/i915/xelpd: Enhanced pipe underrun reporting Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 04/50] drm/i915/xelpd: Define plane capabilities Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 05/50] drm/i915/xelpd: Support 128k plane stride Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 06/50] drm/i915/xelpd: Handle new location of outputs D and E Matt Roper
2021-03-26 16:45 ` Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 07/50] drm/i915/xelpd: Add XE_LPD power wells Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 08/50] drm/i915/xelpd: Handle LPSP for XE_LPD Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 09/50] drm/i915/xelpd: Increase maximum watermark lines to 255 Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 10/50] drm/i915/xelpd: Required bandwidth increases when VT-d is active Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 11/50] drm/i915/xelpd: Add Wa_14011503030 Matt Roper
2021-03-25 21:06 ` Souza, Jose
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 12/50] drm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 13/50] drm/i915/xelpd: Support DP1.4 compression BPPs Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 14/50] drm/i915: Get slice height before computing rc params Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 15/50] drm/i915/xelpd: Calculate VDSC RC parameters Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 16/50] drm/i915/xelpd: Add rc_qp_table for rcparams calculation Matt Roper
2021-04-07 12:58 ` Jani Nikula
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 17/50] drm/i915/xelpd: Add VRR guardband for VRR CTL Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 18/50] drm/i915/adl_p: Add PCI Devices IDs Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 19/50] drm/i915/adl_p: ADL_P device info enabling Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 20/50] drm/i915/adl_p: Add PCH support Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 21/50] drm/i915/adl_p: Add dedicated SAGV watermarks Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 22/50] drm/i915/adl_p: Extend PLANE_WM bits for blocks & lines Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 23/50] drm/i915/adl_p: Load DMC Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 24/50] drm/i915/adl_p: Setup ports/phys Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 25/50] drm/i915/adl_p: Add cdclk support for ADL-P Matt Roper
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 26/50] drm/i915/display/tc: Rename safe_mode functions ownership Matt Roper
2021-03-26 16:31 ` Imre Deak [this message]
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 27/50] drm/i915/adl_p: Handle TC cold Matt Roper
2021-03-26 16:30 ` Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 28/50] drm/i915/adl_p: Implement TC sequences Matt Roper
2021-03-26 16:03 ` Imre Deak
2021-03-25 18:06 ` [Intel-gfx] [PATCH v2 29/50] drm/i915/adl_p: Enable modular fia Matt Roper
2021-03-26 16:31 ` Imre Deak
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 30/50] drm/i915/adl_p: Don't config MBUS and DBUF during display initialization Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 31/50] drm/i915/adl_p: Add ddb allocation support Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 32/50] drm/i915: Introduce MBUS relative dbuf offsets Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 33/50] drm/i915: Move intel_modeset_all_pipes() Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 34/50] drm/i915/adl_p: MBUS programming Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 35/50] drm/i915/adl_p: Tx escape clock with DSI Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 36/50] drm/i915/adl_p: Add initial ADL_P Workarounds Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 37/50] drm/i915/adlp: Define GuC/HuC for Alderlake_P Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 38/50] drm/i915/adl_p: Define and use ADL-P specific DP translation tables Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 39/50] drm/i915/adl_p: Enable/disable loadgen sharing Matt Roper
2021-03-26 16:18 ` Imre Deak
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 40/50] drm/i915/adl_p: Add PLL Support Matt Roper
2021-03-26 16:25 ` Imre Deak
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 41/50] drm/i915/bigjoiner: Mode validation with uncompressed pipe joiner Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 42/50] drm/i915/bigjoiner: Avoid dsc_compute_config for uncompressed bigjoiner Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 43/50] drm/i915/bigjoiner: atomic commit changes for uncompressed joiner Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 44/50] drm/i915/adlp: Add PIPE_MISC2 programming Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 45/50] drm/i915/adl_p: Update memory bandwidth parameters Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 46/50] drm/i915/adl_p: Implement Wa_22011091694 Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 47/50] drm/i915/display/adl_p: Implement Wa_22011320316 Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 48/50] drm/i915/display/adl_p: Remove CCS support Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 49/50] drm/i915/perf: Enable OA formats for ADL_P Matt Roper
2021-03-25 18:07 ` [Intel-gfx] [PATCH v2 50/50] drm/i915/display/adl_p: Implement PSR changes Matt Roper
2021-03-25 22:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Introduce Alder Lake-P (rev2) Patchwork
2021-03-25 22:45 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2021-03-25 22:48 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2021-03-25 23:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-03-26 4:33 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-04-21 11:03 ` [Intel-gfx] [PATCH v2 00/50] Introduce Alder Lake-P Jani Nikula
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