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From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs
Date: Tue,  3 May 2022 21:22:25 +0300	[thread overview]
Message-ID: <20220503182242.18797-10-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20220503182242.18797-1-ville.syrjala@linux.intel.com>

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Use the "[CRTC:%d:%s]'/etc. format for some of the modeset debugs
so we know more about what has happened during the modeset state
computation.

Also tweak the connector bpp debug message a bit to make it less
confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 22 +++++++++++++-------
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ac476976dc0b..8d6cbfbaf20d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5040,8 +5040,8 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
 
 	if (bpp < crtc_state->pipe_bpp) {
 		drm_dbg_kms(&i915->drm,
-			    "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
-			    "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
+			    "[CONNECTOR:%d:%s] Limiting display bpp to %d "
+			    "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
 			    connector->base.id, connector->name,
 			    bpp, 3 * info->bpc,
 			    3 * conn_state->max_requested_bpc,
@@ -5691,7 +5691,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 
 		if (!check_single_encoder_cloning(state, crtc, encoder)) {
 			drm_dbg_kms(&i915->drm,
-				    "rejecting invalid cloning configuration\n");
+				    "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
+				    encoder->base.base.id, encoder->base.name);
 			return -EINVAL;
 		}
 
@@ -5732,7 +5733,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		if (ret == -EDEADLK)
 			return ret;
 		if (ret < 0) {
-			drm_dbg_kms(&i915->drm, "Encoder config failure: %d\n", ret);
+			drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
+				    encoder->base.base.id, encoder->base.name, ret);
 			return ret;
 		}
 	}
@@ -5748,15 +5750,18 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 		return ret;
 	if (ret == -EAGAIN) {
 		if (drm_WARN(&i915->drm, !retry,
-			     "loop in pipe configuration computation\n"))
+			     "[CRTC:%d:%s] loop in pipe configuration computation\n",
+			     crtc->base.base.id, crtc->base.name))
 			return -EINVAL;
 
-		drm_dbg_kms(&i915->drm, "CRTC bw constrained, retrying\n");
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
+			    crtc->base.base.id, crtc->base.name);
 		retry = false;
 		goto encoder_retry;
 	}
 	if (ret < 0) {
-		drm_dbg_kms(&i915->drm, "CRTC config failure: %d\n", ret);
+		drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
+			    crtc->base.base.id, crtc->base.name, ret);
 		return ret;
 	}
 
@@ -5767,7 +5772,8 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
 	crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
 		!crtc_state->dither_force_disable;
 	drm_dbg_kms(&i915->drm,
-		    "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
+		    "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
+		    crtc->base.base.id, crtc->base.name,
 		    base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
 
 	return 0;
-- 
2.35.1


  parent reply	other threads:[~2022-05-03 18:23 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 18:22 [Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-05-03 18:22 ` [Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
2022-05-16 12:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-05-16 13:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() Ville Syrjala
2022-05-16 12:29   ` Jani Nikula
2022-05-16 12:29   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT() Ville Syrjala
2022-05-16 12:36   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/ Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` Ville Syrjala [this message]
2022-05-16 12:41   ` [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock() Ville Syrjala
2022-05-04 12:33   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:43     ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params Ville Syrjala
2022-05-04 21:21   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:52     ` Jani Nikula
2022-05-16 12:50   ` [Intel-gfx] [PATCH " Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-05-25 10:53   ` Jani Nikula
2022-05-25 11:28     ` Ville Syrjälä
2022-05-03 18:22 ` [Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier Ville Syrjala
2022-05-25 10:57   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout Ville Syrjala
2022-05-25 10:58   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-05-25 11:03   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 16/26] drm/i915: Make all clock " Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-05-25 11:08   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare() Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-05-25 11:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-05-25 11:24   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL Ville Syrjala
2022-05-25 11:30   ` Jani Nikula
2022-05-25 18:16     ` Matt Roper
2022-05-03 18:22 ` [Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always Ville Syrjala
2022-05-30 12:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 19:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Make fastset not suck and allow seamless M/N changes Patchwork
2022-05-04 15:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2) Patchwork
2022-05-04 15:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3) Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  1:52 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4) Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  3:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-05  9:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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