From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/
Date: Mon, 16 May 2022 15:39:48 +0300 [thread overview]
Message-ID: <87sfp9fy7f.fsf@intel.com> (raw)
In-Reply-To: <20220503182242.18797-9-ville.syrjala@linux.intel.com>
On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename some of the 'pipe_config's to the more modern
> 'crtc_state'.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 62 ++++++++++----------
> 1 file changed, 31 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 4615cf3564eb..ac476976dc0b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5013,10 +5013,10 @@ static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
>
> static int
> compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
> - struct intel_crtc_state *pipe_config)
> + struct intel_crtc_state *crtc_state)
> {
> struct drm_connector *connector = conn_state->connector;
> - struct drm_i915_private *i915 = to_i915(pipe_config->uapi.crtc->dev);
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> const struct drm_display_info *info = &connector->display_info;
> int bpp;
>
> @@ -5038,16 +5038,16 @@ compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
> return -EINVAL;
> }
>
> - if (bpp < pipe_config->pipe_bpp) {
> + if (bpp < crtc_state->pipe_bpp) {
> drm_dbg_kms(&i915->drm,
> "[CONNECTOR:%d:%s] Limiting display bpp to %d instead of "
> "EDID bpp %d, requested bpp %d, max platform bpp %d\n",
> connector->base.id, connector->name,
> bpp, 3 * info->bpc,
> 3 * conn_state->max_requested_bpc,
> - pipe_config->pipe_bpp);
> + crtc_state->pipe_bpp);
>
> - pipe_config->pipe_bpp = bpp;
> + crtc_state->pipe_bpp = bpp;
> }
>
> return 0;
> @@ -5058,7 +5058,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> - struct intel_crtc_state *pipe_config =
> + struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> @@ -5072,7 +5072,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
> else
> bpp = 8*3;
>
> - pipe_config->pipe_bpp = bpp;
> + crtc_state->pipe_bpp = bpp;
>
> /* Clamp display bpp to connector max bpp */
> for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> @@ -5081,7 +5081,7 @@ compute_baseline_pipe_bpp(struct intel_atomic_state *state,
> if (connector_state->crtc != &crtc->base)
> continue;
>
> - ret = compute_sink_pipe_bpp(connector_state, pipe_config);
> + ret = compute_sink_pipe_bpp(connector_state, crtc_state);
> if (ret)
> return ret;
> }
> @@ -5638,7 +5638,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> - struct intel_crtc_state *pipe_config =
> + struct intel_crtc_state *crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct drm_connector *connector;
> struct drm_connector_state *connector_state;
> @@ -5646,28 +5646,28 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> int base_bpp, ret, i;
> bool retry = true;
>
> - pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
> + crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
>
> - pipe_config->framestart_delay = 1;
> + crtc_state->framestart_delay = 1;
>
> /*
> * Sanitize sync polarity flags based on requested ones. If neither
> * positive or negative polarity is requested, treat this as meaning
> * negative polarity.
> */
> - if (!(pipe_config->hw.adjusted_mode.flags &
> + if (!(crtc_state->hw.adjusted_mode.flags &
> (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
> - pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
> + crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
>
> - if (!(pipe_config->hw.adjusted_mode.flags &
> + if (!(crtc_state->hw.adjusted_mode.flags &
> (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
> - pipe_config->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
> + crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
>
> ret = compute_baseline_pipe_bpp(state, crtc);
> if (ret)
> return ret;
>
> - base_bpp = pipe_config->pipe_bpp;
> + base_bpp = crtc_state->pipe_bpp;
>
> /*
> * Determine the real pipe dimensions. Note that stereo modes can
> @@ -5677,9 +5677,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> * computation to clearly distinguish it from the adjusted mode, which
> * can be changed by the connectors in the below retry loop.
> */
> - drm_mode_get_hv_timing(&pipe_config->hw.mode,
> + drm_mode_get_hv_timing(&crtc_state->hw.mode,
> &pipe_src_w, &pipe_src_h);
> - drm_rect_init(&pipe_config->pipe_src, 0, 0,
> + drm_rect_init(&crtc_state->pipe_src, 0, 0,
> pipe_src_w, pipe_src_h);
>
> for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
> @@ -5700,20 +5700,20 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> * hooks so that the hooks can use this information safely.
> */
> if (encoder->compute_output_type)
> - pipe_config->output_types |=
> - BIT(encoder->compute_output_type(encoder, pipe_config,
> + crtc_state->output_types |=
> + BIT(encoder->compute_output_type(encoder, crtc_state,
> connector_state));
> else
> - pipe_config->output_types |= BIT(encoder->type);
> + crtc_state->output_types |= BIT(encoder->type);
> }
>
> encoder_retry:
> /* Ensure the port clock defaults are reset when retrying. */
> - pipe_config->port_clock = 0;
> - pipe_config->pixel_multiplier = 1;
> + crtc_state->port_clock = 0;
> + crtc_state->pixel_multiplier = 1;
>
> /* Fill in default crtc timings, allow encoders to overwrite them. */
> - drm_mode_set_crtcinfo(&pipe_config->hw.adjusted_mode,
> + drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
> CRTC_STEREO_DOUBLE);
>
> /* Pass our mode to the connectors and the CRTC to give them a chance to
> @@ -5727,7 +5727,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> if (connector_state->crtc != &crtc->base)
> continue;
>
> - ret = encoder->compute_config(encoder, pipe_config,
> + ret = encoder->compute_config(encoder, crtc_state,
> connector_state);
> if (ret == -EDEADLK)
> return ret;
> @@ -5739,9 +5739,9 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
>
> /* Set default port clock if not overwritten by the encoder. Needs to be
> * done afterwards in case the encoder adjusts the mode. */
> - if (!pipe_config->port_clock)
> - pipe_config->port_clock = pipe_config->hw.adjusted_mode.crtc_clock
> - * pipe_config->pixel_multiplier;
> + if (!crtc_state->port_clock)
> + crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
> + * crtc_state->pixel_multiplier;
>
> ret = intel_crtc_compute_config(state, crtc);
> if (ret == -EDEADLK)
> @@ -5764,11 +5764,11 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> * only enable it on 6bpc panels and when its not a compliance
> * test requesting 6bpc video pattern.
> */
> - pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
> - !pipe_config->dither_force_disable;
> + crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
> + !crtc_state->dither_force_disable;
> drm_dbg_kms(&i915->drm,
> "hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
> - base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
> + base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
>
> return 0;
> }
--
Jani Nikula, Intel Open Source Graphics Center
next prev parent reply other threads:[~2022-05-16 12:39 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-03 18:22 [Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-05-03 18:22 ` [Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
2022-05-16 12:11 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-05-16 12:12 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs Ville Syrjala
2022-05-16 12:12 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-05-16 13:07 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() Ville Syrjala
2022-05-16 12:29 ` Jani Nikula
2022-05-16 12:29 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT() Ville Syrjala
2022-05-16 12:36 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention Ville Syrjala
2022-05-16 12:39 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/ Ville Syrjala
2022-05-16 12:39 ` Jani Nikula [this message]
2022-05-03 18:22 ` [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs Ville Syrjala
2022-05-16 12:41 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock() Ville Syrjala
2022-05-04 12:33 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:43 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params Ville Syrjala
2022-05-04 21:21 ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:52 ` Jani Nikula
2022-05-16 12:50 ` [Intel-gfx] [PATCH " Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-05-25 10:53 ` Jani Nikula
2022-05-25 11:28 ` Ville Syrjälä
2022-05-03 18:22 ` [Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier Ville Syrjala
2022-05-25 10:57 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout Ville Syrjala
2022-05-25 10:58 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-05-25 11:03 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 16/26] drm/i915: Make all clock " Ville Syrjala
2022-05-25 11:07 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-05-25 11:07 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-05-25 11:08 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-05-25 11:09 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare() Ville Syrjala
2022-05-25 11:09 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-05-25 11:11 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-05-25 11:24 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL Ville Syrjala
2022-05-25 11:30 ` Jani Nikula
2022-05-25 18:16 ` Matt Roper
2022-05-03 18:22 ` [Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always Ville Syrjala
2022-05-30 12:07 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations Ville Syrjala
2022-05-30 12:09 ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-05-30 12:09 ` Jani Nikula
2022-05-03 19:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Make fastset not suck and allow seamless M/N changes Patchwork
2022-05-04 15:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2) Patchwork
2022-05-04 15:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05 1:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3) Patchwork
2022-05-05 1:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05 1:52 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05 2:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4) Patchwork
2022-05-05 2:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05 3:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-05 9:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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