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From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy
Date: Wed, 25 May 2022 14:03:46 +0300	[thread overview]
Message-ID: <8735gxvppp.fsf@intel.com> (raw)
In-Reply-To: <20220503182242.18797-16-ville.syrjala@linux.intel.com>

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Now that we no longer fuzz M/N during fastset these should
> match exctly.
>
> TODO: we may need to do something for fastboot here as the
> VBIOS/GOP may not compute M/N exactly the same way we do.
> Though I guess we could try to match the VBIOS/GOP exactly.

I see that later patches change the M/N calculation, and that may be
enough.

But if GOP isn't consistent about this (I don't know), it's going to be
whack-a-mole if we get regression reports on not having fastboot.

Mmh. If we support seamless M/N change, could we do that on fastboot?

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 49 ++++----------------
>  1 file changed, 8 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 86971be92e57..198c6340a463 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5832,47 +5832,15 @@ bool intel_fuzzy_clock_check(int clock1, int clock2)
>  	return false;
>  }
>  
> -static bool
> -intel_compare_m_n(unsigned int m, unsigned int n,
> -		  unsigned int m2, unsigned int n2,
> -		  bool exact)
> -{
> -	if (m == m2 && n == n2)
> -		return true;
> -
> -	if (exact || !m || !n || !m2 || !n2)
> -		return false;
> -
> -	BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
> -
> -	if (n > n2) {
> -		while (n > n2) {
> -			m2 <<= 1;
> -			n2 <<= 1;
> -		}
> -	} else if (n < n2) {
> -		while (n < n2) {
> -			m <<= 1;
> -			n <<= 1;
> -		}
> -	}
> -
> -	if (n != n2)
> -		return false;
> -
> -	return intel_fuzzy_clock_check(m, m2);
> -}
> -
>  static bool
>  intel_compare_link_m_n(const struct intel_link_m_n *m_n,
> -		       const struct intel_link_m_n *m2_n2,
> -		       bool exact)
> +		       const struct intel_link_m_n *m2_n2)
>  {
>  	return m_n->tu == m2_n2->tu &&
> -		intel_compare_m_n(m_n->data_m, m_n->data_n,
> -				  m2_n2->data_m, m2_n2->data_n, exact) &&
> -		intel_compare_m_n(m_n->link_m, m_n->link_n,
> -				  m2_n2->link_m, m2_n2->link_n, exact);
> +		m_n->data_m == m2_n2->data_m &&
> +		m_n->data_n == m2_n2->data_n &&
> +		m_n->link_m == m2_n2->link_m &&
> +		m_n->link_n == m2_n2->link_n;
>  }
>  
>  static bool
> @@ -6066,8 +6034,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  
>  #define PIPE_CONF_CHECK_M_N(name) do { \
>  	if (!intel_compare_link_m_n(&current_config->name, \
> -				    &pipe_config->name,\
> -				    !fastset)) { \
> +				    &pipe_config->name)) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name), \
>  				     "(expected tu %i data %i/%i link %i/%i, " \
>  				     "found tu %i, data %i/%i link %i/%i)", \
> @@ -6114,9 +6081,9 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>   */
>  #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) do { \
>  	if (!intel_compare_link_m_n(&current_config->name, \
> -				    &pipe_config->name, !fastset) && \
> +				    &pipe_config->name) && \
>  	    !intel_compare_link_m_n(&current_config->alt_name, \
> -				    &pipe_config->name, !fastset)) { \
> +				    &pipe_config->name)) { \
>  		pipe_config_mismatch(fastset, crtc, __stringify(name), \
>  				     "(expected tu %i data %i/%i link %i/%i, " \
>  				     "or tu %i data %i/%i link %i/%i, " \

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-05-25 11:03 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 18:22 [Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-05-03 18:22 ` [Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
2022-05-16 12:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-05-16 13:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() Ville Syrjala
2022-05-16 12:29   ` Jani Nikula
2022-05-16 12:29   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT() Ville Syrjala
2022-05-16 12:36   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/ Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs Ville Syrjala
2022-05-16 12:41   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock() Ville Syrjala
2022-05-04 12:33   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:43     ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params Ville Syrjala
2022-05-04 21:21   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:52     ` Jani Nikula
2022-05-16 12:50   ` [Intel-gfx] [PATCH " Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-05-25 10:53   ` Jani Nikula
2022-05-25 11:28     ` Ville Syrjälä
2022-05-03 18:22 ` [Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier Ville Syrjala
2022-05-25 10:57   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout Ville Syrjala
2022-05-25 10:58   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-05-25 11:03   ` Jani Nikula [this message]
2022-05-03 18:22 ` [Intel-gfx] [PATCH 16/26] drm/i915: Make all clock " Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-05-25 11:08   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare() Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-05-25 11:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-05-25 11:24   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL Ville Syrjala
2022-05-25 11:30   ` Jani Nikula
2022-05-25 18:16     ` Matt Roper
2022-05-03 18:22 ` [Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always Ville Syrjala
2022-05-30 12:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 19:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Make fastset not suck and allow seamless M/N changes Patchwork
2022-05-04 15:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2) Patchwork
2022-05-04 15:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3) Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  1:52 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4) Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  3:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-05  9:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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