Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
	intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config()
Date: Mon, 16 May 2022 16:07:59 +0300	[thread overview]
Message-ID: <87ee0tfwwg.fsf@intel.com> (raw)
In-Reply-To: <20220503182242.18797-5-ville.syrjala@linux.intel.com>

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Only reassign the pipe's DPLL if it's going through a full
> .compute_config() cycle. If OTOH it's just getting modeset
> eg. in order to change cdclk there doesn't seem much point in
> picking a new DPLL for it.
>
> This should also prevent .get_dplls() from seeing a funky port_clock
> for DP even in cases where the readout produces a non-standard
> clock and we (for some reason) have decided to not fully recompute
> the state to remedy the situation.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

A bit unsure if I can appreciate all the subtleties here, but

Reviewed-by: Jani Nikula <jani.nikula@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 17 +----------------
>  drivers/gpu/drm/i915/display/intel_dpll.c    |  6 ++----
>  2 files changed, 3 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5e50e0d56088..7d488d320762 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6955,20 +6955,6 @@ intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state)
>  	}
>  }
>  
> -static void intel_modeset_clear_plls(struct intel_atomic_state *state)
> -{
> -	struct intel_crtc_state *new_crtc_state;
> -	struct intel_crtc *crtc;
> -	int i;
> -
> -	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> -		if (!intel_crtc_needs_modeset(new_crtc_state))
> -			continue;
> -
> -		intel_release_shared_dplls(state, crtc);
> -	}
> -}
> -
>  /*
>   * This implements the workaround described in the "notes" section of the mode
>   * set sequence documentation. When going from no pipes or single pipe to
> @@ -7802,6 +7788,7 @@ static int intel_atomic_check(struct drm_device *dev,
>  			if (ret)
>  				goto fail;
>  
> +			intel_release_shared_dplls(state, crtc);
>  			continue;
>  		}
>  
> @@ -7849,8 +7836,6 @@ static int intel_atomic_check(struct drm_device *dev,
>  		ret = intel_modeset_calc_cdclk(state);
>  		if (ret)
>  			return ret;
> -
> -		intel_modeset_clear_plls(state);
>  	}
>  
>  	ret = intel_atomic_check_crtcs(state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
> index 2b3f72550e5a..afd30c6cc34c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll.c
> @@ -1436,11 +1436,9 @@ int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
>  	int ret;
>  
>  	drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
> +	drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll);
>  
> -	if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll))
> -		return 0;
> -
> -	if (!crtc_state->hw.enable)
> +	if (!crtc_state->hw.enable || crtc_state->shared_dpll)
>  		return 0;
>  
>  	if (!i915->dpll_funcs->crtc_get_shared_dpll)

-- 
Jani Nikula, Intel Open Source Graphics Center

  reply	other threads:[~2022-05-16 13:08 UTC|newest]

Thread overview: 69+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-03 18:22 [Intel-gfx] [PATCH 00/26] drm/i915: Make fastset not suck and allow seamless M/N changes Ville Syrjala
2022-05-03 18:22 ` [Intel-gfx] [PATCH 01/26] drm/i915: Split shared dpll .get_dplls() into compute and get phases Ville Syrjala
2022-05-16 12:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 02/26] drm/i915: Do .crtc_compute_clock() earlier Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 03/26] drm/i915: Clean up DPLL related debugs Ville Syrjala
2022-05-16 12:12   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 04/26] drm/i915: Reassign DPLLs only for crtcs going throug .compute_config() Ville Syrjala
2022-05-16 13:07   ` Jani Nikula [this message]
2022-05-03 18:22 ` [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS() Ville Syrjala
2022-05-16 12:29   ` Jani Nikula
2022-05-16 12:29   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 06/26] drm/i915: Extract PIPE_CONF_CHECK_RECT() Ville Syrjala
2022-05-16 12:36   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 07/26] drm/i915: Adjust intel_modeset_pipe_config() & co. calling convention Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 08/26] drm/i915: s/pipe_config/crtc_state/ Ville Syrjala
2022-05-16 12:39   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 09/26] drm/i915: Improve modeset debugs Ville Syrjala
2022-05-16 12:41   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 10/26] drm/i915: Extract intel_crtc_dotclock() Ville Syrjala
2022-05-04 12:33   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:43     ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 11/26] drm/i915: Introduce struct iclkip_params Ville Syrjala
2022-05-04 21:21   ` [Intel-gfx] [PATCH v2 " Ville Syrjala
2022-05-16 12:52     ` Jani Nikula
2022-05-16 12:50   ` [Intel-gfx] [PATCH " Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 12/26] drm/i915: Feed the DPLL output freq back into crtc_state Ville Syrjala
2022-05-25 10:53   ` Jani Nikula
2022-05-25 11:28     ` Ville Syrjälä
2022-05-03 18:22 ` [Intel-gfx] [PATCH 13/26] drm/i915: Compute clocks earlier Ville Syrjala
2022-05-25 10:57   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 14/26] drm/i915: Skip FDI vs. dotclock sanity check during readout Ville Syrjala
2022-05-25 10:58   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 15/26] drm/i915: Make M/N checks non-fuzzy Ville Syrjala
2022-05-25 11:03   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 16/26] drm/i915: Make all clock " Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 17/26] drm/i915: Set active dpll early for icl+ Ville Syrjala
2022-05-25 11:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 18/26] drm/i915: Nuke fastet state copy hacks Ville Syrjala
2022-05-25 11:08   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 19/26] drm/i915: Skip intel_modeset_pipe_config_late() if the pipe is not enabled Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 20/26] drm/i915: Check hw.enable and hw.active in intel_pipe_config_compare() Ville Syrjala
2022-05-25 11:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 21/26] drm/i915: Add intel_panel_highest_mode() Ville Syrjala
2022-05-25 11:11   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 22/26] drm/i915: Allow M/N change during fastset on bdw+ Ville Syrjala
2022-05-25 11:24   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 23/26] drm/i915: Require an exact DP link freq match for the DG2 PLL Ville Syrjala
2022-05-25 11:30   ` Jani Nikula
2022-05-25 18:16     ` Matt Roper
2022-05-03 18:22 ` [Intel-gfx] [PATCH 24/26] drm/i915: Use a fixed N value always Ville Syrjala
2022-05-30 12:07   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 25/26] drm/i915: Round to closest in M/N calculations Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 18:22 ` [Intel-gfx] [PATCH 26/26] drm/i915: Round TMDS clock to nearest Ville Syrjala
2022-05-30 12:09   ` Jani Nikula
2022-05-03 19:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Make fastset not suck and allow seamless M/N changes Patchwork
2022-05-04 15:07 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev2) Patchwork
2022-05-04 15:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev3) Patchwork
2022-05-05  1:21 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  1:52 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Make fastset not suck and allow seamless M/N changes (rev4) Patchwork
2022-05-05  2:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-05-05  3:16 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-05-05  9:12 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87ee0tfwwg.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=ville.syrjala@linux.intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox