Re: [Intel-gfx] [PATCH 05/26] drm/i915: Extract PIPE_CONF_CHECK_TIMINGS()

[Jani Nikula <jani.nikula@linux.intel.com>]

On Tue, 03 May 2022, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Deduplicate the crtc_ timigns comparisons.

*timings

>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 45 ++++++++------------
>  1 file changed, 18 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7d488d320762..e38d93beafdd 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6073,6 +6073,21 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	} \
>  } while (0)
>  
> +#define PIPE_CONF_CHECK_TIMINGS(name) do { \
> +	PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
> +	PIPE_CONF_CHECK_I(name.crtc_htotal); \
> +	PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
> +	PIPE_CONF_CHECK_I(name.crtc_vtotal); \
> +	PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
> +	PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
> +	PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
> +} while (0)
> +
>  /* This is required for BDW+ where there is only one set of registers for
>   * switching between high and low RR.
>   * This macro can be used whenever a comparison has to be made between one
> @@ -6190,33 +6205,8 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  	PIPE_CONF_CHECK_I(framestart_delay);
>  	PIPE_CONF_CHECK_I(msa_timing_delay);
>  
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_hsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_vsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hdisplay);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_htotal);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hblank_end);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_hsync_end);
> -
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vdisplay);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vtotal);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vblank_end);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_start);
> -	PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_vsync_end);
> +	PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
> +	PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
>  
>  	PIPE_CONF_CHECK_I(pixel_multiplier);
>  
> @@ -6392,6 +6382,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
>  #undef PIPE_CONF_CHECK_FLAGS
>  #undef PIPE_CONF_CHECK_CLOCK_FUZZY
>  #undef PIPE_CONF_CHECK_COLOR_LUT
> +#undef PIPE_CONF_CHECK_TIMINGS
>  #undef PIPE_CONF_QUIRK
>  
>  	return ret;

-- 
Jani Nikula, Intel Open Source Graphics Center