From: Ville Syrjala <ville.syrjala@linux.intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Takashi Iwai <tiwai@suse.de>
Subject: [Intel-gfx] [PATCH 04/22] drm/i915/audio: Exract struct ilk_audio_regs
Date: Tue, 11 Oct 2022 19:59:53 +0300 [thread overview]
Message-ID: <20221011170011.17198-5-ville.syrjala@linux.intel.com> (raw)
In-Reply-To: <20221011170011.17198-1-ville.syrjala@linux.intel.com>
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The "ilk" audio codec codepaths have some duplicated code
to figure out the correct registers to use on each platform.
Extrat that into a single place.
Cc: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Cc: Kai Vehmanen <kai.vehmanen@linux.intel.com>
Cc: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_audio.c | 85 +++++++++++-----------
1 file changed, 43 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 5517e0a6d868..baa69151fc09 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -665,6 +665,32 @@ static void hsw_audio_codec_enable(struct intel_encoder *encoder,
mutex_unlock(&i915->display.audio.mutex);
}
+struct ilk_audio_regs {
+ i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
+};
+
+static void ilk_audio_regs_init(struct drm_i915_private *i915,
+ enum pipe pipe,
+ struct ilk_audio_regs *regs)
+{
+ if (HAS_PCH_IBX(i915)) {
+ regs->hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
+ regs->aud_config = IBX_AUD_CFG(pipe);
+ regs->aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
+ regs->aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ regs->hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
+ regs->aud_config = VLV_AUD_CFG(pipe);
+ regs->aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
+ regs->aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
+ } else {
+ regs->hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
+ regs->aud_config = CPT_AUD_CFG(pipe);
+ regs->aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
+ regs->aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
+ }
+}
+
static void ilk_audio_codec_disable(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
@@ -673,39 +699,30 @@ static void ilk_audio_codec_disable(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
+ struct ilk_audio_regs regs;
u32 tmp, eldv;
- i915_reg_t aud_config, aud_cntrl_st2;
if (drm_WARN_ON(&i915->drm, port == PORT_A))
return;
- if (HAS_PCH_IBX(i915)) {
- aud_config = IBX_AUD_CFG(pipe);
- aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
- } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
- aud_config = VLV_AUD_CFG(pipe);
- aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
- } else {
- aud_config = CPT_AUD_CFG(pipe);
- aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
- }
+ ilk_audio_regs_init(i915, pipe, ®s);
/* Disable timestamps */
- tmp = intel_de_read(i915, aud_config);
+ tmp = intel_de_read(i915, regs.aud_config);
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp |= AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_UPPER_N_MASK;
tmp &= ~AUD_CONFIG_LOWER_N_MASK;
if (intel_crtc_has_dp_encoder(old_crtc_state))
tmp |= AUD_CONFIG_N_VALUE_INDEX;
- intel_de_write(i915, aud_config, tmp);
+ intel_de_write(i915, regs.aud_config, tmp);
eldv = IBX_ELD_VALID(port);
/* Invalidate ELD */
- tmp = intel_de_read(i915, aud_cntrl_st2);
+ tmp = intel_de_read(i915, regs.aud_cntrl_st2);
tmp &= ~eldv;
- intel_de_write(i915, aud_cntrl_st2, tmp);
+ intel_de_write(i915, regs.aud_cntrl_st2, tmp);
}
static void ilk_audio_codec_enable(struct intel_encoder *encoder,
@@ -718,9 +735,9 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
enum pipe pipe = crtc->pipe;
enum port port = encoder->port;
const u8 *eld = connector->eld;
+ struct ilk_audio_regs regs;
u32 tmp, eldv;
int len, i;
- i915_reg_t hdmiw_hdmiedid, aud_config, aud_cntl_st, aud_cntrl_st2;
if (drm_WARN_ON(&i915->drm, port == PORT_A))
return;
@@ -732,49 +749,33 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
* infrastructure is not there yet.
*/
- if (HAS_PCH_IBX(i915)) {
- hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
- aud_config = IBX_AUD_CFG(pipe);
- aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
- aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
- } else if (IS_VALLEYVIEW(i915) ||
- IS_CHERRYVIEW(i915)) {
- hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
- aud_config = VLV_AUD_CFG(pipe);
- aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
- aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
- } else {
- hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
- aud_config = CPT_AUD_CFG(pipe);
- aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
- aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
- }
+ ilk_audio_regs_init(i915, pipe, ®s);
eldv = IBX_ELD_VALID(port);
/* Invalidate ELD */
- tmp = intel_de_read(i915, aud_cntrl_st2);
+ tmp = intel_de_read(i915, regs.aud_cntrl_st2);
tmp &= ~eldv;
- intel_de_write(i915, aud_cntrl_st2, tmp);
+ intel_de_write(i915, regs.aud_cntrl_st2, tmp);
/* Reset ELD write address */
- tmp = intel_de_read(i915, aud_cntl_st);
+ tmp = intel_de_read(i915, regs.aud_cntl_st);
tmp &= ~IBX_ELD_ADDRESS_MASK;
- intel_de_write(i915, aud_cntl_st, tmp);
+ intel_de_write(i915, regs.aud_cntl_st, tmp);
/* Up to 84 bytes of hw ELD buffer */
len = min(drm_eld_size(eld), 84);
for (i = 0; i < len / 4; i++)
- intel_de_write(i915, hdmiw_hdmiedid,
+ intel_de_write(i915, regs.hdmiw_hdmiedid,
*((const u32 *)eld + i));
/* ELD valid */
- tmp = intel_de_read(i915, aud_cntrl_st2);
+ tmp = intel_de_read(i915, regs.aud_cntrl_st2);
tmp |= eldv;
- intel_de_write(i915, aud_cntrl_st2, tmp);
+ intel_de_write(i915, regs.aud_cntrl_st2, tmp);
/* Enable timestamps */
- tmp = intel_de_read(i915, aud_config);
+ tmp = intel_de_read(i915, regs.aud_config);
tmp &= ~AUD_CONFIG_N_VALUE_INDEX;
tmp &= ~AUD_CONFIG_N_PROG_ENABLE;
tmp &= ~AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK;
@@ -782,7 +783,7 @@ static void ilk_audio_codec_enable(struct intel_encoder *encoder,
tmp |= AUD_CONFIG_N_VALUE_INDEX;
else
tmp |= audio_config_hdmi_pixel_clock(crtc_state);
- intel_de_write(i915, aud_config, tmp);
+ intel_de_write(i915, regs.aud_config, tmp);
}
/**
--
2.35.1
next prev parent reply other threads:[~2022-10-11 17:02 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-11 16:59 [Intel-gfx] [PATCH 00/22] drm/i915: ELD precompute and readout Ville Syrjala
2022-10-11 16:59 ` [Intel-gfx] [PATCH 01/22] drm/i915/audio: s/dev_priv/i915/ Ville Syrjala
2022-10-12 14:35 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 02/22] drm/i915/audio: Nuke leftover ROUNDING_FACTOR Ville Syrjala
2022-10-12 14:36 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 03/22] drm/i915/audio: Remove CL/BLC audio stuff Ville Syrjala
2022-10-12 14:36 ` Jani Nikula
2022-10-11 16:59 ` Ville Syrjala [this message]
2022-10-12 14:36 ` [Intel-gfx] [PATCH 04/22] drm/i915/audio: Exract struct ilk_audio_regs Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 05/22] drm/i915/audio: Use REG_BIT() & co Ville Syrjala
2022-10-12 14:37 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 06/22] drm/i915/audio: Unify register bit naming Ville Syrjala
2022-10-12 14:37 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 07/22] drm/i915/audio: Protect singleton register with a lock Ville Syrjala
2022-10-12 14:38 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 08/22] drm/i915/audio: Nuke intel_eld_uptodate() Ville Syrjala
2022-10-12 14:40 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 09/22] drm/i915/audio: Read ELD buffer size from hardware Ville Syrjala
2022-10-12 14:41 ` Jani Nikula
2022-10-12 14:46 ` Jani Nikula
2022-10-11 16:59 ` [Intel-gfx] [PATCH 10/22] drm/i915/audio: Make sure we write the whole ELD buffer Ville Syrjala
2022-10-12 14:28 ` Jani Nikula
2022-10-12 15:03 ` Ville Syrjälä
2022-10-12 16:06 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 11/22] drm/i915/audio: Use u32* for ELD Ville Syrjala
2022-10-12 14:42 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 12/22] drm/i915/audio: Use intel_de_rmw() for most audio registers Ville Syrjala
2022-10-12 14:33 ` Jani Nikula
2022-10-12 15:05 ` Ville Syrjälä
2022-10-11 17:00 ` [Intel-gfx] [PATCH 13/22] drm/i915/audio: Split "ELD valid" vs. audio PD on hsw+ Ville Syrjala
2022-10-12 15:01 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 14/22] drm/i915/audio: Do the vblank waits Ville Syrjala
2022-10-12 15:01 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 15/22] drm/i915/audio: Precompute the ELD Ville Syrjala
2022-10-12 15:11 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 16/22] drm/i915/audio: Hardware ELD readout Ville Syrjala
2022-10-12 15:19 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 17/22] drm/i915/sdvo: Extract intel_sdvo_has_audio() Ville Syrjala
2022-10-12 15:15 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 18/22] drm/i915/sdvo: Precompute the ELD Ville Syrjala
2022-10-12 15:16 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 19/22] drm/i915/sdvo: Do ELD hardware readout Ville Syrjala
2022-10-12 15:22 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 20/22] drm/i915/audio: Hook up ELD into the state checker Ville Syrjala
2022-10-12 15:25 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 21/22] drm/i915/audio: Include ELD in the state dump Ville Syrjala
2022-10-12 15:26 ` Jani Nikula
2022-10-11 17:00 ` [Intel-gfx] [PATCH 22/22] hax: drm/i915/audio: Make HSW hardware ELD buffer sort of work Ville Syrjala
2022-10-12 10:49 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/audio: Resume HSW/BDW HDA controller around ELD access Ville Syrjala
2022-10-12 11:08 ` Ville Syrjälä
2022-10-12 11:42 ` Kai Vehmanen
2022-10-12 13:53 ` Kai Vehmanen
2022-10-12 14:24 ` Ville Syrjälä
2022-10-19 18:06 ` Ville Syrjälä
2022-10-14 10:51 ` Kai Vehmanen
2022-10-19 18:43 ` Ville Syrjälä
2022-10-11 17:39 ` [Intel-gfx] [PATCH 00/22] drm/i915: ELD precompute and readout Jani Nikula
2022-10-11 20:38 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-10-11 20:38 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-11 21:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-12 12:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: ELD precompute and readout (rev2) Patchwork
2022-10-12 12:33 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-10-12 12:58 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-10-14 9:03 ` [Intel-gfx] [PATCH 00/22] drm/i915: ELD precompute and readout Borah, Chaitanya Kumar
2022-10-14 9:13 ` Jani Nikula
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