[PATCH v12 0/9] Implement CMRR Support

[PATCH v12 0/9] Implement CMRR Support

[Mitul Golani]

CMRR is a display feature that uses adaptive sync
framework to vary Vtotal slightly to match the
content rate exactly without frame drops. This
feature is a variation of VRR where it varies Vtotal
slightly (between additional 0 and 1 Vtotal scanlines)
to match content rate exactly without frame drops
using the adaptive sync framework.

enable this feature by programing new registers for
CMRR enable, CMRR_M, CMRR_N, vmin=vmax=flipline.The
CMRR_M/CMRR_N ratio represents the fractional part
in (actual refresh rate/target refresh rate) * origVTotal.

--v6:
- CMRR handling in co-existatnce of LRR and DRRS
- Correct vtotal paramas accuracy and add 2 digit precision.

--v7:
- Rebased patches in-accordance to AS SDP merge.
- Add neccessary gaurd to prevent crtc_state mismatch
during intel_vrr_get_config.

-v8:
- Add support for AS SDP for CMRR.
- update palce holder for CMRR register(Jani).
- Make CMRR as subset of FAVT, as per comments in patch#3.

-v9:
- Add CMRR register definitions to separate intel_vrr_reg.h.
- Remove cmrr_enabling/disabling, use vrr.enable instead.
- Update AS SDP pack function to accomodate target_rr_divider.
- Remove duplicated lines to compute vrr_vsync params.
- Set cmrr.enable with a separate patch at last.

-v10:
- Separate VRR related register definitions.
- Add dependency header intel_display_reg_defs.h.
- Rename file name to intel_vrr_regs.h instead of reg.h.
- Revert removed line.
- Since vrr.enable and cmrr.enable are not mutually exclusive,
handle accordingly.
- is_edp is not required inside is_cmrr_frac_required function.
- Add video_mode_required flag for future enhancement.
- Correct cmrr_m/cmrr_n calculation.
- target_rr_divider is bools so handle accordingly.

-v11:
- Move VRR related register and bits to separate file
intel_vrr_regs.h.
- Correct file header macro to intel_vrr_regs.h.
- Remove adding CMRR flag to vrr_ctl register during
set_transcoder_timing.
- Replace vrr.enable flag to cmrr.enable where added mistakenly.
- Move cmrr computation patch to last and set other other required
  params before computing cmrr.enable.

-v12:
- Add patch to fix check patch issues for VRR related registers
in i915_reg.h then move them to intel_vrr_regs.h with separate
patch.
- Use drm_mode_vrefresh instead of manual refresh rate calculation.

Mitul Golani (7):
  gpu/drm/i915: Update indentation for VRR registers and bits
  drm/i915: Separate VRR related register definitions
  drm/i915: Define and compute Transcoder CMRR registers
  drm/i915: Update trans_vrr_ctl flag when cmrr is computed
  drm/dp: Add refresh rate divider to struct representing AS SDP
  drm/i915/display: Add support for pack and unpack
  drm/i915/display: Compute Adaptive sync SDP params

Ville Syrjälä (2):
  drm/i915: Protect CRC reg macro arguments for consistency
  drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest

-- 
2.25.1

[PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

It's probably a good idea to start protecting all macro arguments
to avoid any cargo-cult mistakes when people go looking for examples
of how to define these things.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-8-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 .../drm/i915/display/intel_pipe_crc_regs.h    | 26 +++++++++----------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
index 383910a785f6..4e65f51d34e6 100644
--- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
@@ -9,7 +9,7 @@
 #include "intel_display_reg_defs.h"
 
 #define _PIPE_CRC_CTL_A			0x60050
-#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A)
+#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_CTL_A)
 #define   PIPE_CRC_ENABLE		REG_BIT(31)
 /* skl+ source selection */
 #define   PIPE_CRC_SOURCE_MASK_SKL	REG_GENMASK(30, 28)
@@ -76,19 +76,19 @@
 #define   PIPE_CRC_EXP_RES2_MASK	REG_BIT(22, 0) /* pre-ivb */
 
 #define _PIPE_CRC_RES_RED_A		0x60060
-#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A)
+#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RED_A)
 
 #define _PIPE_CRC_RES_GREEN_A		0x60064
-#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A)
+#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_GREEN_A)
 
 #define _PIPE_CRC_RES_BLUE_A		0x60068
-#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A)
+#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_BLUE_A)
 
 #define _PIPE_CRC_RES_RES1_A_I915	0x6006c /* i915+ */
-#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
+#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)
 
 #define _PIPE_CRC_RES_RES2_A_G4X	0x60080 /* g4x+ */
-#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
+#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)
 
 /* ivb */
 #define _PIPE_CRC_EXP_2_A_IVB		0x60054
@@ -117,36 +117,36 @@
 /* ivb */
 #define _PIPE_CRC_RES_1_A_IVB		0x60064
 #define _PIPE_CRC_RES_1_B_IVB		0x61064
-#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
+#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
 
 /* ivb */
 #define _PIPE_CRC_RES_2_A_IVB		0x60068
 #define _PIPE_CRC_RES_2_B_IVB		0x61068
-#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
+#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
 
 /* ivb */
 #define _PIPE_CRC_RES_3_A_IVB		0x6006c
 #define _PIPE_CRC_RES_3_B_IVB		0x6106c
-#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
+#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
 
 /* ivb */
 #define _PIPE_CRC_RES_4_A_IVB		0x60070
 #define _PIPE_CRC_RES_4_B_IVB		0x61070
-#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
+#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
 
 /* ivb */
 #define _PIPE_CRC_RES_5_A_IVB		0x60074
 #define _PIPE_CRC_RES_5_B_IVB		0x61074
-#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE(pipe, _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
+#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE((pipe), _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
 
 /* hsw+ */
 #define _PIPE_CRC_EXP_A_HSW		0x60054
 #define _PIPE_CRC_EXP_B_HSW		0x61054
-#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE(pipe, _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
+#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE((pipe), _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
 
 /* hsw+ */
 #define _PIPE_CRC_RES_A_HSW		0x60064
 #define _PIPE_CRC_RES_B_HSW		0x61064
-#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE(pipe, _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
+#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE((pipe), _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
 
 #endif /* __INTEL_PIPE_CRC_REGS_H__ */
-- 
2.25.1

RE: [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for consistency

[Golani, Mitulkumar Ajitkumar]

Hi,

I made a mistake while creating patch and this was sent by mistake. Please ignore this patch. I will rebase my patch series and send the correct version.

Sorry for inconvenience.

Regards,
Mitul

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mitul
> Golani
> Sent: Wednesday, June 5, 2024 5:58 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v12 1/9] drm/i915: Protect CRC reg macro arguments for
> consistency
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> It's probably a good idea to start protecting all macro arguments to avoid any
> cargo-cult mistakes when people go looking for examples of how to define
> these things.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20240531115342.2763-
> 8-ville.syrjala@linux.intel.com
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../drm/i915/display/intel_pipe_crc_regs.h    | 26 +++++++++----------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> index 383910a785f6..4e65f51d34e6 100644
> --- a/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
> @@ -9,7 +9,7 @@
>  #include "intel_display_reg_defs.h"
> 
>  #define _PIPE_CRC_CTL_A			0x60050
> -#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_CTL_A)
> +#define PIPE_CRC_CTL(dev_priv, pipe)		_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_CTL_A)
>  #define   PIPE_CRC_ENABLE		REG_BIT(31)
>  /* skl+ source selection */
>  #define   PIPE_CRC_SOURCE_MASK_SKL	REG_GENMASK(30, 28)
> @@ -76,19 +76,19 @@
>  #define   PIPE_CRC_EXP_RES2_MASK	REG_BIT(22, 0) /* pre-ivb */
> 
>  #define _PIPE_CRC_RES_RED_A		0x60060
> -#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_RED_A)
> +#define PIPE_CRC_RES_RED(dev_priv, pipe)	_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_RES_RED_A)
> 
>  #define _PIPE_CRC_RES_GREEN_A		0x60064
> -#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_GREEN_A)
> +#define PIPE_CRC_RES_GREEN(dev_priv, pipe)	_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_RES_GREEN_A)
> 
>  #define _PIPE_CRC_RES_BLUE_A		0x60068
> -#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2(dev_priv,
> pipe, _PIPE_CRC_RES_BLUE_A)
> +#define PIPE_CRC_RES_BLUE(dev_priv, pipe)	_MMIO_TRANS2((dev_priv),
> (pipe), _PIPE_CRC_RES_BLUE_A)
> 
>  #define _PIPE_CRC_RES_RES1_A_I915	0x6006c /* i915+ */
> -#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)
> 	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915)
> +#define PIPE_CRC_RES_RES1_I915(dev_priv, pipe)
> 	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES1_A_I915)
> 
>  #define _PIPE_CRC_RES_RES2_A_G4X	0x60080 /* g4x+ */
> -#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)
> 	_MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X)
> +#define PIPE_CRC_RES_RES2_G4X(dev_priv, pipe)
> 	_MMIO_TRANS2((dev_priv), (pipe), _PIPE_CRC_RES_RES2_A_G4X)
> 
>  /* ivb */
>  #define _PIPE_CRC_EXP_2_A_IVB		0x60054
> @@ -117,36 +117,36 @@
>  /* ivb */
>  #define _PIPE_CRC_RES_1_A_IVB		0x60064
>  #define _PIPE_CRC_RES_1_B_IVB		0x61064
> -#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
> +#define PIPE_CRC_RES_1_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_1_A_IVB, _PIPE_CRC_RES_1_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_2_A_IVB		0x60068
>  #define _PIPE_CRC_RES_2_B_IVB		0x61068
> -#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
> +#define PIPE_CRC_RES_2_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_2_A_IVB, _PIPE_CRC_RES_2_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_3_A_IVB		0x6006c
>  #define _PIPE_CRC_RES_3_B_IVB		0x6106c
> -#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
> +#define PIPE_CRC_RES_3_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_3_A_IVB, _PIPE_CRC_RES_3_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_4_A_IVB		0x60070
>  #define _PIPE_CRC_RES_4_B_IVB		0x61070
> -#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
> +#define PIPE_CRC_RES_4_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_4_A_IVB, _PIPE_CRC_RES_4_B_IVB)
> 
>  /* ivb */
>  #define _PIPE_CRC_RES_5_A_IVB		0x60074
>  #define _PIPE_CRC_RES_5_B_IVB		0x61074
> -#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
> +#define PIPE_CRC_RES_5_IVB(pipe)		_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_5_A_IVB, _PIPE_CRC_RES_5_B_IVB)
> 
>  /* hsw+ */
>  #define _PIPE_CRC_EXP_A_HSW		0x60054
>  #define _PIPE_CRC_EXP_B_HSW		0x61054
> -#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE(pipe,
> _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
> +#define PIPE_CRC_EXP_HSW(pipe)			_MMIO_PIPE((pipe),
> _PIPE_CRC_EXP_A_HSW, _PIPE_CRC_EXP_B_HSW)
> 
>  /* hsw+ */
>  #define _PIPE_CRC_RES_A_HSW		0x60064
>  #define _PIPE_CRC_RES_B_HSW		0x61064
> -#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE(pipe,
> _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
> +#define PIPE_CRC_RES_HSW(pipe)			_MMIO_PIPE((pipe),
> _PIPE_CRC_RES_A_HSW, _PIPE_CRC_RES_B_HSW)
> 
>  #endif /* __INTEL_PIPE_CRC_REGS_H__ */
> --
> 2.25.1

[PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest

[Mitul Golani]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

---
 integration-manifest | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)
 create mode 100644 integration-manifest

diff --git a/integration-manifest b/integration-manifest
new file mode 100644
index 000000000000..d840964a2208
--- /dev/null
+++ b/integration-manifest
@@ -0,0 +1,28 @@
+drm drm-fixes c3f38fa61af77b49866b006939479069cd451173
+	Linux 6.10-rc2
+drm-misc drm-misc-fixes 629f2b4e05225e53125aaf7ff0b87d5d53897128
+	drm/panel: sitronix-st7789v: Add check for of_drm_get_panel_orientation
+drm-intel drm-intel-fixes c3f38fa61af77b49866b006939479069cd451173
+	Linux 6.10-rc2
+drm-xe drm-xe-fixes 0698ff57bf327d9a5735a898f78161b8dada160b
+	drm/xe/pf: Update the LMTT when freeing VF GT config
+drm drm-next c3f38fa61af77b49866b006939479069cd451173
+	Linux 6.10-rc2
+drm-misc drm-misc-next-fixes 539d33b5783804f22a62bd62ff463dfd1cef4265
+	drm/komeda: remove unused struct 'gamma_curve_segment'
+drm-intel drm-intel-next-fixes 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
+	Linux 6.10-rc1
+drm-xe drm-xe-next-fixes d69c3d4b53829097b8948d6791ea32c07de3faab
+	drm/xe/ads: Use flexible-array
+drm-misc drm-misc-next 310ec03841a36e3f45fb528f0dfdfe5b9e84b037
+	dma-buf: align fd_flags and heap_flags with dma_heap_allocation_data
+drm-intel drm-intel-next 17419f5c6d409bcce5d094279a6fed5d5dbdba12
+	drm/i915: Protect CRC reg macro arguments for consistency
+drm-intel drm-intel-gt-next a09d2327a9ba8e3f5be238bc1b7ca2809255b464
+	drm/i915/gt: Fix CCS id's calculation for CCS mode setting
+drm-xe drm-xe-next 8b01f970ee890574b3607c85781354a765c849bd
+	drm/xe: Use missing lock in relay_needs_worker
+drm-intel topic/core-for-CI a51e92845f99879e971677482b0f5fd96ef10d3c
+	thunderbolt: Add Kconfig option to disable PCIe tunneling
+drm-xe topic/xe-for-CI 428c3ef38ef5565140b2104f0d3dafdae9056ca9
+	Revert "drm/xe/gsc: define GSC FW for LNL"
-- 
2.25.1

RE: [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest

[Golani, Mitulkumar Ajitkumar]

Hi,

Similar to Patch #1 this was sent by mistake. Please ignore this patch. I will rebase my patch series and send the correct version.

Sorry for inconvenience.

Regards,
Mitul

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Mitul
> Golani
> Sent: Wednesday, June 5, 2024 5:58 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: dri-devel@lists.freedesktop.org; Nautiyal, Ankit K
> <ankit.k.nautiyal@intel.com>; Nikula, Jani <jani.nikula@intel.com>
> Subject: [PATCH v12 2/9] drm-tip: 2024y-06m-05d-09h-52m-50s UTC
> integration manifest
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> ---
>  integration-manifest | 28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
>  create mode 100644 integration-manifest
> 
> diff --git a/integration-manifest b/integration-manifest new file mode 100644
> index 000000000000..d840964a2208
> --- /dev/null
> +++ b/integration-manifest
> @@ -0,0 +1,28 @@
> +drm drm-fixes c3f38fa61af77b49866b006939479069cd451173
> +	Linux 6.10-rc2
> +drm-misc drm-misc-fixes 629f2b4e05225e53125aaf7ff0b87d5d53897128
> +	drm/panel: sitronix-st7789v: Add check for
> +of_drm_get_panel_orientation drm-intel drm-intel-fixes
> c3f38fa61af77b49866b006939479069cd451173
> +	Linux 6.10-rc2
> +drm-xe drm-xe-fixes 0698ff57bf327d9a5735a898f78161b8dada160b
> +	drm/xe/pf: Update the LMTT when freeing VF GT config drm drm-next
> +c3f38fa61af77b49866b006939479069cd451173
> +	Linux 6.10-rc2
> +drm-misc drm-misc-next-fixes
> 539d33b5783804f22a62bd62ff463dfd1cef4265
> +	drm/komeda: remove unused struct 'gamma_curve_segment'
> +drm-intel drm-intel-next-fixes 1613e604df0cd359cf2a7fbd9be7a0bcfacfabd0
> +	Linux 6.10-rc1
> +drm-xe drm-xe-next-fixes d69c3d4b53829097b8948d6791ea32c07de3faab
> +	drm/xe/ads: Use flexible-array
> +drm-misc drm-misc-next 310ec03841a36e3f45fb528f0dfdfe5b9e84b037
> +	dma-buf: align fd_flags and heap_flags with
> dma_heap_allocation_data
> +drm-intel drm-intel-next 17419f5c6d409bcce5d094279a6fed5d5dbdba12
> +	drm/i915: Protect CRC reg macro arguments for consistency drm-intel
> +drm-intel-gt-next a09d2327a9ba8e3f5be238bc1b7ca2809255b464
> +	drm/i915/gt: Fix CCS id's calculation for CCS mode setting drm-xe
> +drm-xe-next 8b01f970ee890574b3607c85781354a765c849bd
> +	drm/xe: Use missing lock in relay_needs_worker drm-intel
> +topic/core-for-CI a51e92845f99879e971677482b0f5fd96ef10d3c
> +	thunderbolt: Add Kconfig option to disable PCIe tunneling drm-xe
> +topic/xe-for-CI 428c3ef38ef5565140b2104f0d3dafdae9056ca9
> +	Revert "drm/xe/gsc: define GSC FW for LNL"
> --
> 2.25.1

[PATCH v12 3/9] gpu/drm/i915: Update indentation for VRR registers and bits

[Mitul Golani]

Update the indentation for the VRR register definition and
its bits, and fix checkpatch issues to ensure smooth movement
of registers and bits.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 0569a23b83b2..6b39211b5469 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1152,7 +1152,7 @@
 #define _TRANS_VRR_CTL_B		0x61420
 #define _TRANS_VRR_CTL_C		0x62420
 #define _TRANS_VRR_CTL_D		0x63420
-#define TRANS_VRR_CTL(dev_priv, trans)			_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
+#define TRANS_VRR_CTL(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
 #define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
 #define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
 #define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
@@ -1160,7 +1160,8 @@
 #define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
 #define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
 #define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
-#define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
+#define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \
+								(x))
 
 #define _TRANS_VRR_VMAX_A		0x60424
 #define _TRANS_VRR_VMAX_B		0x61424
@@ -1190,7 +1191,7 @@
 #define _TRANS_VRR_STATUS_B		0x6142C
 #define _TRANS_VRR_STATUS_C		0x6242C
 #define _TRANS_VRR_STATUS_D		0x6342C
-#define TRANS_VRR_STATUS(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
+#define TRANS_VRR_STATUS(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
 #define   VRR_STATUS_VMAX_REACHED	REG_BIT(31)
 #define   VRR_STATUS_NOFLIP_TILL_BNDR	REG_BIT(30)
 #define   VRR_STATUS_FLIP_BEF_BNDR	REG_BIT(29)
@@ -1241,7 +1242,7 @@
 #define   TRANS_PUSH_SEND		REG_BIT(30)
 
 #define _TRANS_VRR_VSYNC_A		0x60078
-#define TRANS_VRR_VSYNC(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
+#define TRANS_VRR_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
 #define VRR_VSYNC_END_MASK		REG_GENMASK(28, 16)
 #define VRR_VSYNC_END(vsync_end)	REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
 #define VRR_VSYNC_START_MASK		REG_GENMASK(12, 0)
-- 
2.25.1

[PATCH v12 4/9] drm/i915: Separate VRR related register definitions

[Mitul Golani]

Move VRR related register definitions to a separate file called
intel_vrr_regs.h.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c      |   1 +
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 112 ++++++++++++++++++
 drivers/gpu/drm/i915/i915_reg.h               | 101 ----------------
 3 files changed, 113 insertions(+), 101 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_vrr_regs.h

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 5f3657aa8313..871e6e6a184a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -9,6 +9,7 @@
 #include "intel_de.h"
 #include "intel_display_types.h"
 #include "intel_vrr.h"
+#include "intel_vrr_regs.h"
 #include "intel_dp.h"
 
 bool intel_vrr_is_capable(struct intel_connector *connector)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
new file mode 100644
index 000000000000..d4eb74ee72a7
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __INTEL_VRR_REGS_H__
+#define __INTEL_VRR_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+/* VRR registers */
+#define _TRANS_VRR_CTL_A                0x60420
+#define _TRANS_VRR_CTL_B                0x61420
+#define _TRANS_VRR_CTL_C                0x62420
+#define _TRANS_VRR_CTL_D                0x63420
+#define TRANS_VRR_CTL(dev_priv, trans)          _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
+#define   VRR_CTL_VRR_ENABLE                    REG_BIT(31)
+#define   VRR_CTL_IGN_MAX_SHIFT                 REG_BIT(30)
+#define   VRR_CTL_FLIP_LINE_EN                  REG_BIT(29)
+#define   VRR_CTL_PIPELINE_FULL_MASK            REG_GENMASK(10, 3)
+#define   VRR_CTL_PIPELINE_FULL(x)              REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
+#define   VRR_CTL_PIPELINE_FULL_OVERRIDE        REG_BIT(0)
+#define   XELPD_VRR_CTL_VRR_GUARDBAND_MASK      REG_GENMASK(15, 0)
+#define   XELPD_VRR_CTL_VRR_GUARDBAND(x)        REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \
+								(x))
+
+#define _TRANS_VRR_VMAX_A               0x60424
+#define _TRANS_VRR_VMAX_B               0x61424
+#define _TRANS_VRR_VMAX_C               0x62424
+#define _TRANS_VRR_VMAX_D               0x63424
+#define TRANS_VRR_VMAX(dev_priv, trans)         _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
+#define   VRR_VMAX_MASK                 REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_VMIN_A               0x60434
+#define _TRANS_VRR_VMIN_B               0x61434
+#define _TRANS_VRR_VMIN_C               0x62434
+#define _TRANS_VRR_VMIN_D               0x63434
+#define TRANS_VRR_VMIN(dev_priv, trans)         _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
+#define   VRR_VMIN_MASK                 REG_GENMASK(15, 0)
+
+#define _TRANS_VRR_VMAXSHIFT_A          0x60428
+#define _TRANS_VRR_VMAXSHIFT_B          0x61428
+#define _TRANS_VRR_VMAXSHIFT_C          0x62428
+#define _TRANS_VRR_VMAXSHIFT_D          0x63428
+#define TRANS_VRR_VMAXSHIFT(dev_priv, trans)    _MMIO_TRANS2(dev_priv, trans, \
+					_TRANS_VRR_VMAXSHIFT_A)
+#define   VRR_VMAXSHIFT_DEC_MASK        REG_GENMASK(29, 16)
+#define   VRR_VMAXSHIFT_DEC             REG_BIT(16)
+#define   VRR_VMAXSHIFT_INC_MASK        REG_GENMASK(12, 0)
+
+#define _TRANS_VRR_STATUS_A             0x6042C
+#define _TRANS_VRR_STATUS_B             0x6142C
+#define _TRANS_VRR_STATUS_C             0x6242C
+#define _TRANS_VRR_STATUS_D             0x6342C
+#define TRANS_VRR_STATUS(dev_priv, trans)       _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
+#define   VRR_STATUS_VMAX_REACHED       REG_BIT(31)
+#define   VRR_STATUS_NOFLIP_TILL_BNDR   REG_BIT(30)
+#define   VRR_STATUS_FLIP_BEF_BNDR      REG_BIT(29)
+#define   VRR_STATUS_NO_FLIP_FRAME      REG_BIT(28)
+#define   VRR_STATUS_VRR_EN_LIVE        REG_BIT(27)
+#define   VRR_STATUS_FLIPS_SERVICED     REG_BIT(26)
+#define   VRR_STATUS_VBLANK_MASK        REG_GENMASK(22, 20)
+#define   STATUS_FSM_IDLE               REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
+#define   STATUS_FSM_WAIT_TILL_FDB      REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
+#define   STATUS_FSM_WAIT_TILL_FS       REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
+#define   STATUS_FSM_WAIT_TILL_FLIP     REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
+#define   STATUS_FSM_PIPELINE_FILL      REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
+#define   STATUS_FSM_ACTIVE             REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
+#define   STATUS_FSM_LEGACY_VBLANK      REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
+
+#define _TRANS_VRR_VTOTAL_PREV_A        0x60480
+#define _TRANS_VRR_VTOTAL_PREV_B        0x61480
+#define _TRANS_VRR_VTOTAL_PREV_C        0x62480
+#define _TRANS_VRR_VTOTAL_PREV_D        0x63480
+#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans)  _MMIO_TRANS2(dev_priv, trans, \
+					_TRANS_VRR_VTOTAL_PREV_A)
+#define   VRR_VTOTAL_FLIP_BEFR_BNDR     REG_BIT(31)
+#define   VRR_VTOTAL_FLIP_AFTER_BNDR    REG_BIT(30)
+#define   VRR_VTOTAL_FLIP_AFTER_DBLBUF  REG_BIT(29)
+#define   VRR_VTOTAL_PREV_FRAME_MASK    REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_FLIPLINE_A           0x60438
+#define _TRANS_VRR_FLIPLINE_B           0x61438
+#define _TRANS_VRR_FLIPLINE_C           0x62438
+#define _TRANS_VRR_FLIPLINE_D           0x63438
+#define TRANS_VRR_FLIPLINE(dev_priv, trans)     _MMIO_TRANS2(dev_priv, trans, \
+					_TRANS_VRR_FLIPLINE_A)
+#define   VRR_FLIPLINE_MASK             REG_GENMASK(19, 0)
+
+#define _TRANS_VRR_STATUS2_A            0x6043C
+#define _TRANS_VRR_STATUS2_B            0x6143C
+#define _TRANS_VRR_STATUS2_C            0x6243C
+#define _TRANS_VRR_STATUS2_D            0x6343C
+#define TRANS_VRR_STATUS2(dev_priv, trans)      _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
+#define   VRR_STATUS2_VERT_LN_CNT_MASK  REG_GENMASK(19, 0)
+
+#define _TRANS_PUSH_A                   0x60A70
+#define _TRANS_PUSH_B                   0x61A70
+#define _TRANS_PUSH_C                   0x62A70
+#define _TRANS_PUSH_D                   0x63A70
+#define TRANS_PUSH(dev_priv, trans)             _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
+#define   TRANS_PUSH_EN                 REG_BIT(31)
+#define   TRANS_PUSH_SEND               REG_BIT(30)
+
+#define _TRANS_VRR_VSYNC_A              0x60078
+#define TRANS_VRR_VSYNC(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
+#define VRR_VSYNC_END_MASK              REG_GENMASK(28, 16)
+#define VRR_VSYNC_END(vsync_end)        REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
+#define VRR_VSYNC_START_MASK            REG_GENMASK(12, 0)
+#define VRR_VSYNC_START(vsync_start)    REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
+
+#endif /* __INTEL_VRR_REGS__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6b39211b5469..7356d6e0e071 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1147,107 +1147,6 @@
 #define PIPESRC(pipe)		_MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC)
 #define TRANS_MULT(trans)	_MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A)
 
-/* VRR registers */
-#define _TRANS_VRR_CTL_A		0x60420
-#define _TRANS_VRR_CTL_B		0x61420
-#define _TRANS_VRR_CTL_C		0x62420
-#define _TRANS_VRR_CTL_D		0x63420
-#define TRANS_VRR_CTL(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A)
-#define   VRR_CTL_VRR_ENABLE			REG_BIT(31)
-#define   VRR_CTL_IGN_MAX_SHIFT			REG_BIT(30)
-#define   VRR_CTL_FLIP_LINE_EN			REG_BIT(29)
-#define   VRR_CTL_PIPELINE_FULL_MASK		REG_GENMASK(10, 3)
-#define   VRR_CTL_PIPELINE_FULL(x)		REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
-#define   VRR_CTL_PIPELINE_FULL_OVERRIDE	REG_BIT(0)
-#define	  XELPD_VRR_CTL_VRR_GUARDBAND_MASK	REG_GENMASK(15, 0)
-#define	  XELPD_VRR_CTL_VRR_GUARDBAND(x)	REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, \
-								(x))
-
-#define _TRANS_VRR_VMAX_A		0x60424
-#define _TRANS_VRR_VMAX_B		0x61424
-#define _TRANS_VRR_VMAX_C		0x62424
-#define _TRANS_VRR_VMAX_D		0x63424
-#define TRANS_VRR_VMAX(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A)
-#define   VRR_VMAX_MASK			REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_VMIN_A		0x60434
-#define _TRANS_VRR_VMIN_B		0x61434
-#define _TRANS_VRR_VMIN_C		0x62434
-#define _TRANS_VRR_VMIN_D		0x63434
-#define TRANS_VRR_VMIN(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A)
-#define   VRR_VMIN_MASK			REG_GENMASK(15, 0)
-
-#define _TRANS_VRR_VMAXSHIFT_A		0x60428
-#define _TRANS_VRR_VMAXSHIFT_B		0x61428
-#define _TRANS_VRR_VMAXSHIFT_C		0x62428
-#define _TRANS_VRR_VMAXSHIFT_D		0x63428
-#define TRANS_VRR_VMAXSHIFT(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, \
-					_TRANS_VRR_VMAXSHIFT_A)
-#define   VRR_VMAXSHIFT_DEC_MASK	REG_GENMASK(29, 16)
-#define   VRR_VMAXSHIFT_DEC		REG_BIT(16)
-#define   VRR_VMAXSHIFT_INC_MASK	REG_GENMASK(12, 0)
-
-#define _TRANS_VRR_STATUS_A		0x6042C
-#define _TRANS_VRR_STATUS_B		0x6142C
-#define _TRANS_VRR_STATUS_C		0x6242C
-#define _TRANS_VRR_STATUS_D		0x6342C
-#define TRANS_VRR_STATUS(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A)
-#define   VRR_STATUS_VMAX_REACHED	REG_BIT(31)
-#define   VRR_STATUS_NOFLIP_TILL_BNDR	REG_BIT(30)
-#define   VRR_STATUS_FLIP_BEF_BNDR	REG_BIT(29)
-#define   VRR_STATUS_NO_FLIP_FRAME	REG_BIT(28)
-#define   VRR_STATUS_VRR_EN_LIVE	REG_BIT(27)
-#define   VRR_STATUS_FLIPS_SERVICED	REG_BIT(26)
-#define   VRR_STATUS_VBLANK_MASK	REG_GENMASK(22, 20)
-#define   STATUS_FSM_IDLE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 0)
-#define   STATUS_FSM_WAIT_TILL_FDB	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 1)
-#define   STATUS_FSM_WAIT_TILL_FS	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 2)
-#define   STATUS_FSM_WAIT_TILL_FLIP	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 3)
-#define   STATUS_FSM_PIPELINE_FILL	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 4)
-#define   STATUS_FSM_ACTIVE		REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 5)
-#define   STATUS_FSM_LEGACY_VBLANK	REG_FIELD_PREP(VRR_STATUS_VBLANK_MASK, 6)
-
-#define _TRANS_VRR_VTOTAL_PREV_A	0x60480
-#define _TRANS_VRR_VTOTAL_PREV_B	0x61480
-#define _TRANS_VRR_VTOTAL_PREV_C	0x62480
-#define _TRANS_VRR_VTOTAL_PREV_D	0x63480
-#define TRANS_VRR_VTOTAL_PREV(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, \
-					_TRANS_VRR_VTOTAL_PREV_A)
-#define   VRR_VTOTAL_FLIP_BEFR_BNDR	REG_BIT(31)
-#define   VRR_VTOTAL_FLIP_AFTER_BNDR	REG_BIT(30)
-#define   VRR_VTOTAL_FLIP_AFTER_DBLBUF	REG_BIT(29)
-#define   VRR_VTOTAL_PREV_FRAME_MASK	REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_FLIPLINE_A		0x60438
-#define _TRANS_VRR_FLIPLINE_B		0x61438
-#define _TRANS_VRR_FLIPLINE_C		0x62438
-#define _TRANS_VRR_FLIPLINE_D		0x63438
-#define TRANS_VRR_FLIPLINE(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, \
-					_TRANS_VRR_FLIPLINE_A)
-#define   VRR_FLIPLINE_MASK		REG_GENMASK(19, 0)
-
-#define _TRANS_VRR_STATUS2_A		0x6043C
-#define _TRANS_VRR_STATUS2_B		0x6143C
-#define _TRANS_VRR_STATUS2_C		0x6243C
-#define _TRANS_VRR_STATUS2_D		0x6343C
-#define TRANS_VRR_STATUS2(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A)
-#define   VRR_STATUS2_VERT_LN_CNT_MASK	REG_GENMASK(19, 0)
-
-#define _TRANS_PUSH_A			0x60A70
-#define _TRANS_PUSH_B			0x61A70
-#define _TRANS_PUSH_C			0x62A70
-#define _TRANS_PUSH_D			0x63A70
-#define TRANS_PUSH(dev_priv, trans)		_MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A)
-#define   TRANS_PUSH_EN			REG_BIT(31)
-#define   TRANS_PUSH_SEND		REG_BIT(30)
-
-#define _TRANS_VRR_VSYNC_A		0x60078
-#define TRANS_VRR_VSYNC(dev_priv, trans)	_MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A)
-#define VRR_VSYNC_END_MASK		REG_GENMASK(28, 16)
-#define VRR_VSYNC_END(vsync_end)	REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end))
-#define VRR_VSYNC_START_MASK		REG_GENMASK(12, 0)
-#define VRR_VSYNC_START(vsync_start)	REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
-
 /* VGA port control */
 #define ADPA			_MMIO(0x61100)
 #define PCH_ADPA                _MMIO(0xe1100)
-- 
2.25.1

[PATCH v12 5/9] drm/i915: Define and compute Transcoder CMRR registers

[Mitul Golani]

Add register definitions for Transcoder Fixed Average
Vtotal mode/CMRR function, with the necessary bitfields.
Compute these registers when CMRR is enabled, extending
Adaptive refresh rate capabilities.

--v2:
- Use intel_de_read64_2x32 in intel_vrr_get_config. [Jani]
- Fix indent and order based on register offset. [Jani]

--v3:
- Removing RFC tag.

--v4:
- Update place holder for CMRR register definition. (Jani)

--v5:
- Add CMRR register definitions to a separate file intel_vrr_reg.h.

--v6:
- Fixed indentation. (Jani)
- Add dependency header intel_display_reg_defs.h. (Jani)
- Rename file name to intel_vrr_regs.h instead of reg.h (Jani)

--v7:
- Remove adding CMRR flag to vrr_ctl register during set_transcoder_timing,
as it is already being done during intel_vrr_enable. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 23 ++++++++++++++++++-
 .../drm/i915/display/intel_display_types.h    |  6 +++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 20 ++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr_regs.h | 14 +++++++++++
 4 files changed, 62 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7370acdd6b8b..29d750d2e6f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1005,6 +1005,13 @@ static bool vrr_params_changed(const struct intel_crtc_state *old_crtc_state,
 		old_crtc_state->vrr.pipeline_full != new_crtc_state->vrr.pipeline_full;
 }
 
+static bool cmrr_params_changed(const struct intel_crtc_state *old_crtc_state,
+				const struct intel_crtc_state *new_crtc_state)
+{
+	return old_crtc_state->cmrr.cmrr_m != new_crtc_state->cmrr.cmrr_m ||
+		old_crtc_state->cmrr.cmrr_n != new_crtc_state->cmrr.cmrr_n;
+}
+
 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 			 const struct intel_crtc_state *new_crtc_state)
 {
@@ -5054,6 +5061,16 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	} \
 } while (0)
 
+#define PIPE_CONF_CHECK_LLI(name) do { \
+	if (current_config->name != pipe_config->name) { \
+		pipe_config_mismatch(&p, fastset, crtc, __stringify(name), \
+				     "(expected %lli, found %lli)", \
+				     current_config->name, \
+				     pipe_config->name); \
+		ret = false; \
+	} \
+} while (0)
+
 #define PIPE_CONF_CHECK_BOOL(name) do { \
 	if (current_config->name != pipe_config->name) { \
 		BUILD_BUG_ON_MSG(!__same_type(current_config->name, bool), \
@@ -5432,10 +5449,13 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 		PIPE_CONF_CHECK_I(vrr.guardband);
 		PIPE_CONF_CHECK_I(vrr.vsync_start);
 		PIPE_CONF_CHECK_I(vrr.vsync_end);
+		PIPE_CONF_CHECK_LLI(cmrr.cmrr_m);
+		PIPE_CONF_CHECK_LLI(cmrr.cmrr_n);
 	}
 
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
+#undef PIPE_CONF_CHECK_LLI
 #undef PIPE_CONF_CHECK_BOOL
 #undef PIPE_CONF_CHECK_P
 #undef PIPE_CONF_CHECK_FLAGS
@@ -6824,7 +6844,8 @@ static void intel_pre_update_crtc(struct intel_atomic_state *state,
 		    intel_crtc_needs_fastset(new_crtc_state))
 			icl_set_pipe_chicken(new_crtc_state);
 
-		if (vrr_params_changed(old_crtc_state, new_crtc_state))
+		if (vrr_params_changed(old_crtc_state, new_crtc_state) ||
+		    cmrr_params_changed(old_crtc_state, new_crtc_state))
 			intel_vrr_set_transcoder_timings(new_crtc_state);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 77609656317b..62ed3c9db94a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1401,6 +1401,12 @@ struct intel_crtc_state {
 		u32 vsync_end, vsync_start;
 	} vrr;
 
+	/* Content Match Refresh Rate state */
+	struct {
+		bool enable;
+		u64 cmrr_n, cmrr_m;
+	} cmrr;
+
 	/* Stream Splitter for eDP MSO */
 	struct {
 		bool enable;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 871e6e6a184a..d2f854d9d18b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -219,6 +219,17 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
 		return;
 	}
 
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(dev_priv, TRANS_CMRR_M_HI(dev_priv, cpu_transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_m));
+		intel_de_write(dev_priv, TRANS_CMRR_N_HI(dev_priv, cpu_transcoder),
+			       upper_32_bits(crtc_state->cmrr.cmrr_n));
+		intel_de_write(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+			       lower_32_bits(crtc_state->cmrr.cmrr_n));
+	}
+
 	intel_de_write(dev_priv, TRANS_VRR_VMIN(dev_priv, cpu_transcoder),
 		       crtc_state->vrr.vmin - 1);
 	intel_de_write(dev_priv, TRANS_VRR_VMAX(dev_priv, cpu_transcoder),
@@ -307,6 +318,15 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state)
 
 	crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE;
 
+	if (crtc_state->cmrr.enable) {
+		crtc_state->cmrr.cmrr_n =
+			intel_de_read64_2x32(dev_priv, TRANS_CMRR_N_LO(dev_priv, cpu_transcoder),
+					     TRANS_CMRR_N_HI(dev_priv, cpu_transcoder));
+		crtc_state->cmrr.cmrr_m =
+			intel_de_read64_2x32(dev_priv, TRANS_CMRR_M_LO(dev_priv, cpu_transcoder),
+					     TRANS_CMRR_M_HI(dev_priv, cpu_transcoder));
+	}
+
 	if (DISPLAY_VER(dev_priv) >= 13)
 		crtc_state->vrr.guardband =
 			REG_FIELD_GET(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, trans_vrr_ctl);
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index d4eb74ee72a7..1aeb0cd45068 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -109,4 +109,18 @@
 #define VRR_VSYNC_START_MASK            REG_GENMASK(12, 0)
 #define VRR_VSYNC_START(vsync_start)    REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start))
 
+/*CMRR Registers*/
+
+#define _TRANS_CMRR_M_LO_A			0x604F0
+#define TRANS_CMRR_M_LO(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_LO_A)
+
+#define _TRANS_CMRR_M_HI_A			0x604F4
+#define TRANS_CMRR_M_HI(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_M_HI_A)
+
+#define _TRANS_CMRR_N_LO_A			0x604F8
+#define TRANS_CMRR_N_LO(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_LO_A)
+
+#define _TRANS_CMRR_N_HI_A			0x604FC
+#define TRANS_CMRR_N_HI(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
+
 #endif /* __INTEL_VRR_REGS__ */
-- 
2.25.1

[PATCH v12 6/9] drm/i915: Update trans_vrr_ctl flag when cmrr is computed

[Mitul Golani]

Add/update trans_vrr_ctl flag when crtc_state->cmrr.enable
is set, With this commit setting the stage for subsequent
CMRR enablement.

--v2:
- Check pipe active state in cmrr enabling. [Jani]
- Remove usage of bitwise OR on booleans. [Jani]
- Revert unrelated changes. [Jani]
- Update intel_vrr_enable, vrr and cmrr enable conditions. [Jani]
- Simplify whole if-ladder in intel_vrr_enable. [Jani]
- Revert patch restructuring mistakes in intel_vrr_get_config. [Jani]

--v3:
- Check pipe active state in cmrr disabling.[Jani]
- Correct messed up condition in intel_vrr_enable. [Jani]

--v4:
- Removing RFC tag.

--v5:
- CMRR handling in co-existatnce of LRR and DRRS.

--v7:
- Rebase on top of AS SDP merge.

--v8:
- Remove cmrr_enabling/disabling and update commit message. (Ankit)

--v9:
- Revert removed line(Ankit).

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c      | 10 ++++++++--
 drivers/gpu/drm/i915/display/intel_vrr_regs.h |  2 ++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index d2f854d9d18b..19b364074de0 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -282,8 +282,14 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state)
 			       VRR_VSYNC_END(crtc_state->vrr.vsync_end) |
 			       VRR_VSYNC_START(crtc_state->vrr.vsync_start));
 
-	intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
-		       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	if (crtc_state->cmrr.enable) {
+		intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+			       VRR_CTL_VRR_ENABLE | VRR_CTL_CMRR_ENABLE |
+			       trans_vrr_ctl(crtc_state));
+	} else {
+		intel_de_write(dev_priv, TRANS_VRR_CTL(dev_priv, cpu_transcoder),
+			       VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state));
+	}
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
index 1aeb0cd45068..577b0abb66db 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
@@ -123,4 +123,6 @@
 #define _TRANS_CMRR_N_HI_A			0x604FC
 #define TRANS_CMRR_N_HI(dev_priv, trans)        _MMIO_TRANS2(dev_priv, trans, _TRANS_CMRR_N_HI_A)
 
+#define VRR_CTL_CMRR_ENABLE			REG_BIT(27)
+
 #endif /* __INTEL_VRR_REGS__ */
-- 
2.25.1

[PATCH v12 7/9] drm/dp: Add refresh rate divider to struct representing AS SDP

[Mitul Golani]

Add target_rr_divider to structure representing AS SDP.
It is valid only in FAVT mode, sink device ignores the bit in AVT
mode.

--v2:
- Update commit header and send patch to dri-devel.

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Arun R Murthy <arun.r.murthy@intel.com>
---
 include/drm/display/drm_dp_helper.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/include/drm/display/drm_dp_helper.h b/include/drm/display/drm_dp_helper.h
index 8defcc399f42..ea03e1dd26ba 100644
--- a/include/drm/display/drm_dp_helper.h
+++ b/include/drm/display/drm_dp_helper.h
@@ -122,6 +122,7 @@ struct drm_dp_as_sdp {
 	int target_rr;
 	int duration_incr_ms;
 	int duration_decr_ms;
+	bool target_rr_divider;
 	enum operation_mode mode;
 };
 
-- 
2.25.1

[PATCH v12 8/9] drm/i915/display: Add support for pack and unpack

[Mitul Golani]

Add support of pack and unpack for target_rr_divider.

--v2:
- Set Target Refresh Rate Divider bit when related
AS SDP bit is set (Ankit).

--v3:
- target_rr_divider is bools so set accordingly (Ankit).
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index fd054e16850d..ac81b172b1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4232,6 +4232,9 @@ static ssize_t intel_dp_as_sdp_pack(const struct drm_dp_as_sdp *as_sdp,
 	sdp->db[3] = as_sdp->target_rr & 0xFF;
 	sdp->db[4] = (as_sdp->target_rr >> 8) & 0x3;
 
+	if (as_sdp->target_rr_divider)
+		sdp->db[4] |= 0x20;
+
 	return length;
 }
 
@@ -4413,6 +4416,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
 	as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
 	as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
 	as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
+	as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
 
 	return 0;
 }
-- 
2.25.1

[PATCH v12 9/9] drm/i915/display: Compute Adaptive sync SDP params

[Mitul Golani]

Compute params for Adaptive Sync SDP when Fixed Average Vtotal
mode is enabled.

--v2:
Since vrr.enable is set in case of cmrr also, handle accordingly(Ankit).

--v3:
- Since vrr.enable is set in case of cmrr also, handle
accordingly(Ankit).
- check cmrr.enable when CMRR flags are set during intel_dp_compute_as_sdp.

--v4:
- Use drm_mode_vrefresh instead of manual calculation (Ankit).

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.golani@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 14 +++++++++++---
 1 file changed, 11 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ac81b172b1ec..b5915c23302f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2637,11 +2637,19 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 	/* Currently only DP_AS_SDP_AVT_FIXED_VTOTAL mode supported */
 	as_sdp->sdp_type = DP_SDP_ADAPTIVE_SYNC;
 	as_sdp->length = 0x9;
-	as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
-	as_sdp->vtotal = adjusted_mode->vtotal;
-	as_sdp->target_rr = 0;
 	as_sdp->duration_incr_ms = 0;
 	as_sdp->duration_incr_ms = 0;
+
+	if (crtc_state->cmrr.enable) {
+		as_sdp->mode = DP_AS_SDP_FAVT_TRR_REACHED;
+		as_sdp->vtotal = adjusted_mode->vtotal;
+		as_sdp->target_rr = drm_mode_vrefresh(adjusted_mode);
+		as_sdp->target_rr_divider = true;
+	} else {
+		as_sdp->mode = DP_AS_SDP_AVT_FIXED_VTOTAL;
+		as_sdp->vtotal = adjusted_mode->vtotal;
+		as_sdp->target_rr = 0;
+	}
 }
 
 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-- 
2.25.1

✗ Fi.CI.BUILD: failure for Implement CMRR Support (rev12)

[Patchwork]

== Series Details ==

Series: Implement CMRR Support (rev12)
URL   : https://patchwork.freedesktop.org/series/126443/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/126443/revisions/12/mbox/ not applied
Applying: drm/i915: Protect CRC reg macro arguments for consistency
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_pipe_crc_regs.h
Falling back to patching base and 3-way merge...
No changes -- Patch already applied.
Applying: drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest
Using index info to reconstruct a base tree...
Falling back to patching base and 3-way merge...
CONFLICT (add/add): Merge conflict in integration-manifest
Auto-merging integration-manifest
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0002 drm-tip: 2024y-06m-05d-09h-52m-50s UTC integration manifest
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced