[PATCH 00/32] drm/i915/display: Add initial support for Xe3p_LPD

[PATCH 00/32] drm/i915/display: Add initial support for Xe3p_LPD

[Gustavo Sousa]

This series adds initial support for Xe3p_LPD, Intel's display
architecture with IP version 35.

This series contains basic enabling patches and does not provide
complete support for the display IP yet. More involved features, like
the new PHY implementation and ALPM will come as separate patch series.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
Ankit Nautiyal (1):
      drm/i915/xe3p_lpd: Drop support for interlace mode

Gustavo Sousa (12):
      drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()
      drm/i915/dram: Add field ecc_impacting_de
      drm/i915/xe3p_lpd: Wait for AUX channel power status
      drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment
      drm/i915/xe3p_lpd: Add CDCLK table
      drm/i915/xe3p_lpd: Load DMC firmware
      drm/i915/xe3p_lpd: Extend Wa_16025573575
      drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D
      drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc
      drm/i915/power: Use intel_encoder_is_tc()
      drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()
      drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation

Jouni Högander (1):
      drm/i915/xe3p_lpd: PSR SU minimum lines is 4

Juha-pekka Heikkila (1):
      drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format

Luca Coelho (1):
      drm/i915/wm: don't use method1 in Xe3p_LPD onwards

Matt Atwood (1):
      drm/i915/xe3p_lpd: Update bandwidth parameters

Matt Roper (2):
      drm/xe/nvl: Define NVL-S platform
      drm/i915/xe3p_lpd: Drop north display reset option programming

Ravi Kumar Vodapalli (1):
      drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

Sai Teja Pottumuttu (8):
      drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features
      drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields
      drm/i915/xe3p_lpd: Support UINT16 formats
      drm/i915/xe3p_lpd: Extend FBC support to UINT16 formats
      drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces
      drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints
      drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks
      drm/i915/nvls: Add NVL-S display support

Vinod Govindapillai (4):
      drm/i915/xe3p_lpd: Enable system caching for FBC
      drm/i915/xe3p_lpd: Introduce pixel normalizer config support
      drm/i915/xe3p_lpd: Add FBC support for FP16 formats
      drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC

 drivers/gpu/drm/i915/display/intel_bios.c          |  20 ++-
 drivers/gpu/drm/i915/display/intel_bios.h          |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c            |  48 ++++--
 drivers/gpu/drm/i915/display/intel_cdclk.c         |  44 +++++-
 drivers/gpu/drm/i915/display/intel_color.c         |  13 +-
 drivers/gpu/drm/i915/display/intel_ddi.c           |   7 +
 drivers/gpu/drm/i915/display/intel_display.c       |  33 ++++-
 .../gpu/drm/i915/display/intel_display_device.c    |   6 +
 .../gpu/drm/i915/display/intel_display_device.h    |   4 +-
 drivers/gpu/drm/i915/display/intel_display_power.c |   3 +
 .../drm/i915/display/intel_display_power_well.c    |  58 ++++++--
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  51 ++++++-
 drivers/gpu/drm/i915/display/intel_display_types.h |   4 +
 drivers/gpu/drm/i915/display/intel_display_wa.c    |   3 +-
 drivers/gpu/drm/i915/display/intel_dmc.c           |  12 +-
 drivers/gpu/drm/i915/display/intel_fbc.c           | 126 +++++++++++++++-
 drivers/gpu/drm/i915/display/intel_fbc.h           |   1 +
 drivers/gpu/drm/i915/display/intel_fbc_regs.h      |   9 ++
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 100 ++++++++++++-
 drivers/gpu/drm/i915/display/intel_plane.c         |   3 +
 drivers/gpu/drm/i915/display/intel_psr.c           |  25 ++++
 drivers/gpu/drm/i915/display/intel_tc.c            | 151 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h      |   7 +-
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 162 +++++++++++++++------
 .../drm/i915/display/skl_universal_plane_regs.h    |  25 +++-
 drivers/gpu/drm/i915/display/skl_watermark.c       |  25 +++-
 drivers/gpu/drm/i915/display/skl_watermark_regs.h  |  12 +-
 drivers/gpu/drm/i915/i915_reg.h                    |   1 +
 drivers/gpu/drm/i915/soc/intel_dram.c              |   4 +
 drivers/gpu/drm/i915/soc/intel_dram.h              |   1 +
 drivers/gpu/drm/xe/xe_pci.c                        |   9 ++
 drivers/gpu/drm/xe/xe_platform_types.h             |   1 +
 include/drm/intel/pciids.h                         |   9 ++
 33 files changed, 861 insertions(+), 118 deletions(-)
---
base-commit: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb
change-id: 20251014-xe3p_lpd-basic-enabling-eb4424698b44

Best regards,
--  
Gustavo Sousa <gustavo.sousa@intel.com>

[PATCH 01/32] drm/xe/nvl: Define NVL-S platform

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

Provide the basic platform definitions and PCI IDs for NVL-S.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
This is brought as a dependency from the series for Xe,
https://patchwork.freedesktop.org/series/155866/, so the display side
can be reviewed independently.
---
 drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
 drivers/gpu/drm/xe/xe_platform_types.h | 1 +
 include/drm/intel/pciids.h             | 9 +++++++++
 3 files changed, 19 insertions(+)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 24a38904bb50..cc29678be1fa 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -373,6 +373,14 @@ static const struct xe_device_desc ptl_desc = {
 	.vm_max_level = 4,
 };
 
+static const struct xe_device_desc nvls_desc = {
+	PLATFORM(NOVALAKE_S),
+	.dma_mask_size = 46,
+	.has_display = true,
+	.max_gt_per_tile = 2,
+	.require_force_probe = true,
+};
+
 #undef PLATFORM
 __diag_pop();
 
@@ -401,6 +409,7 @@ static const struct pci_device_id pciidlist[] = {
 	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
 	{ }
 };
 MODULE_DEVICE_TABLE(pci, pciidlist);
diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
index 3e332214c7bb..78286285c249 100644
--- a/drivers/gpu/drm/xe/xe_platform_types.h
+++ b/drivers/gpu/drm/xe/xe_platform_types.h
@@ -24,6 +24,7 @@ enum xe_platform {
 	XE_LUNARLAKE,
 	XE_BATTLEMAGE,
 	XE_PANTHERLAKE,
+	XE_NOVALAKE_S,
 };
 
 enum xe_subplatform {
diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
index 452c1de606ff..13c592e1a28c 100644
--- a/include/drm/intel/pciids.h
+++ b/include/drm/intel/pciids.h
@@ -887,4 +887,13 @@
 	MACRO__(0xFD80, ## __VA_ARGS__), \
 	MACRO__(0xFD81, ## __VA_ARGS__)
 
+/* NVL-S */
+#define INTEL_NVLS_IDS(MACRO__, ...) \
+	MACRO__(0xD740, ## __VA_ARGS__), \
+	MACRO__(0xD741, ## __VA_ARGS__), \
+	MACRO__(0xD742, ## __VA_ARGS__), \
+	MACRO__(0xD743, ## __VA_ARGS__), \
+	MACRO__(0xD744, ## __VA_ARGS__), \
+	MACRO__(0xD745, ## __VA_ARGS__)
+
 #endif /* __PCIIDS_H__ */

-- 
2.51.0

[PATCH 02/32] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Xe3p_LPD (display version 35) is similar to Xe2_LPD with respect to the
features described by struct intel_display_device_info, so reuse its
device descriptor.

Bspec: 74304
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index f3f1f25b0f38..a38de39ed98c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1507,6 +1507,7 @@ static const struct {
 	{ 20,  0, &xe2_lpd_display },
 	{ 30,  0, &xe2_lpd_display },
 	{ 30,  2, &wcl_display },
+	{ 35,  0, &xe2_lpd_display },
 };
 
 static const struct intel_display_device_info *

-- 
2.51.0

[PATCH 03/32] drm/i915/xe3p_lpd: Drop north display reset option programming

[Gustavo Sousa]

From: Matt Roper <matthew.d.roper@intel.com>

The NDE_RSTWRN_OPT has been removed on Xe3p platforms and reset option
programming is no longer necessary during display init.

Bspec: 68846, 69137
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index da4babfd6bcb..821f5097e9c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1436,6 +1436,9 @@ static void intel_pch_reset_handshake(struct intel_display *display,
 	i915_reg_t reg;
 	u32 reset_bits;
 
+	if (DISPLAY_VER(display) >= 35)
+		return;
+
 	if (display->platform.ivybridge) {
 		reg = GEN7_MSG_CTL;
 		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;

-- 
2.51.0

[PATCH 04/32] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()

[Gustavo Sousa]

Looking at the current if-ladder in intel_bw_init_hw(), we see that
Xe2_HPD contains two entries, differing only for ECC memories.  In an
upcoming change for Xe3p_LPD, we will have a similar case.

Let's improving readability by using braces and allowing adding extra
conditions for each case.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index b53bcb693e79..8f5b86cd91b6 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -812,29 +812,30 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (!HAS_DISPLAY(display))
 		return;
 
-	if (DISPLAY_VERx100(display) >= 3002)
+	if (DISPLAY_VERx100(display) >= 3002) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
-	else if (DISPLAY_VER(display) >= 30)
+	} else if (DISPLAY_VER(display) >= 30) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
-	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
-		 dram_info->type == INTEL_DRAM_GDDR_ECC)
-		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
-	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
-		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
-	else if (DISPLAY_VER(display) >= 14)
+	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
+		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
+			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
+		else
+			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
+	} else if (DISPLAY_VER(display) >= 14) {
 		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
-	else if (display->platform.dg2)
+	} else if (display->platform.dg2) {
 		dg2_get_bw_info(display);
-	else if (display->platform.alderlake_p)
+	} else if (display->platform.alderlake_p) {
 		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
-	else if (display->platform.alderlake_s)
+	} else if (display->platform.alderlake_s) {
 		tgl_get_bw_info(display, dram_info, &adls_sa_info);
-	else if (display->platform.rocketlake)
+	} else if (display->platform.rocketlake) {
 		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
-	else if (DISPLAY_VER(display) == 12)
+	} else if (DISPLAY_VER(display) == 12) {
 		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
-	else if (DISPLAY_VER(display) == 11)
+	} else if (DISPLAY_VER(display) == 11) {
 		icl_get_bw_info(display, dram_info, &icl_sa_info);
+	}
 }
 
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)

-- 
2.51.0

[PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de

[Gustavo Sousa]

Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
that indicates whether the memory has enabled ECC that limits display
bandwidth.  Add the field ecc_impacting_de to struct dram_info to
contain that information and set it appropriately when probing for
memory info.  We will use that field when updating bandwidth parameters
for Xe3p_LPD.

Bspec: 69131
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h       | 1 +
 drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
 drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
 3 files changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 354ef75ef6a5..5bf3b4ab2baa 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1233,6 +1233,7 @@
 #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
 
 #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
+#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
 #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
 #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
 #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
index 8841cfe1cac8..bf9f8e38d6ba 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.c
+++ b/drivers/gpu/drm/i915/soc/intel_dram.c
@@ -685,6 +685,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
 
 static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
 {
+	struct intel_display *display = i915->display;
 	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
 
 	switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
@@ -723,6 +724,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
 	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
 	/* PSF GV points not supported in D14+ */
 
+	if (DISPLAY_VER(display) >= 35)
+		dram_info->ecc_impacting_de = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
index 03a973f1c941..ac77f1ab409f 100644
--- a/drivers/gpu/drm/i915/soc/intel_dram.h
+++ b/drivers/gpu/drm/i915/soc/intel_dram.h
@@ -30,6 +30,7 @@ struct dram_info {
 	u8 num_channels;
 	u8 num_qgv_points;
 	u8 num_psf_gv_points;
+	bool ecc_impacting_de; /* Only valid from Xe3p_LPD onward. */
 	bool symmetric_memory;
 	bool has_16gb_dimms;
 };

-- 
2.51.0

[PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters

[Gustavo Sousa]

From: Matt Atwood <matthew.s.atwood@intel.com>

Bandwidth parameters for Xe3p_LPD are basically the same as for Xe3_LPD.
However, now Xe3p_LPD has the ecc_impacting_de field, which could impact
how the derating is defined.

For the cases where that field is true, we use xe3p_lpd_ecc_sa_info,
similarly to what was done for Xe2_HPD.  Note, however, that Bspec
specifies the ECC derating value only for GDDR memory.  For now, we just
re-use the value that was defined for Xe2_HPD, namely 45.  We need to
confirm with the hardware team what would be the correct value(s) to use
for the ECC case.

Bspec: 68859, 69131
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8f5b86cd91b6..f0940ff9d19b 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -461,6 +461,20 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
 	.derating = 10,
 };
 
+static const struct intel_sa_info xe3p_lpd_ecc_sa_info = {
+	.deburst = 32,
+	.deprogbwlimit = 65, /* GB/s */
+	.displayrtids = 256,
+	/*
+	 * FIXME: The Bspec only shows that derating for ECC should be 45 for
+	 * GDDR memory and does not mention other types of memory.  For now, we
+	 * just re-use that value, but we need to confirm whether that is
+	 * correct or if there are different values depending on the memory
+	 * type.
+	 */
+	.derating = 45,
+};
+
 static int icl_get_bw_info(struct intel_display *display,
 			   const struct dram_info *dram_info,
 			   const struct intel_sa_info *sa)
@@ -812,7 +826,12 @@ void intel_bw_init_hw(struct intel_display *display)
 	if (!HAS_DISPLAY(display))
 		return;
 
-	if (DISPLAY_VERx100(display) >= 3002) {
+	if (DISPLAY_VER(display) >= 35) {
+		if (dram_info->ecc_impacting_de)
+			tgl_get_bw_info(display, dram_info, &xe3p_lpd_ecc_sa_info);
+		else
+			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
+	} else if (DISPLAY_VERx100(display) >= 3002) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
 	} else if (DISPLAY_VER(display) >= 30) {
 		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);

-- 
2.51.0

[PATCH 07/32] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

On Xe3p_LPD, the dbuf blocks fields of different registers are now
documented as 13-bit fields. The dbuf isn't really large enough to need
the 13th bit, but let's go ahead and update the definition now just in
case some new display IP in future ends up needing the larger size. The
extra bit is an unused bit in previous display versions, so we can
safely just extend the existing definition.

Bspec: 69847, 69880, 72053
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index ca9fdfbbe57c..479bb3f7f92b 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -324,7 +324,7 @@
 #define   PLANE_WM_IGNORE_LINES			REG_BIT(30)
 #define   PLANE_WM_AUTO_MIN_ALLOC_EN		REG_BIT(29)
 #define   PLANE_WM_LINES_MASK			REG_GENMASK(26, 14)
-#define   PLANE_WM_BLOCKS_MASK			REG_GENMASK(11, 0)
+#define   PLANE_WM_BLOCKS_MASK			REG_GENMASK(12, 0)
 
 #define _PLANE_WM_SAGV_1_A			0x70258
 #define _PLANE_WM_SAGV_1_B			0x71258
@@ -375,10 +375,10 @@
 							_PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
 							_PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
 
-/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
-#define   PLANE_BUF_END_MASK			REG_GENMASK(27, 16)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */
+#define   PLANE_BUF_END_MASK			REG_GENMASK(28, 16)
 #define   PLANE_BUF_END(end)			REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
-#define   PLANE_BUF_START_MASK			REG_GENMASK(11, 0)
+#define   PLANE_BUF_START_MASK			REG_GENMASK(12, 0)
 #define   PLANE_BUF_START(start)		REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
 
 #define _PLANE_MIN_BUF_CFG_1_A			0x70274
@@ -389,9 +389,9 @@
 							_PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
 							_PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
 #define	  PLANE_AUTO_MIN_DBUF_EN		REG_BIT(31)
-#define	  PLANE_MIN_DBUF_BLOCKS_MASK		REG_GENMASK(27, 16)
+#define	  PLANE_MIN_DBUF_BLOCKS_MASK		REG_GENMASK(28, 16)
 #define	  PLANE_MIN_DBUF_BLOCKS(val)		REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
-#define	  PLANE_INTERIM_DBUF_BLOCKS_MASK	REG_GENMASK(11, 0)
+#define	  PLANE_INTERIM_DBUF_BLOCKS_MASK	REG_GENMASK(12, 0)
 #define	  PLANE_INTERIM_DBUF_BLOCKS(val)	REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
 
 /* tgl+ */

-- 
2.51.0

[PATCH 08/32] drm/i915/xe3p_lpd: Support UINT16 formats

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Starting from display Xe3p_LPD, UINT16 formats are also supported. Add
its corresponding PLANE_CTL bit and add the format in the necessary
functions.

Bspec: 68904, 69853
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 96 +++++++++++++++-------
 .../drm/i915/display/skl_universal_plane_regs.h    |  1 +
 2 files changed, 68 insertions(+), 29 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 0319174adf95..530adff81b99 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -136,36 +136,47 @@ static const u32 icl_sdr_uv_plane_formats[] = {
 	DRM_FORMAT_XVYU2101010,
 };
 
+#define ICL_HDR_PLANE_FORMATS		\
+	DRM_FORMAT_C8,			\
+	DRM_FORMAT_RGB565,		\
+	DRM_FORMAT_XRGB8888,		\
+	DRM_FORMAT_XBGR8888,		\
+	DRM_FORMAT_ARGB8888,		\
+	DRM_FORMAT_ABGR8888,		\
+	DRM_FORMAT_XRGB2101010,		\
+	DRM_FORMAT_XBGR2101010,		\
+	DRM_FORMAT_ARGB2101010,		\
+	DRM_FORMAT_ABGR2101010,		\
+	DRM_FORMAT_XRGB16161616F,	\
+	DRM_FORMAT_XBGR16161616F,	\
+	DRM_FORMAT_ARGB16161616F,	\
+	DRM_FORMAT_ABGR16161616F,	\
+	DRM_FORMAT_YUYV,		\
+	DRM_FORMAT_YVYU,		\
+	DRM_FORMAT_UYVY,		\
+	DRM_FORMAT_VYUY,		\
+	DRM_FORMAT_NV12,		\
+	DRM_FORMAT_P010,		\
+	DRM_FORMAT_P012,		\
+	DRM_FORMAT_P016,		\
+	DRM_FORMAT_Y210,		\
+	DRM_FORMAT_Y212,		\
+	DRM_FORMAT_Y216,		\
+	DRM_FORMAT_XYUV8888,		\
+	DRM_FORMAT_XVYU2101010,		\
+	DRM_FORMAT_XVYU12_16161616,	\
+	DRM_FORMAT_XVYU16161616
+
 static const u32 icl_hdr_plane_formats[] = {
-	DRM_FORMAT_C8,
-	DRM_FORMAT_RGB565,
-	DRM_FORMAT_XRGB8888,
-	DRM_FORMAT_XBGR8888,
-	DRM_FORMAT_ARGB8888,
-	DRM_FORMAT_ABGR8888,
-	DRM_FORMAT_XRGB2101010,
-	DRM_FORMAT_XBGR2101010,
-	DRM_FORMAT_ARGB2101010,
-	DRM_FORMAT_ABGR2101010,
-	DRM_FORMAT_XRGB16161616F,
-	DRM_FORMAT_XBGR16161616F,
-	DRM_FORMAT_ARGB16161616F,
-	DRM_FORMAT_ABGR16161616F,
-	DRM_FORMAT_YUYV,
-	DRM_FORMAT_YVYU,
-	DRM_FORMAT_UYVY,
-	DRM_FORMAT_VYUY,
-	DRM_FORMAT_NV12,
-	DRM_FORMAT_P010,
-	DRM_FORMAT_P012,
-	DRM_FORMAT_P016,
-	DRM_FORMAT_Y210,
-	DRM_FORMAT_Y212,
-	DRM_FORMAT_Y216,
-	DRM_FORMAT_XYUV8888,
-	DRM_FORMAT_XVYU2101010,
-	DRM_FORMAT_XVYU12_16161616,
-	DRM_FORMAT_XVYU16161616,
+	ICL_HDR_PLANE_FORMATS,
+};
+
+static const u32 xe3p_lpd_hdr_plane_formats[] = {
+	ICL_HDR_PLANE_FORMATS,
+	DRM_FORMAT_XRGB16161616,
+	DRM_FORMAT_XBGR16161616,
+	DRM_FORMAT_ARGB16161616,
+	DRM_FORMAT_ABGR16161616,
 };
 
 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
@@ -220,6 +231,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 			else
 				return DRM_FORMAT_XRGB2101010;
 		}
+	case PLANE_CTL_FORMAT_XRGB_16161616:
+		if (rgb_order) {
+			if (alpha)
+				return DRM_FORMAT_ABGR16161616;
+			else
+				return DRM_FORMAT_XBGR16161616;
+		} else {
+			if (alpha)
+				return DRM_FORMAT_ARGB16161616;
+			else
+				return DRM_FORMAT_XRGB16161616;
+		}
 	case PLANE_CTL_FORMAT_XRGB_16161616F:
 		if (rgb_order) {
 			if (alpha)
@@ -960,6 +983,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
 	case DRM_FORMAT_XRGB2101010:
 	case DRM_FORMAT_ARGB2101010:
 		return PLANE_CTL_FORMAT_XRGB_2101010;
+	case DRM_FORMAT_XBGR16161616:
+	case DRM_FORMAT_ABGR16161616:
+		return PLANE_CTL_FORMAT_XRGB_16161616 | PLANE_CTL_ORDER_RGBX;
+	case DRM_FORMAT_XRGB16161616:
+	case DRM_FORMAT_ARGB16161616:
+		return PLANE_CTL_FORMAT_XRGB_16161616;
 	case DRM_FORMAT_XBGR16161616F:
 	case DRM_FORMAT_ABGR16161616F:
 		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
@@ -2479,6 +2508,11 @@ static const u32 *icl_get_plane_formats(struct intel_display *display,
 					int *num_formats)
 {
 	if (icl_is_hdr_plane(display, plane_id)) {
+		if (DISPLAY_VER(display) >= 35) {
+			*num_formats = ARRAY_SIZE(xe3p_lpd_hdr_plane_formats);
+			return xe3p_lpd_hdr_plane_formats;
+		}
+
 		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
 		return icl_hdr_plane_formats;
 	} else if (icl_is_nv12_y_plane(display, plane_id)) {
@@ -2637,6 +2671,10 @@ static bool tgl_plane_format_mod_supported(struct drm_plane *_plane,
 	case DRM_FORMAT_RGB565:
 	case DRM_FORMAT_XVYU2101010:
 	case DRM_FORMAT_C8:
+	case DRM_FORMAT_XBGR16161616:
+	case DRM_FORMAT_ABGR16161616:
+	case DRM_FORMAT_XRGB16161616:
+	case DRM_FORMAT_ARGB16161616:
 	case DRM_FORMAT_Y210:
 	case DRM_FORMAT_Y212:
 	case DRM_FORMAT_Y216:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 479bb3f7f92b..84cf565bd653 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -64,6 +64,7 @@
 #define   PLANE_CTL_FORMAT_Y410			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
 #define   PLANE_CTL_FORMAT_Y412			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
 #define   PLANE_CTL_FORMAT_Y416			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
+#define   PLANE_CTL_FORMAT_XRGB_16161616	REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 18)
 #define   PLANE_CTL_PIPE_CSC_ENABLE		REG_BIT(23) /* Pre-GLK */
 #define   PLANE_CTL_KEY_ENABLE_MASK		REG_GENMASK(22, 21)
 #define   PLANE_CTL_KEY_ENABLE_SOURCE		REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)

-- 
2.51.0

[PATCH 09/32] drm/i915/xe3p_lpd: Extend FBC support to UINT16 formats

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Starting Xe3p_LPD, FBC is supported on UINT16 formats as well. Also
UINT16 being a 64bpp format, will use cpp of 8 for cfb stride and thus
size calculations.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
BSpec: 68881, 68904, 69560
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 42 ++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 4edb4342833e..39d257267f9b 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -142,15 +142,25 @@ static unsigned int intel_fbc_plane_stride(const struct intel_plane_state *plane
 	return stride;
 }
 
-static unsigned int intel_fbc_cfb_cpp(void)
+static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_state)
 {
-	return 4; /* FBC always 4 bytes per pixel */
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_XRGB16161616:
+	case DRM_FORMAT_XBGR16161616:
+	case DRM_FORMAT_ARGB16161616:
+	case DRM_FORMAT_ABGR16161616:
+		return 8;
+	default:
+		return 4;
+	}
 }
 
 /* plane stride based cfb stride in bytes, assuming 1:1 compression limit */
 static unsigned int intel_fbc_plane_cfb_stride(const struct intel_plane_state *plane_state)
 {
-	unsigned int cpp = intel_fbc_cfb_cpp();
+	unsigned int cpp = intel_fbc_cfb_cpp(plane_state);
 
 	return intel_fbc_plane_stride(plane_state) * cpp;
 }
@@ -204,7 +214,7 @@ static unsigned int intel_fbc_cfb_stride(const struct intel_plane_state *plane_s
 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
 	unsigned int stride = intel_fbc_plane_cfb_stride(plane_state);
 	unsigned int width = drm_rect_width(&plane_state->uapi.src) >> 16;
-	unsigned int cpp = intel_fbc_cfb_cpp();
+	unsigned int cpp = intel_fbc_cfb_cpp(plane_state);
 
 	return _intel_fbc_cfb_stride(display, cpp, width, stride);
 }
@@ -1079,11 +1089,33 @@ static bool lnl_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_
 	}
 }
 
+static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *plane_state)
+{
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_XRGB8888:
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ARGB8888:
+	case DRM_FORMAT_ABGR8888:
+	case DRM_FORMAT_RGB565:
+	case DRM_FORMAT_XRGB16161616:
+	case DRM_FORMAT_XBGR16161616:
+	case DRM_FORMAT_ARGB16161616:
+	case DRM_FORMAT_ABGR16161616:
+		return true;
+	default:
+		return false;
+	}
+}
+
 static bool pixel_format_is_valid(const struct intel_plane_state *plane_state)
 {
 	struct intel_display *display = to_intel_display(plane_state->uapi.plane->dev);
 
-	if (DISPLAY_VER(display) >= 20)
+	if (DISPLAY_VER(display) >= 35)
+		return xe3p_lpd_fbc_pixel_format_is_valid(plane_state);
+	else if (DISPLAY_VER(display) >= 20)
 		return lnl_fbc_pixel_format_is_valid(plane_state);
 	else if (DISPLAY_VER(display) >= 5 || display->platform.g4x)
 		return g4x_fbc_pixel_format_is_valid(plane_state);

-- 
2.51.0

[PATCH 10/32] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Starting from Xe3p_LPD, linear surfaces also support horizontal flip.

Bspec: 68904
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 530adff81b99..9f1111324dab 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1753,7 +1753,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
 	}
 
 	if (rotation & DRM_MODE_REFLECT_X &&
-	    fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+	    fb->modifier == DRM_FORMAT_MOD_LINEAR &&
+	    DISPLAY_VER(display) < 35) {
 		drm_dbg_kms(display->drm,
 			    "[PLANE:%d:%s] horizontal flip is not supported with linear surface formats\n",
 			    plane->base.base.id, plane->base.name);

-- 
2.51.0

[PATCH 11/32] drm/i915/xe3p_lpd: Wait for AUX channel power status

[Gustavo Sousa]

The LT PHY in Xe3p_LPD allows polling for the AUX channel power status
to verify completion of power up and down. As such, let's use that field
to have a more precise waiting time instead of a fixed one.

Bspec: 68967
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c    | 32 +++++++++++++++++-----
 1 file changed, 25 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5e88b930f5aa..ba2552adb58b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1858,23 +1858,41 @@ static void xelpdp_aux_power_well_enable(struct intel_display *display,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
 
-	/*
-	 * The power status flag cannot be used to determine whether aux
-	 * power wells have finished powering up.  Instead we're
-	 * expected to just wait a fixed 600us after raising the request
-	 * bit.
-	 */
-	usleep_range(600, 1200);
+	if (DISPLAY_VER(display) >= 35) {
+		if (intel_de_wait_for_set(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+					  XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
+			drm_warn(display->drm,
+				 "Timeout waiting for PHY %c AUX channel power to be up\n",
+				 phy_name(phy));
+	} else {
+		/*
+		 * The power status flag cannot be used to determine whether aux
+		 * power wells have finished powering up.  Instead we're
+		 * expected to just wait a fixed 600us after raising the request
+		 * bit.
+		 */
+		usleep_range(600, 1200);
+	}
 }
 
 static void xelpdp_aux_power_well_disable(struct intel_display *display,
 					  struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
+	enum phy phy = icl_aux_pw_to_phy(display, power_well);
 
 	intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
 		     XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
 		     0);
+
+	if (DISPLAY_VER(display) >= 35) {
+		if (intel_de_wait_for_clear(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch),
+					    XELPDP_DP_AUX_CH_CTL_POWER_STATUS, 1))
+			drm_warn(display->drm,
+				 "Timeout waiting for PHY %c AUX channel power to be down\n",
+				 phy_name(phy));
+	}
+
 	usleep_range(10, 30);
 }
 

-- 
2.51.0

[PATCH 12/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Currently there is no way in the driver to classify the underruns into
different categories. Starting with Xe3p_LPD, we get two new registers
and some bits in existing registers which can help us categorise the
underruns and let us know possible reason behind the underrun.

Bspec: 69111, 69561, 74411, 74412
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h  |  31 +++++++
 drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 100 ++++++++++++++++++++-
 2 files changed, 130 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9d71e26a4fa2..9e2414b730db 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -882,6 +882,36 @@
 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
 #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
 
+#define _UNDERRUN_DBG1_A				0x70064
+#define _UNDERRUN_DBG1_B				0x71064
+#define UNDERRUN_DBG1(pipe)				_MMIO_PIPE(pipe, \
+								   _UNDERRUN_DBG1_A, \
+								   _UNDERRUN_DBG1_B)
+#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK		REG_GENMASK(29, 24)
+#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_PLANE_CURSOR	REG_BIT(24)
+#define   UNDERRUN_DDB_EMPTY_MASK			REG_GENMASK(21, 16)
+#define   UNDERRUN_DDB_EMPTY_PLANE_CURSOR		REG_BIT(16)
+#define   UNDERRUN_DBUF_NOT_FILLED_MASK			REG_GENMASK(13, 8)
+#define   UNDERRUN_DBUF_NOT_FILLED_PLANE_CURSOR		REG_BIT(8)
+#define   UNDERRUN_BELOW_WM0_MASK			REG_GENMASK(5, 0)
+#define   UNDERRUN_BELOW_WM0_PLANE_CURSOR		REG_BIT(0)
+
+#define _UNDERRUN_DBG2_A				0x70068
+#define _UNDERRUN_DBG2_B				0x71068
+#define UNDERRUN_DBG2(pipe)				_MMIO_PIPE(pipe, \
+								   _UNDERRUN_DBG2_A, \
+								   _UNDERRUN_DBG2_B)
+#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN		REG_BIT(31)
+#define   UNDERRUN_PIPE_FRAME_COUNT_MASK		REG_GENMASK(30, 20)
+#define   UNDERRUN_LINE_COUNT_MASK			REG_GENMASK(19, 0)
+
+#define _FBC_DEBUG_STATUS_A				0x43220
+#define _FBC_DEBUG_STATUS_B				0x43260
+#define FBC_DEBUG_STATUS(pipe)				_MMIO_PIPE(pipe, \
+								   _FBC_DEBUG_STATUS_A, \
+								   _FBC_DEBUG_STATUS_B)
+#define   FBC_UNDERRUN_DECOMPRESSION			REG_BIT(27)
+
 #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
 #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
 #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
@@ -1416,6 +1446,7 @@
 
 #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
 #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
+#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
 
 #define FUSE_STRAP		_MMIO(0x42014)
 #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index c2ce8461ac9e..753872ad28ed 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -352,6 +352,101 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
 	return old;
 }
 
+static void snprintf_underrun_planes(char *buf, size_t len,
+				     u32 underrun_dbg, u32 underrun_cursor)
+{
+	snprintf(buf, len, "%s%s%s%s%s%s",
+		 underrun_dbg & (underrun_cursor << 1) ? "[1]" : "",
+		 underrun_dbg & (underrun_cursor << 2) ? "[2]" : "",
+		 underrun_dbg & (underrun_cursor << 3) ? "[3]" : "",
+		 underrun_dbg & (underrun_cursor << 4) ? "[4]" : "",
+		 underrun_dbg & (underrun_cursor << 5) ? "[5]" : "",
+		 underrun_dbg & underrun_cursor ? "[C]" : "");
+}
+
+static void xe3p_lpd_log_underrun(struct intel_display *display,
+				  enum pipe pipe)
+{
+	u32 underrun_dbg1;
+	u32 underrun_dbg2;
+	u32 fbc_debug_status;
+	u32 dcpr_status;
+	char planes[32];
+
+	/*
+	 * UNDERRUN_DBG1 reports the following things
+	 * 1. If DBUF block is not valid
+	 * 2. If DDB is empty
+	 * 3. If streamer could not completely fill DBUF at the end of vblank
+	 * 4. Each enabled plane/cursor below watermark 0
+	 */
+	underrun_dbg1 = intel_de_read(display, UNDERRUN_DBG1(pipe));
+	intel_de_write(display, UNDERRUN_DBG1(pipe), underrun_dbg1);
+
+	if (underrun_dbg1 & UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK) {
+		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
+					 UNDERRUN_DBUF_BLOCK_NOT_VALID_PLANE_CURSOR);
+		drm_err(display->drm,
+			"Pipe %c FIFO underrun: DBUF block not valid for plane(s):  %s\n",
+			pipe_name(pipe), planes);
+	}
+
+	if (underrun_dbg1 & UNDERRUN_DDB_EMPTY_MASK) {
+		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
+					 UNDERRUN_DDB_EMPTY_PLANE_CURSOR);
+		drm_err(display->drm, "Pipe %c FIFO underrun: DDB empty for plane(s):  %s\n",
+			pipe_name(pipe), planes);
+	}
+
+	if (underrun_dbg1 & UNDERRUN_DBUF_NOT_FILLED_MASK) {
+		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
+					 UNDERRUN_DBUF_NOT_FILLED_PLANE_CURSOR);
+		drm_err(display->drm, "Pipe %c FIFO underrun: DBUF not filled for plane(s):  %s\n",
+			pipe_name(pipe), planes);
+	}
+
+	if (underrun_dbg1 & UNDERRUN_BELOW_WM0_MASK) {
+		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
+					 UNDERRUN_BELOW_WM0_PLANE_CURSOR);
+		drm_err(display->drm, "Pipe %c FIFO underrun: Below watermark 0 on plane(s):  %s\n",
+			pipe_name(pipe), planes);
+	}
+
+	/*
+	 * UNDERRUN_DBG2 reports the frame count and line count when the underrun started.
+	 */
+	underrun_dbg2 = intel_de_read(display, UNDERRUN_DBG2(pipe));
+	if (underrun_dbg2 & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
+		intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
+		drm_err(display->drm, "Pipe %c FIFO underrun: Frame count: %u, Line count: %u\n",
+			pipe_name(pipe),
+			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, underrun_dbg2),
+			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, underrun_dbg2));
+	}
+
+	/*
+	 * FBC_DEBUG_STATUS's FBC_UNDERRUN_DECOMPRESSION indicates if FBC was
+	 * decompressing when underrun got triggered.
+	 */
+	fbc_debug_status = intel_de_read(display, FBC_DEBUG_STATUS(pipe));
+	if (fbc_debug_status & FBC_UNDERRUN_DECOMPRESSION) {
+		intel_de_write(display, FBC_DEBUG_STATUS(pipe), FBC_UNDERRUN_DECOMPRESSION);
+		drm_err(display->drm, "Pipe %c FIFO underrun: FBC decompression\n",
+			pipe_name(pipe));
+	}
+
+	/*
+	 * GEN12_DCPR_STATUS_1's XE3P_UNDERRUN_PKGC, indicates that underrun started
+	 * while pkgc was blocking memory.
+	 */
+	dcpr_status = intel_de_read(display, GEN12_DCPR_STATUS_1);
+	if (dcpr_status & XE3P_UNDERRUN_PKGC) {
+		intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
+		drm_err(display->drm, "Pipe %c FIFO underrun: Pkgc blocking memory\n",
+			pipe_name(pipe));
+	}
+}
+
 /**
  * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
  * @display: display device instance
@@ -378,7 +473,10 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
 	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
 		trace_intel_cpu_fifo_underrun(display, pipe);
 
-		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
+		if (DISPLAY_VER(display) >= 35)
+			xe3p_lpd_log_underrun(display, pipe);
+		else
+			drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
 	}
 
 	intel_fbc_handle_fifo_underrun_irq(display);

-- 
2.51.0

[PATCH 13/32] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

With Xe3p_LPD, the SKL_BOTTOM_COLOR_GAMMA_ENABLE and
SKL_BOTTOM_COLOR_CSC_ENABLE bits are being removed. Thus, we need not
set gamma_enable nor csc_enable in crtc_state.

Note that GAMMA_MODE.POST_CSC_GAMMA_ENABLE and CSC_MODE.ICL_CSC_ENABLE
are the documented alternatives for the bottom color bits being removed.
But as these suggested bits are being checked in state checker as part
of gamma_mode, csc_mode fields and as gamma_enable/csc_enable are not
being used anywhere else functionally post ICL, we need not set these
fields in crtc_state.

Bspec: 69734
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 51db70d07fae..9102f3eb0bc4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1090,18 +1090,19 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	u32 tmp;
 
 	crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
 	crtc_state->csc_mode = ilk_read_csc_mode(crtc);
 
-	tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
+	if (DISPLAY_VER(display) < 35) {
+		u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
 
-	if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
-		crtc_state->gamma_enable = true;
+		if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
+			crtc_state->gamma_enable = true;
 
-	if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
-		crtc_state->csc_enable = true;
+		if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
+			crtc_state->csc_enable = true;
+	}
 }
 
 static void skl_color_commit_arm(struct intel_dsb *dsb,

-- 
2.51.0

[PATCH 14/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

[Gustavo Sousa]

From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>

Some of the register fields of MBUS_CTL and DBUF_CTL register are
changed for Xe3p_LPD platforms. Update the changed fields in the driver.
Below are the changes:

MBUS_CTL:
	Translation Throttle Min
		It changed from BIT[15:13] to BIT[16:13]

DBUF_CTL:
	Min Tracker State Service
		It changed from BIT[18:16] to BIT[20:16]
        Max Tracker State Service
		It changed to from BIT[23:19] to BIT[14:10]
		but using default value, so no need to define
		in code.

Bspec: 68868, 68872
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c      | 16 ++++++++++++----
 drivers/gpu/drm/i915/display/skl_watermark_regs.h | 12 ++++++++++--
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 9df9ee137bf9..41f64e347436 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3505,7 +3505,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
 	if (!HAS_MBUS_JOINING(display))
 		return;
 
-	if (DISPLAY_VER(display) >= 20)
+	if (DISPLAY_VER(display) >= 35)
+		intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
+			     XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
+	else if (DISPLAY_VER(display) >= 20)
 		intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
 			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
 
@@ -3516,9 +3519,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
 		    ratio, str_yes_no(joined_mbus));
 
 	for_each_dbuf_slice(display, slice)
-		intel_de_rmw(display, DBUF_CTL_S(slice),
-			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
-			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+		if (DISPLAY_VER(display) >= 35)
+			intel_de_rmw(display, DBUF_CTL_S(slice),
+				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
+		else
+			intel_de_rmw(display, DBUF_CTL_S(slice),
+				     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+				     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
 }
 
 static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index c5572fc0e847..7e0877303e05 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -41,7 +41,11 @@
 #define   MBUS_JOIN_PIPE_SELECT(pipe)		REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
 #define   MBUS_JOIN_PIPE_SELECT_NONE		MBUS_JOIN_PIPE_SELECT(7)
 #define   MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
-#define   MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
+#define   MBUS_TRANSLATION_THROTTLE_MIN(val) \
+		REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
+#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(16, 13)
+#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) \
+		REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
 
 /*
  * The below are numbered starting from "S1" on gen11/gen12, but starting
@@ -65,7 +69,11 @@
 #define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
 #define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
 #define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(18, 16) /* ADL-P+ */
-#define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
+#define  DBUF_MIN_TRACKER_STATE_SERVICE(x) \
+		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
+#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(20, 16)
+#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) \
+		REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
 
 #define MTL_LATENCY_LP0_LP1		_MMIO(0x45780)
 #define MTL_LATENCY_LP2_LP3		_MMIO(0x45784)

-- 
2.51.0

[PATCH 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment

[Gustavo Sousa]

When reading memory latencies for watermark calculations, previous
display releases instructed to apply an adjustment of adding a certain
value (e.g. 6us) to all levels when the level 0's memory latency read
from hardware was zero.

For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
add that value to the other levels.  Update adjust_wm_latency()
accordingly.

Bspec: 68986, 69126
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 41f64e347436..88342d07727f 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3249,6 +3249,13 @@ adjust_wm_latency(struct intel_display *display)
 
 	make_wm_latency_monotonic(display);
 
+	/*
+	 * Xe3p asks to ignore wm[0] read from the register and always
+	 * use the adjustment done with read_latency.
+	 */
+	if (DISPLAY_VER(display) >= 35)
+		wm[0] = 0;
+
 	/*
 	 * WaWmMemoryReadLatency
 	 *

-- 
2.51.0

[PATCH 16/32] drm/i915/xe3p_lpd: Add CDCLK table

[Gustavo Sousa]

Add CDCLK table for Xe3p_LPD.

Just as with Xe3_LPD, we don't need to send voltage index info in the
PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs.

With the new CDCLK table, we also need to update the maximum CDCLK value
returned by intel_update_max_cdclk().

Bspec: 68861, 68863
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f2e092f89ddd..ffd8cab2d565 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1534,6 +1534,41 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
 	{}
 };
 
+static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
+	{ .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
+	{ .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
+	{ .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
+	{ .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
+	{ .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
+	{ .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
+	{ .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
+	{ .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
+	{ .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
+	{ .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
+	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
+	{ .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
+	{}
+};
+
 static const int cdclk_squash_len = 16;
 
 static int cdclk_squash_divider(u16 waveform)
@@ -3555,7 +3590,9 @@ static int intel_compute_max_dotclk(struct intel_display *display)
  */
 void intel_update_max_cdclk(struct intel_display *display)
 {
-	if (DISPLAY_VERx100(display) >= 3002) {
+	if (DISPLAY_VER(display) >= 35) {
+		display->cdclk.max_cdclk_freq = 787200;
+	} else if (DISPLAY_VERx100(display) >= 3002) {
 		display->cdclk.max_cdclk_freq = 480000;
 	} else if (DISPLAY_VER(display) >= 30) {
 		display->cdclk.max_cdclk_freq = 691200;
@@ -3906,7 +3943,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
  */
 void intel_init_cdclk_hooks(struct intel_display *display)
 {
-	if (DISPLAY_VER(display) >= 30) {
+	if (DISPLAY_VER(display) >= 35) {
+		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
+		display->cdclk.table = xe3p_lpd_cdclk_table;
+	} else if (DISPLAY_VER(display) >= 30) {
 		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
 		display->cdclk.table = xe3lpd_cdclk_table;
 	} else if (DISPLAY_VER(display) >= 20) {

-- 
2.51.0

[PATCH 17/32] drm/i915/xe3p_lpd: Load DMC firmware

[Gustavo Sousa]

Load the DMC firmware for Xe3p_LPD.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 517bebb0b4aa..c496e7a5c003 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -127,6 +127,9 @@ static bool dmc_firmware_param_disabled(struct intel_display *display)
 #define DISPLAY_VER13_DMC_MAX_FW_SIZE	0x20000
 #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
 
+#define XE3P_LPD_DMC_PATH		DMC_PATH(xe3p_lpd)
+MODULE_FIRMWARE(XE3P_LPD_DMC_PATH);
+
 #define XE3LPD_DMC_PATH			DMC_PATH(xe3lpd)
 MODULE_FIRMWARE(XE3LPD_DMC_PATH);
 
@@ -184,7 +187,10 @@ static const char *dmc_firmware_default(struct intel_display *display, u32 *size
 	const char *fw_path = NULL;
 	u32 max_fw_size = 0;
 
-	if (DISPLAY_VERx100(display) == 3002 ||
+	if (DISPLAY_VERx100(display) == 3500) {
+		fw_path = XE3P_LPD_DMC_PATH;
+		max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
+	} else if (DISPLAY_VERx100(display) == 3002 ||
 	    DISPLAY_VERx100(display) == 3000) {
 		fw_path = XE3LPD_DMC_PATH;
 		max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;

-- 
2.51.0

[PATCH 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode

[Gustavo Sousa]

From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>

Interlace mode is officially removed from HW from Xe3p_LPD.  The
register TRANS_VSYNCSHIFT and the bits in TRANS_CONF are now removed, so
make sure we do not set/get these anymore.

Bspec: 69961, 70000
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d5b2612d4ec2..6ac718192e1c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2631,7 +2631,7 @@ static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_sta
 		crtc_vblank_start = 1;
 	}
 
-	if (DISPLAY_VER(display) >= 4)
+	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
 		intel_de_write(display,
 			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
 			       vsyncshift);
@@ -2769,7 +2769,7 @@ static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 
-	if (DISPLAY_VER(display) == 2)
+	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
 		return false;
 
 	if (DISPLAY_VER(display) >= 9 ||
@@ -3160,10 +3160,12 @@ static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
 	if (display->platform.haswell && crtc_state->dither)
 		val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
-	else
-		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+	if (DISPLAY_VER(display) < 35) {
+		if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
+			val |= TRANSCONF_INTERLACE_IF_ID_ILK;
+		else
+			val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+	}
 
 	if (display->platform.haswell &&
 	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)

-- 
2.51.0

[PATCH 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4

[Gustavo Sousa]

From: Jouni Högander <jouni.hogander@intel.com>

Ensure the minimum selective update line count is 4 in case of display
version 35 and onwards.

Bspec: 69887
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 2131473cead6..c663ca91f490 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2701,6 +2701,29 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
 		intel_psr_apply_pr_link_on_su_wa(crtc_state);
 }
 
+static void intel_psr_su_area_min_lines(struct intel_crtc_state *crtc_state)
+{
+	struct intel_display *display = to_intel_display(crtc_state);
+	struct drm_rect damaged_area;
+
+	/*
+	 * Bspec mentions 4 being minimum lines in SU for display version
+	 * 35 and onwards.
+	 */
+	if (DISPLAY_VER(display) < 35 || drm_rect_height(&crtc_state->psr2_su_area) >= 4)
+		return;
+
+	damaged_area.x1 = crtc_state->psr2_su_area.x1;
+	damaged_area.y1 = crtc_state->psr2_su_area.y1;
+	damaged_area.x2 = crtc_state->psr2_su_area.x2;
+	damaged_area.y2 = crtc_state->psr2_su_area.y2;
+
+	damaged_area.y2 +=  4 - drm_rect_height(&damaged_area);
+	drm_rect_intersect(&damaged_area, &crtc_state->pipe_src);
+	damaged_area.y1 -=  4 - drm_rect_height(&damaged_area);
+	clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
+}
+
 int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 				struct intel_crtc *crtc)
 {
@@ -2809,6 +2832,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	if (full_update)
 		goto skip_sel_fetch_set_loop;
 
+	intel_psr_su_area_min_lines(crtc_state);
+
 	intel_psr_apply_su_area_workarounds(crtc_state);
 
 	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);

-- 
2.51.0

[PATCH 20/32] drm/i915/xe3p_lpd: Enable system caching for FBC

[Gustavo Sousa]

From: Vinod Govindapillai <vinod.govindapillai@intel.com>

Configure one of the FBC instances to use system caching. FBC
read/write requests are tagged as cacheable till a programmed
limit is reached by the hw.

Bspec: 74722
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c      | 47 +++++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc_regs.h |  9 +++++
 2 files changed, 56 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 39d257267f9b..75c78bef54f2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -127,6 +127,9 @@ struct intel_fbc {
 	 */
 	struct intel_fbc_state state;
 	const char *no_fbc_reason;
+
+	/* Only one of FBC instances can use the system cache */
+	bool own_sys_cache;
 };
 
 /* plane stride in pixels */
@@ -571,12 +574,51 @@ static bool ilk_fbc_is_compressing(struct intel_fbc *fbc)
 	return intel_de_read(fbc->display, ILK_DPFC_STATUS(fbc->id)) & DPFC_COMP_SEG_MASK;
 }
 
+static void nvl_fbc_program_system_cache(struct intel_fbc *fbc, bool enable)
+{
+	struct intel_display *display = fbc->display;
+	u32 cfb_offset, usage;
+
+	lockdep_assert_held(&fbc->lock);
+
+	usage = intel_de_read(display, NVL_FBC_SYS_CACHE_USAGE_CFG);
+
+	/* System cache already being used by another pipe */
+	if (enable && (usage & FBC_SYS_CACHE_TAG_USE_RES_SPACE))
+		return;
+
+	/* Only the fbc instance which owns system cache can disable it */
+	if (!enable && !fbc->own_sys_cache)
+		return;
+
+	/*
+	 * Not programming the cache limit and cache reading enable bits explicitly
+	 * here. The default values should take care of those and that could leave
+	 * adjustments of those bits to the system hw policy
+	 *
+	 * TODO: check if we need to explicitly program these?
+	 */
+	cfb_offset = enable ? i915_gem_stolen_node_offset(fbc->compressed_fb) : 0;
+	usage |= FBC_SYS_CACHE_START_BASE(cfb_offset);
+	usage |= enable ? FBC_SYS_CACHE_TAG_USE_RES_SPACE : FBC_SYS_CACHE_TAG_DONT_CACHE;
+
+	intel_de_write(display, NVL_FBC_SYS_CACHE_USAGE_CFG, usage);
+
+	fbc->own_sys_cache = enable;
+
+	drm_dbg_kms(display->drm, "System caching for FBC[%d] %s\n",
+		    fbc->id, enable ? "configured" : "cleared");
+}
+
 static void ilk_fbc_program_cfb(struct intel_fbc *fbc)
 {
 	struct intel_display *display = fbc->display;
 
 	intel_de_write(display, ILK_DPFC_CB_BASE(fbc->id),
 		       i915_gem_stolen_node_offset(fbc->compressed_fb));
+
+	if (DISPLAY_VER(display) >= 35)
+		nvl_fbc_program_system_cache(fbc, true);
 }
 
 static const struct intel_fbc_funcs ilk_fbc_funcs = {
@@ -951,6 +993,8 @@ static void intel_fbc_program_workarounds(struct intel_fbc *fbc)
 
 static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 {
+	struct intel_display *display = fbc->display;
+
 	if (WARN_ON(intel_fbc_hw_is_active(fbc)))
 		return;
 
@@ -958,6 +1002,9 @@ static void __intel_fbc_cleanup_cfb(struct intel_fbc *fbc)
 		i915_gem_stolen_remove_node(fbc->compressed_llb);
 	if (i915_gem_stolen_node_allocated(fbc->compressed_fb))
 		i915_gem_stolen_remove_node(fbc->compressed_fb);
+
+	if (DISPLAY_VER(display) >= 35)
+		nvl_fbc_program_system_cache(fbc, false);
 }
 
 void intel_fbc_cleanup(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
index b1d0161a3196..264799bba7e0 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h
@@ -126,4 +126,13 @@
 #define   FBC_REND_NUKE			REG_BIT(2)
 #define   FBC_REND_CACHE_CLEAN		REG_BIT(1)
 
+#define NVL_FBC_SYS_CACHE_USAGE_CFG             _MMIO(0x1344E0)
+#define   FBC_SYS_CACHE_START_BASE_MASK         REG_GENMASK(31, 16)
+#define   FBC_SYS_CACHE_START_BASE(base)        REG_FIELD_PREP(FBC_SYS_CACHE_START_BASE_MASK, (base))
+#define   FBC_SYS_CACHEABLE_RANGE_MASK          REG_GENMASK(15, 4)
+#define   FBC_SYS_CACHEABLE_RANGE(range)        REG_FIELD_PREP(FBC_SYS_CACHEABLE_RANGE_MASK, (range))
+#define   FBC_SYS_CACHE_TAG_MASK                REG_GENMASK(3, 2)
+#define   FBC_SYS_CACHE_TAG_DONT_CACHE          REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 0)
+#define   FBC_SYS_CACHE_TAG_USE_RES_SPACE       REG_FIELD_PREP(FBC_SYS_CACHE_TAG_MASK, 3)
+
 #endif /* __INTEL_FBC_REGS__ */

-- 
2.51.0

[PATCH 21/32] drm/i915/xe3p_lpd: Extend Wa_16025573575

[Gustavo Sousa]

Wa_16025573575 also applies to Xe3p_LPD, so let's include it in the IP
version checks.

Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_wa.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 31cd2c9cd488..f897ad3862f7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -49,7 +49,8 @@ void intel_display_wa_apply(struct intel_display *display)
  */
 static bool intel_display_needs_wa_16025573575(struct intel_display *display)
 {
-	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
+	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
+		DISPLAY_VERx100(display) == 3500;
 }
 
 /*

-- 
2.51.0

[PATCH 22/32] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format

[Gustavo Sousa]

From: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>

Disable support for odd panning and size in y direction when running on
display version 35 and using semiplanar formats.

Bspec: 68903
Signed-off-by: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_plane.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
index 074de9275951..8de4e15fae6b 100644
--- a/drivers/gpu/drm/i915/display/intel_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_plane.c
@@ -1050,6 +1050,9 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 		     DISPLAY_VERx100(display) == 3002) &&
 		     src_x % 2 != 0)
 			hsub = 2;
+
+		if (DISPLAY_VER(display) == 35)
+			vsub = 2;
 	} else {
 		hsub = fb->format->hsub;
 		vsub = fb->format->vsub;

-- 
2.51.0

[PATCH 23/32] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D

[Gustavo Sousa]

Xe3p_LPD has the same behavior as for Xe3_LPD with respect to DMC
context data for pipes C and D, which are lost when their power wells
are disabled.  As such, let's extend the condition for Xe3_LPD in
need_pipedmc_load_mmio() to also catch Xe3p_LPD.

Bspec: 68851
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index c496e7a5c003..8ede90c033d8 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -668,11 +668,11 @@ static bool need_pipedmc_load_program(struct intel_display *display)
 static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
 {
 	/*
-	 * PTL:
+	 * Xe3_LPD/Xe3p_LPD:
 	 * - pipe A/B DMC doesn't need save/restore
 	 * - pipe C/D DMC is in PG0, needs manual save/restore
 	 */
-	if (DISPLAY_VER(display) == 30)
+	if (IS_DISPLAY_VER(display, 30, 35))
 		return pipe >= PIPE_C;
 
 	/*

-- 
2.51.0

[PATCH 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support

[Gustavo Sousa]

From: Vinod Govindapillai <vinod.govindapillai@intel.com>

To enable FBC for FP16 formats, we need to enable the pixel normalizer
block. Introduce the register definitions and the initial steps for
configuring the pixel normalizer block. In this patch the pixel
normalizer block is kept as disabled. The follow-up patches will handle
configuring the pixel normalizer block for hdr planes for FP16 formats.

Bspec: 69863
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h      |  3 +++
 drivers/gpu/drm/i915/display/skl_universal_plane.c      | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 11 +++++++++++
 3 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 87b7cec35320..13652e2996a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -679,6 +679,9 @@ struct intel_plane_state {
 	/* surface address register */
 	u32 surf;
 
+	/* plane pixel normalizer config for Xe3p_LPD+ FBC FP16 */
+	u32 pixel_normalizer;
+
 	/*
 	 * scaler_id
 	 *    = -1 : not using a scaler
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 9f1111324dab..16a9c141281b 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -893,6 +893,12 @@ static void skl_write_plane_wm(struct intel_dsb *dsb,
 				   xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb));
 }
 
+static void
+xe3p_lpd_plane_check_pixel_normalizer(struct intel_plane_state *plane_state)
+{
+	plane_state->pixel_normalizer = 0;
+}
+
 static void
 skl_plane_disable_arm(struct intel_dsb *dsb,
 		      struct intel_plane *plane,
@@ -1671,6 +1677,11 @@ icl_plane_update_arm(struct intel_dsb *dsb,
 
 	icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
 
+	/* Only the HDR planes can have pixel normalizer */
+	if (DISPLAY_VER(display) >= 35 && icl_is_hdr_plane(display, plane_id))
+		intel_de_write_dsb(display, dsb,
+				   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id),
+				   plane_state->pixel_normalizer);
 	/*
 	 * The control register self-arms if the plane was previously
 	 * disabled. Try to make the plane enable atomic by writing
@@ -2385,6 +2396,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
 		plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
 	}
 
+	/* Pixel normalizer for Xe3p_LPD+ */
+	if (DISPLAY_VER(display) >= 35 && icl_is_hdr_plane(display, plane->id))
+		xe3p_lpd_plane_check_pixel_normalizer(plane_state);
+
 	plane_state->ctl = skl_plane_ctl(plane_state);
 
 	if (DISPLAY_VER(display) >= 10)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 84cf565bd653..11c713f9b237 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -456,4 +456,15 @@
 								_SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \
 								_SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B)
 
+#define _PLANE_PIXEL_NORMALIZE_1_A		0x701a8
+#define _PLANE_PIXEL_NORMALIZE_2_A		0x702a8
+#define _PLANE_PIXEL_NORMALIZE_1_B		0x711a8
+#define _PLANE_PIXEL_NORMALIZE_2_B		0x712a8
+#define PLANE_PIXEL_NORMALIZE(pipe, plane)	_MMIO_SKL_PLANE((pipe), (plane), \
+								_PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B, \
+								_PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
+#define   PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
+#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
+#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val))
+
 #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */

-- 
2.51.0

[PATCH 25/32] drm/i915/xe3p_lpd: Add FBC support for FP16 formats

[Gustavo Sousa]

From: Vinod Govindapillai <vinod.govindapillai@intel.com>

Add supported FP16 formats for FBC. FBC can be enabled with FP16 formats
only when plane pixel normalizer block is enabled.

Bspec: 6881, 69863, 68904
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fbc.c | 37 ++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_fbc.h |  1 +
 2 files changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 75c78bef54f2..715a9acabe89 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -64,6 +64,7 @@
 #include "intel_fbc.h"
 #include "intel_fbc_regs.h"
 #include "intel_frontbuffer.h"
+#include "skl_universal_plane_regs.h"
 
 #define for_each_fbc_id(__display, __fbc_id) \
 	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
@@ -154,6 +155,8 @@ static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_stat
 	case DRM_FORMAT_XBGR16161616:
 	case DRM_FORMAT_ARGB16161616:
 	case DRM_FORMAT_ABGR16161616:
+	case DRM_FORMAT_ARGB16161616F:
+	case DRM_FORMAT_ABGR16161616F:
 		return 8;
 	default:
 		return 4;
@@ -696,6 +699,30 @@ static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
 		     CHICKEN_FBC_STRIDE_MASK, val);
 }
 
+static bool
+xe3p_lpd_fbc_is_fp16_format(const struct intel_plane_state *plane_state)
+{
+	const struct drm_framebuffer *fb = plane_state->hw.fb;
+
+	switch (fb->format->format) {
+	case DRM_FORMAT_ARGB16161616F:
+	case DRM_FORMAT_ABGR16161616F:
+		return true;
+	default:
+		return false;
+	}
+}
+
+bool
+intel_fbc_is_fp16_format_supported(const struct intel_plane_state *plane_state)
+{
+	struct intel_display *display = to_intel_display(plane_state);
+
+	if (DISPLAY_VER(display) >= 35)
+		return xe3p_lpd_fbc_is_fp16_format(plane_state);
+
+	return false;
+}
 static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
 {
 	struct intel_display *display = fbc->display;
@@ -811,6 +838,8 @@ static void intel_fbc_nuke(struct intel_fbc *fbc)
 static void intel_fbc_activate(struct intel_fbc *fbc)
 {
 	struct intel_display *display = fbc->display;
+	struct intel_plane *plane = fbc->state.plane;
+	struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state);
 
 	lockdep_assert_held(&fbc->lock);
 
@@ -823,6 +852,11 @@ static void intel_fbc_activate(struct intel_fbc *fbc)
 	 */
 	drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));
 
+	drm_WARN_ON(display->drm,
+		    DISPLAY_VER(display) >= 35 &&
+		    xe3p_lpd_fbc_is_fp16_format(plane_state) &&
+		    (plane_state->pixel_normalizer & PLANE_PIXEL_NORMALIZE_ENABLE) == 0);
+
 	intel_fbc_hw_activate(fbc);
 	intel_fbc_nuke(fbc);
 
@@ -1140,6 +1174,9 @@ static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *p
 {
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 
+	if (xe3p_lpd_fbc_is_fp16_format(plane_state))
+		return true;
+
 	switch (fb->format->format) {
 	case DRM_FORMAT_XRGB8888:
 	case DRM_FORMAT_XBGR8888:
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 0e715cb6b4e6..e14dc359ecf5 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -52,5 +52,6 @@ void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
 				  struct intel_crtc *crtc);
 void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
 				       struct intel_plane *plane);
+bool intel_fbc_is_fp16_format_supported(const struct intel_plane_state *plane_state);
 
 #endif /* __INTEL_FBC_H__ */

-- 
2.51.0

[PATCH 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC

[Gustavo Sousa]

From: Vinod Govindapillai <vinod.govindapillai@intel.com>

There is a hw restriction that we could enable the FBC for FP16
formats only if the pixel normalization block is enabled. Hence
enable the pixel normalizer block with normalzation factor as
1.0 for the supported FP16 formats to get the FBC enabled. Two
existing helper function definitions are moved up to avoid the
forward declarations as part of this patch as well.

Bspec: 69863, 68881
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_universal_plane.c | 50 ++++++++++++++--------
 .../drm/i915/display/skl_universal_plane_regs.h    |  1 +
 2 files changed, 33 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 16a9c141281b..ae1bf6beac95 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -486,6 +486,23 @@ static int skl_plane_max_height(const struct drm_framebuffer *fb,
 	return 4096;
 }
 
+static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
+{
+	return pipe - PIPE_A + INTEL_FBC_A;
+}
+
+static bool skl_plane_has_fbc(struct intel_display *display,
+			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
+{
+	if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)
+		return false;
+
+	if (DISPLAY_VER(display) >= 20)
+		return icl_is_hdr_plane(display, plane_id);
+	else
+		return plane_id == PLANE_1;
+}
+
 static int icl_plane_max_height(const struct drm_framebuffer *fb,
 				int color_plane,
 				unsigned int rotation)
@@ -896,7 +913,21 @@ static void skl_write_plane_wm(struct intel_dsb *dsb,
 static void
 xe3p_lpd_plane_check_pixel_normalizer(struct intel_plane_state *plane_state)
 {
-	plane_state->pixel_normalizer = 0;
+	struct intel_display *display = to_intel_display(plane_state);
+	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
+	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
+	u32 reg = 0;
+
+	/*
+	 * To enable FBC for FP16 formats, enable pixel normalizer with
+	 * normalization factor as 1.0
+	 */
+	if (skl_plane_has_fbc(display, fbc_id, plane->id) &&
+	    intel_fbc_is_fp16_format_supported(plane_state))
+		reg = PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) |
+		      PLANE_PIXEL_NORMALIZE_ENABLE;
+
+	plane_state->pixel_normalizer = reg;
 }
 
 static void
@@ -2449,23 +2480,6 @@ void icl_link_nv12_planes(struct intel_plane_state *uv_plane_state,
 	}
 }
 
-static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
-{
-	return pipe - PIPE_A + INTEL_FBC_A;
-}
-
-static bool skl_plane_has_fbc(struct intel_display *display,
-			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
-{
-	if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)
-		return false;
-
-	if (DISPLAY_VER(display) >= 20)
-		return icl_is_hdr_plane(display, plane_id);
-	else
-		return plane_id == PLANE_1;
-}
-
 static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
 				       enum pipe pipe, enum plane_id plane_id)
 {
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index 11c713f9b237..eb25de5d1778 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -466,5 +466,6 @@
 #define   PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
 #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
 #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val))
+#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0		0x3c00
 
 #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */

-- 
2.51.0

[PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Gustavo Sousa]

VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
configuring SoC for TC ports and PHYs.  Update the code to match the
updates in VBT.

The new field dedicated_external is used to represent TC ports that are
connected to PHYs outside of the Type-C subsystem, meaning that they
behave like dedicated ports and don't require the extra Type-C
programming.  In an upcoming change, we will update the driver to take
this field into consideration when detecting the type of port.

The new field dyn_port_over_tc is used to inform that the TC port can be
dynamically allocated for a legacy connector in the Type-C subsystem,
which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
that field in order to handle the IOM resource management programming
required for that.

Note that, when dedicated_external is set, the fields dp_usb_type_c and
tbt are tagged as "don't care" in the spec, so they should be ignored in
that case, so also make sure to update the accessor functions to take
that into consideration.

Bspec: 20124, 68954, 74304
Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
 3 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 3596dce84c28..e466728ced0f 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
 {
 	BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
 
-	if (version > 263)
+	if (version > 264)
 		return -ENOENT;
 	else if (version >= 263)
 		return 44;
@@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
 
 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
 {
+	if (intel_bios_encoder_is_dedicated_external(devdata))
+		return false;
+
 	return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
 }
 
 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
 {
+	if (intel_bios_encoder_is_dedicated_external(devdata))
+		return false;
+
 	return devdata->display->vbt.version >= 209 && devdata->child.tbt;
 }
 
+bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
+{
+	return devdata->display->vbt.version >= 264 &&
+		devdata->child.dedicated_external;
+}
+
+bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
+{
+	return devdata->display->vbt.version >= 264 &&
+		devdata->child.dyn_port_over_tc;
+}
+
 bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
 {
 	return devdata && devdata->child.lane_reversal;
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index f9e438b2787b..75dff27b4228 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
 bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
+bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
+bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
 bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 70e31520c560..f07ab64a8d97 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -554,7 +554,12 @@ struct child_device_config {
 	u8 dvo_function;
 	u8 dp_usb_type_c:1;					/* 195+ */
 	u8 tbt:1;						/* 209+ */
-	u8 flags2_reserved:2;					/* 195+ */
+	/*
+	 * Fields dp_usb_type_c and tbt must be ignored when
+	 * dedicated_external is set.
+	 */
+	u8 dedicated_external:1;				/* 264+ */
+	u8 dyn_port_over_tc:1;					/* 264+ */
 	u8 dp_port_trace_length:4;				/* 209+ */
 	u8 dp_gpio_index;					/* 195+ */
 	u16 dp_gpio_pin_num;					/* 195+ */

-- 
2.51.0

[PATCH 28/32] drm/i915/power: Use intel_encoder_is_tc()

[Gustavo Sousa]

Starting with Xe3p_LPD, when intel_phy_is_tc() returns true, it does
not necessarily mean that the port is connected to a PHY in the Type-C
subsystem.  The reason is that there is now a VBT field called
dedicated_external that will indicate that a Type-C capable port is
connected to a (most likely) combo/dedicated PHY.  When that's the case,
we must not do the extra programming required for Type-C connections.

In an upcoming change, we will modify intel_encoder_is_tc() to take the
VBT field dedicated_external into consideration.  Update
intel_display_power_well.c to use that function instead of
intel_phy_is_tc().

Note that, even though icl_aux_power_well_{enable,disable} are not part
of Xe3p_LPD's display paths, we modify them anyway for uniformity.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c    | 26 +++++++++++++++-------
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index ba2552adb58b..e8200672dcf3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -256,8 +256,9 @@ aux_ch_to_digital_port(struct intel_display *display,
 	return NULL;
 }
 
-static enum phy icl_aux_pw_to_phy(struct intel_display *display,
-				  const struct i915_power_well *power_well)
+static struct intel_encoder *
+icl_aux_pw_to_encoder(struct intel_display *display,
+		      const struct i915_power_well *power_well)
 {
 	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
 	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display, aux_ch);
@@ -269,7 +270,15 @@ static enum phy icl_aux_pw_to_phy(struct intel_display *display,
 	 * as HDMI-only and routed to a combo PHY, the encoder either won't be
 	 * present at all or it will not have an aux_ch assigned.
 	 */
-	return dig_port ? intel_encoder_to_phy(&dig_port->base) : PHY_NONE;
+	return dig_port ? &dig_port->base : NULL;
+}
+
+static enum phy icl_aux_pw_to_phy(struct intel_display *display,
+				  const struct i915_power_well *power_well)
+{
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
+
+	return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE;
 }
 
 static void hsw_wait_for_power_well_enable(struct intel_display *display,
@@ -568,9 +577,9 @@ static void
 icl_aux_power_well_enable(struct intel_display *display,
 			  struct i915_power_well *power_well)
 {
-	enum phy phy = icl_aux_pw_to_phy(display, power_well);
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (encoder && intel_encoder_is_tc(encoder))
 		return icl_tc_phy_aux_power_well_enable(display, power_well);
 	else if (display->platform.icelake)
 		return icl_combo_phy_aux_power_well_enable(display,
@@ -583,9 +592,9 @@ static void
 icl_aux_power_well_disable(struct intel_display *display,
 			   struct i915_power_well *power_well)
 {
-	enum phy phy = icl_aux_pw_to_phy(display, power_well);
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (encoder && intel_encoder_is_tc(encoder))
 		return hsw_power_well_disable(display, power_well);
 	else if (display->platform.icelake)
 		return icl_combo_phy_aux_power_well_disable(display,
@@ -1847,10 +1856,11 @@ tgl_tc_cold_off_power_well_is_enabled(struct intel_display *display,
 static void xelpdp_aux_power_well_enable(struct intel_display *display,
 					 struct i915_power_well *power_well)
 {
+	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display, power_well);
 	enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
 	enum phy phy = icl_aux_pw_to_phy(display, power_well);
 
-	if (intel_phy_is_tc(display, phy))
+	if (encoder && intel_encoder_is_tc(encoder))
 		icl_tc_port_assert_ref_held(display, power_well,
 					    aux_ch_to_digital_port(display, aux_ch));
 

-- 
2.51.0

[PATCH 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Gustavo Sousa]

Starting with Xe3p_LPD, the VBT has a new field, called in the driver
"dedicated_external", which tells that a Type-C capable port is
physically connected to a PHY outside of the Type-C subsystem.  When
that's the case, the driver must not do the extra Type-C programming for
that port.  Update intel_encoder_is_tc() to check for that case.

While at it, add a note to intel_phy_is_tc() to remind us that it is
about whether the respective port is a Type-C capable port rather than
the PHY itself.

(Maybe it would be a nice idea to rename intel_phy_is_tc()?)

Note that this was handled with a new bool member added to struct
intel_digital_port instead of having querying the VBT directly because
VBT memory is freed (intel_bios_driver_remove) before encoder cleanup
(intel_ddi_encoder_destroy), which would cause an oops to happen when
the latter calls intel_encoder_is_tc().  This could be fixed by keeping
VBT data around longer, but that's left for a follow-up work, if deemed
necessary.

Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c           |  7 +++++++
 drivers/gpu/drm/i915/display/intel_display.c       | 19 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
 3 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index c09aa759f4d4..6fcbebb81263 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5343,6 +5343,13 @@ void intel_ddi_init(struct intel_display *display,
 			goto err;
 	}
 
+	if (intel_bios_encoder_is_dedicated_external(devdata)) {
+		dig_port->dedicated_external = true;
+		drm_dbg_kms(display->drm,
+			    "Port %c is dedicated external\n",
+			    port_name(port));
+	}
+
 	if (intel_encoder_is_tc(encoder)) {
 		bool is_legacy =
 			!intel_bios_encoder_supports_typec_usb(devdata) &&
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6ac718192e1c..46474199d1ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1778,7 +1778,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
 		return false;
 }
 
-/* Prefer intel_encoder_is_tc() */
+/*
+ * This function returns true if the DDI port respective to the PHY enumeration
+ * is a Type-C capable port.
+ *
+ * Depending on the VBT, the port might be configured
+ * as a "dedicated external" port, meaning that actual physical PHY is outside
+ * of the Type-C subsystem and, as such, not really a "Type-C PHY".
+ *
+ * Prefer intel_encoder_is_tc(), especially if you really need to know if we
+ * are dealing with Type-C connections.
+ */
 bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
 {
 	/*
@@ -1863,6 +1873,13 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder)
 {
 	struct intel_display *display = to_intel_display(encoder);
 
+	if (intel_encoder_is_dig_port(encoder)) {
+		struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+
+		if (dig_port->dedicated_external)
+			return false;
+	}
+
 	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 13652e2996a4..b5b9351501b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1909,6 +1909,7 @@ struct intel_digital_port {
 	bool lane_reversal;
 	bool ddi_a_4_lanes;
 	bool release_cl2_override;
+	bool dedicated_external;
 	u8 max_lanes;
 	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
 	enum aux_ch aux_ch;

-- 
2.51.0

[PATCH 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards

[Gustavo Sousa]

From: Luca Coelho <luciano.coelho@intel.com>

Starting from display version 35, we don't need to use method1 to
calculate the watermark values anymore, so skip it.

Bspec: 68985
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 88342d07727f..fba7448c4920 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1809,6 +1809,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 
 	if (wp->y_tiled) {
 		selected_result = max_fixed16(method2, wp->y_tile_minimum);
+	} else if (DISPLAY_VER(display) >= 35) {
+		selected_result = method2;
 	} else {
 		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
 		     wp->dbuf_block_size < 1) &&

-- 
2.51.0

[PATCH 31/32] drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation

[Gustavo Sousa]

Xe3p_LPD has a new feature that allows the driver to allocate at runtime
the DDI (TC ones) port to drive a legacy connection on the Type-C
subsystem.  This allows better resource utilization, because now there
is no need to statically reserve ports for legacy connectors on the
Type-C subsystem.

That said, our driver is not yet ready for the dynamic allocation.
Thus, as an incremental step, let's add the logic containing the
required programming sequence for the allocation, but, instead of
selecting the first available port, we try so use the 1:1 mapping
expected by the driver today.

Bspec: 68954
Co-developed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---

NOTE: This patch is still a WIP. There are some opens to resolve here.
Nevertheless, I'm sending it here for early feedback.

For the HIP-index stuff, I have a local refactor started and need to
finish it up and send it.

The other open is about concurrent calls to iom_dp_resource_lock().  It
is likely that we need to have a software lock to prevent concurrent
access to IOM_DP_HW_RESOURCE_SEMAPHORE from our driver.
---
 drivers/gpu/drm/i915/display/intel_display_regs.h |  20 ++-
 drivers/gpu/drm/i915/display/intel_tc.c           | 151 +++++++++++++++++++++-
 2 files changed, 169 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e2414b730db..edf2ea847ed1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2923,6 +2923,25 @@ enum skl_power_gate {
 #define   DP_PIN_ASSIGNMENT(idx, x)		((x) << ((idx) * 4))
 /* See enum intel_tc_pin_assignment for the pin assignment field values. */
 
+/*
+ * FIXME: There is also a definition for this register in intel_dkl_phy_regs.h.
+ * We need to consolidate the definitions.
+ */
+#define HIP_INDEX_REG0				_MMIO(0x1010a0)
+#define   HIP_168_INDEX_MASK			REG_GENMASK(3, 0)
+#define   HIP_168_IOM_RES_MGMT			REG_FIELD_PREP(HIP_168_INDEX_MASK, 0x1)
+
+#define IOM_DP_HW_RESOURCE_SEMAPHORE		_MMIO(0x168038)
+#define   IOM_DP_HW_SEMLOCK			REG_BIT(31)
+#define   IOM_REQUESTOR_ID_MASK			REG_GENMASK(3, 0)
+#define   IOM_REQUESTOR_ID_DISPLAY_ENGINE	REG_FIELD_PREP(IOM_REQUESTOR_ID_MASK, 0x4)
+
+#define IOM_DP_RESOURCE_MNG			_MMIO(0x16802c)
+#define   IOM_DDI_CONSUMER_SHIFT(tc_port)	((tc_port) * 4)
+#define   IOM_DDI_CONSUMER_MASK(tc_port)	(0xf << IOM_DDI_CONSUMER_SHIFT(tc_port))
+#define   IOM_DDI_CONSUMER(tc_port, x)		((x) << IOM_DDI_CONSUMER_SHIFT(tc_port))
+#define   IOM_DDI_CONSUMER_STATIC_TC(tc_port)	IOM_DDI_CONSUMER(tc_port, 0x8 + (tc_port))
+
 #define _TCSS_DDI_STATUS_1			0x161500
 #define _TCSS_DDI_STATUS_2			0x161504
 #define TCSS_DDI_STATUS(tc)			_MMIO(_PICK_EVEN(tc, \
@@ -2961,5 +2980,4 @@ enum skl_power_gate {
 #define   MTL_TRDPRE_MASK		REG_GENMASK(7, 0)
 
 
-
 #endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index c4a5601c5107..5a0e2d9cccd3 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -10,6 +10,7 @@
 #include "i915_reg.h"
 #include "i915_utils.h"
 #include "intel_atomic.h"
+#include "intel_bios.h"
 #include "intel_cx0_phy_regs.h"
 #include "intel_ddi.h"
 #include "intel_de.h"
@@ -25,6 +26,9 @@
 #include "intel_modeset_lock.h"
 #include "intel_tc.h"
 
+#define IOM_DP_RES_SEMAPHORE_LOCK_TIMEOUT_US	10
+#define IOM_DP_RES_SEMAPHORE_RETRY_TIMEOUT_US	10000
+
 enum tc_port_mode {
 	TC_PORT_DISCONNECTED,
 	TC_PORT_TBT_ALT,
@@ -1200,6 +1204,143 @@ static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
 	__tc_cold_unblock(tc, domain, tc_cold_wref);
 }
 
+static void iom_res_mgmt_prepare_reg_access(struct intel_display *display)
+{
+	/*
+	 * IOM resource management registers live in the 2nd 4KB page of IOM
+	 * address space. So we need to configure HIP_INDEX_REG0 with the
+	 * correct index.
+	 *
+	 * FIXME: We need to have this and dekel PHY implementation using a
+	 * common abstraction to access registers on the HIP-indexed ranges, and
+	 * this function would then be dropped.
+	 */
+	intel_de_rmw(display, HIP_INDEX_REG0,
+		     HIP_168_INDEX_MASK, HIP_168_IOM_RES_MGMT);
+}
+
+/*
+ * FIXME: This function also needs to avoid concurrent accesses from the driver
+ * itself, possibly via a software lock.
+ */
+static int iom_dp_resource_lock(struct intel_tc_port *tc)
+{
+	struct intel_display *display = to_intel_display(tc->dig_port);
+	u32 val = IOM_DP_HW_SEMLOCK | IOM_REQUESTOR_ID_DISPLAY_ENGINE;
+	int ret;
+
+	iom_res_mgmt_prepare_reg_access(display);
+	ret = poll_timeout_us(intel_de_write(display, IOM_DP_HW_RESOURCE_SEMAPHORE, val),
+			      (intel_de_read(display, IOM_DP_HW_RESOURCE_SEMAPHORE) & val) == val,
+			      IOM_DP_RES_SEMAPHORE_LOCK_TIMEOUT_US,
+			      IOM_DP_RES_SEMAPHORE_RETRY_TIMEOUT_US, false);
+
+	if (ret)
+		drm_err(display->drm, "Port %s: timeout trying to lock IOM semaphore\n",
+			tc->port_name);
+
+	return ret;
+}
+
+static void iom_dp_resource_unlock(struct intel_tc_port *tc)
+{
+	struct intel_display *display = to_intel_display(tc->dig_port);
+
+	iom_res_mgmt_prepare_reg_access(display);
+	intel_de_write(display, IOM_DP_HW_RESOURCE_SEMAPHORE, IOM_REQUESTOR_ID_DISPLAY_ENGINE);
+}
+
+static bool xe3p_tc_iom_allocate_ddi(struct intel_tc_port *tc, bool allocate)
+{
+	struct intel_display *display = to_intel_display(tc->dig_port);
+	struct intel_digital_port *dig_port = tc->dig_port;
+	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
+	u32 val;
+	u32 consumer;
+	u32 expected_consumer;
+	bool ret;
+
+	if (DISPLAY_VER(display) < 35)
+		return true;
+
+	if (tc->mode != TC_PORT_LEGACY)
+		return true;
+
+	if (!intel_bios_encoder_supports_dyn_port_over_tc(dig_port->base.devdata))
+		return true;
+
+	if (iom_dp_resource_lock(tc))
+		return false;
+
+	val = intel_de_read(display, IOM_DP_RESOURCE_MNG);
+
+	consumer = val & IOM_DDI_CONSUMER_MASK(tc_port);
+	consumer >>= IOM_DDI_CONSUMER_SHIFT(tc_port);
+
+	/*
+	 * Bspec instructs to select first available DDI, but our driver is not
+	 * ready for such dynamic allocation yet. For now, we force a "static"
+	 * allocation: map the physical port (where HPD happens) to the
+	 * encoder's DDI (logical TC port, represented by tc_port).
+	 */
+	expected_consumer = IOM_DDI_CONSUMER_STATIC_TC(tc_port);
+	expected_consumer >>= IOM_DDI_CONSUMER_SHIFT(tc_port);
+
+	if (allocate) {
+		struct intel_encoder *other_encoder;
+
+		/*
+		 * Check if this encoder's DDI is already allocated for another
+		 * physical port, which could have happened prior to the driver
+		 * taking over (e.g. GOP).
+		 */
+		for_each_intel_encoder(display->drm, other_encoder) {
+			enum tc_port other_tc_port = intel_encoder_to_tc(other_encoder);
+			u32 other_consumer;
+
+			if (tc_port == TC_PORT_NONE || other_tc_port == tc_port)
+				continue;
+
+			other_consumer = val & IOM_DDI_CONSUMER_MASK(other_tc_port);
+			other_consumer >>= IOM_DDI_CONSUMER_SHIFT(other_tc_port);
+			if (other_consumer == expected_consumer) {
+				drm_err(display->drm, "Port %s: expected consumer %u already allocated another DDI; IOM_DP_RESOURCE_MNG=0x%08x\n",
+					tc->port_name, expected_consumer, val);
+				ret = false;
+				goto out_resource_unlock;
+			}
+		}
+
+		if (consumer == 0) {
+			/* DDI is free to use, let's allocate it. */
+			val &= ~IOM_DDI_CONSUMER_MASK(tc_port);
+			val |= IOM_DDI_CONSUMER(tc_port, expected_consumer);
+			intel_de_write(display, IOM_DP_RESOURCE_MNG, val);
+			ret = true;
+		} else if (consumer == expected_consumer) {
+			/*
+			 * Nothing to do, as the expected "static" DDI allocation is
+			 * already in place.
+			 */
+			ret = true;
+		} else {
+			drm_err(display->drm, "Port %s: DDI already allocated for consumer %u; IOM_DP_RESOURCE_MNG=0x%08x\n",
+				tc->port_name, consumer, val);
+			ret = false;
+		}
+	} else {
+		drm_WARN_ON(display->drm, consumer != expected_consumer);
+		val &= ~IOM_DDI_CONSUMER_MASK(tc_port);
+		intel_de_write(display, IOM_DP_RESOURCE_MNG, val);
+		ret = true;
+	}
+
+out_resource_unlock:
+	iom_dp_resource_unlock(tc);
+
+	return ret;
+}
+
 static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
 {
 	tc->lock_wakeref = tc_cold_block(tc);
@@ -1210,9 +1351,12 @@ static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
 		return true;
 	}
 
-	if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
+	if (!xe3p_tc_iom_allocate_ddi(tc, true))
 		goto out_unblock_tccold;
 
+	if (!xelpdp_tc_phy_enable_tcss_power(tc, true))
+		goto out_deallocate_ddi;
+
 	xelpdp_tc_phy_take_ownership(tc, true);
 
 	read_pin_configuration(tc);
@@ -1226,6 +1370,9 @@ static bool xelpdp_tc_phy_connect(struct intel_tc_port *tc, int required_lanes)
 	xelpdp_tc_phy_take_ownership(tc, false);
 	xelpdp_tc_phy_wait_for_tcss_power(tc, false);
 
+out_deallocate_ddi:
+	xe3p_tc_iom_allocate_ddi(tc, false);
+
 out_unblock_tccold:
 	tc_cold_unblock(tc, fetch_and_zero(&tc->lock_wakeref));
 
@@ -1236,6 +1383,8 @@ static void xelpdp_tc_phy_disconnect(struct intel_tc_port *tc)
 {
 	switch (tc->mode) {
 	case TC_PORT_LEGACY:
+		xe3p_tc_iom_allocate_ddi(tc, false);
+		fallthrough;
 	case TC_PORT_DP_ALT:
 		xelpdp_tc_phy_take_ownership(tc, false);
 		xelpdp_tc_phy_enable_tcss_power(tc, false);

-- 
2.51.0

[PATCH 32/32] drm/i915/nvls: Add NVL-S display support

[Gustavo Sousa]

From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>

Add platform description and PCI IDs for NVL-S.

BSpec: 74201
Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_device.h | 4 +++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index a38de39ed98c..2350ade1419c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1420,6 +1420,10 @@ static const struct platform_desc ptl_desc = {
 	}
 };
 
+static const struct platform_desc nvl_desc = {
+	PLATFORM(novalake),
+};
+
 __diag_pop();
 
 /*
@@ -1495,6 +1499,7 @@ static const struct {
 	INTEL_BMG_IDS(INTEL_DISPLAY_DEVICE, &bmg_desc),
 	INTEL_PTL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
 	INTEL_WCL_IDS(INTEL_DISPLAY_DEVICE, &ptl_desc),
+	INTEL_NVLS_IDS(INTEL_DISPLAY_DEVICE, &nvl_desc),
 };
 
 static const struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 8fdb8a0a4282..ed03630f9dcc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -102,7 +102,9 @@ struct pci_dev;
 	func(battlemage) \
 	/* Display ver 30 (based on GMD ID) */ \
 	func(pantherlake) \
-	func(pantherlake_wildcatlake)
+	func(pantherlake_wildcatlake) \
+	/* Display ver 35 (based on GMD ID) */ \
+	func(novalake)
 
 
 #define __MEMBER(name) unsigned long name:1;

-- 
2.51.0

RE: [PATCH 28/32] drm/i915/power: Use intel_encoder_is_tc()

[Kandpal, Suraj]

> Subject: [PATCH 28/32] drm/i915/power: Use intel_encoder_is_tc()
> 
> Starting with Xe3p_LPD, when intel_phy_is_tc() returns true, it does not
> necessarily mean that the port is connected to a PHY in the Type-C subsystem.
> The reason is that there is now a VBT field called dedicated_external that will
> indicate that a Type-C capable port is connected to a (most likely)
> combo/dedicated PHY.  When that's the case, we must not do the extra
> programming required for Type-C connections.
> 
> In an upcoming change, we will modify intel_encoder_is_tc() to take the VBT
> field dedicated_external into consideration.  Update intel_display_power_well.c
> to use that function instead of intel_phy_is_tc().
> 
> Note that, even though icl_aux_power_well_{enable,disable} are not part of
> Xe3p_LPD's display paths, we modify them anyway for uniformity.
> 
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  .../drm/i915/display/intel_display_power_well.c    | 26 +++++++++++++++-------
>  1 file changed, 18 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index ba2552adb58b..e8200672dcf3 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -256,8 +256,9 @@ aux_ch_to_digital_port(struct intel_display *display,
>  	return NULL;
>  }
> 
> -static enum phy icl_aux_pw_to_phy(struct intel_display *display,
> -				  const struct i915_power_well *power_well)
> +static struct intel_encoder *
> +icl_aux_pw_to_encoder(struct intel_display *display,
> +		      const struct i915_power_well *power_well)
>  {
>  	enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
>  	struct intel_digital_port *dig_port = aux_ch_to_digital_port(display,
> aux_ch); @@ -269,7 +270,15 @@ static enum phy icl_aux_pw_to_phy(struct
> intel_display *display,
>  	 * as HDMI-only and routed to a combo PHY, the encoder either won't
> be
>  	 * present at all or it will not have an aux_ch assigned.
>  	 */
> -	return dig_port ? intel_encoder_to_phy(&dig_port->base) :
> PHY_NONE;
> +	return dig_port ? &dig_port->base : NULL; }
> +
> +static enum phy icl_aux_pw_to_phy(struct intel_display *display,
> +				  const struct i915_power_well *power_well) {
> +	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display,
> +power_well);
> +
> +	return encoder ? intel_encoder_to_phy(encoder) : PHY_NONE;
>  }
> 
>  static void hsw_wait_for_power_well_enable(struct intel_display *display, @@
> -568,9 +577,9 @@ static void  icl_aux_power_well_enable(struct intel_display
> *display,
>  			  struct i915_power_well *power_well)  {
> -	enum phy phy = icl_aux_pw_to_phy(display, power_well);
> +	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display,
> +power_well);
> 
> -	if (intel_phy_is_tc(display, phy))
> +	if (encoder && intel_encoder_is_tc(encoder))
>  		return icl_tc_phy_aux_power_well_enable(display,
> power_well);
>  	else if (display->platform.icelake)
>  		return icl_combo_phy_aux_power_well_enable(display,
> @@ -583,9 +592,9 @@ static void
>  icl_aux_power_well_disable(struct intel_display *display,
>  			   struct i915_power_well *power_well)  {
> -	enum phy phy = icl_aux_pw_to_phy(display, power_well);
> +	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display,
> +power_well);
> 
> -	if (intel_phy_is_tc(display, phy))
> +	if (encoder && intel_encoder_is_tc(encoder))
>  		return hsw_power_well_disable(display, power_well);
>  	else if (display->platform.icelake)
>  		return icl_combo_phy_aux_power_well_disable(display,
> @@ -1847,10 +1856,11 @@ tgl_tc_cold_off_power_well_is_enabled(struct
> intel_display *display,  static void xelpdp_aux_power_well_enable(struct
> intel_display *display,
>  					 struct i915_power_well *power_well)
> {
> +	struct intel_encoder *encoder = icl_aux_pw_to_encoder(display,
> +power_well);
>  	enum aux_ch aux_ch = i915_power_well_instance(power_well)-
> >xelpdp.aux_ch;
>  	enum phy phy = icl_aux_pw_to_phy(display, power_well);
> 
> -	if (intel_phy_is_tc(display, phy))
> +	if (encoder && intel_encoder_is_tc(encoder))
>  		icl_tc_port_assert_ref_held(display, power_well,
>  					    aux_ch_to_digital_port(display,
> aux_ch));
> 
> 
> --
> 2.51.0

RE: [PATCH 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode

[Kandpal, Suraj]

> Subject: [PATCH 18/32] drm/i915/xe3p_lpd: Drop support for interlace mode
> 
> From: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> 
> Interlace mode is officially removed from HW from Xe3p_LPD.  The register
> TRANS_VSYNCSHIFT and the bits in TRANS_CONF are now removed, so make
> sure we do not set/get these anymore.
> 
> Bspec: 69961, 70000
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d5b2612d4ec2..6ac718192e1c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -2631,7 +2631,7 @@ static void intel_set_transcoder_timings(const struct
> intel_crtc_state *crtc_sta
>  		crtc_vblank_start = 1;
>  	}
> 
> -	if (DISPLAY_VER(display) >= 4)
> +	if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 35)
>  		intel_de_write(display,
>  			       TRANS_VSYNCSHIFT(display, cpu_transcoder),
>  			       vsyncshift);
> @@ -2769,7 +2769,7 @@ static bool intel_pipe_is_interlaced(const struct
> intel_crtc_state *crtc_state)
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
> 
> -	if (DISPLAY_VER(display) == 2)
> +	if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 35)
>  		return false;
> 
>  	if (DISPLAY_VER(display) >= 9 ||
> @@ -3160,10 +3160,12 @@ static void hsw_set_transconf(const struct
> intel_crtc_state *crtc_state)
>  	if (display->platform.haswell && crtc_state->dither)
>  		val |= TRANSCONF_DITHER_EN |
> TRANSCONF_DITHER_TYPE_SP;
> 
> -	if (crtc_state->hw.adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> -		val |= TRANSCONF_INTERLACE_IF_ID_ILK;
> -	else
> -		val |= TRANSCONF_INTERLACE_PF_PD_ILK;
> +	if (DISPLAY_VER(display) < 35) {
> +		if (crtc_state->hw.adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE)
> +			val |= TRANSCONF_INTERLACE_IF_ID_ILK;
> +		else
> +			val |= TRANSCONF_INTERLACE_PF_PD_ILK;
> +	}
> 
>  	if (display->platform.haswell &&
>  	    crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
> 
> --
> 2.51.0

✓ i915.CI.BAT: success for drm/i915/display: Add initial support for Xe3p_LPD

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5718 bytes --]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD
URL   : https://patchwork.freedesktop.org/series/155952/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17362 -> Patchwork_155952v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/index.html

Participating hosts (41 -> 39)
------------------------------

  Missing    (2): fi-glk-j4005 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_155952v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
    - bat-dg2-11:         [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-dg2-11/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-dg2-11/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  * igt@runner@aborted:
    - fi-bsw-n3050:       NOTRUN -> [FAIL][7] ([i915#15124])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/fi-bsw-n3050/igt@runner@aborted.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [DMESG-FAIL][8] ([i915#12061]) -> [PASS][9] +1 other test pass
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-mtlp-8/igt@i915_selftest@live.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@sanitycheck:
    - bat-apl-1:          [DMESG-WARN][10] ([i915#13735]) -> [PASS][11] +77 other tests pass
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-apl-1/igt@i915_selftest@live@sanitycheck.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-apl-1/igt@i915_selftest@live@sanitycheck.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][12] ([i915#12061]) -> [PASS][13] +1 other test pass
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-arlh-3/igt@i915_selftest@live@workarounds.html
    - bat-dg2-9:          [DMESG-FAIL][14] ([i915#12061]) -> [PASS][15] +1 other test pass
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - bat-apl-1:          [DMESG-WARN][16] ([i915#13735] / [i915#180]) -> [PASS][17] +49 other tests pass
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-apl-1/igt@kms_pm_rpm@basic-pci-d3-state.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-apl-1/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@basic-rte:
    - bat-rpls-4:         [DMESG-WARN][18] ([i915#13400]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-rpls-4/igt@kms_pm_rpm@basic-rte.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-rpls-4/igt@kms_pm_rpm@basic-rte.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][20] ([i915#12061] / [i915#14204]) -> [DMESG-FAIL][21] ([i915#12061] / [i915#13929])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-atsm-1/igt@i915_selftest@live.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-atsm-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][22] ([i915#14204]) -> [DMESG-FAIL][23] ([i915#13929])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/bat-atsm-1/igt@i915_selftest@live@mman.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13400]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13400
  [i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
  [i915#15124]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15124
  [i915#180]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/180


Build changes
-------------

  * Linux: CI_DRM_17362 -> Patchwork_155952v1

  CI-20190529: 20190529
  CI_DRM_17362: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8582: 8582
  Patchwork_155952v1: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/index.html

[-- Attachment #2: Type: text/html, Size: 7293 bytes --]

Re: [PATCH 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards

[Shekhar Chauhan]

On 10/15/2025 8:45, Gustavo Sousa wrote:
> From: Luca Coelho <luciano.coelho@intel.com>
>
> Starting from display version 35, we don't need to use method1 to

In the patch title and this description, can we have something which 
explains what exactly is method1 or method2? Seems too vague.

-shekhar

> calculate the watermark values anymore, so skip it.
>
> Bspec: 68985
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>   drivers/gpu/drm/i915/display/skl_watermark.c | 2 ++
>   1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 88342d07727f..fba7448c4920 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -1809,6 +1809,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>   
>   	if (wp->y_tiled) {
>   		selected_result = max_fixed16(method2, wp->y_tile_minimum);
> +	} else if (DISPLAY_VER(display) >= 35) {
> +		selected_result = method2;
>   	} else {
>   		if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
>   		     wp->dbuf_block_size < 1) &&
>

Re: [PATCH 01/32] drm/xe/nvl: Define NVL-S platform

[Shekhar Chauhan]

On 10/15/2025 8:45, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Provide the basic platform definitions and PCI IDs for NVL-S.
>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
> This is brought as a dependency from the series for Xe,
> https://patchwork.freedesktop.org/series/155866/, so the display side
> can be reviewed independently.

Some of the changes below are redundant w.r.t the Xe series you 
mentioned above, but maintainers can take care of that while applying 
these patches.

LGTM,
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>

> ---
>   drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
>   drivers/gpu/drm/xe/xe_platform_types.h | 1 +
>   include/drm/intel/pciids.h             | 9 +++++++++
>   3 files changed, 19 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 24a38904bb50..cc29678be1fa 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -373,6 +373,14 @@ static const struct xe_device_desc ptl_desc = {
>   	.vm_max_level = 4,
>   };
>   
> +static const struct xe_device_desc nvls_desc = {
> +	PLATFORM(NOVALAKE_S),
> +	.dma_mask_size = 46,
> +	.has_display = true,
> +	.max_gt_per_tile = 2,
> +	.require_force_probe = true,
> +};
> +
>   #undef PLATFORM
>   __diag_pop();
>   
> @@ -401,6 +409,7 @@ static const struct pci_device_id pciidlist[] = {
>   	INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>   	INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>   	INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
> +	INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>   	{ }
>   };
>   MODULE_DEVICE_TABLE(pci, pciidlist);
> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
> index 3e332214c7bb..78286285c249 100644
> --- a/drivers/gpu/drm/xe/xe_platform_types.h
> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
> @@ -24,6 +24,7 @@ enum xe_platform {
>   	XE_LUNARLAKE,
>   	XE_BATTLEMAGE,
>   	XE_PANTHERLAKE,
> +	XE_NOVALAKE_S,
>   };
>   
>   enum xe_subplatform {
> diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
> index 452c1de606ff..13c592e1a28c 100644
> --- a/include/drm/intel/pciids.h
> +++ b/include/drm/intel/pciids.h
> @@ -887,4 +887,13 @@
>   	MACRO__(0xFD80, ## __VA_ARGS__), \
>   	MACRO__(0xFD81, ## __VA_ARGS__)
>   
> +/* NVL-S */
> +#define INTEL_NVLS_IDS(MACRO__, ...) \
> +	MACRO__(0xD740, ## __VA_ARGS__), \
> +	MACRO__(0xD741, ## __VA_ARGS__), \
> +	MACRO__(0xD742, ## __VA_ARGS__), \
> +	MACRO__(0xD743, ## __VA_ARGS__), \
> +	MACRO__(0xD744, ## __VA_ARGS__), \
> +	MACRO__(0xD745, ## __VA_ARGS__)
> +
>   #endif /* __PCIIDS_H__ */
>

Re: [PATCH 01/32] drm/xe/nvl: Define NVL-S platform

[Shekhar Chauhan]

On 10/15/2025 13:37, Shekhar Chauhan wrote:
>
> On 10/15/2025 8:45, Gustavo Sousa wrote:
>> From: Matt Roper <matthew.d.roper@intel.com>
>>
>> Provide the basic platform definitions and PCI IDs for NVL-S.
>>
>> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>> This is brought as a dependency from the series for Xe,
>> https://patchwork.freedesktop.org/series/155866/, so the display side
>> can be reviewed independently.
Wait, I realise, its the exact same patch brought in for dependency 
issues. My bad. Though, the patch looks clean, the RB stands.
>
> Some of the changes below are redundant w.r.t the Xe series you 
> mentioned above, but maintainers can take care of that while applying 
> these patches.
>
> LGTM,
> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>
>> ---
>>   drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
>>   drivers/gpu/drm/xe/xe_platform_types.h | 1 +
>>   include/drm/intel/pciids.h             | 9 +++++++++
>>   3 files changed, 19 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>> index 24a38904bb50..cc29678be1fa 100644
>> --- a/drivers/gpu/drm/xe/xe_pci.c
>> +++ b/drivers/gpu/drm/xe/xe_pci.c
>> @@ -373,6 +373,14 @@ static const struct xe_device_desc ptl_desc = {
>>       .vm_max_level = 4,
>>   };
>>   +static const struct xe_device_desc nvls_desc = {
>> +    PLATFORM(NOVALAKE_S),
>> +    .dma_mask_size = 46,
>> +    .has_display = true,
>> +    .max_gt_per_tile = 2,
>> +    .require_force_probe = true,
>> +};
>> +
>>   #undef PLATFORM
>>   __diag_pop();
>>   @@ -401,6 +409,7 @@ static const struct pci_device_id pciidlist[] = {
>>       INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>>       INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>>       INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>> +    INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>>       { }
>>   };
>>   MODULE_DEVICE_TABLE(pci, pciidlist);
>> diff --git a/drivers/gpu/drm/xe/xe_platform_types.h 
>> b/drivers/gpu/drm/xe/xe_platform_types.h
>> index 3e332214c7bb..78286285c249 100644
>> --- a/drivers/gpu/drm/xe/xe_platform_types.h
>> +++ b/drivers/gpu/drm/xe/xe_platform_types.h
>> @@ -24,6 +24,7 @@ enum xe_platform {
>>       XE_LUNARLAKE,
>>       XE_BATTLEMAGE,
>>       XE_PANTHERLAKE,
>> +    XE_NOVALAKE_S,
>>   };
>>     enum xe_subplatform {
>> diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
>> index 452c1de606ff..13c592e1a28c 100644
>> --- a/include/drm/intel/pciids.h
>> +++ b/include/drm/intel/pciids.h
>> @@ -887,4 +887,13 @@
>>       MACRO__(0xFD80, ## __VA_ARGS__), \
>>       MACRO__(0xFD81, ## __VA_ARGS__)
>>   +/* NVL-S */
>> +#define INTEL_NVLS_IDS(MACRO__, ...) \
>> +    MACRO__(0xD740, ## __VA_ARGS__), \
>> +    MACRO__(0xD741, ## __VA_ARGS__), \
>> +    MACRO__(0xD742, ## __VA_ARGS__), \
>> +    MACRO__(0xD743, ## __VA_ARGS__), \
>> +    MACRO__(0xD744, ## __VA_ARGS__), \
>> +    MACRO__(0xD745, ## __VA_ARGS__)
>> +
>>   #endif /* __PCIIDS_H__ */
>>

Re: [PATCH 02/32] drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features

[Shekhar Chauhan]

On 10/15/2025 8:45, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
>
> Xe3p_LPD (display version 35) is similar to Xe2_LPD with respect to the
> features described by struct intel_display_device_info, so reuse its
> device descriptor.
>
> Bspec: 74304
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Maybe we can add Bspec: 74201 as well, but nothing that might stop the 
block the patch, so with that aside, LGTM,

Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display_device.c | 1 +
>   1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index f3f1f25b0f38..a38de39ed98c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -1507,6 +1507,7 @@ static const struct {
>   	{ 20,  0, &xe2_lpd_display },
>   	{ 30,  0, &xe2_lpd_display },
>   	{ 30,  2, &wcl_display },
> +	{ 35,  0, &xe2_lpd_display },
>   };
>   
>   static const struct intel_display_device_info *
>

Re: [PATCH 21/32] drm/i915/xe3p_lpd: Extend Wa_16025573575

[Shekhar Chauhan]

On 10/15/2025 8:45, Gustavo Sousa wrote:
> Wa_16025573575 also applies to Xe3p_LPD, so let's include it in the IP
> version checks.
>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
LGTM,
Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_display_wa.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 31cd2c9cd488..f897ad3862f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -49,7 +49,8 @@ void intel_display_wa_apply(struct intel_display *display)
>    */
>   static bool intel_display_needs_wa_16025573575(struct intel_display *display)
>   {
> -	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002;
> +	return DISPLAY_VERx100(display) == 3000 || DISPLAY_VERx100(display) == 3002 ||
> +		DISPLAY_VERx100(display) == 3500;
>   }
>   
>   /*
>

✓ i915.CI.Full: success for drm/i915/display: Add initial support for Xe3p_LPD

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 197613 bytes --]

== Series Details ==

Series: drm/i915/display: Add initial support for Xe3p_LPD
URL   : https://patchwork.freedesktop.org/series/155952/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_17362_full -> Patchwork_155952v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts

New tests
---------

  New tests have been introduced between CI_DRM_17362_full and Patchwork_155952v1_full:

### New IGT tests (326) ###

  * igt@kms_atomic@plane-overlay-legacy@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.46] s

  * igt@kms_atomic@test-only@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.28] s

  * igt@kms_atomic_interruptible@legacy-dpms@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [6.17] s

  * igt@kms_atomic_interruptible@legacy-dpms@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [6.20] s

  * igt@kms_atomic_interruptible@legacy-pageflip@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [6.24] s

  * igt@kms_atomic_interruptible@universal-setplane-primary@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [6.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-mc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-mc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.29] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-mc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-mc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-cc-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-cc-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.20] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-4-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-linear-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-linear-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-linear-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-linear-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-x-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-x-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-x-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-1-x-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-linear-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-linear-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-x-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-x-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.28] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-rc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.23] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.18] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-a-hdmi-a-4-y-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.21] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-mc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-mc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.28] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-mc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-mc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-cc-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-cc-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-4-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-linear-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-linear-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-linear-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-linear-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-linear-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-linear-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-x-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-x-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.28] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-rc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-4-y-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-mc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-mc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.24] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-mc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-mc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-cc-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-cc-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-4-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-linear-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-linear-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-linear-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-linear-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.10] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.11] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-2-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-linear-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-linear-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-x-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-x-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.26] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-rc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-4-y-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-mc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-mc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.26] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-mc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-mc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-mc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-mc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-cc-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-cc-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-cc-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-4-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-linear-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-linear-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-linear-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-linear-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-4-mc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-4-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-1-x-to-4-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-linear-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-linear-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-linear-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-linear-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-linear-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-x-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-x-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-x-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-x-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-x-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-cc-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-cc-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-cc-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-cc-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.26] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-rc-ccs-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-to-linear:
    - Statuses : 1 pass(s)
    - Exec time: [0.15] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-to-x:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-to-y:
    - Statuses : 1 pass(s)
    - Exec time: [0.13] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-to-y-rc-ccs:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_flip_tiling@flip-change-tiling@pipe-d-hdmi-a-4-y-to-y-rc-ccs-cc:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_invalid_mode@bad-hsync-end@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-hsync-end@pipe-b-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-hsync-end@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-hsync-start@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.05] s

  * igt@kms_invalid_mode@bad-hsync-start@pipe-b-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-hsync-start@pipe-c-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-hsync-start@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-htotal@pipe-a-hdmi-a-2:
    - Statuses : 2 pass(s)
    - Exec time: [0.00, 0.04] s

  * igt@kms_invalid_mode@bad-htotal@pipe-b-hdmi-a-2:
    - Statuses : 2 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_invalid_mode@bad-htotal@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-vsync-start@pipe-a-hdmi-a-2:
    - Statuses : 3 pass(s)
    - Exec time: [0.00, 0.05] s

  * igt@kms_invalid_mode@bad-vsync-start@pipe-b-hdmi-a-2:
    - Statuses : 3 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-vsync-start@pipe-c-hdmi-a-2:
    - Statuses : 3 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@bad-vsync-start@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@int-max-clock@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@int-max-clock@pipe-b-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@int-max-clock@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@uint-max-clock@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.04] s

  * igt@kms_invalid_mode@uint-max-clock@pipe-b-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@uint-max-clock@pipe-c-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@uint-max-clock@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-clock@pipe-a-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.09] s

  * igt@kms_invalid_mode@zero-clock@pipe-a-hdmi-a-2:
    - Statuses : 2 pass(s)
    - Exec time: [0.00, 0.04] s

  * igt@kms_invalid_mode@zero-clock@pipe-b-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-clock@pipe-b-hdmi-a-2:
    - Statuses : 2 pass(s)
    - Exec time: [0.0, 0.00] s

  * igt@kms_invalid_mode@zero-clock@pipe-c-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-clock@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-clock@pipe-d-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-hdisplay@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.04] s

  * igt@kms_invalid_mode@zero-hdisplay@pipe-b-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-hdisplay@pipe-c-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-hdisplay@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-vdisplay@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.04] s

  * igt@kms_invalid_mode@zero-vdisplay@pipe-b-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.00] s

  * igt@kms_invalid_mode@zero-vdisplay@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.0] s

  * igt@kms_sequence@get-busy@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.61] s

  * igt@kms_sequence@get-busy@pipe-b-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.40] s

  * igt@kms_sequence@get-busy@pipe-c-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.40] s

  * igt@kms_sequence@get-busy@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.41] s

  * igt@kms_sequence@get-idle@pipe-a-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [2.40] s

  * igt@kms_sequence@get-idle@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.58] s

  * igt@kms_sequence@get-idle@pipe-b-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [2.28] s

  * igt@kms_sequence@get-idle@pipe-b-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.46] s

  * igt@kms_sequence@get-idle@pipe-c-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [2.31] s

  * igt@kms_sequence@get-idle@pipe-d-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [2.30] s

  * igt@kms_sequence@queue-idle@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.59] s

  * igt@kms_sequence@queue-idle@pipe-b-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.46] s

  * igt@kms_sequence@queue-idle@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.46] s

  * igt@kms_universal_plane@cursor-fb-leak@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.49] s

  * igt@kms_vblank@crtc-id@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.35] s

  * igt@kms_vblank@crtc-id@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.22] s

  * igt@kms_vblank@invalid@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.28] s

  * igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [13.83] s

  * igt@kms_vblank@query-forked-busy-hang@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [26.75] s

  * igt@kms_vblank@query-forked-busy-hang@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [13.81] s

  * igt@kms_vblank@query-forked-busy-hang@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [25.00] s

  * igt@kms_vblank@query-forked-busy@pipe-d-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.48] s

  * igt@kms_vblank@query-forked-hang@pipe-b-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.56] s

  * igt@kms_vblank@query-idle@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.34] s

  * igt@kms_vblank@query-idle@pipe-c-hdmi-a-1:
    - Statuses : 1 pass(s)
    - Exec time: [2.40] s

  * igt@kms_vblank@query-idle@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [2.37] s

  * igt@kms_vblank@query-idle@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.17] s

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.95] s

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-c-hdmi-a-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.81] s

  * igt@kms_vblank@ts-continuation-dpms-rpm@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.83] s

  * igt@kms_vblank@ts-continuation-idle-hang@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [6.96] s

  * igt@kms_vblank@ts-continuation-idle-hang@pipe-c-hdmi-a-1:
    - Statuses : 1 pass(s)
    - Exec time: [6.96] s

  * igt@kms_vblank@ts-continuation-idle-hang@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [7.03] s

  * igt@kms_vblank@ts-continuation-idle@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.35] s

  * igt@kms_vblank@ts-continuation-idle@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.17] s

  * igt@kms_vblank@ts-continuation-modeset-hang@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [26.95] s

  * igt@kms_vblank@ts-continuation-modeset-hang@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [25.00] s

  * igt@kms_vblank@ts-continuation-modeset-rpm@pipe-a-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [1.02] s

  * igt@kms_vblank@ts-continuation-modeset-rpm@pipe-c-hdmi-a-1:
    - Statuses : 1 pass(s)
    - Exec time: [0.88] s

  * igt@kms_vblank@ts-continuation-modeset-rpm@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [0.99] s

  * igt@kms_vblank@ts-continuation-modeset@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.46] s

  * igt@kms_vblank@ts-continuation-modeset@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [0.26] s

  * igt@kms_vblank@wait-forked-busy-hang@pipe-a-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [26.48] s

  * igt@kms_vblank@wait-forked-busy-hang@pipe-d-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [24.93] s

  * igt@kms_vblank@wait-forked-busy@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.55] s

  * igt@kms_vblank@wait-forked-busy@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.39] s

  * igt@kms_vblank@wait-idle@pipe-a-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.31] s

  * igt@kms_vblank@wait-idle@pipe-d-hdmi-a-4:
    - Statuses : 1 pass(s)
    - Exec time: [2.17] s

  

Known issues
------------

  Here are the changes found in Patchwork_155952v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-rkl:          NOTRUN -> [SKIP][1] ([i915#8411])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-mtlp:         NOTRUN -> [SKIP][2] ([i915#8411])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@api_intel_bb@object-reloc-purge-cache.html
    - shard-dg2:          NOTRUN -> [SKIP][3] ([i915#8411])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@api_intel_bb@simple-bb-ctx:
    - shard-rkl:          [PASS][4] -> [DMESG-WARN][5] ([i915#12917] / [i915#12964]) +1 other test dmesg-warn
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-8/igt@api_intel_bb@simple-bb-ctx.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@api_intel_bb@simple-bb-ctx.html

  * igt@device_reset@cold-reset-bound:
    - shard-tglu-1:       NOTRUN -> [SKIP][6] ([i915#11078])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@device_reset@cold-reset-bound.html
    - shard-dg2:          NOTRUN -> [SKIP][7] ([i915#11078])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@device_reset@cold-reset-bound.html

  * igt@fbdev@read:
    - shard-rkl:          [PASS][8] -> [SKIP][9] ([i915#14544] / [i915#2582])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@fbdev@read.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@fbdev@read.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-mtlp:         NOTRUN -> [SKIP][10] ([i915#3555] / [i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu:         NOTRUN -> [SKIP][11] ([i915#13008])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-dg2-9:        NOTRUN -> [INCOMPLETE][12] ([i915#13356])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0:
    - shard-dg2-9:        NOTRUN -> [INCOMPLETE][13] ([i915#12392] / [i915#13356])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_ccs@suspend-resume@xmajor-compressed-compfmt0-smem-lmem0.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg2:          NOTRUN -> [SKIP][14] ([i915#7697])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_close_race@multigpu-basic-process.html
    - shard-tglu-1:       NOTRUN -> [SKIP][15] ([i915#7697])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu:         NOTRUN -> [SKIP][16] ([i915#7697])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-rkl:          NOTRUN -> [SKIP][17] ([i915#6335])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk:          NOTRUN -> [INCOMPLETE][18] ([i915#12353]) +1 other test incomplete
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk9/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_ctx_persistence@heartbeat-hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][19] ([i915#8555])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_ctx_persistence@heartbeat-hang.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-dg2-9:        NOTRUN -> [SKIP][20] ([i915#280])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-dg2:          NOTRUN -> [SKIP][21] ([i915#280])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@gem_ctx_sseu@mmap-args.html
    - shard-mtlp:         NOTRUN -> [SKIP][22] ([i915#280])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@in-flight-suspend:
    - shard-rkl:          [PASS][23] -> [DMESG-WARN][24] ([i915#12964]) +14 other tests dmesg-warn
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-8/igt@gem_eio@in-flight-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@bonded-false-hang:
    - shard-dg2:          NOTRUN -> [SKIP][25] ([i915#4812])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_exec_balancer@bonded-false-hang.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-tglu-1:       NOTRUN -> [SKIP][26] ([i915#4525])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_balancer@sliced:
    - shard-dg2-9:        NOTRUN -> [SKIP][27] ([i915#4812]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_exec_balancer@sliced.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-tglu-1:       NOTRUN -> [SKIP][28] ([i915#6334]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][29] ([i915#6344])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_endless@dispatch@vcs1:
    - shard-dg1:          [PASS][30] -> [TIMEOUT][31] ([i915#3778]) +1 other test timeout
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-18/igt@gem_exec_endless@dispatch@vcs1.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-15/igt@gem_exec_endless@dispatch@vcs1.html

  * igt@gem_exec_flush@basic-batch-kernel-default-uc:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#3539] / [i915#4852])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@gem_exec_flush@basic-batch-kernel-default-uc.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg2-9:        NOTRUN -> [SKIP][33] ([i915#3539] / [i915#4852])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg2-9:        NOTRUN -> [SKIP][34] ([i915#3539])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_reloc@basic-cpu-gtt-active:
    - shard-rkl:          NOTRUN -> [SKIP][35] ([i915#14544] / [i915#3281]) +1 other test skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-gtt-active.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#3281]) +8 other tests skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#3281]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_reloc@basic-wc-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][38] ([i915#3281])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_exec_reloc@basic-wc-gtt.html

  * igt@gem_exec_reloc@basic-wc-noreloc:
    - shard-dg2-9:        NOTRUN -> [SKIP][39] ([i915#3281]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_exec_reloc@basic-wc-noreloc.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][40] ([i915#4537] / [i915#4812])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_exec_schedule@semaphore-power:
    - shard-dg2-9:        NOTRUN -> [SKIP][41] ([i915#4537] / [i915#4812])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_exec_schedule@semaphore-power.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [PASS][42] -> [INCOMPLETE][43] ([i915#13356]) +1 other test incomplete
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg2-1/igt@gem_exec_suspend@basic-s0.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-10/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-dg1:          [PASS][44] -> [DMESG-WARN][45] ([i915#4423]) +1 other test dmesg-warn
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-15/igt@gem_exec_suspend@basic-s3-devices.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-18/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_fenced_exec_thrash@no-spare-fences:
    - shard-dg2:          NOTRUN -> [SKIP][46] ([i915#4860]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_fenced_exec_thrash@no-spare-fences.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-rkl:          NOTRUN -> [SKIP][47] ([i915#4613]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-tglu-1:       NOTRUN -> [SKIP][48] ([i915#4613]) +2 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-glk:          NOTRUN -> [SKIP][49] ([i915#4613]) +4 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk6/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_lmem_swapping@verify-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][50] ([i915#4613])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_lmem_swapping@verify-ccs.html

  * igt@gem_lmem_swapping@verify-random-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][51] ([i915#4613]) +2 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@gem_lmem_swapping@verify-random-ccs.html

  * igt@gem_mmap@basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][52] ([i915#4083]) +1 other test skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@big-bo-tiledy:
    - shard-dg2-9:        NOTRUN -> [SKIP][53] ([i915#4077]) +3 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_mmap_gtt@big-bo-tiledy.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][54] ([i915#4077]) +8 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@close:
    - shard-dg2:          NOTRUN -> [SKIP][55] ([i915#4083]) +4 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_mmap_wc@close.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-dg2:          NOTRUN -> [SKIP][56] ([i915#3282]) +3 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@gem_partial_pwrite_pread@reads-uncached.html
    - shard-mtlp:         NOTRUN -> [SKIP][57] ([i915#3282])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-glk:          NOTRUN -> [WARN][58] ([i915#14702] / [i915#2658])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk9/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pwrite@basic-self:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#3282])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@gem_pwrite@basic-self.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-dg2-9:        NOTRUN -> [SKIP][60] ([i915#4270]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@reject-modify-context-protection-off-1:
    - shard-rkl:          [PASS][61] -> [TIMEOUT][62] ([i915#12917] / [i915#12964]) +2 other tests timeout
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-8/igt@gem_pxp@reject-modify-context-protection-off-1.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@gem_pxp@reject-modify-context-protection-off-1.html

  * igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
    - shard-dg2:          NOTRUN -> [SKIP][63] ([i915#4270]) +2 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html

  * igt@gem_readwrite@read-bad-handle:
    - shard-dg2-9:        NOTRUN -> [SKIP][64] ([i915#3282]) +2 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_readwrite@read-bad-handle.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][65] ([i915#5190] / [i915#8428])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][66] ([i915#8428])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_render_copy@y-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#5190] / [i915#8428]) +6 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html

  * igt@gem_set_tiling_vs_pwrite:
    - shard-dg2-9:        NOTRUN -> [SKIP][68] ([i915#4079])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_set_tiling_vs_pwrite.html

  * igt@gem_softpin@evict-snoop:
    - shard-dg2:          NOTRUN -> [SKIP][69] ([i915#4885])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gem_softpin@evict-snoop.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-dg2:          NOTRUN -> [SKIP][70] ([i915#3297]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@gem_userptr_blits@coherency-sync.html
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#3297])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglu-1:       NOTRUN -> [SKIP][72] ([i915#3297] / [i915#3323])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate:
    - shard-dg2-9:        NOTRUN -> [SKIP][73] ([i915#3297] / [i915#4880])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_userptr_blits@map-fixed-invalidate.html

  * igt@gem_userptr_blits@relocations:
    - shard-dg2-9:        NOTRUN -> [SKIP][74] ([i915#3281] / [i915#3297])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-tglu-1:       NOTRUN -> [SKIP][75] ([i915#3297])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-tglu:         NOTRUN -> [SKIP][76] ([i915#3297]) +2 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen3_render_linear_blits:
    - shard-dg2:          NOTRUN -> [SKIP][77] +11 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gen3_render_linear_blits.html

  * igt@gen9_exec_parse@batch-invalid-length:
    - shard-dg2-9:        NOTRUN -> [SKIP][78] ([i915#2856])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@gen9_exec_parse@batch-invalid-length.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-mtlp:         NOTRUN -> [SKIP][79] ([i915#2856])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-tglu-1:       NOTRUN -> [SKIP][80] ([i915#2527] / [i915#2856]) +2 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@gen9_exec_parse@secure-batches.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-dg2:          NOTRUN -> [SKIP][81] ([i915#2856]) +2 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@gen9_exec_parse@shadow-peek.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#2527] / [i915#2856]) +2 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_drm_fdinfo@busy-idle@vcs0:
    - shard-dg2-9:        NOTRUN -> [SKIP][83] ([i915#14073]) +7 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@i915_drm_fdinfo@busy-idle@vcs0.html

  * igt@i915_drm_fdinfo@busy@rcs0:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#14073]) +6 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@i915_drm_fdinfo@busy@rcs0.html

  * igt@i915_drm_fdinfo@busy@vecs1:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#14073]) +7 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@i915_drm_fdinfo@busy@vecs1.html

  * igt@i915_drm_fdinfo@virtual-busy-idle-all:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#14118]) +1 other test skip
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@i915_drm_fdinfo@virtual-busy-idle-all.html

  * igt@i915_module_load@reload-no-display:
    - shard-tglu-1:       NOTRUN -> [DMESG-WARN][87] ([i915#13029] / [i915#14545])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@i915_module_load@reload-no-display.html

  * igt@i915_module_load@resize-bar:
    - shard-rkl:          NOTRUN -> [SKIP][88] ([i915#6412])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-tglu-1:       NOTRUN -> [SKIP][89] ([i915#8399])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_rps@basic-api:
    - shard-dg2:          NOTRUN -> [SKIP][90] ([i915#11681] / [i915#6621])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_pm_rps@thresholds-idle:
    - shard-dg2-9:        NOTRUN -> [SKIP][91] ([i915#11681])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@i915_pm_rps@thresholds-idle.html

  * igt@i915_pm_rps@thresholds-park:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#11681])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@i915_pm_rps@thresholds-park.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][93] -> [SKIP][94] ([i915#7984])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-mtlp-2/igt@i915_power@sanity.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-6/igt@i915_power@sanity.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         [PASS][95] -> [DMESG-FAIL][96] ([i915#12061]) +1 other test dmesg-fail
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-mtlp-7/igt@i915_selftest@live@workarounds.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-2/igt@i915_selftest@live@workarounds.html

  * igt@intel_hwmon@hwmon-write:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#7707])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@intel_hwmon@hwmon-write.html

  * igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
    - shard-mtlp:         NOTRUN -> [SKIP][98] ([i915#4212])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#4212])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglu-1:       NOTRUN -> [SKIP][100] ([i915#12454] / [i915#12712])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-mtlp:         NOTRUN -> [SKIP][101] ([i915#1769] / [i915#3555])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-rkl:          NOTRUN -> [SKIP][102] ([i915#1769] / [i915#3555])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][103] ([i915#5286]) +3 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][104] ([i915#5286]) +2 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#5286])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-16bpp-rotate-270:
    - shard-tglu:         NOTRUN -> [SKIP][106] +45 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_big_fb@linear-16bpp-rotate-270.html

  * igt@kms_big_fb@linear-64bpp-rotate-270:
    - shard-dg2-9:        NOTRUN -> [SKIP][107] +4 other tests skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_big_fb@linear-64bpp-rotate-270.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0:
    - shard-glk:          NOTRUN -> [FAIL][108] ([i915#5138])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#3638])
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#4538] / [i915#5190]) +10 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_big_fb@y-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-dg2-9:        NOTRUN -> [SKIP][111] ([i915#4538] / [i915#5190]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-addfb:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#5190])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_big_fb@yf-tiled-addfb.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][113] ([i915#6095]) +64 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#10307] / [i915#10434] / [i915#6095])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][115] ([i915#6095]) +4 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-edp-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][116] ([i915#6095]) +94 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-13/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][117] ([i915#10307] / [i915#6095]) +19 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][118] ([i915#12313]) +1 other test skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#14544]) +3 other tests skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#14098] / [i915#6095]) +44 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][121] ([i915#12805])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#6095]) +49 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][123] ([i915#6095]) +4 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#6095]) +13 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-b-dp-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#12313])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#6095]) +51 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#10307] / [i915#6095]) +125 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-10/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-rc-ccs-cc@pipe-c-dp-3.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][128] ([i915#4423] / [i915#6095])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-16/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][129] ([i915#12313])
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_chamelium_color@ctm-blue-to-red:
    - shard-mtlp:         NOTRUN -> [SKIP][130] +3 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_chamelium_color@ctm-blue-to-red.html

  * igt@kms_chamelium_edid@dp-edid-read:
    - shard-dg2-9:        NOTRUN -> [SKIP][131] ([i915#11151] / [i915#7828]) +4 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_chamelium_edid@dp-edid-read.html

  * igt@kms_chamelium_edid@dp-mode-timings:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#11151] / [i915#7828]) +4 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_chamelium_edid@dp-mode-timings.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#11151] / [i915#7828]) +8 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@hdmi-cmp-planar-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][134] ([i915#11151] / [i915#7828]) +4 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_chamelium_frames@hdmi-cmp-planar-formats.html

  * igt@kms_chamelium_frames@vga-frame-dump:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#11151] / [i915#14544] / [i915#7828])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_chamelium_frames@vga-frame-dump.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-mtlp:         NOTRUN -> [SKIP][136] ([i915#11151] / [i915#7828])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_color@deep-color:
    - shard-dg2-9:        NOTRUN -> [SKIP][137] ([i915#12655] / [i915#3555])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_color@deep-color.html

  * igt@kms_color@gamma:
    - shard-rkl:          [PASS][138] -> [SKIP][139] ([i915#12655] / [i915#14544]) +1 other test skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_color@gamma.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_color@gamma.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-9:        NOTRUN -> [SKIP][140] ([i915#7118] / [i915#9424])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#3116] / [i915#3299])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][142] ([i915#3116] / [i915#3299])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-dg2:          NOTRUN -> [SKIP][143] ([i915#3299])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-0:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#9424])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_content_protection@lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu-1:       NOTRUN -> [SKIP][145] ([i915#6944] / [i915#9424])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-tglu:         NOTRUN -> [SKIP][146] ([i915#6944] / [i915#7116] / [i915#7118])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-tglu-1:       NOTRUN -> [SKIP][147] ([i915#13049]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-256x256:
    - shard-rkl:          [PASS][148] -> [SKIP][149] ([i915#14544]) +52 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-256x256.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-256x256.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu-1:       NOTRUN -> [FAIL][150] ([i915#13566]) +3 other tests fail
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-512x512:
    - shard-dg2-9:        NOTRUN -> [SKIP][151] ([i915#13049]) +1 other test skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_cursor_crc@cursor-onscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][152] -> [FAIL][153] ([i915#13566]) +1 other test fail
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-tglu-5/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-3/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][154] ([i915#13566]) +3 other tests fail
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-3/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-random-max-size:
    - shard-glk:          NOTRUN -> [SKIP][155] +205 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk9/igt@kms_cursor_crc@cursor-random-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-tglu:         NOTRUN -> [FAIL][156] ([i915#13566]) +1 other test fail
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-dg2:          NOTRUN -> [SKIP][157] ([i915#3555]) +7 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_cursor_crc@cursor-sliding-32x10.html
    - shard-mtlp:         NOTRUN -> [SKIP][158] ([i915#3555] / [i915#8814]) +1 other test skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#4103] / [i915#4213]) +1 other test skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - shard-glk10:        NOTRUN -> [SKIP][160] ([i915#11190]) +5 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk10/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
    - shard-dg2:          NOTRUN -> [SKIP][161] ([i915#13046] / [i915#5354]) +1 other test skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][162] +6 other tests skip
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglu-1:       NOTRUN -> [SKIP][163] ([i915#4103])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2:          NOTRUN -> [SKIP][164] ([i915#9833])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#3555] / [i915#3804])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][166] ([i915#3804])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-tglu:         NOTRUN -> [SKIP][167] ([i915#13749])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-dg2-9:        NOTRUN -> [SKIP][168] ([i915#13749])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-tglu-1:       NOTRUN -> [SKIP][169] ([i915#13748])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#13748])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-tglu:         NOTRUN -> [SKIP][171] ([i915#13707])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#13707])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_draw_crc@draw-method-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][173] ([i915#8812])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_draw_crc@draw-method-mmap-wc.html

  * igt@kms_dsc@dsc-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][174] ([i915#3555] / [i915#3840])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#3840] / [i915#9688])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_dsc@dsc-fractional-bpp.html
    - shard-tglu-1:       NOTRUN -> [SKIP][176] ([i915#3840])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#3840])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][178] ([i915#3555] / [i915#3840])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-dg2:          NOTRUN -> [SKIP][179] ([i915#3840] / [i915#9053])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-rkl:          [PASS][180] -> [SKIP][181] ([i915#14544] / [i915#14561])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_fbcon_fbt@fbc.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][182] ([i915#658]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_feature_discovery@psr1.html
    - shard-tglu-1:       NOTRUN -> [SKIP][183] ([i915#658])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-tglu-1:       NOTRUN -> [SKIP][184] ([i915#3637] / [i915#9934]) +4 other tests skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][185] ([i915#9934]) +1 other test skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][186] ([i915#8381]) +1 other test skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-flip-vs-fences-interruptible:
    - shard-mtlp:         NOTRUN -> [SKIP][187] ([i915#8381])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_flip@2x-flip-vs-fences-interruptible.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#14544] / [i915#9934])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-dg2:          NOTRUN -> [SKIP][189] ([i915#9934]) +6 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-nonexisting-fb:
    - shard-tglu:         NOTRUN -> [SKIP][190] ([i915#3637] / [i915#9934]) +8 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_flip@2x-nonexisting-fb.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#14544] / [i915#3637])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-rkl:          [PASS][192] -> [SKIP][193] ([i915#14544] / [i915#3637]) +7 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-dg2:          [PASS][194] -> [ABORT][195] ([i915#15132])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg2-5/igt@kms_flip@flip-vs-suspend.html
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-10/igt@kms_flip@flip-vs-suspend.html
    - shard-glk:          NOTRUN -> [INCOMPLETE][196] ([i915#12745] / [i915#4839])
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk6/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][197] ([i915#12745])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk6/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend@d-dp3:
    - shard-dg2:          NOTRUN -> [ABORT][198] ([i915#15132])
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-10/igt@kms_flip@flip-vs-suspend@d-dp3.html

  * igt@kms_flip@flip-vs-wf_vblank-interruptible:
    - shard-tglu:         [PASS][199] -> [FAIL][200] ([i915#10826]) +1 other test fail
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-tglu-8/igt@kms_flip@flip-vs-wf_vblank-interruptible.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-8/igt@kms_flip@flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] ([i915#2672] / [i915#3555]) +3 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][202] ([i915#2587] / [i915#2672]) +5 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][203] ([i915#2672] / [i915#3555]) +1 other test skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][204] ([i915#2672] / [i915#3555])
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][205] ([i915#2672] / [i915#3555] / [i915#5190]) +3 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][206] ([i915#2672] / [i915#3555] / [i915#8813]) +1 other test skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][207] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#14544] / [i915#3555])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][209] ([i915#2587] / [i915#2672]) +1 other test skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-rkl:          [PASS][210] -> [SKIP][211] ([i915#14544] / [i915#3555]) +3 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][212] ([i915#2672]) +2 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][213] ([i915#2672]) +3 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][214] ([i915#8708]) +16 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg2-9:        NOTRUN -> [SKIP][215] ([i915#5354]) +9 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][216] ([i915#8708]) +5 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - shard-rkl:          [PASS][217] -> [SKIP][218] ([i915#14544] / [i915#1849] / [i915#5354]) +8 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#10055])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-tiling-y.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2-9:        NOTRUN -> [SKIP][220] ([i915#15102] / [i915#3458]) +5 other tests skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][221] ([i915#8708])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][222] ([i915#1825]) +3 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][223] ([i915#1825]) +10 other tests skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][224] ([i915#15102]) +12 other tests skip
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][225] ([i915#5439])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][226] ([i915#15102] / [i915#3458]) +12 other tests skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#14544] / [i915#1849] / [i915#5354]) +4 other tests skip
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][228] ([i915#5354]) +24 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][229] ([i915#15102] / [i915#3023]) +10 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][230] ([i915#15102]) +13 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#3555] / [i915#8228])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-tglu:         NOTRUN -> [SKIP][232] ([i915#3555] / [i915#8228])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_invalid_mode@zero-hdisplay:
    - shard-rkl:          [PASS][233] -> [SKIP][234] ([i915#14544] / [i915#3555] / [i915#8826])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_invalid_mode@zero-hdisplay.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_invalid_mode@zero-hdisplay.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][235] ([i915#10656])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][236] ([i915#13688])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][237] ([i915#12339]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-dg2-9:        NOTRUN -> [SKIP][238] ([i915#10656])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][239] ([i915#12394]) +1 other test skip
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-dg2:          NOTRUN -> [SKIP][240] ([i915#4816])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][241] ([i915#6301])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
    - shard-tglu-1:       NOTRUN -> [SKIP][242] +43 other tests skip
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes.html

  * igt@kms_pipe_crc_basic@read-crc:
    - shard-rkl:          [PASS][243] -> [SKIP][244] ([i915#11190] / [i915#14544])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_pipe_crc_basic@read-crc.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_pipe_crc_basic@read-crc.html

  * igt@kms_plane@planar-pixel-format-settings:
    - shard-rkl:          [PASS][245] -> [SKIP][246] ([i915#14544] / [i915#9581])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_plane@planar-pixel-format-settings.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane@planar-pixel-format-settings.html

  * igt@kms_plane@plane-panning-bottom-right:
    - shard-rkl:          [PASS][247] -> [SKIP][248] ([i915#14544] / [i915#8825])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_plane@plane-panning-bottom-right.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane@plane-panning-bottom-right.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-rkl:          [PASS][249] -> [SKIP][250] ([i915#14544] / [i915#7294])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_plane_alpha_blend@alpha-opaque-fb.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-tglu:         NOTRUN -> [SKIP][251] ([i915#13958])
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-rkl:          NOTRUN -> [SKIP][252] ([i915#13958])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][253] ([i915#14259])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_plane_scaling@intel-max-src-size:
    - shard-dg2:          NOTRUN -> [SKIP][254] ([i915#6953] / [i915#9423])
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_plane_scaling@intel-max-src-size.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers:
    - shard-rkl:          [PASS][255] -> [SKIP][256] ([i915#14544] / [i915#8152])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-modifiers.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][257] ([i915#12247]) +4 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d:
    - shard-tglu-1:       NOTRUN -> [SKIP][258] ([i915#12247]) +4 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a:
    - shard-rkl:          [PASS][259] -> [SKIP][260] ([i915#12247] / [i915#14544]) +4 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5-upscale-factor-0-25@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25:
    - shard-rkl:          [PASS][261] -> [SKIP][262] ([i915#14544] / [i915#6953] / [i915#8152]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-75-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75:
    - shard-rkl:          [PASS][263] -> [SKIP][264] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152]) +1 other test skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b:
    - shard-rkl:          [PASS][265] -> [SKIP][266] ([i915#12247] / [i915#14544] / [i915#8152]) +5 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-75@pipe-b.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][267] ([i915#9812])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][268] ([i915#12343])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg2:          NOTRUN -> [SKIP][269] ([i915#3828])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_pm_dc@dc5-retention-flops.html
    - shard-mtlp:         NOTRUN -> [SKIP][270] ([i915#3828])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-glk10:        NOTRUN -> [SKIP][271] +529 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk10/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-rkl:          NOTRUN -> [SKIP][272] ([i915#8430])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@cursor:
    - shard-rkl:          [PASS][273] -> [SKIP][274] ([i915#14544] / [i915#1849])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_pm_rpm@cursor.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_pm_rpm@cursor.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-rkl:          [PASS][275] -> [SKIP][276] ([i915#15073])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg2:          NOTRUN -> [SKIP][277] ([i915#15073]) +1 other test skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-tglu-1:       NOTRUN -> [SKIP][278] ([i915#15073])
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [PASS][279] -> [SKIP][280] ([i915#15073])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg2-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
    - shard-tglu:         NOTRUN -> [SKIP][281] ([i915#15073]) +2 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html

  * igt@kms_prime@basic-modeset-hybrid:
    - shard-rkl:          NOTRUN -> [SKIP][282] ([i915#6524])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_prime@basic-modeset-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2:          NOTRUN -> [SKIP][283] ([i915#6524] / [i915#6805])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-1/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf:
    - shard-tglu:         NOTRUN -> [SKIP][284] ([i915#11520]) +5 other tests skip
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_psr2_sf@fbc-pr-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-dg2-9:        NOTRUN -> [SKIP][285] ([i915#11520]) +1 other test skip
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][286] ([i915#11520]) +7 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#11520]) +3 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-mtlp:         NOTRUN -> [SKIP][288] ([i915#12316])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-glk10:        NOTRUN -> [SKIP][289] ([i915#11520]) +13 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk10/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][290] ([i915#11520]) +5 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][291] ([i915#11520]) +6 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk9/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-dg2-9:        NOTRUN -> [SKIP][292] ([i915#9683])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-pr-sprite-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][293] ([i915#9688])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_psr@fbc-pr-sprite-mmap-gtt.html

  * igt@kms_psr@fbc-psr-cursor-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][294] ([i915#9732]) +14 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_psr@fbc-psr-cursor-plane-onoff.html

  * igt@kms_psr@fbc-psr2-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][295] ([i915#9732]) +15 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_psr@fbc-psr2-basic.html

  * igt@kms_psr@psr-sprite-mmap-cpu:
    - shard-dg2-9:        NOTRUN -> [SKIP][296] ([i915#1072] / [i915#9732]) +5 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_psr@psr-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-cursor-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][297] ([i915#1072] / [i915#9732]) +3 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_psr@psr2-cursor-mmap-gtt.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][298] ([i915#1072] / [i915#9732]) +23 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][299] ([i915#9685])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-tglu:         NOTRUN -> [SKIP][300] ([i915#5289])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-rotation-270:
    - shard-dg2:          NOTRUN -> [SKIP][301] ([i915#12755]) +1 other test skip
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_rotation_crc@primary-rotation-270.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg2-9:        NOTRUN -> [SKIP][302] ([i915#12755])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-dg2:          NOTRUN -> [SKIP][303] ([i915#12755] / [i915#5190]) +1 other test skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
    - shard-tglu-1:       NOTRUN -> [SKIP][304] ([i915#5289])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-full-aspect:
    - shard-tglu:         NOTRUN -> [SKIP][305] ([i915#3555]) +4 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_scaling_modes@scaling-mode-full-aspect.html

  * igt@kms_selftest@drm_cmdline_parser@drm_test_cmdline_tv_options:
    - shard-dg2-9:        NOTRUN -> [FAIL][306] ([i915#15119]) +2 other tests fail
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_selftest@drm_cmdline_parser@drm_test_cmdline_tv_options.html
    - shard-glk:          NOTRUN -> [FAIL][307] ([i915#15119]) +2 other tests fail
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk6/igt@kms_selftest@drm_cmdline_parser@drm_test_cmdline_tv_options.html

  * igt@kms_selftest@drm_dp_mst_helper@drm_test_dp_mst_calc_pbn_div:
    - shard-tglu:         NOTRUN -> [FAIL][308] ([i915#15119]) +3 other tests fail
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_selftest@drm_dp_mst_helper@drm_test_dp_mst_calc_pbn_div.html

  * igt@kms_selftest@drm_plane_helper@drm_test_check_invalid_plane_state:
    - shard-tglu-1:       NOTRUN -> [FAIL][309] ([i915#15119]) +2 other tests fail
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_selftest@drm_plane_helper@drm_test_check_invalid_plane_state.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-dg2-9:        NOTRUN -> [SKIP][310] ([i915#3555])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-mtlp:         NOTRUN -> [SKIP][311] ([i915#3555] / [i915#8809])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][312] ([i915#12276]) +1 other test incomplete
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk1/igt@kms_vblank@ts-continuation-dpms-suspend@pipe-a-hdmi-a-1.html

  * igt@kms_vblank@wait-forked-busy-hang@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][313] ([i915#12964]) +7 other tests dmesg-warn
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_vblank@wait-forked-busy-hang@pipe-a-hdmi-a-2.html

  * igt@kms_vrr@flip-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][314] ([i915#3555])
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@negative-basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][315] ([i915#3555] / [i915#9906])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][316] ([i915#9906])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-dg2-9:        NOTRUN -> [SKIP][317] ([i915#9906])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@kms_writeback@writeback-check-output:
    - shard-tglu-1:       NOTRUN -> [SKIP][318] ([i915#2437])
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-tglu:         NOTRUN -> [SKIP][319] ([i915#2437] / [i915#9412]) +1 other test skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-rkl:          NOTRUN -> [SKIP][320] ([i915#2437])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@mi-rpc:
    - shard-dg2:          NOTRUN -> [SKIP][321] ([i915#2434])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@perf@mi-rpc.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          NOTRUN -> [FAIL][322] ([i915#4349]) +4 other tests fail
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@perf_pmu@busy-double-start@vecs1.html

  * igt@perf_pmu@module-unload:
    - shard-tglu-1:       NOTRUN -> [FAIL][323] ([i915#14433])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-1/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-dg2-9:        NOTRUN -> [SKIP][324] ([i915#8516])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-9/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@basic-read:
    - shard-dg2:          NOTRUN -> [SKIP][325] ([i915#3291] / [i915#3708])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@prime_vgem@basic-read.html

  * igt@prime_vgem@fence-read-hang:
    - shard-dg2:          NOTRUN -> [SKIP][326] ([i915#3708])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-5/igt@prime_vgem@fence-read-hang.html

  * igt@sriov_basic@bind-unbind-vf@vf-4:
    - shard-tglu:         NOTRUN -> [FAIL][327] ([i915#12910]) +9 other tests fail
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-4/igt@sriov_basic@bind-unbind-vf@vf-4.html

  
#### Possible fixes ####

  * igt@fbdev@write:
    - shard-rkl:          [SKIP][328] ([i915#14544] / [i915#2582]) -> [PASS][329]
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@fbdev@write.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@fbdev@write.html

  * igt@gem_eio@reset-stress:
    - shard-dg1:          [FAIL][330] ([i915#5784]) -> [PASS][331]
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-19/igt@gem_eio@reset-stress.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-13/igt@gem_eio@reset-stress.html

  * igt@gem_eio@wait-wedge-1us:
    - shard-dg1:          [DMESG-WARN][332] ([i915#4391] / [i915#4423]) -> [PASS][333]
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-17/igt@gem_eio@wait-wedge-1us.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-17/igt@gem_eio@wait-wedge-1us.html

  * igt@gem_mmap_offset@clear-via-pagefault:
    - shard-mtlp:         [ABORT][334] ([i915#14809]) -> [PASS][335] +1 other test pass
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-mtlp-5/igt@gem_mmap_offset@clear-via-pagefault.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-mtlp-4/igt@gem_mmap_offset@clear-via-pagefault.html

  * igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
    - shard-rkl:          [TIMEOUT][336] ([i915#12917] / [i915#12964]) -> [PASS][337]
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html

  * igt@gem_workarounds@suspend-resume-fd:
    - shard-rkl:          [INCOMPLETE][338] ([i915#13356]) -> [PASS][339]
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-3/igt@gem_workarounds@suspend-resume-fd.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_workarounds@suspend-resume-fd.html

  * igt@i915_selftest@live@gt_pm:
    - shard-rkl:          [DMESG-FAIL][340] ([i915#12942]) -> [PASS][341] +1 other test pass
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@i915_selftest@live@gt_pm.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@i915_selftest@live@gt_pm.html

  * igt@i915_suspend@basic-s3-without-i915:
    - shard-rkl:          [INCOMPLETE][342] ([i915#4817]) -> [PASS][343]
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-tglu:         [FAIL][344] ([i915#14857]) -> [PASS][345] +1 other test pass
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-tglu-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_color@ctm-negative:
    - shard-rkl:          [SKIP][346] ([i915#12655] / [i915#14544]) -> [PASS][347]
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_color@ctm-negative.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_color@ctm-negative.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          [FAIL][348] ([i915#13566]) -> [PASS][349] +1 other test pass
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-4/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - shard-rkl:          [SKIP][350] ([i915#11190] / [i915#14544]) -> [PASS][351] +2 other tests pass
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-rkl:          [FAIL][352] ([i915#2346]) -> [PASS][353]
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_draw_crc@draw-method-blt:
    - shard-dg1:          [DMESG-WARN][354] ([i915#4423]) -> [PASS][355]
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-13/igt@kms_draw_crc@draw-method-blt.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-13/igt@kms_draw_crc@draw-method-blt.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1:
    - shard-snb:          [TIMEOUT][356] ([i915#14033]) -> [PASS][357] +1 other test pass
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-snb6/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-snb7/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-rkl:          [SKIP][358] ([i915#14544] / [i915#3637]) -> [PASS][359] +4 other tests pass
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-rkl:          [SKIP][360] ([i915#14544] / [i915#3555]) -> [PASS][361] +5 other tests pass
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * {igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-gtt}:
    - shard-rkl:          [SKIP][362] ([i915#14544]) -> [PASS][363] +48 other tests pass
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-gtt.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite:
    - shard-rkl:          [SKIP][364] ([i915#14544] / [i915#1849] / [i915#5354]) -> [PASS][365] +9 other tests pass
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-pwrite.html

  * igt@kms_invalid_mode@zero-clock:
    - shard-rkl:          [SKIP][366] ([i915#14544] / [i915#3555] / [i915#8826]) -> [PASS][367] +2 other tests pass
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_invalid_mode@zero-clock.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_invalid_mode@zero-clock.html

  * igt@kms_plane@plane-panning-top-left:
    - shard-rkl:          [SKIP][368] ([i915#14544] / [i915#8825]) -> [PASS][369] +2 other tests pass
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane@plane-panning-top-left.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_plane@plane-panning-top-left.html

  * igt@kms_plane_alpha_blend@constant-alpha-mid:
    - shard-rkl:          [SKIP][370] ([i915#14544] / [i915#7294]) -> [PASS][371]
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_alpha_blend@constant-alpha-mid.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_plane_alpha_blend@constant-alpha-mid.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format:
    - shard-rkl:          [SKIP][372] ([i915#14544] / [i915#8152]) -> [PASS][373]
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-pixel-format.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5:
    - shard-rkl:          [SKIP][374] ([i915#12247] / [i915#14544] / [i915#6953] / [i915#8152]) -> [PASS][375]
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a:
    - shard-rkl:          [SKIP][376] ([i915#12247] / [i915#14544]) -> [PASS][377] +2 other tests pass
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25:
    - shard-rkl:          [SKIP][378] ([i915#14544] / [i915#3555] / [i915#6953] / [i915#8152]) -> [PASS][379]
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_plane_scaling@planes-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b:
    - shard-rkl:          [SKIP][380] ([i915#12247] / [i915#14544] / [i915#8152]) -> [PASS][381] +2 other tests pass
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_plane_scaling@planes-upscale-factor-0-25@pipe-b.html

  * igt@kms_pm_rpm@fences:
    - shard-rkl:          [SKIP][382] ([i915#14544] / [i915#1849]) -> [PASS][383]
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_pm_rpm@fences.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_pm_rpm@fences.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          [SKIP][384] ([i915#14544] / [i915#15073]) -> [PASS][385]
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-dg2:          [SKIP][386] ([i915#15073]) -> [PASS][387]
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg2-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][388] ([i915#15073]) -> [PASS][389] +1 other test pass
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@perf@gen12-group-concurrent-oa-buffer-read:
    - shard-tglu:         [FAIL][390] ([i915#10538]) -> [PASS][391]
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-tglu-9/igt@perf@gen12-group-concurrent-oa-buffer-read.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-tglu-7/igt@perf@gen12-group-concurrent-oa-buffer-read.html

  * igt@perf_pmu@semaphore-wait:
    - shard-rkl:          [DMESG-WARN][392] ([i915#12964]) -> [PASS][393] +25 other tests pass
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@perf_pmu@semaphore-wait.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@perf_pmu@semaphore-wait.html

  
#### Warnings ####

  * igt@gem_basic@multigpu-create-close:
    - shard-rkl:          [SKIP][394] ([i915#7697]) -> [SKIP][395] ([i915#14544] / [i915#7697])
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@gem_basic@multigpu-create-close.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          [SKIP][396] ([i915#14544] / [i915#9323]) -> [SKIP][397] ([i915#9323])
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][398] ([i915#14544] / [i915#7697]) -> [SKIP][399] ([i915#7697])
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          [SKIP][400] ([i915#280]) -> [SKIP][401] ([i915#14544] / [i915#280])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@gem_ctx_sseu@engines.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_ctx_sseu@engines.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][402] ([i915#4525]) -> [SKIP][403] ([i915#14544] / [i915#4525]) +1 other test skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@gem_exec_balancer@parallel.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-rkl:          [SKIP][404] ([i915#6334]) -> [SKIP][405] ([i915#14544] / [i915#6334]) +1 other test skip
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@gem_exec_capture@capture-invisible@smem0.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_reloc@basic-cpu-read-active:
    - shard-rkl:          [SKIP][406] ([i915#14544] / [i915#3281]) -> [SKIP][407] ([i915#3281]) +4 other tests skip
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-read-active.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@gem_exec_reloc@basic-cpu-read-active.html

  * igt@gem_exec_reloc@basic-write-read:
    - shard-rkl:          [SKIP][408] ([i915#3281]) -> [SKIP][409] ([i915#14544] / [i915#3281]) +10 other tests skip
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@gem_exec_reloc@basic-write-read.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-rkl:          [SKIP][410] ([i915#14544] / [i915#4613]) -> [SKIP][411] ([i915#4613]) +2 other tests skip
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_lmem_swapping@massive-random.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-rkl:          [SKIP][412] ([i915#4613]) -> [SKIP][413] ([i915#14544] / [i915#4613]) +1 other test skip
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@gem_lmem_swapping@parallel-random.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_media_vme:
    - shard-rkl:          [SKIP][414] ([i915#14544] / [i915#284]) -> [SKIP][415] ([i915#284])
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_media_vme.html
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@gem_media_vme.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-rkl:          [SKIP][416] ([i915#14544] / [i915#3282]) -> [SKIP][417] ([i915#3282]) +6 other tests skip
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads.html
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_pxp@create-valid-protected-context:
    - shard-rkl:          [TIMEOUT][418] ([i915#12964]) -> [SKIP][419] ([i915#4270])
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_pxp@create-valid-protected-context.html
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_pxp@create-valid-protected-context.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-rkl:          [SKIP][420] ([i915#4270]) -> [SKIP][421] ([i915#14544] / [i915#4270])
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-rkl:          [SKIP][422] ([i915#14544] / [i915#4270]) -> [TIMEOUT][423] ([i915#12964])
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_pxp@fail-invalid-protected-context.html
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-rkl:          [TIMEOUT][424] ([i915#12917] / [i915#12964]) -> [SKIP][425] ([i915#13717])
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@gem_pxp@hw-rejects-pxp-context.html
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_readwrite@beyond-eob:
    - shard-rkl:          [SKIP][426] ([i915#3282]) -> [SKIP][427] ([i915#14544] / [i915#3282]) +4 other tests skip
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@gem_readwrite@beyond-eob.html
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_readwrite@beyond-eob.html

  * igt@gem_set_tiling_vs_blt@tiled-to-untiled:
    - shard-rkl:          [SKIP][428] ([i915#14544] / [i915#8411]) -> [SKIP][429] ([i915#8411])
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gem_set_tiling_vs_blt@tiled-to-untiled.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-rkl:          [SKIP][430] ([i915#3297] / [i915#3323]) -> [SKIP][431] ([i915#14544] / [i915#3297] / [i915#3323])
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@gem_userptr_blits@dmabuf-sync.html
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-rkl:          [SKIP][432] ([i915#14544] / [i915#3297]) -> [SKIP][433] ([i915#3297]) +1 other test skip
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gem_userptr_blits@dmabuf-unsync.html
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-rkl:          [SKIP][434] ([i915#3297]) -> [SKIP][435] ([i915#14544] / [i915#3297])
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@gem_userptr_blits@unsync-overlap.html
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          [SKIP][436] ([i915#14544] / [i915#2527]) -> [SKIP][437] ([i915#2527]) +2 other tests skip
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@gen9_exec_parse@bb-oversize.html
   [437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          [SKIP][438] ([i915#2527]) -> [SKIP][439] ([i915#14544] / [i915#2527]) +3 other tests skip
   [438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@gen9_exec_parse@bb-start-param.html
   [439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-rkl:          [SKIP][440] ([i915#8399]) -> [SKIP][441] ([i915#14544] / [i915#8399])
   [440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@i915_pm_freq_api@freq-basic-api.html
   [441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-rkl:          [SKIP][442] ([i915#14498] / [i915#14544]) -> [SKIP][443] ([i915#14498])
   [442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle.html
   [443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_power@sanity:
    - shard-rkl:          [SKIP][444] ([i915#14544] / [i915#7984]) -> [SKIP][445] ([i915#7984])
   [444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@i915_power@sanity.html
   [445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@i915_power@sanity.html

  * igt@intel_hwmon@hwmon-read:
    - shard-rkl:          [SKIP][446] ([i915#7707]) -> [SKIP][447] ([i915#14544] / [i915#7707])
   [446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@intel_hwmon@hwmon-read.html
   [447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@intel_hwmon@hwmon-read.html

  * igt@intel_hwmon@hwmon-write:
    - shard-rkl:          [SKIP][448] ([i915#14544] / [i915#7707]) -> [SKIP][449] ([i915#7707])
   [448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@intel_hwmon@hwmon-write.html
   [449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@intel_hwmon@hwmon-write.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [INCOMPLETE][450] ([i915#12761]) -> [SKIP][451] ([i915#14544])
   [450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_async_flips@async-flip-suspend-resume.html
   [451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-rkl:          [SKIP][452] ([i915#14544]) -> [SKIP][453] ([i915#5286]) +4 other tests skip
   [452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_big_fb@4-tiled-addfb.html
   [453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][454] ([i915#5286]) -> [SKIP][455] ([i915#14544]) +4 other tests skip
   [454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html
   [455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-rkl:          [SKIP][456] ([i915#3638]) -> [SKIP][457] ([i915#14544]) +3 other tests skip
   [456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html
   [457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-270:
    - shard-rkl:          [SKIP][458] ([i915#14544]) -> [SKIP][459] ([i915#3638]) +2 other tests skip
   [458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html
   [459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_big_fb@y-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
    - shard-rkl:          [SKIP][460] ([i915#14544]) -> [SKIP][461] +14 other tests skip
   [460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
   [461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg1:          [SKIP][462] ([i915#4538]) -> [SKIP][463] ([i915#4423] / [i915#4538])
   [462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
   [463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-18/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][464] ([i915#14544]) -> [SKIP][465] ([i915#14098] / [i915#6095]) +12 other tests skip
   [464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html
   [465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs:
    - shard-rkl:          [SKIP][466] ([i915#14098] / [i915#6095]) -> [SKIP][467] ([i915#14544]) +12 other tests skip
   [466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html
   [467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][468] ([i915#12313]) -> [SKIP][469] ([i915#14544]) +1 other test skip
   [468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
   [469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][470] ([i915#14544]) -> [SKIP][471] ([i915#12805])
   [470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][472] ([i915#14098] / [i915#6095]) -> [SKIP][473] ([i915#6095])
   [472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [473]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs:
    - shard-dg1:          [SKIP][474] ([i915#4423] / [i915#6095]) -> [SKIP][475] ([i915#6095]) +1 other test skip
   [474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-16/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html
   [475]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-16/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
    - shard-dg1:          [SKIP][476] ([i915#6095]) -> [SKIP][477] ([i915#4423] / [i915#6095])
   [476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-12/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
   [477]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-16/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html

  * igt@kms_cdclk@mode-transition:
    - shard-rkl:          [SKIP][478] ([i915#14544] / [i915#3742]) -> [SKIP][479] ([i915#3742])
   [478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_cdclk@mode-transition.html
   [479]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@plane-scaling:
    - shard-rkl:          [SKIP][480] ([i915#3742]) -> [SKIP][481] ([i915#14544] / [i915#3742])
   [480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_cdclk@plane-scaling.html
   [481]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_cdclk@plane-scaling.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-rkl:          [SKIP][482] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][483] ([i915#11151] / [i915#7828]) +6 other tests skip
   [482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
   [483]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_chamelium_hpd@vga-hpd-for-each-pipe:
    - shard-rkl:          [SKIP][484] ([i915#11151] / [i915#7828]) -> [SKIP][485] ([i915#11151] / [i915#14544] / [i915#7828]) +7 other tests skip
   [484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html
   [485]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_chamelium_hpd@vga-hpd-for-each-pipe.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          [SKIP][486] ([i915#14544]) -> [SKIP][487] ([i915#7118] / [i915#9424])
   [486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_content_protection@atomic.html
   [487]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          [SKIP][488] ([i915#14544]) -> [SKIP][489] ([i915#3116])
   [488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
   [489]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-1:
    - shard-rkl:          [SKIP][490] ([i915#14544]) -> [SKIP][491] ([i915#9424])
   [490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_content_protection@lic-type-1.html
   [491]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][492] ([i915#9424]) -> [SKIP][493] ([i915#14544])
   [492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_content_protection@mei-interface.html
   [493]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-rkl:          [SKIP][494] ([i915#14544]) -> [SKIP][495] ([i915#3555]) +4 other tests skip
   [494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-32x32.html
   [495]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          [SKIP][496] ([i915#14544]) -> [SKIP][497] ([i915#13049]) +1 other test skip
   [496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_cursor_crc@cursor-random-512x170.html
   [497]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-rapid-movement-512x170:
    - shard-rkl:          [SKIP][498] ([i915#13049]) -> [SKIP][499] ([i915#14544]) +2 other tests skip
   [498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
   [499]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-rkl:          [SKIP][500] ([i915#14544]) -> [FAIL][501] ([i915#13566])
   [500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-256x85.html
   [501]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-rkl:          [SKIP][502] -> [SKIP][503] ([i915#14544]) +13 other tests skip
   [502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [503]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-rkl:          [SKIP][504] ([i915#11190] / [i915#14544]) -> [SKIP][505] ([i915#4103])
   [504]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [505]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          [SKIP][506] ([i915#13691]) -> [SKIP][507] ([i915#14544])
   [506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_display_modes@extended-mode-basic.html
   [507]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dp_aux_dev:
    - shard-rkl:          [SKIP][508] ([i915#1257]) -> [SKIP][509] ([i915#1257] / [i915#14544])
   [508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_dp_aux_dev.html
   [509]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_dp_aux_dev.html

  * igt@kms_dp_link_training@non-uhbr-mst:
    - shard-rkl:          [SKIP][510] ([i915#14544]) -> [SKIP][511] ([i915#13749])
   [510]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_dp_link_training@non-uhbr-mst.html
   [511]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_dp_link_training@non-uhbr-mst.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-rkl:          [SKIP][512] ([i915#13748]) -> [SKIP][513] ([i915#14544])
   [512]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_dp_link_training@uhbr-mst.html
   [513]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          [SKIP][514] ([i915#13707]) -> [SKIP][515] ([i915#14544])
   [514]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_dp_linktrain_fallback@dsc-fallback.html
   [515]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          [SKIP][516] ([i915#1839]) -> [SKIP][517] ([i915#14544] / [i915#1839])
   [516]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_feature_discovery@display-4x.html
   [517]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          [SKIP][518] ([i915#14544] / [i915#9337]) -> [SKIP][519] ([i915#9337])
   [518]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_feature_discovery@dp-mst.html
   [519]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr2:
    - shard-rkl:          [SKIP][520] ([i915#14544] / [i915#658]) -> [SKIP][521] ([i915#658])
   [520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_feature_discovery@psr2.html
   [521]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          [INCOMPLETE][522] ([i915#12745] / [i915#4839]) -> [INCOMPLETE][523] ([i915#12314] / [i915#12745] / [i915#4839] / [i915#6113])
   [522]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-glk6/igt@kms_flip@2x-flip-vs-suspend.html
   [523]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk5/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          [INCOMPLETE][524] ([i915#4839]) -> [INCOMPLETE][525] ([i915#12314] / [i915#4839] / [i915#6113])
   [524]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-glk6/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html
   [525]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-glk5/igt@kms_flip@2x-flip-vs-suspend@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          [SKIP][526] ([i915#9934]) -> [SKIP][527] ([i915#14544] / [i915#9934]) +4 other tests skip
   [526]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_flip@2x-plain-flip.html
   [527]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-rkl:          [SKIP][528] ([i915#14544] / [i915#9934]) -> [SKIP][529] ([i915#9934]) +4 other tests skip
   [528]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_flip@2x-plain-flip-interruptible.html
   [529]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_flip@2x-plain-flip-interruptible.html
    - shard-dg1:          [SKIP][530] ([i915#9934]) -> [SKIP][531] ([i915#4423] / [i915#9934])
   [530]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-12/igt@kms_flip@2x-plain-flip-interruptible.html
   [531]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-16/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - shard-rkl:          [SKIP][532] ([i915#14544] / [i915#3637]) -> [DMESG-WARN][533] ([i915#12964]) +1 other test dmesg-warn
   [532]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_flip@basic-flip-vs-wf_vblank.html
   [533]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-rkl:          [SKIP][534] ([i915#2672] / [i915#3555]) -> [SKIP][535] ([i915#14544] / [i915#3555]) +3 other tests skip
   [534]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [535]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][536] ([i915#14544] / [i915#3555]) -> [SKIP][537] ([i915#2672] / [i915#3555]) +1 other test skip
   [536]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html
   [537]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt:
    - shard-rkl:          [SKIP][538] -> [SKIP][539] ([i915#14544] / [i915#1849] / [i915#5354])
   [538]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html
   [539]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
    - shard-rkl:          [SKIP][540] ([i915#1825]) -> [SKIP][541] ([i915#14544] / [i915#1849] / [i915#5354]) +35 other tests skip
   [540]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
   [541]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          [SKIP][542] ([i915#5439]) -> [SKIP][543] ([i915#14544] / [i915#1849] / [i915#5354])
   [542]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
   [543]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-rkl:          [SKIP][544] ([i915#15102] / [i915#3023]) -> [SKIP][545] ([i915#14544] / [i915#1849] / [i915#5354]) +15 other tests skip
   [544]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [545]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][546] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][547] ([i915#1825]) +32 other tests skip
   [546]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
   [547]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][548] ([i915#4423]) -> [SKIP][549]
   [548]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html
   [549]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-rkl:          [SKIP][550] ([i915#9766]) -> [SKIP][551] ([i915#14544] / [i915#1849] / [i915#5354])
   [550]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
   [551]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][552] ([i915#14544] / [i915#1849] / [i915#5354]) -> [SKIP][553] ([i915#15102] / [i915#3023]) +13 other tests skip
   [552]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html
   [553]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][554] -> [SKIP][555] ([i915#4423]) +2 other tests skip
   [554]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite.html
   [555]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          [SKIP][556] ([i915#15102] / [i915#3458]) -> [SKIP][557] ([i915#10433] / [i915#15102] / [i915#3458]) +2 other tests skip
   [556]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
   [557]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
    - shard-dg1:          [SKIP][558] ([i915#15102] / [i915#3458]) -> [SKIP][559] ([i915#15102] / [i915#3458] / [i915#4423]) +1 other test skip
   [558]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
   [559]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-slowdraw:
    - shard-dg2:          [SKIP][560] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][561] ([i915#15102] / [i915#3458]) +1 other test skip
   [560]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-slowdraw.html
   [561]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-dg2-7/igt@kms_frontbuffer_tracking@psr-slowdraw.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          [SKIP][562] ([i915#14544]) -> [SKIP][563] ([i915#3555] / [i915#8228])
   [562]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_hdr@bpc-switch-dpms.html
   [563]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          [SKIP][564] ([i915#12713]) -> [SKIP][565] ([i915#14544])
   [564]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_hdr@brightness-with-hdr.html
   [565]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@static-toggle:
    - shard-rkl:          [SKIP][566] ([i915#3555] / [i915#8228]) -> [SKIP][567] ([i915#14544])
   [566]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_hdr@static-toggle.html
   [567]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          [SKIP][568] ([i915#12339] / [i915#14544]) -> [SKIP][569] ([i915#12339])
   [568]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_joiner@basic-ultra-joiner.html
   [569]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-rkl:          [SKIP][570] ([i915#12388]) -> [SKIP][571] ([i915#12388] / [i915#14544]) +1 other test skip
   [570]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [571]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-rkl:          [SKIP][572] ([i915#12394]) -> [SKIP][573] ([i915#12394] / [i915#14544]) +1 other test skip
   [572]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html
   [573]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          [SKIP][574] ([i915#14544]) -> [SKIP][575] ([i915#6301])
   [574]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_panel_fitting@legacy.html
   [575]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_multiple@2x-tiling-none:
    - shard-rkl:          [SKIP][576] ([i915#14544]) -> [SKIP][577] ([i915#13958])
   [576]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-none.html
   [577]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_plane_multiple@2x-tiling-none.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation:
    - shard-rkl:          [SKIP][578] ([i915#12247]) -> [SKIP][579] ([i915#12247] / [i915#14544] / [i915#8152]) +1 other test skip
   [578]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation.html
   [579]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation.html

  * igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][580] ([i915#12247]) -> [SKIP][581] ([i915#12247] / [i915#14544])
   [580]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a.html
   [581]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-factor-0-25-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-rkl:          [SKIP][582] ([i915#14544] / [i915#5354]) -> [SKIP][583] ([i915#5354]) +1 other test skip
   [582]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_pm_backlight@fade-with-suspend.html
   [583]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-rkl:          [FAIL][584] ([i915#9295]) -> [SKIP][585] ([i915#3361])
   [584]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_pm_dc@dc6-dpms.html
   [585]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][586] ([i915#9340]) -> [SKIP][587] ([i915#14544] / [i915#9340])
   [586]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_pm_lpsp@kms-lpsp.html
   [587]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_rpm@cursor-dpms:
    - shard-rkl:          [DMESG-WARN][588] ([i915#12964]) -> [SKIP][589] ([i915#12916] / [i915#14544])
   [588]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_pm_rpm@cursor-dpms.html
   [589]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_pm_rpm@cursor-dpms.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-rkl:          [SKIP][590] ([i915#12916]) -> [SKIP][591] ([i915#15073])
   [590]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@kms_pm_rpm@dpms-lpsp.html
   [591]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [DMESG-WARN][592] ([i915#12964]) -> [SKIP][593] ([i915#15073])
   [592]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [593]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-8/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-rkl:          [SKIP][594] ([i915#14544] / [i915#6524]) -> [SKIP][595] ([i915#6524])
   [594]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html
   [595]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][596] ([i915#11520] / [i915#14544]) -> [SKIP][597] ([i915#11520]) +5 other tests skip
   [596]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
   [597]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][598] ([i915#11520]) -> [SKIP][599] ([i915#11520] / [i915#14544]) +7 other tests skip
   [598]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
   [599]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@fbc-psr-primary-page-flip:
    - shard-rkl:          [SKIP][600] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][601] ([i915#1072] / [i915#9732]) +17 other tests skip
   [600]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_psr@fbc-psr-primary-page-flip.html
   [601]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_psr@fbc-psr-primary-page-flip.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          [SKIP][602] ([i915#1072] / [i915#9732]) -> [SKIP][603] ([i915#1072] / [i915#14544] / [i915#9732]) +19 other tests skip
   [602]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_psr@fbc-psr2-sprite-render.html
   [603]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-rkl:          [SKIP][604] ([i915#9685]) -> [SKIP][605] ([i915#14544] / [i915#9685])
   [604]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
   [605]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-rkl:          [SKIP][606] ([i915#14544]) -> [SKIP][607] ([i915#5289])
   [606]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [607]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_rotation_crc@sprite-rotation-270:
    - shard-rkl:          [DMESG-WARN][608] ([i915#12964]) -> [SKIP][609] ([i915#14544]) +1 other test skip
   [608]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_rotation_crc@sprite-rotation-270.html
   [609]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_rotation_crc@sprite-rotation-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-rkl:          [SKIP][610] ([i915#3555]) -> [SKIP][611] ([i915#14544]) +2 other tests skip
   [610]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@kms_scaling_modes@scaling-mode-center.html
   [611]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_create:
    - shard-rkl:          [ABORT][612] -> [FAIL][613] ([i915#15119])
   [612]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_create.html
   [613]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_create.html

  * igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free:
    - shard-rkl:          [DMESG-FAIL][614] ([i915#13179]) -> [ABORT][615] ([i915#13179])
   [614]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html
   [615]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-7/igt@kms_selftest@drm_framebuffer@drm_test_framebuffer_free.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-rkl:          [SKIP][616] ([i915#3555]) -> [SKIP][617] ([i915#14544] / [i915#3555])
   [616]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@kms_setmode@invalid-clone-single-crtc.html
   [617]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vblank@wait-forked-busy-hang:
    - shard-rkl:          [SKIP][618] ([i915#14544]) -> [DMESG-WARN][619] ([i915#12964]) +3 other tests dmesg-warn
   [618]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_vblank@wait-forked-busy-hang.html
   [619]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_vblank@wait-forked-busy-hang.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-rkl:          [SKIP][620] ([i915#9906]) -> [SKIP][621] ([i915#14544])
   [620]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-4/igt@kms_vrr@seamless-rr-switch-virtual.html
   [621]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_writeback@writeback-fb-id-xrgb2101010:
    - shard-rkl:          [SKIP][622] ([i915#14544] / [i915#2437] / [i915#9412]) -> [SKIP][623] ([i915#2437] / [i915#9412])
   [622]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-6/igt@kms_writeback@writeback-fb-id-xrgb2101010.html
   [623]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-5/igt@kms_writeback@writeback-fb-id-xrgb2101010.html

  * igt@perf_pmu@most-busy-idle-check-all:
    - shard-rkl:          [FAIL][624] ([i915#4349]) -> [DMESG-WARN][625] ([i915#12964]) +1 other test dmesg-warn
   [624]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-2/igt@perf_pmu@most-busy-idle-check-all.html
   [625]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@perf_pmu@most-busy-idle-check-all.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          [SKIP][626] ([i915#3291] / [i915#3708]) -> [SKIP][627] ([i915#14544] / [i915#3291] / [i915#3708])
   [626]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@prime_vgem@basic-write.html
   [627]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@prime_vgem@basic-write.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          [SKIP][628] ([i915#9917]) -> [SKIP][629] ([i915#14544] / [i915#9917])
   [628]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17362/shard-rkl-5/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
   [629]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/shard-rkl-6/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
  [i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10826
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11190
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12339]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12339
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12353]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12353
  [i915#12388]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12388
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12916]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12916
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12942]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12942
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13688
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14033]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14033
  [i915#14073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14073
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14118
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14561
  [i915#14702]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14702
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14809
  [i915#14857]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14857
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15119]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15119
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7294]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7294
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8152
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
  [i915#8826]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8826
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9581]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9581
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_17362 -> Patchwork_155952v1

  CI-20190529: 20190529
  CI_DRM_17362: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8582: 8582
  Patchwork_155952v1: c6c2a6f0013cf24b117a1dd397c9e0530ff2f4cb @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_155952v1/index.html

[-- Attachment #2: Type: text/html, Size: 263585 bytes --]

Re: [PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
> that indicates whether the memory has enabled ECC that limits display
> bandwidth.  Add the field ecc_impacting_de to struct dram_info to
> contain that information and set it appropriately when probing for
> memory info.  We will use that field when updating bandwidth parameters
> for Xe3p_LPD.

Could the field name be more accurate than "ecc impacting de"? It sounds
quite handwavy to me.

BR,
Jani.

>
> Bspec: 69131
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h       | 1 +
>  drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
>  drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
>  3 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 354ef75ef6a5..5bf3b4ab2baa 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1233,6 +1233,7 @@
>  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
>  
>  #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
>  #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
>  #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
>  #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> index 8841cfe1cac8..bf9f8e38d6ba 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> @@ -685,6 +685,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
>  
>  static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
>  {
> +	struct intel_display *display = i915->display;
>  	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
>  
>  	switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
> @@ -723,6 +724,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
>  	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
>  	/* PSF GV points not supported in D14+ */
>  
> +	if (DISPLAY_VER(display) >= 35)
> +		dram_info->ecc_impacting_de = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
> index 03a973f1c941..ac77f1ab409f 100644
> --- a/drivers/gpu/drm/i915/soc/intel_dram.h
> +++ b/drivers/gpu/drm/i915/soc/intel_dram.h
> @@ -30,6 +30,7 @@ struct dram_info {
>  	u8 num_channels;
>  	u8 num_qgv_points;
>  	u8 num_psf_gv_points;
> +	bool ecc_impacting_de; /* Only valid from Xe3p_LPD onward. */
>  	bool symmetric_memory;
>  	bool has_16gb_dimms;
>  };

-- 
Jani Nikula, Intel

Re: [PATCH 12/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
>
> Currently there is no way in the driver to classify the underruns into
> different categories. Starting with Xe3p_LPD, we get two new registers
> and some bits in existing registers which can help us categorise the
> underruns and let us know possible reason behind the underrun.
>
> Bspec: 69111, 69561, 74411, 74412
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h  |  31 +++++++
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 100 ++++++++++++++++++++-
>  2 files changed, 130 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4fa2..9e2414b730db 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -882,6 +882,36 @@
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>  
> +#define _UNDERRUN_DBG1_A				0x70064
> +#define _UNDERRUN_DBG1_B				0x71064
> +#define UNDERRUN_DBG1(pipe)				_MMIO_PIPE(pipe, \
> +								   _UNDERRUN_DBG1_A, \
> +								   _UNDERRUN_DBG1_B)
> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK		REG_GENMASK(29, 24)
> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_PLANE_CURSOR	REG_BIT(24)
> +#define   UNDERRUN_DDB_EMPTY_MASK			REG_GENMASK(21, 16)
> +#define   UNDERRUN_DDB_EMPTY_PLANE_CURSOR		REG_BIT(16)
> +#define   UNDERRUN_DBUF_NOT_FILLED_MASK			REG_GENMASK(13, 8)
> +#define   UNDERRUN_DBUF_NOT_FILLED_PLANE_CURSOR		REG_BIT(8)
> +#define   UNDERRUN_BELOW_WM0_MASK			REG_GENMASK(5, 0)
> +#define   UNDERRUN_BELOW_WM0_PLANE_CURSOR		REG_BIT(0)
> +
> +#define _UNDERRUN_DBG2_A				0x70068
> +#define _UNDERRUN_DBG2_B				0x71068
> +#define UNDERRUN_DBG2(pipe)				_MMIO_PIPE(pipe, \
> +								   _UNDERRUN_DBG2_A, \
> +								   _UNDERRUN_DBG2_B)
> +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN		REG_BIT(31)
> +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK		REG_GENMASK(30, 20)
> +#define   UNDERRUN_LINE_COUNT_MASK			REG_GENMASK(19, 0)
> +
> +#define _FBC_DEBUG_STATUS_A				0x43220
> +#define _FBC_DEBUG_STATUS_B				0x43260
> +#define FBC_DEBUG_STATUS(pipe)				_MMIO_PIPE(pipe, \
> +								   _FBC_DEBUG_STATUS_A, \
> +								   _FBC_DEBUG_STATUS_B)
> +#define   FBC_UNDERRUN_DECOMPRESSION			REG_BIT(27)
> +
>  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>  #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
>  #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
> @@ -1416,6 +1446,7 @@
>  
>  #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
>  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> +#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
>  
>  #define FUSE_STRAP		_MMIO(0x42014)
>  #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index c2ce8461ac9e..753872ad28ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -352,6 +352,101 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
>  	return old;
>  }
>  
> +static void snprintf_underrun_planes(char *buf, size_t len,
> +				     u32 underrun_dbg, u32 underrun_cursor)
> +{
> +	snprintf(buf, len, "%s%s%s%s%s%s",
> +		 underrun_dbg & (underrun_cursor << 1) ? "[1]" : "",
> +		 underrun_dbg & (underrun_cursor << 2) ? "[2]" : "",
> +		 underrun_dbg & (underrun_cursor << 3) ? "[3]" : "",
> +		 underrun_dbg & (underrun_cursor << 4) ? "[4]" : "",
> +		 underrun_dbg & (underrun_cursor << 5) ? "[5]" : "",
> +		 underrun_dbg & underrun_cursor ? "[C]" : "");
> +}

I'm pretty sure this could be made cleaner by using seq_buf.

> +
> +static void xe3p_lpd_log_underrun(struct intel_display *display,
> +				  enum pipe pipe)
> +{
> +	u32 underrun_dbg1;
> +	u32 underrun_dbg2;
> +	u32 fbc_debug_status;
> +	u32 dcpr_status;
> +	char planes[32];
> +
> +	/*
> +	 * UNDERRUN_DBG1 reports the following things
> +	 * 1. If DBUF block is not valid
> +	 * 2. If DDB is empty
> +	 * 3. If streamer could not completely fill DBUF at the end of vblank
> +	 * 4. Each enabled plane/cursor below watermark 0
> +	 */
> +	underrun_dbg1 = intel_de_read(display, UNDERRUN_DBG1(pipe));
> +	intel_de_write(display, UNDERRUN_DBG1(pipe), underrun_dbg1);
> +
> +	if (underrun_dbg1 & UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_DBUF_BLOCK_NOT_VALID_PLANE_CURSOR);
> +		drm_err(display->drm,
> +			"Pipe %c FIFO underrun: DBUF block not valid for plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	if (underrun_dbg1 & UNDERRUN_DDB_EMPTY_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_DDB_EMPTY_PLANE_CURSOR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: DDB empty for plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	if (underrun_dbg1 & UNDERRUN_DBUF_NOT_FILLED_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_DBUF_NOT_FILLED_PLANE_CURSOR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: DBUF not filled for plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	if (underrun_dbg1 & UNDERRUN_BELOW_WM0_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_BELOW_WM0_PLANE_CURSOR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: Below watermark 0 on plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	/*
> +	 * UNDERRUN_DBG2 reports the frame count and line count when the underrun started.
> +	 */
> +	underrun_dbg2 = intel_de_read(display, UNDERRUN_DBG2(pipe));
> +	if (underrun_dbg2 & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
> +		intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: Frame count: %u, Line count: %u\n",
> +			pipe_name(pipe),
> +			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, underrun_dbg2),
> +			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, underrun_dbg2));
> +	}
> +
> +	/*
> +	 * FBC_DEBUG_STATUS's FBC_UNDERRUN_DECOMPRESSION indicates if FBC was
> +	 * decompressing when underrun got triggered.
> +	 */
> +	fbc_debug_status = intel_de_read(display, FBC_DEBUG_STATUS(pipe));
> +	if (fbc_debug_status & FBC_UNDERRUN_DECOMPRESSION) {
> +		intel_de_write(display, FBC_DEBUG_STATUS(pipe), FBC_UNDERRUN_DECOMPRESSION);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: FBC decompression\n",
> +			pipe_name(pipe));
> +	}
> +
> +	/*
> +	 * GEN12_DCPR_STATUS_1's XE3P_UNDERRUN_PKGC, indicates that underrun started
> +	 * while pkgc was blocking memory.
> +	 */
> +	dcpr_status = intel_de_read(display, GEN12_DCPR_STATUS_1);
> +	if (dcpr_status & XE3P_UNDERRUN_PKGC) {
> +		intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: Pkgc blocking memory\n",
> +			pipe_name(pipe));
> +	}
> +}
> +
>  /**
>   * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
>   * @display: display device instance
> @@ -378,7 +473,10 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
>  	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
>  		trace_intel_cpu_fifo_underrun(display, pipe);
>  
> -		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
> +		if (DISPLAY_VER(display) >= 35)
> +			xe3p_lpd_log_underrun(display, pipe);
> +		else
> +			drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
>  	}
>  
>  	intel_fbc_handle_fifo_underrun_irq(display);

-- 
Jani Nikula, Intel

Re: [PATCH 14/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>
> Some of the register fields of MBUS_CTL and DBUF_CTL register are
> changed for Xe3p_LPD platforms. Update the changed fields in the driver.
> Below are the changes:
>
> MBUS_CTL:
> 	Translation Throttle Min
> 		It changed from BIT[15:13] to BIT[16:13]
>
> DBUF_CTL:
> 	Min Tracker State Service
> 		It changed from BIT[18:16] to BIT[20:16]
>         Max Tracker State Service
> 		It changed to from BIT[23:19] to BIT[14:10]
> 		but using default value, so no need to define
> 		in code.
>
> Bspec: 68868, 68872
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c      | 16 ++++++++++++----
>  drivers/gpu/drm/i915/display/skl_watermark_regs.h | 12 ++++++++++--
>  2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 9df9ee137bf9..41f64e347436 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3505,7 +3505,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
>  	if (!HAS_MBUS_JOINING(display))
>  		return;
>  
> -	if (DISPLAY_VER(display) >= 20)
> +	if (DISPLAY_VER(display) >= 35)
> +		intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
> +			     XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
> +	else if (DISPLAY_VER(display) >= 20)
>  		intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
>  			     MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
>  
> @@ -3516,9 +3519,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
>  		    ratio, str_yes_no(joined_mbus));
>  
>  	for_each_dbuf_slice(display, slice)
> -		intel_de_rmw(display, DBUF_CTL_S(slice),
> -			     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> -			     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> +		if (DISPLAY_VER(display) >= 35)
> +			intel_de_rmw(display, DBUF_CTL_S(slice),
> +				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +				     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
> +		else
> +			intel_de_rmw(display, DBUF_CTL_S(slice),
> +				     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
> +				     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
>  }
>  
>  static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> index c5572fc0e847..7e0877303e05 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
> @@ -41,7 +41,11 @@
>  #define   MBUS_JOIN_PIPE_SELECT(pipe)		REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
>  #define   MBUS_JOIN_PIPE_SELECT_NONE		MBUS_JOIN_PIPE_SELECT(7)
>  #define   MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(15, 13)
> -#define   MBUS_TRANSLATION_THROTTLE_MIN(val)	REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
> +#define   MBUS_TRANSLATION_THROTTLE_MIN(val) \
> +		REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
> +#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK	REG_GENMASK(16, 13)
> +#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) \
> +		REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>  
>  /*
>   * The below are numbered starting from "S1" on gen11/gen12, but starting
> @@ -65,7 +69,11 @@
>  #define  DBUF_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(23, 19)
>  #define  DBUF_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
>  #define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(18, 16) /* ADL-P+ */
> -#define  DBUF_MIN_TRACKER_STATE_SERVICE(x)		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
> +#define  DBUF_MIN_TRACKER_STATE_SERVICE(x) \
> +		REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
> +#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK	REG_GENMASK(20, 16)
> +#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) \
> +		REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)

Please just keep the long lines in this file. In this case, I think it's
cleaner.


>  
>  #define MTL_LATENCY_LP0_LP1		_MMIO(0x45780)
>  #define MTL_LATENCY_LP2_LP3		_MMIO(0x45784)

-- 
Jani Nikula, Intel

Re: [PATCH 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> From: Jouni Högander <jouni.hogander@intel.com>
>
> Ensure the minimum selective update line count is 4 in case of display
> version 35 and onwards.
>
> Bspec: 69887
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++++++++++++++++++++
>  1 file changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 2131473cead6..c663ca91f490 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2701,6 +2701,29 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
>  		intel_psr_apply_pr_link_on_su_wa(crtc_state);
>  }
>  
> +static void intel_psr_su_area_min_lines(struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_display *display = to_intel_display(crtc_state);
> +	struct drm_rect damaged_area;
> +
> +	/*
> +	 * Bspec mentions 4 being minimum lines in SU for display version
> +	 * 35 and onwards.
> +	 */
> +	if (DISPLAY_VER(display) < 35 || drm_rect_height(&crtc_state->psr2_su_area) >= 4)
> +		return;
> +
> +	damaged_area.x1 = crtc_state->psr2_su_area.x1;
> +	damaged_area.y1 = crtc_state->psr2_su_area.y1;
> +	damaged_area.x2 = crtc_state->psr2_su_area.x2;
> +	damaged_area.y2 = crtc_state->psr2_su_area.y2;
> +
> +	damaged_area.y2 +=  4 - drm_rect_height(&damaged_area);
> +	drm_rect_intersect(&damaged_area, &crtc_state->pipe_src);
> +	damaged_area.y1 -=  4 - drm_rect_height(&damaged_area);

Stray extra spaces in there.

> +	clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
> +}
> +
>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  				struct intel_crtc *crtc)
>  {
> @@ -2809,6 +2832,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>  	if (full_update)
>  		goto skip_sel_fetch_set_loop;
>  
> +	intel_psr_su_area_min_lines(crtc_state);
> +
>  	intel_psr_apply_su_area_workarounds(crtc_state);
>  
>  	ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);

-- 
Jani Nikula, Intel

Re: [PATCH 12/32] drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints

[Ville Syrjälä]

On Wed, Oct 15, 2025 at 12:15:12AM -0300, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> 
> Currently there is no way in the driver to classify the underruns into
> different categories. Starting with Xe3p_LPD, we get two new registers
> and some bits in existing registers which can help us categorise the
> underruns and let us know possible reason behind the underrun.
> 
> Bspec: 69111, 69561, 74411, 74412
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h  |  31 +++++++
>  drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 100 ++++++++++++++++++++-
>  2 files changed, 130 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 9d71e26a4fa2..9e2414b730db 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -882,6 +882,36 @@
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK		REG_GENMASK(2, 0) /* tgl+ */
>  #define   PIPE_MISC2_FLIP_INFO_PLANE_SEL(plane_id)	REG_FIELD_PREP(PIPE_MISC2_FLIP_INFO_PLANE_SEL_MASK, (plane_id))
>  
> +#define _UNDERRUN_DBG1_A				0x70064
> +#define _UNDERRUN_DBG1_B				0x71064
> +#define UNDERRUN_DBG1(pipe)				_MMIO_PIPE(pipe, \
> +								   _UNDERRUN_DBG1_A, \
> +								   _UNDERRUN_DBG1_B)
> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK		REG_GENMASK(29, 24)
> +#define   UNDERRUN_DBUF_BLOCK_NOT_VALID_PLANE_CURSOR	REG_BIT(24)
> +#define   UNDERRUN_DDB_EMPTY_MASK			REG_GENMASK(21, 16)
> +#define   UNDERRUN_DDB_EMPTY_PLANE_CURSOR		REG_BIT(16)
> +#define   UNDERRUN_DBUF_NOT_FILLED_MASK			REG_GENMASK(13, 8)
> +#define   UNDERRUN_DBUF_NOT_FILLED_PLANE_CURSOR		REG_BIT(8)
> +#define   UNDERRUN_BELOW_WM0_MASK			REG_GENMASK(5, 0)
> +#define   UNDERRUN_BELOW_WM0_PLANE_CURSOR		REG_BIT(0)
> +
> +#define _UNDERRUN_DBG2_A				0x70068
> +#define _UNDERRUN_DBG2_B				0x71068
> +#define UNDERRUN_DBG2(pipe)				_MMIO_PIPE(pipe, \
> +								   _UNDERRUN_DBG2_A, \
> +								   _UNDERRUN_DBG2_B)
> +#define   UNDERRUN_FRAME_LINE_COUNTERS_FROZEN		REG_BIT(31)
> +#define   UNDERRUN_PIPE_FRAME_COUNT_MASK		REG_GENMASK(30, 20)
> +#define   UNDERRUN_LINE_COUNT_MASK			REG_GENMASK(19, 0)
> +
> +#define _FBC_DEBUG_STATUS_A				0x43220
> +#define _FBC_DEBUG_STATUS_B				0x43260
> +#define FBC_DEBUG_STATUS(pipe)				_MMIO_PIPE(pipe, \
> +								   _FBC_DEBUG_STATUS_A, \
> +								   _FBC_DEBUG_STATUS_B)
> +#define   FBC_UNDERRUN_DECOMPRESSION			REG_BIT(27)

FBC stuff doesn't belong here.

> +
>  #define DPINVGTT				_MMIO(VLV_DISPLAY_BASE + 0x7002c) /* VLV/CHV only */
>  #define   DPINVGTT_EN_MASK_CHV				REG_GENMASK(27, 16)
>  #define   DPINVGTT_EN_MASK_VLV				REG_GENMASK(23, 16)
> @@ -1416,6 +1446,7 @@
>  
>  #define GEN12_DCPR_STATUS_1				_MMIO(0x46440)
>  #define  XELPDP_PMDEMAND_INFLIGHT_STATUS		REG_BIT(26)
> +#define  XE3P_UNDERRUN_PKGC				REG_BIT(21)
>  
>  #define FUSE_STRAP		_MMIO(0x42014)
>  #define   ILK_INTERNAL_GRAPHICS_DISABLE	REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index c2ce8461ac9e..753872ad28ed 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -352,6 +352,101 @@ bool intel_set_pch_fifo_underrun_reporting(struct intel_display *display,
>  	return old;
>  }
>  
> +static void snprintf_underrun_planes(char *buf, size_t len,
> +				     u32 underrun_dbg, u32 underrun_cursor)
> +{
> +	snprintf(buf, len, "%s%s%s%s%s%s",
> +		 underrun_dbg & (underrun_cursor << 1) ? "[1]" : "",
> +		 underrun_dbg & (underrun_cursor << 2) ? "[2]" : "",
> +		 underrun_dbg & (underrun_cursor << 3) ? "[3]" : "",
> +		 underrun_dbg & (underrun_cursor << 4) ? "[4]" : "",
> +		 underrun_dbg & (underrun_cursor << 5) ? "[5]" : "",
> +		 underrun_dbg & underrun_cursor ? "[C]" : "");
> +}
> +
> +static void xe3p_lpd_log_underrun(struct intel_display *display,
> +				  enum pipe pipe)
> +{
> +	u32 underrun_dbg1;
> +	u32 underrun_dbg2;
> +	u32 fbc_debug_status;
> +	u32 dcpr_status;
> +	char planes[32];
> +
> +	/*
> +	 * UNDERRUN_DBG1 reports the following things
> +	 * 1. If DBUF block is not valid
> +	 * 2. If DDB is empty
> +	 * 3. If streamer could not completely fill DBUF at the end of vblank
> +	 * 4. Each enabled plane/cursor below watermark 0
> +	 */
> +	underrun_dbg1 = intel_de_read(display, UNDERRUN_DBG1(pipe));
> +	intel_de_write(display, UNDERRUN_DBG1(pipe), underrun_dbg1);
> +
> +	if (underrun_dbg1 & UNDERRUN_DBUF_BLOCK_NOT_VALID_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_DBUF_BLOCK_NOT_VALID_PLANE_CURSOR);
> +		drm_err(display->drm,
> +			"Pipe %c FIFO underrun: DBUF block not valid for plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	if (underrun_dbg1 & UNDERRUN_DDB_EMPTY_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_DDB_EMPTY_PLANE_CURSOR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: DDB empty for plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	if (underrun_dbg1 & UNDERRUN_DBUF_NOT_FILLED_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_DBUF_NOT_FILLED_PLANE_CURSOR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: DBUF not filled for plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	if (underrun_dbg1 & UNDERRUN_BELOW_WM0_MASK) {
> +		snprintf_underrun_planes(planes, sizeof(planes), underrun_dbg1,
> +					 UNDERRUN_BELOW_WM0_PLANE_CURSOR);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: Below watermark 0 on plane(s):  %s\n",
> +			pipe_name(pipe), planes);
> +	}
> +
> +	/*
> +	 * UNDERRUN_DBG2 reports the frame count and line count when the underrun started.
> +	 */
> +	underrun_dbg2 = intel_de_read(display, UNDERRUN_DBG2(pipe));
> +	if (underrun_dbg2 & UNDERRUN_FRAME_LINE_COUNTERS_FROZEN) {
> +		intel_de_write(display, UNDERRUN_DBG2(pipe), UNDERRUN_FRAME_LINE_COUNTERS_FROZEN);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: Frame count: %u, Line count: %u\n",
> +			pipe_name(pipe),
> +			REG_FIELD_GET(UNDERRUN_PIPE_FRAME_COUNT_MASK, underrun_dbg2),
> +			REG_FIELD_GET(UNDERRUN_LINE_COUNT_MASK, underrun_dbg2));
> +	}
> +
> +	/*
> +	 * FBC_DEBUG_STATUS's FBC_UNDERRUN_DECOMPRESSION indicates if FBC was
> +	 * decompressing when underrun got triggered.
> +	 */
> +	fbc_debug_status = intel_de_read(display, FBC_DEBUG_STATUS(pipe));
> +	if (fbc_debug_status & FBC_UNDERRUN_DECOMPRESSION) {
> +		intel_de_write(display, FBC_DEBUG_STATUS(pipe), FBC_UNDERRUN_DECOMPRESSION);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: FBC decompression\n",
> +			pipe_name(pipe));
> +	}
> +
> +	/*
> +	 * GEN12_DCPR_STATUS_1's XE3P_UNDERRUN_PKGC, indicates that underrun started
> +	 * while pkgc was blocking memory.
> +	 */
> +	dcpr_status = intel_de_read(display, GEN12_DCPR_STATUS_1);
> +	if (dcpr_status & XE3P_UNDERRUN_PKGC) {
> +		intel_de_write(display, GEN12_DCPR_STATUS_1, XE3P_UNDERRUN_PKGC);
> +		drm_err(display->drm, "Pipe %c FIFO underrun: Pkgc blocking memory\n",
> +			pipe_name(pipe));
> +	}
> +}
> +
>  /**
>   * intel_cpu_fifo_underrun_irq_handler - handle CPU fifo underrun interrupt
>   * @display: display device instance
> @@ -378,7 +473,10 @@ void intel_cpu_fifo_underrun_irq_handler(struct intel_display *display,
>  	if (intel_set_cpu_fifo_underrun_reporting(display, pipe, false)) {
>  		trace_intel_cpu_fifo_underrun(display, pipe);
>  
> -		drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
> +		if (DISPLAY_VER(display) >= 35)
> +			xe3p_lpd_log_underrun(display, pipe);
> +		else
> +			drm_err(display->drm, "CPU pipe %c FIFO underrun\n", pipe_name(pipe));
>  	}
>  
>  	intel_fbc_handle_fifo_underrun_irq(display);
> 
> -- 
> 2.51.0

-- 
Ville Syrjälä
Intel

Re: [PATCH 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>
> To enable FBC for FP16 formats, we need to enable the pixel normalizer
> block. Introduce the register definitions and the initial steps for
> configuring the pixel normalizer block. In this patch the pixel
> normalizer block is kept as disabled. The follow-up patches will handle
> configuring the pixel normalizer block for hdr planes for FP16 formats.
>
> Bspec: 69863
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h      |  3 +++
>  drivers/gpu/drm/i915/display/skl_universal_plane.c      | 15 +++++++++++++++
>  drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 11 +++++++++++
>  3 files changed, 29 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 87b7cec35320..13652e2996a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -679,6 +679,9 @@ struct intel_plane_state {
>  	/* surface address register */
>  	u32 surf;
>  
> +	/* plane pixel normalizer config for Xe3p_LPD+ FBC FP16 */
> +	u32 pixel_normalizer;

I'm pretty strongly of the opinion that software state should not be
just a 1:1 map of the hardware state. Software state is logical,
hardware state is physical.

The software state should have logical things like "normalize form
factor" and "normalize enable", and the hardware then has those in some
register(s) somewhere.

Please let's not start storing software state as register contents. The
registers and their contents *will* change across platforms.

> +
>  	/*
>  	 * scaler_id
>  	 *    = -1 : not using a scaler
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 9f1111324dab..16a9c141281b 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -893,6 +893,12 @@ static void skl_write_plane_wm(struct intel_dsb *dsb,
>  				   xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb));
>  }
>  
> +static void
> +xe3p_lpd_plane_check_pixel_normalizer(struct intel_plane_state *plane_state)

The function name has nothing to do with what the function does. What
does "check" mean?

> +{
> +	plane_state->pixel_normalizer = 0;
> +}
> +
>  static void
>  skl_plane_disable_arm(struct intel_dsb *dsb,
>  		      struct intel_plane *plane,
> @@ -1671,6 +1677,11 @@ icl_plane_update_arm(struct intel_dsb *dsb,
>  
>  	icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state);
>  
> +	/* Only the HDR planes can have pixel normalizer */
> +	if (DISPLAY_VER(display) >= 35 && icl_is_hdr_plane(display, plane_id))
> +		intel_de_write_dsb(display, dsb,
> +				   PLANE_PIXEL_NORMALIZE(plane->pipe, plane->id),
> +				   plane_state->pixel_normalizer);

This is the place where you'd look at the software state, and construct
what will be written to hardware based on that.

>  	/*
>  	 * The control register self-arms if the plane was previously
>  	 * disabled. Try to make the plane enable atomic by writing
> @@ -2385,6 +2396,10 @@ static int skl_plane_check(struct intel_crtc_state *crtc_state,
>  		plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
>  	}
>  
> +	/* Pixel normalizer for Xe3p_LPD+ */
> +	if (DISPLAY_VER(display) >= 35 && icl_is_hdr_plane(display, plane->id))
> +		xe3p_lpd_plane_check_pixel_normalizer(plane_state);
> +
>  	plane_state->ctl = skl_plane_ctl(plane_state);
>  
>  	if (DISPLAY_VER(display) >= 10)
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 84cf565bd653..11c713f9b237 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -456,4 +456,15 @@
>  								_SEL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \
>  								_SEL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B)
>  
> +#define _PLANE_PIXEL_NORMALIZE_1_A		0x701a8
> +#define _PLANE_PIXEL_NORMALIZE_2_A		0x702a8
> +#define _PLANE_PIXEL_NORMALIZE_1_B		0x711a8
> +#define _PLANE_PIXEL_NORMALIZE_2_B		0x712a8
> +#define PLANE_PIXEL_NORMALIZE(pipe, plane)	_MMIO_SKL_PLANE((pipe), (plane), \
> +								_PLANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B, \
> +								_PLANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
> +#define   PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
> +#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
> +#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val))
> +
>  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH 25/32] drm/i915/xe3p_lpd: Add FBC support for FP16 formats

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>
> Add supported FP16 formats for FBC. FBC can be enabled with FP16 formats
> only when plane pixel normalizer block is enabled.
>
> Bspec: 6881, 69863, 68904
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_fbc.c | 37 ++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_fbc.h |  1 +
>  2 files changed, 38 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 75c78bef54f2..715a9acabe89 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -64,6 +64,7 @@
>  #include "intel_fbc.h"
>  #include "intel_fbc_regs.h"
>  #include "intel_frontbuffer.h"
> +#include "skl_universal_plane_regs.h"
>  
>  #define for_each_fbc_id(__display, __fbc_id) \
>  	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
> @@ -154,6 +155,8 @@ static unsigned int intel_fbc_cfb_cpp(const struct intel_plane_state *plane_stat
>  	case DRM_FORMAT_XBGR16161616:
>  	case DRM_FORMAT_ARGB16161616:
>  	case DRM_FORMAT_ABGR16161616:
> +	case DRM_FORMAT_ARGB16161616F:
> +	case DRM_FORMAT_ABGR16161616F:
>  		return 8;
>  	default:
>  		return 4;
> @@ -696,6 +699,30 @@ static void skl_fbc_program_cfb_stride(struct intel_fbc *fbc)
>  		     CHICKEN_FBC_STRIDE_MASK, val);
>  }
>  
> +static bool
> +xe3p_lpd_fbc_is_fp16_format(const struct intel_plane_state *plane_state)
> +{
> +	const struct drm_framebuffer *fb = plane_state->hw.fb;
> +
> +	switch (fb->format->format) {
> +	case DRM_FORMAT_ARGB16161616F:
> +	case DRM_FORMAT_ABGR16161616F:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +bool
> +intel_fbc_is_fp16_format_supported(const struct intel_plane_state *plane_state)
> +{
> +	struct intel_display *display = to_intel_display(plane_state);
> +
> +	if (DISPLAY_VER(display) >= 35)
> +		return xe3p_lpd_fbc_is_fp16_format(plane_state);
> +
> +	return false;
> +}
>  static u32 ivb_dpfc_ctl(struct intel_fbc *fbc)
>  {
>  	struct intel_display *display = fbc->display;
> @@ -811,6 +838,8 @@ static void intel_fbc_nuke(struct intel_fbc *fbc)
>  static void intel_fbc_activate(struct intel_fbc *fbc)
>  {
>  	struct intel_display *display = fbc->display;
> +	struct intel_plane *plane = fbc->state.plane;
> +	struct intel_plane_state *plane_state = to_intel_plane_state(plane->base.state);
>  
>  	lockdep_assert_held(&fbc->lock);
>  
> @@ -823,6 +852,11 @@ static void intel_fbc_activate(struct intel_fbc *fbc)
>  	 */
>  	drm_WARN_ON(display->drm, fbc->active && HAS_FBC_DIRTY_RECT(display));
>  
> +	drm_WARN_ON(display->drm,
> +		    DISPLAY_VER(display) >= 35 &&
> +		    xe3p_lpd_fbc_is_fp16_format(plane_state) &&
> +		    (plane_state->pixel_normalizer & PLANE_PIXEL_NORMALIZE_ENABLE) == 0);

With the software state being logical, this part here wouldn't have to
do *register* level decoding on the software state. Now the physical and
logical states are conflated.

> +
>  	intel_fbc_hw_activate(fbc);
>  	intel_fbc_nuke(fbc);
>  
> @@ -1140,6 +1174,9 @@ static bool xe3p_lpd_fbc_pixel_format_is_valid(const struct intel_plane_state *p
>  {
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  
> +	if (xe3p_lpd_fbc_is_fp16_format(plane_state))
> +		return true;
> +
>  	switch (fb->format->format) {
>  	case DRM_FORMAT_XRGB8888:
>  	case DRM_FORMAT_XBGR8888:
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
> index 0e715cb6b4e6..e14dc359ecf5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.h
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.h
> @@ -52,5 +52,6 @@ void intel_fbc_prepare_dirty_rect(struct intel_atomic_state *state,
>  				  struct intel_crtc *crtc);
>  void intel_fbc_dirty_rect_update_noarm(struct intel_dsb *dsb,
>  				       struct intel_plane *plane);
> +bool intel_fbc_is_fp16_format_supported(const struct intel_plane_state *plane_state);
>  
>  #endif /* __INTEL_FBC_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH 26/32] drm/i915/xe3p_lpd: Enable pixel normalizer for fp16 formats for FBC

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> From: Vinod Govindapillai <vinod.govindapillai@intel.com>
>
> There is a hw restriction that we could enable the FBC for FP16
> formats only if the pixel normalization block is enabled. Hence
> enable the pixel normalizer block with normalzation factor as
> 1.0 for the supported FP16 formats to get the FBC enabled. Two
> existing helper function definitions are moved up to avoid the
> forward declarations as part of this patch as well.
>
> Bspec: 69863, 68881
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 50 ++++++++++++++--------
>  .../drm/i915/display/skl_universal_plane_regs.h    |  1 +
>  2 files changed, 33 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 16a9c141281b..ae1bf6beac95 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -486,6 +486,23 @@ static int skl_plane_max_height(const struct drm_framebuffer *fb,
>  	return 4096;
>  }
>  
> +static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
> +{
> +	return pipe - PIPE_A + INTEL_FBC_A;
> +}
> +
> +static bool skl_plane_has_fbc(struct intel_display *display,
> +			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
> +{
> +	if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)
> +		return false;
> +
> +	if (DISPLAY_VER(display) >= 20)
> +		return icl_is_hdr_plane(display, plane_id);
> +	else
> +		return plane_id == PLANE_1;
> +}
> +
>  static int icl_plane_max_height(const struct drm_framebuffer *fb,
>  				int color_plane,
>  				unsigned int rotation)
> @@ -896,7 +913,21 @@ static void skl_write_plane_wm(struct intel_dsb *dsb,
>  static void
>  xe3p_lpd_plane_check_pixel_normalizer(struct intel_plane_state *plane_state)
>  {
> -	plane_state->pixel_normalizer = 0;
> +	struct intel_display *display = to_intel_display(plane_state);
> +	struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
> +	enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(plane->pipe);
> +	u32 reg = 0;
> +
> +	/*
> +	 * To enable FBC for FP16 formats, enable pixel normalizer with
> +	 * normalization factor as 1.0
> +	 */
> +	if (skl_plane_has_fbc(display, fbc_id, plane->id) &&
> +	    intel_fbc_is_fp16_format_supported(plane_state))
> +		reg = PLANE_PIXEL_NORMALIZE_NORM_FACTOR(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0) |
> +		      PLANE_PIXEL_NORMALIZE_ENABLE;

Again, this functions should be about software state, and shouldn't have
to concern itself with the register macros.

The function name still doesn't make sense.

> +
> +	plane_state->pixel_normalizer = reg;
>  }
>  
>  static void
> @@ -2449,23 +2480,6 @@ void icl_link_nv12_planes(struct intel_plane_state *uv_plane_state,
>  	}
>  }
>  
> -static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
> -{
> -	return pipe - PIPE_A + INTEL_FBC_A;
> -}
> -
> -static bool skl_plane_has_fbc(struct intel_display *display,
> -			      enum intel_fbc_id fbc_id, enum plane_id plane_id)
> -{
> -	if ((DISPLAY_RUNTIME_INFO(display)->fbc_mask & BIT(fbc_id)) == 0)
> -		return false;
> -
> -	if (DISPLAY_VER(display) >= 20)
> -		return icl_is_hdr_plane(display, plane_id);
> -	else
> -		return plane_id == PLANE_1;
> -}
> -
>  static struct intel_fbc *skl_plane_fbc(struct intel_display *display,
>  				       enum pipe pipe, enum plane_id plane_id)
>  {
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 11c713f9b237..eb25de5d1778 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -466,5 +466,6 @@
>  #define   PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
>  #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
>  #define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK, (val))
> +#define   PLANE_PIXEL_NORMALIZE_NORM_FACTOR_1_0		0x3c00
>  
>  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */

-- 
Jani Nikula, Intel

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
> configuring SoC for TC ports and PHYs.  Update the code to match the
> updates in VBT.
>
> The new field dedicated_external is used to represent TC ports that are
> connected to PHYs outside of the Type-C subsystem, meaning that they
> behave like dedicated ports and don't require the extra Type-C
> programming.  In an upcoming change, we will update the driver to take
> this field into consideration when detecting the type of port.
>
> The new field dyn_port_over_tc is used to inform that the TC port can be
> dynamically allocated for a legacy connector in the Type-C subsystem,
> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
> that field in order to handle the IOM resource management programming
> required for that.
>
> Note that, when dedicated_external is set, the fields dp_usb_type_c and
> tbt are tagged as "don't care" in the spec, so they should be ignored in
> that case, so also make sure to update the accessor functions to take
> that into consideration.
>
> Bspec: 20124, 68954, 74304
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
>  3 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 3596dce84c28..e466728ced0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
>  {
>  	BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>  
> -	if (version > 263)
> +	if (version > 264)
>  		return -ENOENT;
>  	else if (version >= 263)
>  		return 44;
> @@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
>  
>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
>  {
> +	if (intel_bios_encoder_is_dedicated_external(devdata))
> +		return false;
> +

We already have mechanisms for this. Please don't pollute the functions.

dp_usb_type_c should just be set to 0 in a new sanitize_something()
function at the end of parse_ddi_port()

>  	return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
>  }
>  
>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
>  {
> +	if (intel_bios_encoder_is_dedicated_external(devdata))
> +		return false;
> +

Ditto.

tbt should just be set to 0 in a new sanitize_something() function at
the end of parse_ddi_port()

>  	return devdata->display->vbt.version >= 209 && devdata->child.tbt;
>  }
>  
> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
> +{
> +	return devdata->display->vbt.version >= 264 &&
> +		devdata->child.dedicated_external;
> +}
> +
> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
> +{
> +	return devdata->display->vbt.version >= 264 &&
> +		devdata->child.dyn_port_over_tc;
> +}
> +
>  bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
>  {
>  	return devdata && devdata->child.lane_reversal;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> index f9e438b2787b..75dff27b4228 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
>  bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 70e31520c560..f07ab64a8d97 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -554,7 +554,12 @@ struct child_device_config {
>  	u8 dvo_function;
>  	u8 dp_usb_type_c:1;					/* 195+ */
>  	u8 tbt:1;						/* 209+ */
> -	u8 flags2_reserved:2;					/* 195+ */
> +	/*
> +	 * Fields dp_usb_type_c and tbt must be ignored when
> +	 * dedicated_external is set.
> +	 */

We can add that info in the sanitize function. We don't generally add a
whole lot of explanatory text here, because if we did, the file would be
10x consisting mostly of VBT quirk explanations.

> +	u8 dedicated_external:1;				/* 264+ */
> +	u8 dyn_port_over_tc:1;					/* 264+ */
>  	u8 dp_port_trace_length:4;				/* 209+ */
>  	u8 dp_gpio_index;					/* 195+ */
>  	u16 dp_gpio_pin_num;					/* 195+ */

-- 
Jani Nikula, Intel

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
> configuring SoC for TC ports and PHYs.  Update the code to match the
> updates in VBT.
>
> The new field dedicated_external is used to represent TC ports that are
> connected to PHYs outside of the Type-C subsystem, meaning that they
> behave like dedicated ports and don't require the extra Type-C
> programming.  In an upcoming change, we will update the driver to take
> this field into consideration when detecting the type of port.
>
> The new field dyn_port_over_tc is used to inform that the TC port can be
> dynamically allocated for a legacy connector in the Type-C subsystem,
> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
> that field in order to handle the IOM resource management programming
> required for that.

We probably want to add the info to print_ddi_port().

>
> Note that, when dedicated_external is set, the fields dp_usb_type_c and
> tbt are tagged as "don't care" in the spec, so they should be ignored in
> that case, so also make sure to update the accessor functions to take
> that into consideration.
>
> Bspec: 20124, 68954, 74304
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
>  3 files changed, 27 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 3596dce84c28..e466728ced0f 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
>  {
>  	BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>  
> -	if (version > 263)
> +	if (version > 264)
>  		return -ENOENT;
>  	else if (version >= 263)
>  		return 44;
> @@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
>  
>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
>  {
> +	if (intel_bios_encoder_is_dedicated_external(devdata))
> +		return false;
> +
>  	return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
>  }
>  
>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
>  {
> +	if (intel_bios_encoder_is_dedicated_external(devdata))
> +		return false;
> +
>  	return devdata->display->vbt.version >= 209 && devdata->child.tbt;
>  }
>  
> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
> +{
> +	return devdata->display->vbt.version >= 264 &&
> +		devdata->child.dedicated_external;
> +}
> +
> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
> +{
> +	return devdata->display->vbt.version >= 264 &&
> +		devdata->child.dyn_port_over_tc;
> +}
> +
>  bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
>  {
>  	return devdata && devdata->child.lane_reversal;
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
> index f9e438b2787b..75dff27b4228 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
>  bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
>  bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 70e31520c560..f07ab64a8d97 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -554,7 +554,12 @@ struct child_device_config {
>  	u8 dvo_function;
>  	u8 dp_usb_type_c:1;					/* 195+ */
>  	u8 tbt:1;						/* 209+ */
> -	u8 flags2_reserved:2;					/* 195+ */
> +	/*
> +	 * Fields dp_usb_type_c and tbt must be ignored when
> +	 * dedicated_external is set.
> +	 */
> +	u8 dedicated_external:1;				/* 264+ */
> +	u8 dyn_port_over_tc:1;					/* 264+ */
>  	u8 dp_port_trace_length:4;				/* 209+ */
>  	u8 dp_gpio_index;					/* 195+ */
>  	u16 dp_gpio_pin_num;					/* 195+ */

-- 
Jani Nikula, Intel

Re: [PATCH 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Starting with Xe3p_LPD, the VBT has a new field, called in the driver
> "dedicated_external", which tells that a Type-C capable port is
> physically connected to a PHY outside of the Type-C subsystem.  When
> that's the case, the driver must not do the extra Type-C programming for
> that port.  Update intel_encoder_is_tc() to check for that case.
>
> While at it, add a note to intel_phy_is_tc() to remind us that it is
> about whether the respective port is a Type-C capable port rather than
> the PHY itself.
>
> (Maybe it would be a nice idea to rename intel_phy_is_tc()?)
>
> Note that this was handled with a new bool member added to struct
> intel_digital_port instead of having querying the VBT directly because
> VBT memory is freed (intel_bios_driver_remove) before encoder cleanup
> (intel_ddi_encoder_destroy), which would cause an oops to happen when
> the latter calls intel_encoder_is_tc().  This could be fixed by keeping
> VBT data around longer, but that's left for a follow-up work, if deemed
> necessary.
>
> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c           |  7 +++++++
>  drivers/gpu/drm/i915/display/intel_display.c       | 19 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>  3 files changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c09aa759f4d4..6fcbebb81263 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5343,6 +5343,13 @@ void intel_ddi_init(struct intel_display *display,
>  			goto err;
>  	}
>  
> +	if (intel_bios_encoder_is_dedicated_external(devdata)) {
> +		dig_port->dedicated_external = true;
> +		drm_dbg_kms(display->drm,
> +			    "Port %c is dedicated external\n",
> +			    port_name(port));
> +	}

With the information print added in parse_ddi_port(), the printing here
becomes redundant.

> +
>  	if (intel_encoder_is_tc(encoder)) {
>  		bool is_legacy =
>  			!intel_bios_encoder_supports_typec_usb(devdata) &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 6ac718192e1c..46474199d1ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1778,7 +1778,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
>  		return false;
>  }
>  
> -/* Prefer intel_encoder_is_tc() */
> +/*
> + * This function returns true if the DDI port respective to the PHY enumeration
> + * is a Type-C capable port.
> + *
> + * Depending on the VBT, the port might be configured
> + * as a "dedicated external" port, meaning that actual physical PHY is outside
> + * of the Type-C subsystem and, as such, not really a "Type-C PHY".
> + *
> + * Prefer intel_encoder_is_tc(), especially if you really need to know if we
> + * are dealing with Type-C connections.
> + */
>  bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
>  {
>  	/*
> @@ -1863,6 +1873,13 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder)
>  {
>  	struct intel_display *display = to_intel_display(encoder);
>  
> +	if (intel_encoder_is_dig_port(encoder)) {
> +		struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> +
> +		if (dig_port->dedicated_external)

Why go through all the trouble of duplicating the "decicated external"
information in the digital port, when you already have encoder
available, and can just use intel_bios_encoder_is_dedicated_external()
right here?

> +			return false;
> +	}
> +
>  	return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 13652e2996a4..b5b9351501b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1909,6 +1909,7 @@ struct intel_digital_port {
>  	bool lane_reversal;
>  	bool ddi_a_4_lanes;
>  	bool release_cl2_override;
> +	bool dedicated_external;
>  	u8 max_lanes;
>  	/* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
>  	enum aux_ch aux_ch;

-- 
Jani Nikula, Intel

Re: [PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de

[Matt Atwood]

On Wed, Oct 15, 2025 at 05:46:52PM +0300, Jani Nikula wrote:
> On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> > Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
> > that indicates whether the memory has enabled ECC that limits display
> > bandwidth.  Add the field ecc_impacting_de to struct dram_info to
> > contain that information and set it appropriately when probing for
> > memory info.  We will use that field when updating bandwidth parameters
> > for Xe3p_LPD.
> 
> Could the field name be more accurate than "ecc impacting de"? It sounds
> quite handwavy to me.
I quite like it because it matches the field in the register on bspec.
MattA
> 
> BR,
> Jani.
> 
> >
> > Bspec: 69131
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h       | 1 +
> >  drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
> >  drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
> >  3 files changed, 6 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 354ef75ef6a5..5bf3b4ab2baa 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -1233,6 +1233,7 @@
> >  #define   OROM_OFFSET_MASK			REG_GENMASK(20, 16)
> >  
> >  #define MTL_MEM_SS_INFO_GLOBAL			_MMIO(0x45700)
> > +#define   XE3P_ECC_IMPACTING_DE			REG_BIT(12)
> >  #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK	REG_GENMASK(11, 8)
> >  #define   MTL_N_OF_POPULATED_CH_MASK		REG_GENMASK(7, 4)
> >  #define   MTL_DDR_TYPE_MASK			REG_GENMASK(3, 0)
> > diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> > index 8841cfe1cac8..bf9f8e38d6ba 100644
> > --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> > +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> > @@ -685,6 +685,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
> >  
> >  static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
> >  {
> > +	struct intel_display *display = i915->display;
> >  	u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
> >  
> >  	switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
> > @@ -723,6 +724,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
> >  	dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
> >  	/* PSF GV points not supported in D14+ */
> >  
> > +	if (DISPLAY_VER(display) >= 35)
> > +		dram_info->ecc_impacting_de = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
> > index 03a973f1c941..ac77f1ab409f 100644
> > --- a/drivers/gpu/drm/i915/soc/intel_dram.h
> > +++ b/drivers/gpu/drm/i915/soc/intel_dram.h
> > @@ -30,6 +30,7 @@ struct dram_info {
> >  	u8 num_channels;
> >  	u8 num_qgv_points;
> >  	u8 num_psf_gv_points;
> > +	bool ecc_impacting_de; /* Only valid from Xe3p_LPD onward. */
> >  	bool symmetric_memory;
> >  	bool has_16gb_dimms;
> >  };
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH 03/32] drm/i915/xe3p_lpd: Drop north display reset option programming

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:03AM -0300, Gustavo Sousa wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> The NDE_RSTWRN_OPT has been removed on Xe3p platforms and reset option
> programming is no longer necessary during display init.
> 
> Bspec: 68846, 69137

Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index da4babfd6bcb..821f5097e9c0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -1436,6 +1436,9 @@ static void intel_pch_reset_handshake(struct intel_display *display,
>  	i915_reg_t reg;
>  	u32 reset_bits;
>  
> +	if (DISPLAY_VER(display) >= 35)
> +		return;
> +
>  	if (display->platform.ivybridge) {
>  		reg = GEN7_MSG_CTL;
>  		reset_bits = WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK;
> 
> -- 
> 2.51.0
> 

Re: [PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-15 11:46:52-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
>> that indicates whether the memory has enabled ECC that limits display
>> bandwidth.  Add the field ecc_impacting_de to struct dram_info to
>> contain that information and set it appropriately when probing for
>> memory info.  We will use that field when updating bandwidth parameters
>> for Xe3p_LPD.
>
>Could the field name be more accurate than "ecc impacting de"? It sounds
>quite handwavy to me.

Well, perhaps the innacurate part would be the generic "de" instead of
something that refers to the bandwidth?

If so, would you be fine with ecc_impacting_bandwidth?

--
Gustavo Sousa

>
>BR,
>Jani.
>
>>
>> Bspec: 69131
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_reg.h       | 1 +
>>  drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
>>  drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
>>  3 files changed, 6 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 354ef75ef6a5..5bf3b4ab2baa 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -1233,6 +1233,7 @@
>>  #define   OROM_OFFSET_MASK                        REG_GENMASK(20, 16)
>>  
>>  #define MTL_MEM_SS_INFO_GLOBAL                        _MMIO(0x45700)
>> +#define   XE3P_ECC_IMPACTING_DE                        REG_BIT(12)
>>  #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK        REG_GENMASK(11, 8)
>>  #define   MTL_N_OF_POPULATED_CH_MASK                REG_GENMASK(7, 4)
>>  #define   MTL_DDR_TYPE_MASK                        REG_GENMASK(3, 0)
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
>> index 8841cfe1cac8..bf9f8e38d6ba 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
>> @@ -685,6 +685,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
>>  
>>  static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
>>  {
>> +        struct intel_display *display = i915->display;
>>          u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
>>  
>>          switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
>> @@ -723,6 +724,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
>>          dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
>>          /* PSF GV points not supported in D14+ */
>>  
>> +        if (DISPLAY_VER(display) >= 35)
>> +                dram_info->ecc_impacting_de = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
>> +
>>          return 0;
>>  }
>>  
>> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
>> index 03a973f1c941..ac77f1ab409f 100644
>> --- a/drivers/gpu/drm/i915/soc/intel_dram.h
>> +++ b/drivers/gpu/drm/i915/soc/intel_dram.h
>> @@ -30,6 +30,7 @@ struct dram_info {
>>          u8 num_channels;
>>          u8 num_qgv_points;
>>          u8 num_psf_gv_points;
>> +        bool ecc_impacting_de; /* Only valid from Xe3p_LPD onward. */
>>          bool symmetric_memory;
>>          bool has_16gb_dimms;
>>  };
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-15 12:00:51-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> From: Jouni Högander <jouni.hogander@intel.com>
>>
>> Ensure the minimum selective update line count is 4 in case of display
>> version 35 and onwards.
>>
>> Bspec: 69887
>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_psr.c | 25 +++++++++++++++++++++++++
>>  1 file changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 2131473cead6..c663ca91f490 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -2701,6 +2701,29 @@ intel_psr_apply_su_area_workarounds(struct intel_crtc_state *crtc_state)
>>                  intel_psr_apply_pr_link_on_su_wa(crtc_state);
>>  }
>>  
>> +static void intel_psr_su_area_min_lines(struct intel_crtc_state *crtc_state)
>> +{
>> +        struct intel_display *display = to_intel_display(crtc_state);
>> +        struct drm_rect damaged_area;
>> +
>> +        /*
>> +         * Bspec mentions 4 being minimum lines in SU for display version
>> +         * 35 and onwards.
>> +         */
>> +        if (DISPLAY_VER(display) < 35 || drm_rect_height(&crtc_state->psr2_su_area) >= 4)
>> +                return;
>> +
>> +        damaged_area.x1 = crtc_state->psr2_su_area.x1;
>> +        damaged_area.y1 = crtc_state->psr2_su_area.y1;
>> +        damaged_area.x2 = crtc_state->psr2_su_area.x2;
>> +        damaged_area.y2 = crtc_state->psr2_su_area.y2;
>> +
>> +        damaged_area.y2 +=  4 - drm_rect_height(&damaged_area);
>> +        drm_rect_intersect(&damaged_area, &crtc_state->pipe_src);
>> +        damaged_area.y1 -=  4 - drm_rect_height(&damaged_area);
>
>Stray extra spaces in there.

Huh... Interesting that I did not catch this in checkpatch output.

Thanks for noticing.

--
Gustavo Sousa

>
>> +        clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
>> +}
>> +
>>  int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>                                  struct intel_crtc *crtc)
>>  {
>> @@ -2809,6 +2832,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>          if (full_update)
>>                  goto skip_sel_fetch_set_loop;
>>  
>> +        intel_psr_su_area_min_lines(crtc_state);
>> +
>>          intel_psr_apply_su_area_workarounds(crtc_state);
>>  
>>          ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 05/32] drm/i915/dram: Add field ecc_impacting_de

[Matt Atwood]

On Wed, Oct 15, 2025 at 01:13:33PM -0300, Gustavo Sousa wrote:
> Quoting Jani Nikula (2025-10-15 11:46:52-03:00)
> >On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> >> Starting with Xe3p_LPD, we now have a new field in MEM_SS_INFO_GLOBAL
> >> that indicates whether the memory has enabled ECC that limits display
> >> bandwidth.  Add the field ecc_impacting_de to struct dram_info to
> >> contain that information and set it appropriately when probing for
> >> memory info.  We will use that field when updating bandwidth parameters
> >> for Xe3p_LPD.
> >
> >Could the field name be more accurate than "ecc impacting de"? It sounds
> >quite handwavy to me.
> 
> Well, perhaps the innacurate part would be the generic "de" instead of
> something that refers to the bandwidth?
> 
> If so, would you be fine with ecc_impacting_bandwidth?
If we're going to elaborate I'd prefer it to be ecc_impacting_de_bw
1. It matches the name in the first part
2. The additional context talks about what changes

MattA
> 
> --
> Gustavo Sousa
> 
> >
> >BR,
> >Jani.
> >
> >>
> >> Bspec: 69131
> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h       | 1 +
> >>  drivers/gpu/drm/i915/soc/intel_dram.c | 4 ++++
> >>  drivers/gpu/drm/i915/soc/intel_dram.h | 1 +
> >>  3 files changed, 6 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> >> index 354ef75ef6a5..5bf3b4ab2baa 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -1233,6 +1233,7 @@
> >>  #define   OROM_OFFSET_MASK                        REG_GENMASK(20, 16)
> >>  
> >>  #define MTL_MEM_SS_INFO_GLOBAL                        _MMIO(0x45700)
> >> +#define   XE3P_ECC_IMPACTING_DE                        REG_BIT(12)
> >>  #define   MTL_N_OF_ENABLED_QGV_POINTS_MASK        REG_GENMASK(11, 8)
> >>  #define   MTL_N_OF_POPULATED_CH_MASK                REG_GENMASK(7, 4)
> >>  #define   MTL_DDR_TYPE_MASK                        REG_GENMASK(3, 0)
> >> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c b/drivers/gpu/drm/i915/soc/intel_dram.c
> >> index 8841cfe1cac8..bf9f8e38d6ba 100644
> >> --- a/drivers/gpu/drm/i915/soc/intel_dram.c
> >> +++ b/drivers/gpu/drm/i915/soc/intel_dram.c
> >> @@ -685,6 +685,7 @@ static int gen12_get_dram_info(struct drm_i915_private *i915, struct dram_info *
> >>  
> >>  static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info *dram_info)
> >>  {
> >> +        struct intel_display *display = i915->display;
> >>          u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
> >>  
> >>          switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
> >> @@ -723,6 +724,9 @@ static int xelpdp_get_dram_info(struct drm_i915_private *i915, struct dram_info
> >>          dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
> >>          /* PSF GV points not supported in D14+ */
> >>  
> >> +        if (DISPLAY_VER(display) >= 35)
> >> +                dram_info->ecc_impacting_de = REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
> >> +
> >>          return 0;
> >>  }
> >>  
> >> diff --git a/drivers/gpu/drm/i915/soc/intel_dram.h b/drivers/gpu/drm/i915/soc/intel_dram.h
> >> index 03a973f1c941..ac77f1ab409f 100644
> >> --- a/drivers/gpu/drm/i915/soc/intel_dram.h
> >> +++ b/drivers/gpu/drm/i915/soc/intel_dram.h
> >> @@ -30,6 +30,7 @@ struct dram_info {
> >>          u8 num_channels;
> >>          u8 num_qgv_points;
> >>          u8 num_psf_gv_points;
> >> +        bool ecc_impacting_de; /* Only valid from Xe3p_LPD onward. */
> >>          bool symmetric_memory;
> >>          bool has_16gb_dimms;
> >>  };
> >
> >-- 
> >Jani Nikula, Intel

Re: [PATCH 17/32] drm/i915/xe3p_lpd: Load DMC firmware

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:17AM -0300, Gustavo Sousa wrote:
> Load the DMC firmware for Xe3p_LPD.
> 
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 517bebb0b4aa..c496e7a5c003 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -127,6 +127,9 @@ static bool dmc_firmware_param_disabled(struct intel_display *display)
>  #define DISPLAY_VER13_DMC_MAX_FW_SIZE	0x20000
>  #define DISPLAY_VER12_DMC_MAX_FW_SIZE	ICL_DMC_MAX_FW_SIZE
>  
> +#define XE3P_LPD_DMC_PATH		DMC_PATH(xe3p_lpd)
> +MODULE_FIRMWARE(XE3P_LPD_DMC_PATH);
> +
>  #define XE3LPD_DMC_PATH			DMC_PATH(xe3lpd)
>  MODULE_FIRMWARE(XE3LPD_DMC_PATH);
>  
> @@ -184,7 +187,10 @@ static const char *dmc_firmware_default(struct intel_display *display, u32 *size
>  	const char *fw_path = NULL;
>  	u32 max_fw_size = 0;
>  
> -	if (DISPLAY_VERx100(display) == 3002 ||
> +	if (DISPLAY_VERx100(display) == 3500) {
> +		fw_path = XE3P_LPD_DMC_PATH;
> +		max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
> +	} else if (DISPLAY_VERx100(display) == 3002 ||
>  	    DISPLAY_VERx100(display) == 3000) {
>  		fw_path = XE3LPD_DMC_PATH;
>  		max_fw_size = XE2LPD_DMC_MAX_FW_SIZE;
> 
> -- 
> 2.51.0
> 

Re: [PATCH 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-15 12:33:31-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Starting with Xe3p_LPD, the VBT has a new field, called in the driver
>> "dedicated_external", which tells that a Type-C capable port is
>> physically connected to a PHY outside of the Type-C subsystem.  When
>> that's the case, the driver must not do the extra Type-C programming for
>> that port.  Update intel_encoder_is_tc() to check for that case.
>>
>> While at it, add a note to intel_phy_is_tc() to remind us that it is
>> about whether the respective port is a Type-C capable port rather than
>> the PHY itself.
>>
>> (Maybe it would be a nice idea to rename intel_phy_is_tc()?)
>>
>> Note that this was handled with a new bool member added to struct
>> intel_digital_port instead of having querying the VBT directly because
>> VBT memory is freed (intel_bios_driver_remove) before encoder cleanup
>> (intel_ddi_encoder_destroy), which would cause an oops to happen when
>> the latter calls intel_encoder_is_tc().  This could be fixed by keeping
>> VBT data around longer, but that's left for a follow-up work, if deemed
>> necessary.
>>
>> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_ddi.c           |  7 +++++++
>>  drivers/gpu/drm/i915/display/intel_display.c       | 19 ++++++++++++++++++-
>>  drivers/gpu/drm/i915/display/intel_display_types.h |  1 +
>>  3 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index c09aa759f4d4..6fcbebb81263 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -5343,6 +5343,13 @@ void intel_ddi_init(struct intel_display *display,
>>                          goto err;
>>          }
>>  
>> +        if (intel_bios_encoder_is_dedicated_external(devdata)) {
>> +                dig_port->dedicated_external = true;
>> +                drm_dbg_kms(display->drm,
>> +                            "Port %c is dedicated external\n",
>> +                            port_name(port));
>> +        }
>
>With the information print added in parse_ddi_port(), the printing here
>becomes redundant.
>
>> +
>>          if (intel_encoder_is_tc(encoder)) {
>>                  bool is_legacy =
>>                          !intel_bios_encoder_supports_typec_usb(devdata) &&
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 6ac718192e1c..46474199d1ab 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -1778,7 +1778,17 @@ bool intel_phy_is_combo(struct intel_display *display, enum phy phy)
>>                  return false;
>>  }
>>  
>> -/* Prefer intel_encoder_is_tc() */
>> +/*
>> + * This function returns true if the DDI port respective to the PHY enumeration
>> + * is a Type-C capable port.
>> + *
>> + * Depending on the VBT, the port might be configured
>> + * as a "dedicated external" port, meaning that actual physical PHY is outside
>> + * of the Type-C subsystem and, as such, not really a "Type-C PHY".
>> + *
>> + * Prefer intel_encoder_is_tc(), especially if you really need to know if we
>> + * are dealing with Type-C connections.
>> + */
>>  bool intel_phy_is_tc(struct intel_display *display, enum phy phy)
>>  {
>>          /*
>> @@ -1863,6 +1873,13 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder)
>>  {
>>          struct intel_display *display = to_intel_display(encoder);
>>  
>> +        if (intel_encoder_is_dig_port(encoder)) {
>> +                struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> +
>> +                if (dig_port->dedicated_external)
>
>Why go through all the trouble of duplicating the "decicated external"
>information in the digital port, when you already have encoder
>available, and can just use intel_bios_encoder_is_dedicated_external()
>right here?

I believe the last paragraph of the commit message explains the why.
Are you suggesting that we handle the lifespan issue right in this
series instead?

Using intel_bios_encoder_is_dedicated_external() my first approach, but
then we were hit with an oops because the VBT data was not available
anymore in the driver unbind path.

--
Gustavo Sousa

>
>> +                        return false;
>> +        }
>> +
>>          return intel_phy_is_tc(display, intel_encoder_to_phy(encoder));
>>  }
>>  
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 13652e2996a4..b5b9351501b1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1909,6 +1909,7 @@ struct intel_digital_port {
>>          bool lane_reversal;
>>          bool ddi_a_4_lanes;
>>          bool release_cl2_override;
>> +        bool dedicated_external;
>>          u8 max_lanes;
>>          /* Used for DP and ICL+ TypeC/DP and TypeC/HDMI ports. */
>>          enum aux_ch aux_ch;
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 16/32] drm/i915/xe3p_lpd: Add CDCLK table

[Matt Roper]

On Wed, Oct 15, 2025 at 12:15:16AM -0300, Gustavo Sousa wrote:
> Add CDCLK table for Xe3p_LPD.
> 
> Just as with Xe3_LPD, we don't need to send voltage index info in the
> PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs.
> 
> With the new CDCLK table, we also need to update the maximum CDCLK value
> returned by intel_update_max_cdclk().
> 
> Bspec: 68861, 68863
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Table matches the spec and I don't see any new programming/register
changes introduced by this IP.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++++++++++++++++++++--
>  1 file changed, 42 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f2e092f89ddd..ffd8cab2d565 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1534,6 +1534,41 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
>  	{}
>  };
>  
> +static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
> +	{ .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
> +	{ .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
> +	{ .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
> +	{ .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
> +	{ .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
> +	{ .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
> +	{ .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
> +	{ .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
> +	{ .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
> +	{}
> +};
> +
>  static const int cdclk_squash_len = 16;
>  
>  static int cdclk_squash_divider(u16 waveform)
> @@ -3555,7 +3590,9 @@ static int intel_compute_max_dotclk(struct intel_display *display)
>   */
>  void intel_update_max_cdclk(struct intel_display *display)
>  {
> -	if (DISPLAY_VERx100(display) >= 3002) {
> +	if (DISPLAY_VER(display) >= 35) {
> +		display->cdclk.max_cdclk_freq = 787200;
> +	} else if (DISPLAY_VERx100(display) >= 3002) {
>  		display->cdclk.max_cdclk_freq = 480000;
>  	} else if (DISPLAY_VER(display) >= 30) {
>  		display->cdclk.max_cdclk_freq = 691200;
> @@ -3906,7 +3943,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>   */
>  void intel_init_cdclk_hooks(struct intel_display *display)
>  {
> -	if (DISPLAY_VER(display) >= 30) {
> +	if (DISPLAY_VER(display) >= 35) {
> +		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
> +		display->cdclk.table = xe3p_lpd_cdclk_table;
> +	} else if (DISPLAY_VER(display) >= 30) {
>  		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
>  		display->cdclk.table = xe3lpd_cdclk_table;
>  	} else if (DISPLAY_VER(display) >= 20) {
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 04/32] drm/i915/display: Use braces for if-ladder in intel_bw_init_hw()

[Matt Roper]

On Wed, Oct 15, 2025 at 12:15:04AM -0300, Gustavo Sousa wrote:
> Looking at the current if-ladder in intel_bw_init_hw(), we see that
> Xe2_HPD contains two entries, differing only for ECC memories.  In an
> upcoming change for Xe3p_LPD, we will have a similar case.
> 
> Let's improving readability by using braces and allowing adding extra
> conditions for each case.
> 
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 29 +++++++++++++++--------------
>  1 file changed, 15 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index b53bcb693e79..8f5b86cd91b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -812,29 +812,30 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (!HAS_DISPLAY(display))
>  		return;
>  
> -	if (DISPLAY_VERx100(display) >= 3002)
> +	if (DISPLAY_VERx100(display) >= 3002) {
>  		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> -	else if (DISPLAY_VER(display) >= 30)
> +	} else if (DISPLAY_VER(display) >= 30) {
>  		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> -	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx &&
> -		 dram_info->type == INTEL_DRAM_GDDR_ECC)
> -		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> -	else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx)
> -		xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> -	else if (DISPLAY_VER(display) >= 14)
> +	} else if (DISPLAY_VERx100(display) >= 1401 && display->platform.dgfx) {
> +		if (dram_info->type == INTEL_DRAM_GDDR_ECC)
> +			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_ecc_sa_info);
> +		else
> +			xe2_hpd_get_bw_info(display, dram_info, &xe2_hpd_sa_info);
> +	} else if (DISPLAY_VER(display) >= 14) {
>  		tgl_get_bw_info(display, dram_info, &mtl_sa_info);
> -	else if (display->platform.dg2)
> +	} else if (display->platform.dg2) {
>  		dg2_get_bw_info(display);
> -	else if (display->platform.alderlake_p)
> +	} else if (display->platform.alderlake_p) {
>  		tgl_get_bw_info(display, dram_info, &adlp_sa_info);
> -	else if (display->platform.alderlake_s)
> +	} else if (display->platform.alderlake_s) {
>  		tgl_get_bw_info(display, dram_info, &adls_sa_info);
> -	else if (display->platform.rocketlake)
> +	} else if (display->platform.rocketlake) {
>  		tgl_get_bw_info(display, dram_info, &rkl_sa_info);
> -	else if (DISPLAY_VER(display) == 12)
> +	} else if (DISPLAY_VER(display) == 12) {
>  		tgl_get_bw_info(display, dram_info, &tgl_sa_info);
> -	else if (DISPLAY_VER(display) == 11)
> +	} else if (DISPLAY_VER(display) == 11) {
>  		icl_get_bw_info(display, dram_info, &icl_sa_info);
> +	}
>  }
>  
>  static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 16/32] drm/i915/xe3p_lpd: Add CDCLK table

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:16AM -0300, Gustavo Sousa wrote:
> Add CDCLK table for Xe3p_LPD.
> 
> Just as with Xe3_LPD, we don't need to send voltage index info in the
> PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs.
> 
> With the new CDCLK table, we also need to update the maximum CDCLK value
> returned by intel_update_max_cdclk().
> 
> Bspec: 68861, 68863
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c | 44 ++++++++++++++++++++++++++++--
>  1 file changed, 42 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index f2e092f89ddd..ffd8cab2d565 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -1534,6 +1534,41 @@ static const struct intel_cdclk_vals xe3lpd_cdclk_table[] = {
>  	{}
>  };
>  
> +static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = {
> +	{ .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 },
> +	{ .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 },
> +	{ .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa },
> +	{ .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a },
> +	{ .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 },
> +	{ .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 },
> +	{ .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee },
> +	{ .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de },
> +	{ .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe },
> +	{ .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe },
> +	{ .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff },
> +	{ .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff },
> +	{}
> +};
> +
>  static const int cdclk_squash_len = 16;
>  
>  static int cdclk_squash_divider(u16 waveform)
> @@ -3555,7 +3590,9 @@ static int intel_compute_max_dotclk(struct intel_display *display)
>   */
>  void intel_update_max_cdclk(struct intel_display *display)
>  {
> -	if (DISPLAY_VERx100(display) >= 3002) {
> +	if (DISPLAY_VER(display) >= 35) {
> +		display->cdclk.max_cdclk_freq = 787200;
> +	} else if (DISPLAY_VERx100(display) >= 3002) {
>  		display->cdclk.max_cdclk_freq = 480000;
>  	} else if (DISPLAY_VER(display) >= 30) {
>  		display->cdclk.max_cdclk_freq = 691200;
> @@ -3906,7 +3943,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
>   */
>  void intel_init_cdclk_hooks(struct intel_display *display)
>  {
> -	if (DISPLAY_VER(display) >= 30) {
> +	if (DISPLAY_VER(display) >= 35) {
> +		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
> +		display->cdclk.table = xe3p_lpd_cdclk_table;
> +	} else if (DISPLAY_VER(display) >= 30) {
>  		display->funcs.cdclk = &xe3lpd_cdclk_funcs;
>  		display->cdclk.table = xe3lpd_cdclk_table;
>  	} else if (DISPLAY_VER(display) >= 20) {
> 
> -- 
> 2.51.0
> 

Re: [PATCH 01/32] drm/xe/nvl: Define NVL-S platform

[Lucas De Marchi]

On Wed, Oct 15, 2025 at 01:39:02PM +0530, Shekhar Chauhan wrote:
>
>On 10/15/2025 13:37, Shekhar Chauhan wrote:
>>
>>On 10/15/2025 8:45, Gustavo Sousa wrote:
>>>From: Matt Roper <matthew.d.roper@intel.com>
>>>
>>>Provide the basic platform definitions and PCI IDs for NVL-S.
>>>
>>>Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
>>>Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>>---
>>>This is brought as a dependency from the series for Xe,
>>>https://patchwork.freedesktop.org/series/155866/, so the display side
>>>can be reviewed independently.
>Wait, I realise, its the exact same patch brought in for dependency 
>issues. My bad. Though, the patch looks clean, the RB stands.

I prefer that we apply this through drm-xe-next branch, so it makes more
sense to apply together with the other series. Yes, the patch is here
only so it can be built/tested on previous platforms.

Lucas De Marchi

>>
>>Some of the changes below are redundant w.r.t the Xe series you 
>>mentioned above, but maintainers can take care of that while 
>>applying these patches.
>>
>>LGTM,
>>Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
>>
>>>---
>>>  drivers/gpu/drm/xe/xe_pci.c            | 9 +++++++++
>>>  drivers/gpu/drm/xe/xe_platform_types.h | 1 +
>>>  include/drm/intel/pciids.h             | 9 +++++++++
>>>  3 files changed, 19 insertions(+)
>>>
>>>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>>>index 24a38904bb50..cc29678be1fa 100644
>>>--- a/drivers/gpu/drm/xe/xe_pci.c
>>>+++ b/drivers/gpu/drm/xe/xe_pci.c
>>>@@ -373,6 +373,14 @@ static const struct xe_device_desc ptl_desc = {
>>>      .vm_max_level = 4,
>>>  };
>>>  +static const struct xe_device_desc nvls_desc = {
>>>+    PLATFORM(NOVALAKE_S),
>>>+    .dma_mask_size = 46,
>>>+    .has_display = true,
>>>+    .max_gt_per_tile = 2,
>>>+    .require_force_probe = true,
>>>+};
>>>+
>>>  #undef PLATFORM
>>>  __diag_pop();
>>>  @@ -401,6 +409,7 @@ static const struct pci_device_id pciidlist[] = {
>>>      INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
>>>      INTEL_PTL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>>>      INTEL_WCL_IDS(INTEL_VGA_DEVICE, &ptl_desc),
>>>+    INTEL_NVLS_IDS(INTEL_VGA_DEVICE, &nvls_desc),
>>>      { }
>>>  };
>>>  MODULE_DEVICE_TABLE(pci, pciidlist);
>>>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h 
>>>b/drivers/gpu/drm/xe/xe_platform_types.h
>>>index 3e332214c7bb..78286285c249 100644
>>>--- a/drivers/gpu/drm/xe/xe_platform_types.h
>>>+++ b/drivers/gpu/drm/xe/xe_platform_types.h
>>>@@ -24,6 +24,7 @@ enum xe_platform {
>>>      XE_LUNARLAKE,
>>>      XE_BATTLEMAGE,
>>>      XE_PANTHERLAKE,
>>>+    XE_NOVALAKE_S,
>>>  };
>>>    enum xe_subplatform {
>>>diff --git a/include/drm/intel/pciids.h b/include/drm/intel/pciids.h
>>>index 452c1de606ff..13c592e1a28c 100644
>>>--- a/include/drm/intel/pciids.h
>>>+++ b/include/drm/intel/pciids.h
>>>@@ -887,4 +887,13 @@
>>>      MACRO__(0xFD80, ## __VA_ARGS__), \
>>>      MACRO__(0xFD81, ## __VA_ARGS__)
>>>  +/* NVL-S */
>>>+#define INTEL_NVLS_IDS(MACRO__, ...) \
>>>+    MACRO__(0xD740, ## __VA_ARGS__), \
>>>+    MACRO__(0xD741, ## __VA_ARGS__), \
>>>+    MACRO__(0xD742, ## __VA_ARGS__), \
>>>+    MACRO__(0xD743, ## __VA_ARGS__), \
>>>+    MACRO__(0xD744, ## __VA_ARGS__), \
>>>+    MACRO__(0xD745, ## __VA_ARGS__)
>>>+
>>>  #endif /* __PCIIDS_H__ */
>>>

Re: [PATCH 23/32] drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:23AM -0300, Gustavo Sousa wrote:
> Xe3p_LPD has the same behavior as for Xe3_LPD with respect to DMC
> context data for pipes C and D, which are lost when their power wells
> are disabled.  As such, let's extend the condition for Xe3_LPD in
> need_pipedmc_load_mmio() to also catch Xe3p_LPD.
> 
> Bspec: 68851
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index c496e7a5c003..8ede90c033d8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -668,11 +668,11 @@ static bool need_pipedmc_load_program(struct intel_display *display)
>  static bool need_pipedmc_load_mmio(struct intel_display *display, enum pipe pipe)
>  {
>  	/*
> -	 * PTL:
> +	 * Xe3_LPD/Xe3p_LPD:
>  	 * - pipe A/B DMC doesn't need save/restore
>  	 * - pipe C/D DMC is in PG0, needs manual save/restore
>  	 */
> -	if (DISPLAY_VER(display) == 30)
> +	if (IS_DISPLAY_VER(display, 30, 35))
>  		return pipe >= PIPE_C;
>  
>  	/*
> 
> -- 
> 2.51.0
> 

Re: [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters

[Matt Roper]

On Wed, Oct 15, 2025 at 12:15:06AM -0300, Gustavo Sousa wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> Bandwidth parameters for Xe3p_LPD are basically the same as for Xe3_LPD.
> However, now Xe3p_LPD has the ecc_impacting_de field, which could impact
> how the derating is defined.
> 
> For the cases where that field is true, we use xe3p_lpd_ecc_sa_info,
> similarly to what was done for Xe2_HPD.  Note, however, that Bspec
> specifies the ECC derating value only for GDDR memory.  For now, we just
> re-use the value that was defined for Xe2_HPD, namely 45.  We need to
> confirm with the hardware team what would be the correct value(s) to use
> for the ECC case.

I think we need to use .derating = 10.  This specific block of the bspec
is a shared block that applies to lots of IPs/platforms.  GDDR isn't
relevant to an LPD platform and .derating = 10 is the documented value
for all other types of memory.


Matt

> 
> Bspec: 68859, 69131
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 21 ++++++++++++++++++++-
>  1 file changed, 20 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 8f5b86cd91b6..f0940ff9d19b 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -461,6 +461,20 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
>  	.derating = 10,
>  };
>  
> +static const struct intel_sa_info xe3p_lpd_ecc_sa_info = {
> +	.deburst = 32,
> +	.deprogbwlimit = 65, /* GB/s */
> +	.displayrtids = 256,
> +	/*
> +	 * FIXME: The Bspec only shows that derating for ECC should be 45 for
> +	 * GDDR memory and does not mention other types of memory.  For now, we
> +	 * just re-use that value, but we need to confirm whether that is
> +	 * correct or if there are different values depending on the memory
> +	 * type.
> +	 */
> +	.derating = 45,
> +};
> +
>  static int icl_get_bw_info(struct intel_display *display,
>  			   const struct dram_info *dram_info,
>  			   const struct intel_sa_info *sa)
> @@ -812,7 +826,12 @@ void intel_bw_init_hw(struct intel_display *display)
>  	if (!HAS_DISPLAY(display))
>  		return;
>  
> -	if (DISPLAY_VERx100(display) >= 3002) {
> +	if (DISPLAY_VER(display) >= 35) {
> +		if (dram_info->ecc_impacting_de)
> +			tgl_get_bw_info(display, dram_info, &xe3p_lpd_ecc_sa_info);
> +		else
> +			tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> +	} else if (DISPLAY_VERx100(display) >= 3002) {
>  		tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>  	} else if (DISPLAY_VER(display) >= 30) {
>  		tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 07/32] drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields

[Matt Roper]

On Wed, Oct 15, 2025 at 12:15:07AM -0300, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> 
> On Xe3p_LPD, the dbuf blocks fields of different registers are now
> documented as 13-bit fields. The dbuf isn't really large enough to need
> the 13th bit, but let's go ahead and update the definition now just in
> case some new display IP in future ends up needing the larger size. The
> extra bit is an unused bit in previous display versions, so we can
> safely just extend the existing definition.
> 
> Bspec: 69847, 69880, 72053
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 12 ++++++------
>  1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index ca9fdfbbe57c..479bb3f7f92b 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -324,7 +324,7 @@
>  #define   PLANE_WM_IGNORE_LINES			REG_BIT(30)
>  #define   PLANE_WM_AUTO_MIN_ALLOC_EN		REG_BIT(29)
>  #define   PLANE_WM_LINES_MASK			REG_GENMASK(26, 14)
> -#define   PLANE_WM_BLOCKS_MASK			REG_GENMASK(11, 0)
> +#define   PLANE_WM_BLOCKS_MASK			REG_GENMASK(12, 0)
>  
>  #define _PLANE_WM_SAGV_1_A			0x70258
>  #define _PLANE_WM_SAGV_1_B			0x71258
> @@ -375,10 +375,10 @@
>  							_PLANE_BUF_CFG_1_A, _PLANE_BUF_CFG_1_B, \
>  							_PLANE_BUF_CFG_2_A, _PLANE_BUF_CFG_2_B)
>  
> -/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> -#define   PLANE_BUF_END_MASK			REG_GENMASK(27, 16)
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits, xe3p_lpd 13 bits */
> +#define   PLANE_BUF_END_MASK			REG_GENMASK(28, 16)
>  #define   PLANE_BUF_END(end)			REG_FIELD_PREP(PLANE_BUF_END_MASK, (end))
> -#define   PLANE_BUF_START_MASK			REG_GENMASK(11, 0)
> +#define   PLANE_BUF_START_MASK			REG_GENMASK(12, 0)
>  #define   PLANE_BUF_START(start)		REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
>  
>  #define _PLANE_MIN_BUF_CFG_1_A			0x70274
> @@ -389,9 +389,9 @@
>  							_PLANE_MIN_BUF_CFG_1_A, _PLANE_MIN_BUF_CFG_1_B, \
>  							_PLANE_MIN_BUF_CFG_2_A, _PLANE_MIN_BUF_CFG_2_B)
>  #define	  PLANE_AUTO_MIN_DBUF_EN		REG_BIT(31)
> -#define	  PLANE_MIN_DBUF_BLOCKS_MASK		REG_GENMASK(27, 16)
> +#define	  PLANE_MIN_DBUF_BLOCKS_MASK		REG_GENMASK(28, 16)
>  #define	  PLANE_MIN_DBUF_BLOCKS(val)		REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val))
> -#define	  PLANE_INTERIM_DBUF_BLOCKS_MASK	REG_GENMASK(11, 0)
> +#define	  PLANE_INTERIM_DBUF_BLOCKS_MASK	REG_GENMASK(12, 0)
>  #define	  PLANE_INTERIM_DBUF_BLOCKS(val)	REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val))
>  
>  /* tgl+ */
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 10/32] drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces

[Matt Roper]

On Wed, Oct 15, 2025 at 12:15:10AM -0300, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> 
> Starting from Xe3p_LPD, linear surfaces also support horizontal flip.
> 
> Bspec: 68904
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>

> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 530adff81b99..9f1111324dab 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1753,7 +1753,8 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
>  	}
>  
>  	if (rotation & DRM_MODE_REFLECT_X &&
> -	    fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> +	    fb->modifier == DRM_FORMAT_MOD_LINEAR &&
> +	    DISPLAY_VER(display) < 35) {
>  		drm_dbg_kms(display->drm,
>  			    "[PLANE:%d:%s] horizontal flip is not supported with linear surface formats\n",
>  			    plane->base.base.id, plane->base.name);
> 
> -- 
> 2.51.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters

[Gustavo Sousa]

Quoting Matt Roper (2025-10-15 14:48:30-03:00)
>On Wed, Oct 15, 2025 at 12:15:06AM -0300, Gustavo Sousa wrote:
>> From: Matt Atwood <matthew.s.atwood@intel.com>
>> 
>> Bandwidth parameters for Xe3p_LPD are basically the same as for Xe3_LPD.
>> However, now Xe3p_LPD has the ecc_impacting_de field, which could impact
>> how the derating is defined.
>> 
>> For the cases where that field is true, we use xe3p_lpd_ecc_sa_info,
>> similarly to what was done for Xe2_HPD.  Note, however, that Bspec
>> specifies the ECC derating value only for GDDR memory.  For now, we just
>> re-use the value that was defined for Xe2_HPD, namely 45.  We need to
>> confirm with the hardware team what would be the correct value(s) to use
>> for the ECC case.
>
>I think we need to use .derating = 10.  This specific block of the bspec
>is a shared block that applies to lots of IPs/platforms.  GDDR isn't
>relevant to an LPD platform and .derating = 10 is the documented value
>for all other types of memory.

In that case, do mean we should drop the patch adding the field
ecc_impacting_de and unconditionally use xe3lpd_sa_info?

In the meantime I'll try to get clarifications from HW team on this.

--
Gustavo Sousa

>
>
>Matt
>
>> 
>> Bspec: 68859, 69131
>> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bw.c | 21 ++++++++++++++++++++-
>>  1 file changed, 20 insertions(+), 1 deletion(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> index 8f5b86cd91b6..f0940ff9d19b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> @@ -461,6 +461,20 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
>>          .derating = 10,
>>  };
>>  
>> +static const struct intel_sa_info xe3p_lpd_ecc_sa_info = {
>> +        .deburst = 32,
>> +        .deprogbwlimit = 65, /* GB/s */
>> +        .displayrtids = 256,
>> +        /*
>> +         * FIXME: The Bspec only shows that derating for ECC should be 45 for
>> +         * GDDR memory and does not mention other types of memory.  For now, we
>> +         * just re-use that value, but we need to confirm whether that is
>> +         * correct or if there are different values depending on the memory
>> +         * type.
>> +         */
>> +        .derating = 45,
>> +};
>> +
>>  static int icl_get_bw_info(struct intel_display *display,
>>                             const struct dram_info *dram_info,
>>                             const struct intel_sa_info *sa)
>> @@ -812,7 +826,12 @@ void intel_bw_init_hw(struct intel_display *display)
>>          if (!HAS_DISPLAY(display))
>>                  return;
>>  
>> -        if (DISPLAY_VERx100(display) >= 3002) {
>> +        if (DISPLAY_VER(display) >= 35) {
>> +                if (dram_info->ecc_impacting_de)
>> +                        tgl_get_bw_info(display, dram_info, &xe3p_lpd_ecc_sa_info);
>> +                else
>> +                        tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> +        } else if (DISPLAY_VERx100(display) >= 3002) {
>>                  tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>>          } else if (DISPLAY_VER(display) >= 30) {
>>                  tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> 
>> -- 
>> 2.51.0
>> 
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters

[Matt Roper]

On Wed, Oct 15, 2025 at 03:12:34PM -0300, Gustavo Sousa wrote:
> Quoting Matt Roper (2025-10-15 14:48:30-03:00)
> >On Wed, Oct 15, 2025 at 12:15:06AM -0300, Gustavo Sousa wrote:
> >> From: Matt Atwood <matthew.s.atwood@intel.com>
> >> 
> >> Bandwidth parameters for Xe3p_LPD are basically the same as for Xe3_LPD.
> >> However, now Xe3p_LPD has the ecc_impacting_de field, which could impact
> >> how the derating is defined.
> >> 
> >> For the cases where that field is true, we use xe3p_lpd_ecc_sa_info,
> >> similarly to what was done for Xe2_HPD.  Note, however, that Bspec
> >> specifies the ECC derating value only for GDDR memory.  For now, we just
> >> re-use the value that was defined for Xe2_HPD, namely 45.  We need to
> >> confirm with the hardware team what would be the correct value(s) to use
> >> for the ECC case.
> >
> >I think we need to use .derating = 10.  This specific block of the bspec
> >is a shared block that applies to lots of IPs/platforms.  GDDR isn't
> >relevant to an LPD platform and .derating = 10 is the documented value
> >for all other types of memory.
> 
> In that case, do mean we should drop the patch adding the field
> ecc_impacting_de and unconditionally use xe3lpd_sa_info?

They're somewhat orthogonal.  The hardware (or rather firmware I guess?)
now has a way to tell software that there's ECC present that would
impact bandwidth, and in general that notification could be used with
any kind of RAM.  Some platforms will never have a situation where ECC
matters to bandwidth (so this new flag will never be set), some igpu
platforms will have cases where system memory ECC impacts bandwidth, and
some dgpu platforms will have cases where vram ECC impacts bandwidth.
We don't have any relevant rules at the moment, but real details may get
added to the spec later as we get closer to supporting the specific
platform(s) that these IP versions will be incorporated into.  But
adding the general ability to read out the new flag and have it ready
for when platform-specific details start arriving in the future seems
fine to me.  We could add a warning print if the flag is actually
getting set on some platform before we have any rules documenting what
we're supposed to do about it.

In general, I'm wondering if the memory bandwidth numbers are something
that we should consider moving back to platform-based checks.  The
hardware teams tie these kinds of changes to tickets associated with
specific IPs, but that's mostly just because of how the databases for
hardware changes are organized these days.  The reality is that the
details for memory characteristics are something that's more defined by
the underlying platform rather than the IP (and that's especially true
for igpu platforms where where we're talking about system memory that's
used by the CPU and all the other devices on the platform as well).


Matt

> 
> In the meantime I'll try to get clarifications from HW team on this.
> 
> --
> Gustavo Sousa
> 
> >
> >
> >Matt
> >
> >> 
> >> Bspec: 68859, 69131
> >> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_bw.c | 21 ++++++++++++++++++++-
> >>  1 file changed, 20 insertions(+), 1 deletion(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> >> index 8f5b86cd91b6..f0940ff9d19b 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> >> @@ -461,6 +461,20 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
> >>          .derating = 10,
> >>  };
> >>  
> >> +static const struct intel_sa_info xe3p_lpd_ecc_sa_info = {
> >> +        .deburst = 32,
> >> +        .deprogbwlimit = 65, /* GB/s */
> >> +        .displayrtids = 256,
> >> +        /*
> >> +         * FIXME: The Bspec only shows that derating for ECC should be 45 for
> >> +         * GDDR memory and does not mention other types of memory.  For now, we
> >> +         * just re-use that value, but we need to confirm whether that is
> >> +         * correct or if there are different values depending on the memory
> >> +         * type.
> >> +         */
> >> +        .derating = 45,
> >> +};
> >> +
> >>  static int icl_get_bw_info(struct intel_display *display,
> >>                             const struct dram_info *dram_info,
> >>                             const struct intel_sa_info *sa)
> >> @@ -812,7 +826,12 @@ void intel_bw_init_hw(struct intel_display *display)
> >>          if (!HAS_DISPLAY(display))
> >>                  return;
> >>  
> >> -        if (DISPLAY_VERx100(display) >= 3002) {
> >> +        if (DISPLAY_VER(display) >= 35) {
> >> +                if (dram_info->ecc_impacting_de)
> >> +                        tgl_get_bw_info(display, dram_info, &xe3p_lpd_ecc_sa_info);
> >> +                else
> >> +                        tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> >> +        } else if (DISPLAY_VERx100(display) >= 3002) {
> >>                  tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
> >>          } else if (DISPLAY_VER(display) >= 30) {
> >>                  tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
> >> 
> >> -- 
> >> 2.51.0
> >> 
> >
> >-- 
> >Matt Roper
> >Graphics Software Engineer
> >Linux GPU Platform Enablement
> >Intel Corporation

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation

Re: [PATCH 06/32] drm/i915/xe3p_lpd: Update bandwidth parameters

[Gustavo Sousa]

Quoting Matt Roper (2025-10-15 16:12:41-03:00)
>On Wed, Oct 15, 2025 at 03:12:34PM -0300, Gustavo Sousa wrote:
>> Quoting Matt Roper (2025-10-15 14:48:30-03:00)
>> >On Wed, Oct 15, 2025 at 12:15:06AM -0300, Gustavo Sousa wrote:
>> >> From: Matt Atwood <matthew.s.atwood@intel.com>
>> >> 
>> >> Bandwidth parameters for Xe3p_LPD are basically the same as for Xe3_LPD.
>> >> However, now Xe3p_LPD has the ecc_impacting_de field, which could impact
>> >> how the derating is defined.
>> >> 
>> >> For the cases where that field is true, we use xe3p_lpd_ecc_sa_info,
>> >> similarly to what was done for Xe2_HPD.  Note, however, that Bspec
>> >> specifies the ECC derating value only for GDDR memory.  For now, we just
>> >> re-use the value that was defined for Xe2_HPD, namely 45.  We need to
>> >> confirm with the hardware team what would be the correct value(s) to use
>> >> for the ECC case.
>> >
>> >I think we need to use .derating = 10.  This specific block of the bspec
>> >is a shared block that applies to lots of IPs/platforms.  GDDR isn't
>> >relevant to an LPD platform and .derating = 10 is the documented value
>> >for all other types of memory.
>> 
>> In that case, do mean we should drop the patch adding the field
>> ecc_impacting_de and unconditionally use xe3lpd_sa_info?
>
>They're somewhat orthogonal.  The hardware (or rather firmware I guess?)
>now has a way to tell software that there's ECC present that would
>impact bandwidth, and in general that notification could be used with
>any kind of RAM.  Some platforms will never have a situation where ECC
>matters to bandwidth (so this new flag will never be set), some igpu
>platforms will have cases where system memory ECC impacts bandwidth, and
>some dgpu platforms will have cases where vram ECC impacts bandwidth.
>We don't have any relevant rules at the moment, but real details may get
>added to the spec later as we get closer to supporting the specific
>platform(s) that these IP versions will be incorporated into.  But
>adding the general ability to read out the new flag and have it ready
>for when platform-specific details start arriving in the future seems
>fine to me.  We could add a warning print if the flag is actually
>getting set on some platform before we have any rules documenting what
>we're supposed to do about it.

Yep.  Adding a warning sounds good to me.  I think that would be better
as part of the previous patch.

>
>In general, I'm wondering if the memory bandwidth numbers are something
>that we should consider moving back to platform-based checks.  The
>hardware teams tie these kinds of changes to tickets associated with
>specific IPs, but that's mostly just because of how the databases for
>hardware changes are organized these days.  The reality is that the
>details for memory characteristics are something that's more defined by
>the underlying platform rather than the IP (and that's especially true
>for igpu platforms where where we're talking about system memory that's
>used by the CPU and all the other devices on the platform as well).

Hm... Probably.  As an example that illustrates your point, we have PTL
and WCL, which contain the same display architecture, but one different
instance of struct intel_sa_info for each.

--
Gustavo Sousa

>
>
>Matt
>
>> 
>> In the meantime I'll try to get clarifications from HW team on this.
>> 
>> --
>> Gustavo Sousa
>> 
>> >
>> >
>> >Matt
>> >
>> >> 
>> >> Bspec: 68859, 69131
>> >> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
>> >> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> >> ---
>> >>  drivers/gpu/drm/i915/display/intel_bw.c | 21 ++++++++++++++++++++-
>> >>  1 file changed, 20 insertions(+), 1 deletion(-)
>> >> 
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
>> >> index 8f5b86cd91b6..f0940ff9d19b 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_bw.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
>> >> @@ -461,6 +461,20 @@ static const struct intel_sa_info xe3lpd_3002_sa_info = {
>> >>          .derating = 10,
>> >>  };
>> >>  
>> >> +static const struct intel_sa_info xe3p_lpd_ecc_sa_info = {
>> >> +        .deburst = 32,
>> >> +        .deprogbwlimit = 65, /* GB/s */
>> >> +        .displayrtids = 256,
>> >> +        /*
>> >> +         * FIXME: The Bspec only shows that derating for ECC should be 45 for
>> >> +         * GDDR memory and does not mention other types of memory.  For now, we
>> >> +         * just re-use that value, but we need to confirm whether that is
>> >> +         * correct or if there are different values depending on the memory
>> >> +         * type.
>> >> +         */
>> >> +        .derating = 45,
>> >> +};
>> >> +
>> >>  static int icl_get_bw_info(struct intel_display *display,
>> >>                             const struct dram_info *dram_info,
>> >>                             const struct intel_sa_info *sa)
>> >> @@ -812,7 +826,12 @@ void intel_bw_init_hw(struct intel_display *display)
>> >>          if (!HAS_DISPLAY(display))
>> >>                  return;
>> >>  
>> >> -        if (DISPLAY_VERx100(display) >= 3002) {
>> >> +        if (DISPLAY_VER(display) >= 35) {
>> >> +                if (dram_info->ecc_impacting_de)
>> >> +                        tgl_get_bw_info(display, dram_info, &xe3p_lpd_ecc_sa_info);
>> >> +                else
>> >> +                        tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> >> +        } else if (DISPLAY_VERx100(display) >= 3002) {
>> >>                  tgl_get_bw_info(display, dram_info, &xe3lpd_3002_sa_info);
>> >>          } else if (DISPLAY_VER(display) >= 30) {
>> >>                  tgl_get_bw_info(display, dram_info, &xe3lpd_sa_info);
>> >> 
>> >> -- 
>> >> 2.51.0
>> >> 
>> >
>> >-- 
>> >Matt Roper
>> >Graphics Software Engineer
>> >Linux GPU Platform Enablement
>> >Intel Corporation
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation

Re: [PATCH 08/32] drm/i915/xe3p_lpd: Support UINT16 formats

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:08AM -0300, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> 
> Starting from display Xe3p_LPD, UINT16 formats are also supported. Add
> its corresponding PLANE_CTL bit and add the format in the necessary
> functions.
> 
> Bspec: 68904, 69853
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 96 +++++++++++++++-------
>  .../drm/i915/display/skl_universal_plane_regs.h    |  1 +
>  2 files changed, 68 insertions(+), 29 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 0319174adf95..530adff81b99 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -136,36 +136,47 @@ static const u32 icl_sdr_uv_plane_formats[] = {
>  	DRM_FORMAT_XVYU2101010,
>  };
>  
> +#define ICL_HDR_PLANE_FORMATS		\
> +	DRM_FORMAT_C8,			\
> +	DRM_FORMAT_RGB565,		\
> +	DRM_FORMAT_XRGB8888,		\
> +	DRM_FORMAT_XBGR8888,		\
> +	DRM_FORMAT_ARGB8888,		\
> +	DRM_FORMAT_ABGR8888,		\
> +	DRM_FORMAT_XRGB2101010,		\
> +	DRM_FORMAT_XBGR2101010,		\
> +	DRM_FORMAT_ARGB2101010,		\
> +	DRM_FORMAT_ABGR2101010,		\
> +	DRM_FORMAT_XRGB16161616F,	\
> +	DRM_FORMAT_XBGR16161616F,	\
> +	DRM_FORMAT_ARGB16161616F,	\
> +	DRM_FORMAT_ABGR16161616F,	\
> +	DRM_FORMAT_YUYV,		\
> +	DRM_FORMAT_YVYU,		\
> +	DRM_FORMAT_UYVY,		\
> +	DRM_FORMAT_VYUY,		\
> +	DRM_FORMAT_NV12,		\
> +	DRM_FORMAT_P010,		\
> +	DRM_FORMAT_P012,		\
> +	DRM_FORMAT_P016,		\
> +	DRM_FORMAT_Y210,		\
> +	DRM_FORMAT_Y212,		\
> +	DRM_FORMAT_Y216,		\
> +	DRM_FORMAT_XYUV8888,		\
> +	DRM_FORMAT_XVYU2101010,		\
> +	DRM_FORMAT_XVYU12_16161616,	\
> +	DRM_FORMAT_XVYU16161616
> +
>  static const u32 icl_hdr_plane_formats[] = {
> -	DRM_FORMAT_C8,
> -	DRM_FORMAT_RGB565,
> -	DRM_FORMAT_XRGB8888,
> -	DRM_FORMAT_XBGR8888,
> -	DRM_FORMAT_ARGB8888,
> -	DRM_FORMAT_ABGR8888,
> -	DRM_FORMAT_XRGB2101010,
> -	DRM_FORMAT_XBGR2101010,
> -	DRM_FORMAT_ARGB2101010,
> -	DRM_FORMAT_ABGR2101010,
> -	DRM_FORMAT_XRGB16161616F,
> -	DRM_FORMAT_XBGR16161616F,
> -	DRM_FORMAT_ARGB16161616F,
> -	DRM_FORMAT_ABGR16161616F,
> -	DRM_FORMAT_YUYV,
> -	DRM_FORMAT_YVYU,
> -	DRM_FORMAT_UYVY,
> -	DRM_FORMAT_VYUY,
> -	DRM_FORMAT_NV12,
> -	DRM_FORMAT_P010,
> -	DRM_FORMAT_P012,
> -	DRM_FORMAT_P016,
> -	DRM_FORMAT_Y210,
> -	DRM_FORMAT_Y212,
> -	DRM_FORMAT_Y216,
> -	DRM_FORMAT_XYUV8888,
> -	DRM_FORMAT_XVYU2101010,
> -	DRM_FORMAT_XVYU12_16161616,
> -	DRM_FORMAT_XVYU16161616,
> +	ICL_HDR_PLANE_FORMATS,
> +};
> +
> +static const u32 xe3p_lpd_hdr_plane_formats[] = {
> +	ICL_HDR_PLANE_FORMATS,
> +	DRM_FORMAT_XRGB16161616,
> +	DRM_FORMAT_XBGR16161616,
> +	DRM_FORMAT_ARGB16161616,
> +	DRM_FORMAT_ABGR16161616,
>  };
>  
>  int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> @@ -220,6 +231,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
>  			else
>  				return DRM_FORMAT_XRGB2101010;
>  		}
> +	case PLANE_CTL_FORMAT_XRGB_16161616:
> +		if (rgb_order) {
> +			if (alpha)
> +				return DRM_FORMAT_ABGR16161616;
> +			else
> +				return DRM_FORMAT_XBGR16161616;
> +		} else {
> +			if (alpha)
> +				return DRM_FORMAT_ARGB16161616;
> +			else
> +				return DRM_FORMAT_XRGB16161616;
> +		}
>  	case PLANE_CTL_FORMAT_XRGB_16161616F:
>  		if (rgb_order) {
>  			if (alpha)
> @@ -960,6 +983,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
>  	case DRM_FORMAT_XRGB2101010:
>  	case DRM_FORMAT_ARGB2101010:
>  		return PLANE_CTL_FORMAT_XRGB_2101010;
> +	case DRM_FORMAT_XBGR16161616:
> +	case DRM_FORMAT_ABGR16161616:
> +		return PLANE_CTL_FORMAT_XRGB_16161616 | PLANE_CTL_ORDER_RGBX;
> +	case DRM_FORMAT_XRGB16161616:
> +	case DRM_FORMAT_ARGB16161616:
> +		return PLANE_CTL_FORMAT_XRGB_16161616;
>  	case DRM_FORMAT_XBGR16161616F:
>  	case DRM_FORMAT_ABGR16161616F:
>  		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> @@ -2479,6 +2508,11 @@ static const u32 *icl_get_plane_formats(struct intel_display *display,
>  					int *num_formats)
>  {
>  	if (icl_is_hdr_plane(display, plane_id)) {
> +		if (DISPLAY_VER(display) >= 35) {
> +			*num_formats = ARRAY_SIZE(xe3p_lpd_hdr_plane_formats);
> +			return xe3p_lpd_hdr_plane_formats;
> +		}
> +
>  		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
>  		return icl_hdr_plane_formats;
>  	} else if (icl_is_nv12_y_plane(display, plane_id)) {
> @@ -2637,6 +2671,10 @@ static bool tgl_plane_format_mod_supported(struct drm_plane *_plane,
>  	case DRM_FORMAT_RGB565:
>  	case DRM_FORMAT_XVYU2101010:
>  	case DRM_FORMAT_C8:
> +	case DRM_FORMAT_XBGR16161616:
> +	case DRM_FORMAT_ABGR16161616:
> +	case DRM_FORMAT_XRGB16161616:
> +	case DRM_FORMAT_ARGB16161616:
>  	case DRM_FORMAT_Y210:
>  	case DRM_FORMAT_Y212:
>  	case DRM_FORMAT_Y216:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index 479bb3f7f92b..84cf565bd653 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -64,6 +64,7 @@
>  #define   PLANE_CTL_FORMAT_Y410			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
>  #define   PLANE_CTL_FORMAT_Y412			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
>  #define   PLANE_CTL_FORMAT_Y416			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> +#define   PLANE_CTL_FORMAT_XRGB_16161616	REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 18)
>  #define   PLANE_CTL_PIPE_CSC_ENABLE		REG_BIT(23) /* Pre-GLK */
>  #define   PLANE_CTL_KEY_ENABLE_MASK		REG_GENMASK(22, 21)
>  #define   PLANE_CTL_KEY_ENABLE_SOURCE		REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> 
> -- 
> 2.51.0
> 

Re: [PATCH 08/32] drm/i915/xe3p_lpd: Support UINT16 formats

[Matt Atwood]

On Wed, Oct 15, 2025 at 01:23:53PM -0700, Matt Atwood wrote:
> On Wed, Oct 15, 2025 at 12:15:08AM -0300, Gustavo Sousa wrote:
> > From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> > 
> > Starting from display Xe3p_LPD, UINT16 formats are also supported. Add
> > its corresponding PLANE_CTL bit and add the format in the necessary
> > functions.
> > 
> > Bspec: 68904, 69853
Sorry lets include the bspec 68911, review stands
> Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> > Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c | 96 +++++++++++++++-------
> >  .../drm/i915/display/skl_universal_plane_regs.h    |  1 +
> >  2 files changed, 68 insertions(+), 29 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 0319174adf95..530adff81b99 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -136,36 +136,47 @@ static const u32 icl_sdr_uv_plane_formats[] = {
> >  	DRM_FORMAT_XVYU2101010,
> >  };
> >  
> > +#define ICL_HDR_PLANE_FORMATS		\
> > +	DRM_FORMAT_C8,			\
> > +	DRM_FORMAT_RGB565,		\
> > +	DRM_FORMAT_XRGB8888,		\
> > +	DRM_FORMAT_XBGR8888,		\
> > +	DRM_FORMAT_ARGB8888,		\
> > +	DRM_FORMAT_ABGR8888,		\
> > +	DRM_FORMAT_XRGB2101010,		\
> > +	DRM_FORMAT_XBGR2101010,		\
> > +	DRM_FORMAT_ARGB2101010,		\
> > +	DRM_FORMAT_ABGR2101010,		\
> > +	DRM_FORMAT_XRGB16161616F,	\
> > +	DRM_FORMAT_XBGR16161616F,	\
> > +	DRM_FORMAT_ARGB16161616F,	\
> > +	DRM_FORMAT_ABGR16161616F,	\
> > +	DRM_FORMAT_YUYV,		\
> > +	DRM_FORMAT_YVYU,		\
> > +	DRM_FORMAT_UYVY,		\
> > +	DRM_FORMAT_VYUY,		\
> > +	DRM_FORMAT_NV12,		\
> > +	DRM_FORMAT_P010,		\
> > +	DRM_FORMAT_P012,		\
> > +	DRM_FORMAT_P016,		\
> > +	DRM_FORMAT_Y210,		\
> > +	DRM_FORMAT_Y212,		\
> > +	DRM_FORMAT_Y216,		\
> > +	DRM_FORMAT_XYUV8888,		\
> > +	DRM_FORMAT_XVYU2101010,		\
> > +	DRM_FORMAT_XVYU12_16161616,	\
> > +	DRM_FORMAT_XVYU16161616
> > +
> >  static const u32 icl_hdr_plane_formats[] = {
> > -	DRM_FORMAT_C8,
> > -	DRM_FORMAT_RGB565,
> > -	DRM_FORMAT_XRGB8888,
> > -	DRM_FORMAT_XBGR8888,
> > -	DRM_FORMAT_ARGB8888,
> > -	DRM_FORMAT_ABGR8888,
> > -	DRM_FORMAT_XRGB2101010,
> > -	DRM_FORMAT_XBGR2101010,
> > -	DRM_FORMAT_ARGB2101010,
> > -	DRM_FORMAT_ABGR2101010,
> > -	DRM_FORMAT_XRGB16161616F,
> > -	DRM_FORMAT_XBGR16161616F,
> > -	DRM_FORMAT_ARGB16161616F,
> > -	DRM_FORMAT_ABGR16161616F,
> > -	DRM_FORMAT_YUYV,
> > -	DRM_FORMAT_YVYU,
> > -	DRM_FORMAT_UYVY,
> > -	DRM_FORMAT_VYUY,
> > -	DRM_FORMAT_NV12,
> > -	DRM_FORMAT_P010,
> > -	DRM_FORMAT_P012,
> > -	DRM_FORMAT_P016,
> > -	DRM_FORMAT_Y210,
> > -	DRM_FORMAT_Y212,
> > -	DRM_FORMAT_Y216,
> > -	DRM_FORMAT_XYUV8888,
> > -	DRM_FORMAT_XVYU2101010,
> > -	DRM_FORMAT_XVYU12_16161616,
> > -	DRM_FORMAT_XVYU16161616,
> > +	ICL_HDR_PLANE_FORMATS,
> > +};
> > +
> > +static const u32 xe3p_lpd_hdr_plane_formats[] = {
> > +	ICL_HDR_PLANE_FORMATS,
> > +	DRM_FORMAT_XRGB16161616,
> > +	DRM_FORMAT_XBGR16161616,
> > +	DRM_FORMAT_ARGB16161616,
> > +	DRM_FORMAT_ABGR16161616,
> >  };
> >  
> >  int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> > @@ -220,6 +231,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> >  			else
> >  				return DRM_FORMAT_XRGB2101010;
> >  		}
> > +	case PLANE_CTL_FORMAT_XRGB_16161616:
> > +		if (rgb_order) {
> > +			if (alpha)
> > +				return DRM_FORMAT_ABGR16161616;
> > +			else
> > +				return DRM_FORMAT_XBGR16161616;
> > +		} else {
> > +			if (alpha)
> > +				return DRM_FORMAT_ARGB16161616;
> > +			else
> > +				return DRM_FORMAT_XRGB16161616;
> > +		}
> >  	case PLANE_CTL_FORMAT_XRGB_16161616F:
> >  		if (rgb_order) {
> >  			if (alpha)
> > @@ -960,6 +983,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format)
> >  	case DRM_FORMAT_XRGB2101010:
> >  	case DRM_FORMAT_ARGB2101010:
> >  		return PLANE_CTL_FORMAT_XRGB_2101010;
> > +	case DRM_FORMAT_XBGR16161616:
> > +	case DRM_FORMAT_ABGR16161616:
> > +		return PLANE_CTL_FORMAT_XRGB_16161616 | PLANE_CTL_ORDER_RGBX;
> > +	case DRM_FORMAT_XRGB16161616:
> > +	case DRM_FORMAT_ARGB16161616:
> > +		return PLANE_CTL_FORMAT_XRGB_16161616;
> >  	case DRM_FORMAT_XBGR16161616F:
> >  	case DRM_FORMAT_ABGR16161616F:
> >  		return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
> > @@ -2479,6 +2508,11 @@ static const u32 *icl_get_plane_formats(struct intel_display *display,
> >  					int *num_formats)
> >  {
> >  	if (icl_is_hdr_plane(display, plane_id)) {
> > +		if (DISPLAY_VER(display) >= 35) {
> > +			*num_formats = ARRAY_SIZE(xe3p_lpd_hdr_plane_formats);
> > +			return xe3p_lpd_hdr_plane_formats;
> > +		}
> > +
> >  		*num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
> >  		return icl_hdr_plane_formats;
> >  	} else if (icl_is_nv12_y_plane(display, plane_id)) {
> > @@ -2637,6 +2671,10 @@ static bool tgl_plane_format_mod_supported(struct drm_plane *_plane,
> >  	case DRM_FORMAT_RGB565:
> >  	case DRM_FORMAT_XVYU2101010:
> >  	case DRM_FORMAT_C8:
> > +	case DRM_FORMAT_XBGR16161616:
> > +	case DRM_FORMAT_ABGR16161616:
> > +	case DRM_FORMAT_XRGB16161616:
> > +	case DRM_FORMAT_ARGB16161616:
> >  	case DRM_FORMAT_Y210:
> >  	case DRM_FORMAT_Y212:
> >  	case DRM_FORMAT_Y216:
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > index 479bb3f7f92b..84cf565bd653 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > @@ -64,6 +64,7 @@
> >  #define   PLANE_CTL_FORMAT_Y410			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7)
> >  #define   PLANE_CTL_FORMAT_Y412			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9)
> >  #define   PLANE_CTL_FORMAT_Y416			REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11)
> > +#define   PLANE_CTL_FORMAT_XRGB_16161616	REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 18)
> >  #define   PLANE_CTL_PIPE_CSC_ENABLE		REG_BIT(23) /* Pre-GLK */
> >  #define   PLANE_CTL_KEY_ENABLE_MASK		REG_GENMASK(22, 21)
> >  #define   PLANE_CTL_KEY_ENABLE_SOURCE		REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1)
> > 
> > -- 
> > 2.51.0
> > 

Re: [PATCH 14/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-15 11:58:37-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>>
>> Some of the register fields of MBUS_CTL and DBUF_CTL register are
>> changed for Xe3p_LPD platforms. Update the changed fields in the driver.
>> Below are the changes:
>>
>> MBUS_CTL:
>>         Translation Throttle Min
>>                 It changed from BIT[15:13] to BIT[16:13]
>>
>> DBUF_CTL:
>>         Min Tracker State Service
>>                 It changed from BIT[18:16] to BIT[20:16]
>>         Max Tracker State Service
>>                 It changed to from BIT[23:19] to BIT[14:10]
>>                 but using default value, so no need to define
>>                 in code.
>>
>> Bspec: 68868, 68872
>> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/skl_watermark.c      | 16 ++++++++++++----
>>  drivers/gpu/drm/i915/display/skl_watermark_regs.h | 12 ++++++++++--
>>  2 files changed, 22 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 9df9ee137bf9..41f64e347436 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -3505,7 +3505,10 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
>>          if (!HAS_MBUS_JOINING(display))
>>                  return;
>>  
>> -        if (DISPLAY_VER(display) >= 20)
>> +        if (DISPLAY_VER(display) >= 35)
>> +                intel_de_rmw(display, MBUS_CTL, XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK,
>> +                             XE3P_MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
>> +        else if (DISPLAY_VER(display) >= 20)
>>                  intel_de_rmw(display, MBUS_CTL, MBUS_TRANSLATION_THROTTLE_MIN_MASK,
>>                               MBUS_TRANSLATION_THROTTLE_MIN(ratio - 1));
>>  
>> @@ -3516,9 +3519,14 @@ void intel_dbuf_mdclk_cdclk_ratio_update(struct intel_display *display,
>>                      ratio, str_yes_no(joined_mbus));
>>  
>>          for_each_dbuf_slice(display, slice)
>> -                intel_de_rmw(display, DBUF_CTL_S(slice),
>> -                             DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>> -                             DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
>> +                if (DISPLAY_VER(display) >= 35)
>> +                        intel_de_rmw(display, DBUF_CTL_S(slice),
>> +                                     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>> +                                     XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
>> +                else
>> +                        intel_de_rmw(display, DBUF_CTL_S(slice),
>> +                                     DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
>> +                                     DBUF_MIN_TRACKER_STATE_SERVICE(ratio - 1));
>>  }
>>  
>>  static void intel_dbuf_mdclk_min_tracker_update(struct intel_atomic_state *state)
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
>> index c5572fc0e847..7e0877303e05 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
>> @@ -41,7 +41,11 @@
>>  #define   MBUS_JOIN_PIPE_SELECT(pipe)                REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
>>  #define   MBUS_JOIN_PIPE_SELECT_NONE                MBUS_JOIN_PIPE_SELECT(7)
>>  #define   MBUS_TRANSLATION_THROTTLE_MIN_MASK        REG_GENMASK(15, 13)
>> -#define   MBUS_TRANSLATION_THROTTLE_MIN(val)        REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>> +#define   MBUS_TRANSLATION_THROTTLE_MIN(val) \
>> +                REG_FIELD_PREP(MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>> +#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK        REG_GENMASK(16, 13)
>> +#define   XE3P_MBUS_TRANSLATION_THROTTLE_MIN(val) \
>> +                REG_FIELD_PREP(XE3P_MBUS_TRANSLATION_THROTTLE_MIN_MASK, val)
>>  
>>  /*
>>   * The below are numbered starting from "S1" on gen11/gen12, but starting
>> @@ -65,7 +69,11 @@
>>  #define  DBUF_TRACKER_STATE_SERVICE_MASK        REG_GENMASK(23, 19)
>>  #define  DBUF_TRACKER_STATE_SERVICE(x)                REG_FIELD_PREP(DBUF_TRACKER_STATE_SERVICE_MASK, x)
>>  #define  DBUF_MIN_TRACKER_STATE_SERVICE_MASK        REG_GENMASK(18, 16) /* ADL-P+ */
>> -#define  DBUF_MIN_TRACKER_STATE_SERVICE(x)                REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
>> +#define  DBUF_MIN_TRACKER_STATE_SERVICE(x) \
>> +                REG_FIELD_PREP(DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x) /* ADL-P+ */
>> +#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK        REG_GENMASK(20, 16)
>> +#define  XE3P_DBUF_MIN_TRACKER_STATE_SERVICE(x) \
>> +                REG_FIELD_PREP(XE3P_DBUF_MIN_TRACKER_STATE_SERVICE_MASK, x)
>
>Please just keep the long lines in this file. In this case, I think it's
>cleaner.

Alright, done. Because of the length of the new XE3P_* macros, the
column alignment for the definition is off by 1 tab character w.r.t. to
the items above them.  I took a guess and aligned the already existing
ones with one extra tab for each.  Let me know if that's fine to you.

These changes are in still my local tree as I incorporate the remaining
of the review feedback (and also wait a bit more for more feedback).

--
Gustavo Sousa

>
>
>>  
>>  #define MTL_LATENCY_LP0_LP1                _MMIO(0x45780)
>>  #define MTL_LATENCY_LP2_LP3                _MMIO(0x45784)
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 22/32] drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:22AM -0300, Gustavo Sousa wrote:
> From: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>
> 
> Disable support for odd panning and size in y direction when running on
> display version 35 and using semiplanar formats.
> 
> Bspec: 68903
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Juha-pekka Heikkila <juha-pekka.heikkila@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_plane.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_plane.c b/drivers/gpu/drm/i915/display/intel_plane.c
> index 074de9275951..8de4e15fae6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_plane.c
> @@ -1050,6 +1050,9 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
>  		     DISPLAY_VERx100(display) == 3002) &&
>  		     src_x % 2 != 0)
>  			hsub = 2;
> +
> +		if (DISPLAY_VER(display) == 35)
> +			vsub = 2;
>  	} else {
>  		hsub = fb->format->hsub;
>  		vsub = fb->format->vsub;
> 
> -- 
> 2.51.0
> 

Re: [PATCH 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment

[Matt Atwood]

On Wed, Oct 15, 2025 at 12:15:15AM -0300, Gustavo Sousa wrote:
> When reading memory latencies for watermark calculations, previous
> display releases instructed to apply an adjustment of adding a certain
> value (e.g. 6us) to all levels when the level 0's memory latency read
> from hardware was zero.
> 
> For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
> add that value to the other levels.  Update adjust_wm_latency()
> accordingly.
> 
> Bspec: 68986, 69126
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 41f64e347436..88342d07727f 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3249,6 +3249,13 @@ adjust_wm_latency(struct intel_display *display)
>  
>  	make_wm_latency_monotonic(display);
>  
> +	/*
> +	 * Xe3p asks to ignore wm[0] read from the register and always
> +	 * use the adjustment done with read_latency.
> +	 */
> +	if (DISPLAY_VER(display) >= 35)
> +		wm[0] = 0;
> +
>  	/*
>  	 * WaWmMemoryReadLatency
>  	 *
> 
> -- 
> 2.51.0
> 

Re: [PATCH 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment

[Ville Syrjälä]

On Wed, Oct 15, 2025 at 12:15:15AM -0300, Gustavo Sousa wrote:
> When reading memory latencies for watermark calculations, previous
> display releases instructed to apply an adjustment of adding a certain
> value (e.g. 6us) to all levels when the level 0's memory latency read
> from hardware was zero.
> 
> For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
> add that value to the other levels.  Update adjust_wm_latency()
> accordingly.
> 
> Bspec: 68986, 69126
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 41f64e347436..88342d07727f 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3249,6 +3249,13 @@ adjust_wm_latency(struct intel_display *display)
>  
>  	make_wm_latency_monotonic(display);
>  
> +	/*
> +	 * Xe3p asks to ignore wm[0] read from the register and always
> +	 * use the adjustment done with read_latency.
> +	 */
> +	if (DISPLAY_VER(display) >= 35)
> +		wm[0] = 0;

make_wm_latency_monotonic() already used wm[0]. I think this
needs to be the very first thing you do in adjust_wm_latency().

> +
>  	/*
>  	 * WaWmMemoryReadLatency
>  	 *
> 
> -- 
> 2.51.0

-- 
Ville Syrjälä
Intel

Re: [PATCH 13/32] drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks

[Borah, Chaitanya Kumar]

On 10/15/2025 8:45 AM, Gustavo Sousa wrote:
> From: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> 
> With Xe3p_LPD, the SKL_BOTTOM_COLOR_GAMMA_ENABLE and
> SKL_BOTTOM_COLOR_CSC_ENABLE bits are being removed. Thus, we need not
> set gamma_enable nor csc_enable in crtc_state.
> 
> Note that GAMMA_MODE.POST_CSC_GAMMA_ENABLE and CSC_MODE.ICL_CSC_ENABLE
> are the documented alternatives for the bottom color bits being removed.
> But as these suggested bits are being checked in state checker as part
> of gamma_mode, csc_mode fields and as gamma_enable/csc_enable are not
> being used anywhere else functionally post ICL, we need not set these
> fields in crtc_state.


LGTM
Reviewed-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

> 
> Bspec: 69734
> Signed-off-by: Sai Teja Pottumuttu <sai.teja.pottumuttu@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 13 +++++++------
>   1 file changed, 7 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 51db70d07fae..9102f3eb0bc4 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1090,18 +1090,19 @@ static void skl_get_config(struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	u32 tmp;
>   
>   	crtc_state->gamma_mode = hsw_read_gamma_mode(crtc);
>   	crtc_state->csc_mode = ilk_read_csc_mode(crtc);
>   
> -	tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
> +	if (DISPLAY_VER(display) < 35) {
> +		u32 tmp = intel_de_read(display, SKL_BOTTOM_COLOR(crtc->pipe));
>   
> -	if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
> -		crtc_state->gamma_enable = true;
> +		if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
> +			crtc_state->gamma_enable = true;
>   
> -	if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
> -		crtc_state->csc_enable = true;
> +		if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
> +			crtc_state->csc_enable = true;
> +	}
>   }
>   
>   static void skl_color_commit_arm(struct intel_dsb *dsb,
> 

Re: [PATCH 15/32] drm/i915/xe3p_lpd: Always apply level-0 watermark adjustment

[Gustavo Sousa]

Quoting Ville Syrjälä (2025-10-16 18:03:45-03:00)
>On Wed, Oct 15, 2025 at 12:15:15AM -0300, Gustavo Sousa wrote:
>> When reading memory latencies for watermark calculations, previous
>> display releases instructed to apply an adjustment of adding a certain
>> value (e.g. 6us) to all levels when the level 0's memory latency read
>> from hardware was zero.
>> 
>> For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
>> add that value to the other levels.  Update adjust_wm_latency()
>> accordingly.
>> 
>> Bspec: 68986, 69126
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
>>  1 file changed, 7 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 41f64e347436..88342d07727f 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -3249,6 +3249,13 @@ adjust_wm_latency(struct intel_display *display)
>>  
>>          make_wm_latency_monotonic(display);
>>  
>> +        /*
>> +         * Xe3p asks to ignore wm[0] read from the register and always
>> +         * use the adjustment done with read_latency.
>> +         */
>> +        if (DISPLAY_VER(display) >= 35)
>> +                wm[0] = 0;
>
>make_wm_latency_monotonic() already used wm[0]. I think this
>needs to be the very first thing you do in adjust_wm_latency().

Right.  Or as an alternative, maybe we could have
make_wm_latency_monotonic() be the last thing to be done?

I was thinking about having this as the end result:

    |diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
    |index 237af46c1974..b3f8cbadeb99 100644
    |--- a/drivers/gpu/drm/i915/display/skl_watermark.c
    |+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
    |@@ -3213,39 +3213,44 @@ static void
    | adjust_wm_latency(struct intel_display *display)
    | {
    | 	u16 *wm = display->wm.skl_latency;
    |+	int inc = 0;
    | 
    | 	if (display->platform.dg2)
    | 		multiply_wm_latency(display, 2);
    | 
    | 	sanitize_wm_latency(display);
    | 
    |-	make_wm_latency_monotonic(display);
    |-
    | 	/*
    | 	 * Xe3p asks to ignore wm[0] read from the register and always
    | 	 * use the adjustment done with read_latency.
    | 	 */
    |-	if (DISPLAY_VER(display) >= 35)
    |+	if (DISPLAY_VER(display) >= 35) {
    | 		wm[0] = 0;
    |-
    |-	/*
    |-	 * WaWmMemoryReadLatency
    |-	 *
    |-	 * punit doesn't take into account the read latency so we need
    |-	 * to add proper adjustment to each valid level we retrieve
    |-	 * from the punit when level 0 response data is 0us.
    |-	 */
    |-	if (wm[0] == 0)
    |-		increase_wm_latency(display, wm_read_latency(display));
    |+		inc = wm_read_latency(display);
    |+	} else if (wm[0] == 0) {
    |+		/*
    |+		 * WaWmMemoryReadLatency
    |+		 *
    |+		 * punit doesn't take into account the read latency so we need
    |+		 * to add proper adjustment to each valid level we retrieve
    |+		 * from the punit when level 0 response data is 0us.
    |+		 */
    |+		inc = wm_read_latency(display);
    |+	}
    | 
    | 	/*
    | 	 * WA Level-0 adjustment for 16Gb+ DIMMs: SKL+
    | 	 * If we could not get dimm info enable this WA to prevent from
    | 	 * any underrun. If not able to get DIMM info assume 16Gb+ DIMM
    | 	 * to avoid any underrun.
    | 	 */
    | 	if (need_16gb_dimm_wa(display))
    |-		increase_wm_latency(display, 1);
    |+		inc += 1;
    |+
    |+	if (inc)
    |+		increase_wm_latency(display, inc);
    |+
    |+	make_wm_latency_monotonic(display);
    | }
    | 
    | static void mtl_read_wm_latency(struct intel_display *display)


With that, we:

    * make sure to differentiate between WaWmMemoryReadLatency
      and what now is a "normal" Bspec instruction starting with
      Xe3p_LD.

    * have a single call to increase_wm_latency().

It could be split into 2 patches, if you prefer: first to use a single
call to increase_wm_latency() and then another for Xe3p_LPD (which would
include moving make_wm_latency_monotonic()).

What do you think?

--
Gustavo Sousa

>
>> +
>>          /*
>>           * WaWmMemoryReadLatency
>>           *
>> 
>> -- 
>> 2.51.0
>
>-- 
>Ville Syrjälä
>Intel

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-15 12:24:12-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
>> configuring SoC for TC ports and PHYs.  Update the code to match the
>> updates in VBT.
>>
>> The new field dedicated_external is used to represent TC ports that are
>> connected to PHYs outside of the Type-C subsystem, meaning that they
>> behave like dedicated ports and don't require the extra Type-C
>> programming.  In an upcoming change, we will update the driver to take
>> this field into consideration when detecting the type of port.
>>
>> The new field dyn_port_over_tc is used to inform that the TC port can be
>> dynamically allocated for a legacy connector in the Type-C subsystem,
>> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
>> that field in order to handle the IOM resource management programming
>> required for that.
>>
>> Note that, when dedicated_external is set, the fields dp_usb_type_c and
>> tbt are tagged as "don't care" in the spec, so they should be ignored in
>> that case, so also make sure to update the accessor functions to take
>> that into consideration.
>>
>> Bspec: 20124, 68954, 74304
>> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
>>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
>>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
>>  3 files changed, 27 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 3596dce84c28..e466728ced0f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
>>  {
>>          BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>>  
>> -        if (version > 263)
>> +        if (version > 264)
>>                  return -ENOENT;
>>          else if (version >= 263)
>>                  return 44;
>> @@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
>>  
>>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
>>  {
>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>> +                return false;
>> +
>
>We already have mechanisms for this. Please don't pollute the functions.
>
>dp_usb_type_c should just be set to 0 in a new sanitize_something()
>function at the end of parse_ddi_port()
>
>>          return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
>>  }
>>  
>>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
>>  {
>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>> +                return false;
>> +
>
>Ditto.
>
>tbt should just be set to 0 in a new sanitize_something() function at
>the end of parse_ddi_port()

Aren't sanitize_*() functions, at least in the context of intel_bios.c,
for actually fixing bogus information reported by the VBT?

Arguably, that wouldn't be the case for dedicated_external and the
related fields, since it is actually about a new way to interpret bits
for the new version of the VBT.

One of my concerns with the sanitize approach would be gotchas with
anything that tries to use the fields before they are sanitized (e.g.
another sanitization function gets added in the future that would use
one of the sanitized fields).  Perhaps that's never gonna happen?

--
Gustavo Sousa

>
>>          return devdata->display->vbt.version >= 209 && devdata->child.tbt;
>>  }
>>  
>> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
>> +{
>> +        return devdata->display->vbt.version >= 264 &&
>> +                devdata->child.dedicated_external;
>> +}
>> +
>> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
>> +{
>> +        return devdata->display->vbt.version >= 264 &&
>> +                devdata->child.dyn_port_over_tc;
>> +}
>> +
>>  bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
>>  {
>>          return devdata && devdata->child.lane_reversal;
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
>> index f9e438b2787b..75dff27b4228 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.h
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
>> @@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
>>  bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
>> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
>> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
>> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> index 70e31520c560..f07ab64a8d97 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> @@ -554,7 +554,12 @@ struct child_device_config {
>>          u8 dvo_function;
>>          u8 dp_usb_type_c:1;                                        /* 195+ */
>>          u8 tbt:1;                                                /* 209+ */
>> -        u8 flags2_reserved:2;                                        /* 195+ */
>> +        /*
>> +         * Fields dp_usb_type_c and tbt must be ignored when
>> +         * dedicated_external is set.
>> +         */
>
>We can add that info in the sanitize function. We don't generally add a
>whole lot of explanatory text here, because if we did, the file would be
>10x consisting mostly of VBT quirk explanations.
>
>> +        u8 dedicated_external:1;                                /* 264+ */
>> +        u8 dyn_port_over_tc:1;                                        /* 264+ */
>>          u8 dp_port_trace_length:4;                                /* 209+ */
>>          u8 dp_gpio_index;                                        /* 195+ */
>>          u16 dp_gpio_pin_num;                                        /* 195+ */
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-15 12:29:00-03:00)
>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
>> configuring SoC for TC ports and PHYs.  Update the code to match the
>> updates in VBT.
>>
>> The new field dedicated_external is used to represent TC ports that are
>> connected to PHYs outside of the Type-C subsystem, meaning that they
>> behave like dedicated ports and don't require the extra Type-C
>> programming.  In an upcoming change, we will update the driver to take
>> this field into consideration when detecting the type of port.
>>
>> The new field dyn_port_over_tc is used to inform that the TC port can be
>> dynamically allocated for a legacy connector in the Type-C subsystem,
>> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
>> that field in order to handle the IOM resource management programming
>> required for that.
>
>We probably want to add the info to print_ddi_port().

Yep.  Good idea.

I'm currently looking at print_ddi_port() and the one-liner is already
quite long and I don't know we would be able to come up with a good
abbreviation to put there.

Probably just print on its own line?
E.g.:

	dedicated_external = intel_bios_encoder_is_dedicated_external(devdata);
	if (dedicated_external)
		drm_dbg_kms(display->drm,
			    "Port %c is dedicated external\n");


Do you think printing for dyn_port_over_tc is also useful?

--
Gustavo Sousa

>
>>
>> Note that, when dedicated_external is set, the fields dp_usb_type_c and
>> tbt are tagged as "don't care" in the spec, so they should be ignored in
>> that case, so also make sure to update the accessor functions to take
>> that into consideration.
>>
>> Bspec: 20124, 68954, 74304
>> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
>>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
>>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
>>  3 files changed, 27 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>> index 3596dce84c28..e466728ced0f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>> @@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
>>  {
>>          BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>>  
>> -        if (version > 263)
>> +        if (version > 264)
>>                  return -ENOENT;
>>          else if (version >= 263)
>>                  return 44;
>> @@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
>>  
>>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
>>  {
>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>> +                return false;
>> +
>>          return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
>>  }
>>  
>>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
>>  {
>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>> +                return false;
>> +
>>          return devdata->display->vbt.version >= 209 && devdata->child.tbt;
>>  }
>>  
>> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata)
>> +{
>> +        return devdata->display->vbt.version >= 264 &&
>> +                devdata->child.dedicated_external;
>> +}
>> +
>> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata)
>> +{
>> +        return devdata->display->vbt.version >= 264 &&
>> +                devdata->child.dyn_port_over_tc;
>> +}
>> +
>>  bool intel_bios_encoder_lane_reversal(const struct intel_bios_encoder_data *devdata)
>>  {
>>          return devdata && devdata->child.lane_reversal;
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
>> index f9e438b2787b..75dff27b4228 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.h
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
>> @@ -79,6 +79,8 @@ bool intel_bios_encoder_supports_dp(const struct intel_bios_encoder_data *devdat
>>  bool intel_bios_encoder_supports_edp(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata);
>> +bool intel_bios_encoder_is_dedicated_external(const struct intel_bios_encoder_data *devdata);
>> +bool intel_bios_encoder_supports_dyn_port_over_tc(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_dsi(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_supports_dp_dual_mode(const struct intel_bios_encoder_data *devdata);
>>  bool intel_bios_encoder_is_lspcon(const struct intel_bios_encoder_data *devdata);
>> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> index 70e31520c560..f07ab64a8d97 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> @@ -554,7 +554,12 @@ struct child_device_config {
>>          u8 dvo_function;
>>          u8 dp_usb_type_c:1;                                        /* 195+ */
>>          u8 tbt:1;                                                /* 209+ */
>> -        u8 flags2_reserved:2;                                        /* 195+ */
>> +        /*
>> +         * Fields dp_usb_type_c and tbt must be ignored when
>> +         * dedicated_external is set.
>> +         */
>> +        u8 dedicated_external:1;                                /* 264+ */
>> +        u8 dyn_port_over_tc:1;                                        /* 264+ */
>>          u8 dp_port_trace_length:4;                                /* 209+ */
>>          u8 dp_gpio_index;                                        /* 195+ */
>>          u16 dp_gpio_pin_num;                                        /* 195+ */
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Jani Nikula]

On Fri, 17 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-10-15 12:24:12-03:00)
>>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
>>> configuring SoC for TC ports and PHYs.  Update the code to match the
>>> updates in VBT.
>>>
>>> The new field dedicated_external is used to represent TC ports that are
>>> connected to PHYs outside of the Type-C subsystem, meaning that they
>>> behave like dedicated ports and don't require the extra Type-C
>>> programming.  In an upcoming change, we will update the driver to take
>>> this field into consideration when detecting the type of port.
>>>
>>> The new field dyn_port_over_tc is used to inform that the TC port can be
>>> dynamically allocated for a legacy connector in the Type-C subsystem,
>>> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
>>> that field in order to handle the IOM resource management programming
>>> required for that.
>>>
>>> Note that, when dedicated_external is set, the fields dp_usb_type_c and
>>> tbt are tagged as "don't care" in the spec, so they should be ignored in
>>> that case, so also make sure to update the accessor functions to take
>>> that into consideration.
>>>
>>> Bspec: 20124, 68954, 74304
>>> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>> ---
>>>  drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
>>>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
>>>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
>>>  3 files changed, 27 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>>> index 3596dce84c28..e466728ced0f 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>>> @@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
>>>  {
>>>          BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>>>  
>>> -        if (version > 263)
>>> +        if (version > 264)
>>>                  return -ENOENT;
>>>          else if (version >= 263)
>>>                  return 44;
>>> @@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
>>>  
>>>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
>>>  {
>>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>>> +                return false;
>>> +
>>
>>We already have mechanisms for this. Please don't pollute the functions.
>>
>>dp_usb_type_c should just be set to 0 in a new sanitize_something()
>>function at the end of parse_ddi_port()
>>
>>>          return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
>>>  }
>>>  
>>>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
>>>  {
>>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>>> +                return false;
>>> +
>>
>>Ditto.
>>
>>tbt should just be set to 0 in a new sanitize_something() function at
>>the end of parse_ddi_port()
>
> Aren't sanitize_*() functions, at least in the context of intel_bios.c,
> for actually fixing bogus information reported by the VBT?

Yes.

> Arguably, that wouldn't be the case for dedicated_external and the
> related fields, since it is actually about a new way to interpret bits
> for the new version of the VBT.

Well, if the spec says you shouln't have some bits set in combination
with something else, then having those set is bogus, no?

> One of my concerns with the sanitize approach would be gotchas with
> anything that tries to use the fields before they are sanitized (e.g.
> another sanitization function gets added in the future that would use
> one of the sanitized fields).  Perhaps that's never gonna happen?

The sanitization part should be careful about that, obviously.

BR,
Jani.



-- 
Jani Nikula, Intel

Re: [PATCH 24/32] drm/i915/xe3p_lpd: Introduce pixel normalizer config support

[Govindapillai, Vinod]

On Wed, 2025-10-15 at 18:11 +0300, Jani Nikula wrote:
> On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> > From: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > 
> > To enable FBC for FP16 formats, we need to enable the pixel
> > normalizer
> > block. Introduce the register definitions and the initial steps for
> > configuring the pixel normalizer block. In this patch the pixel
> > normalizer block is kept as disabled. The follow-up patches will
> > handle
> > configuring the pixel normalizer block for hdr planes for FP16
> > formats.
> > 
> > Bspec: 69863
> > Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
> > Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
> > Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_types.h      |  3 +++
> >  drivers/gpu/drm/i915/display/skl_universal_plane.c      | 15
> > +++++++++++++++
> >  drivers/gpu/drm/i915/display/skl_universal_plane_regs.h | 11
> > +++++++++++
> >  3 files changed, 29 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 87b7cec35320..13652e2996a4 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -679,6 +679,9 @@ struct intel_plane_state {
> >  	/* surface address register */
> >  	u32 surf;
> >  
> > +	/* plane pixel normalizer config for Xe3p_LPD+ FBC FP16 */
> > +	u32 pixel_normalizer;
> 
> I'm pretty strongly of the opinion that software state should not be
> just a 1:1 map of the hardware state. Software state is logical,
> hardware state is physical.
> 
> The software state should have logical things like "normalize form
> factor" and "normalize enable", and the hardware then has those in
> some
> register(s) somewhere.
> 
> Please let's not start storing software state as register contents.
> The
> registers and their contents *will* change across platforms.

Thanks for the comments. Got your point.

Well.. in this case we are forced to enable the pixel notmalizer with
factor as 1 because of the FBC hw block requirement. So far we don't
have any separate logic to decide on the normalization factor. We hard
code the normalization factor as 1 for display version >= 35 and FP16
format the plane is FBC capable.

So now I am wondering, if we need to maintain a state variable for that
- just directly program register with normalization factor as 1.0 +
enable for FP16 formats?

if (disp >= 35) {
	if (fp16 format && FBC capable plane)
   		intel_de_write_dsb(factor_1_0 | enable)
	else
		intel_de_write_ds(0)
}

Do you have any suggestion on this?

BR
Vinod

> 
> > +
> >  	/*
> >  	 * scaler_id
> >  	 *    = -1 : not using a scaler
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 9f1111324dab..16a9c141281b 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -893,6 +893,12 @@ static void skl_write_plane_wm(struct
> > intel_dsb *dsb,
> >  				  
> > xe3_plane_min_ddb_reg_val(min_ddb, interim_ddb));
> >  }
> >  
> > +static void
> > +xe3p_lpd_plane_check_pixel_normalizer(struct intel_plane_state
> > *plane_state)
> 
> The function name has nothing to do with what the function does. What
> does "check" mean?
> 
> > +{
> > +	plane_state->pixel_normalizer = 0;
> > +}
> > +
> >  static void
> >  skl_plane_disable_arm(struct intel_dsb *dsb,
> >  		      struct intel_plane *plane,
> > @@ -1671,6 +1677,11 @@ icl_plane_update_arm(struct intel_dsb *dsb,
> >  
> >  	icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state,
> > plane_state);
> >  
> > +	/* Only the HDR planes can have pixel normalizer */
> > +	if (DISPLAY_VER(display) >= 35 &&
> > icl_is_hdr_plane(display, plane_id))
> > +		intel_de_write_dsb(display, dsb,
> > +				   PLANE_PIXEL_NORMALIZE(plane-
> > >pipe, plane->id),
> > +				   plane_state->pixel_normalizer);
> 
> This is the place where you'd look at the software state, and
> construct
> what will be written to hardware based on that.
> 
> >  	/*
> >  	 * The control register self-arms if the plane was
> > previously
> >  	 * disabled. Try to make the plane enable atomic by
> > writing
> > @@ -2385,6 +2396,10 @@ static int skl_plane_check(struct
> > intel_crtc_state *crtc_state,
> >  		plane_state->damage = DRM_RECT_INIT(0, 0, 0, 0);
> >  	}
> >  
> > +	/* Pixel normalizer for Xe3p_LPD+ */
> > +	if (DISPLAY_VER(display) >= 35 &&
> > icl_is_hdr_plane(display, plane->id))
> > +		xe3p_lpd_plane_check_pixel_normalizer(plane_state)
> > ;
> > +
> >  	plane_state->ctl = skl_plane_ctl(plane_state);
> >  
> >  	if (DISPLAY_VER(display) >= 10)
> > diff --git
> > a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > index 84cf565bd653..11c713f9b237 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> > @@ -456,4 +456,15 @@
> >  								_S
> > EL_FETCH_PLANE_OFFSET_5_A, _SEL_FETCH_PLANE_OFFSET_5_B, \
> >  								_S
> > EL_FETCH_PLANE_OFFSET_6_A, _SEL_FETCH_PLANE_OFFSET_6_B)
> >  
> > +#define _PLANE_PIXEL_NORMALIZE_1_A		0x701a8
> > +#define _PLANE_PIXEL_NORMALIZE_2_A		0x702a8
> > +#define _PLANE_PIXEL_NORMALIZE_1_B		0x711a8
> > +#define _PLANE_PIXEL_NORMALIZE_2_B		0x712a8
> > +#define PLANE_PIXEL_NORMALIZE(pipe,
> > plane)	_MMIO_SKL_PLANE((pipe), (plane), \
> > +								_P
> > LANE_PIXEL_NORMALIZE_1_A, _PLANE_PIXEL_NORMALIZE_1_B, \
> > +								_P
> > LANE_PIXEL_NORMALIZE_2_A, _PLANE_PIXEL_NORMALIZE_2_B)
> > +#define  
> > PLANE_PIXEL_NORMALIZE_ENABLE			REG_BIT(31)
> > +#define  
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK	REG_GENMASK(15, 0)
> > +#define  
> > PLANE_PIXEL_NORMALIZE_NORM_FACTOR(val)	REG_FIELD_PREP(PLANE_PIXEL_NORMALIZE_NORM_FACTOR_MASK,(val))
> > +
> >  #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
> 

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Gustavo Sousa]

Quoting Jani Nikula (2025-10-20 04:45:40-03:00)
>On Fri, 17 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>> Quoting Jani Nikula (2025-10-15 12:24:12-03:00)
>>>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>>> VBT version 264 adds new fields associated to Xe3p_LPD's new ways of
>>>> configuring SoC for TC ports and PHYs.  Update the code to match the
>>>> updates in VBT.
>>>>
>>>> The new field dedicated_external is used to represent TC ports that are
>>>> connected to PHYs outside of the Type-C subsystem, meaning that they
>>>> behave like dedicated ports and don't require the extra Type-C
>>>> programming.  In an upcoming change, we will update the driver to take
>>>> this field into consideration when detecting the type of port.
>>>>
>>>> The new field dyn_port_over_tc is used to inform that the TC port can be
>>>> dynamically allocated for a legacy connector in the Type-C subsystem,
>>>> which is a new feature in Xe3p_LPD.  In upcoming changes, we will use
>>>> that field in order to handle the IOM resource management programming
>>>> required for that.
>>>>
>>>> Note that, when dedicated_external is set, the fields dp_usb_type_c and
>>>> tbt are tagged as "don't care" in the spec, so they should be ignored in
>>>> that case, so also make sure to update the accessor functions to take
>>>> that into consideration.
>>>>
>>>> Bspec: 20124, 68954, 74304
>>>> Cc: Shekhar Chauhan <shekhar.chauhan@intel.com>
>>>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>>>> ---
>>>>  drivers/gpu/drm/i915/display/intel_bios.c     | 20 +++++++++++++++++++-
>>>>  drivers/gpu/drm/i915/display/intel_bios.h     |  2 ++
>>>>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |  7 ++++++-
>>>>  3 files changed, 27 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
>>>> index 3596dce84c28..e466728ced0f 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_bios.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
>>>> @@ -2777,7 +2777,7 @@ static int child_device_expected_size(u16 version)
>>>>  {
>>>>          BUILD_BUG_ON(sizeof(struct child_device_config) < 40);
>>>>  
>>>> -        if (version > 263)
>>>> +        if (version > 264)
>>>>                  return -ENOENT;
>>>>          else if (version >= 263)
>>>>                  return 44;
>>>> @@ -3714,14 +3714,32 @@ int intel_bios_hdmi_ddc_pin(const struct intel_bios_encoder_data *devdata)
>>>>  
>>>>  bool intel_bios_encoder_supports_typec_usb(const struct intel_bios_encoder_data *devdata)
>>>>  {
>>>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>>>> +                return false;
>>>> +
>>>
>>>We already have mechanisms for this. Please don't pollute the functions.
>>>
>>>dp_usb_type_c should just be set to 0 in a new sanitize_something()
>>>function at the end of parse_ddi_port()
>>>
>>>>          return devdata->display->vbt.version >= 195 && devdata->child.dp_usb_type_c;
>>>>  }
>>>>  
>>>>  bool intel_bios_encoder_supports_tbt(const struct intel_bios_encoder_data *devdata)
>>>>  {
>>>> +        if (intel_bios_encoder_is_dedicated_external(devdata))
>>>> +                return false;
>>>> +
>>>
>>>Ditto.
>>>
>>>tbt should just be set to 0 in a new sanitize_something() function at
>>>the end of parse_ddi_port()
>>
>> Aren't sanitize_*() functions, at least in the context of intel_bios.c,
>> for actually fixing bogus information reported by the VBT?
>
>Yes.
>
>> Arguably, that wouldn't be the case for dedicated_external and the
>> related fields, since it is actually about a new way to interpret bits
>> for the new version of the VBT.
>
>Well, if the spec says you shouln't have some bits set in combination
>with something else, then having those set is bogus, no?

I wouldn't say so, because those bits are tagged as "don't care" for the
dedicated external case (i.e. with "x"s in the truth table).

I'll go ahead with your suggestion.  Then I'll have
sanitize_dedicated_external() logging when it finds those bits set, but
I'll avoid the use of the term "bogus", if you are okay with that.

--
Gustavo Sousa

>
>> One of my concerns with the sanitize approach would be gotchas with
>> anything that tries to use the fields before they are sanitized (e.g.
>> another sanitization function gets added in the future that would use
>> one of the sanitized fields).  Perhaps that's never gonna happen?
>
>The sanitization part should be careful about that, obviously.
>
>BR,
>Jani.
>
>
>
>-- 
>Jani Nikula, Intel

Re: [PATCH 27/32] drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc

[Jani Nikula]

On Fri, 17 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-10-15 12:29:00-03:00)
>>We probably want to add the info to print_ddi_port().
>
> Yep.  Good idea.
>
> I'm currently looking at print_ddi_port() and the one-liner is already
> quite long and I don't know we would be able to come up with a good
> abbreviation to put there.

Yeah, it is...

>
> Probably just print on its own line?
> E.g.:
>
> 	dedicated_external = intel_bios_encoder_is_dedicated_external(devdata);
> 	if (dedicated_external)
> 		drm_dbg_kms(display->drm,
> 			    "Port %c is dedicated external\n");

Ack.

> Do you think printing for dyn_port_over_tc is also useful?

We'll only know when we're debugging some issue! ;)

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 29/32] drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc()

[Jani Nikula]

On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
> Quoting Jani Nikula (2025-10-15 12:33:31-03:00)
>>On Wed, 15 Oct 2025, Gustavo Sousa <gustavo.sousa@intel.com> wrote:
>>> @@ -1863,6 +1873,13 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder)
>>>  {
>>>          struct intel_display *display = to_intel_display(encoder);
>>>  
>>> +        if (intel_encoder_is_dig_port(encoder)) {
>>> +                struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>>> +
>>> +                if (dig_port->dedicated_external)
>>
>>Why go through all the trouble of duplicating the "decicated external"
>>information in the digital port, when you already have encoder
>>available, and can just use intel_bios_encoder_is_dedicated_external()
>>right here?
>
> I believe the last paragraph of the commit message explains the why.
> Are you suggesting that we handle the lifespan issue right in this
> series instead?
>
> Using intel_bios_encoder_is_dedicated_external() my first approach, but
> then we were hit with an oops because the VBT data was not available
> anymore in the driver unbind path.

Ugh. I think this deserves a comment, perhaps accompanied with a FIXME,
not just a mention in the commit message.

BR,
Jani.


-- 
Jani Nikula, Intel

Re: [PATCH 30/32] drm/i915/wm: don't use method1 in Xe3p_LPD onwards

[Gustavo Sousa]

Quoting Shekhar Chauhan (2025-10-15 05:02:40-03:00)
>
>On 10/15/2025 8:45, Gustavo Sousa wrote:
>> From: Luca Coelho <luciano.coelho@intel.com>
>>
>> Starting from display version 35, we don't need to use method1 to
>
>In the patch title and this description, can we have something which 
>explains what exactly is method1 or method2? Seems too vague.

Hm... The referred Bspec has the descriptions of each method.

--
Gustavo Sousa

>
>-shekhar
>
>> calculate the watermark values anymore, so skip it.
>>
>> Bspec: 68985
>> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
>> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/skl_watermark.c | 2 ++
>>   1 file changed, 2 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
>> index 88342d07727f..fba7448c4920 100644
>> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
>> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
>> @@ -1809,6 +1809,8 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>>   
>>           if (wp->y_tiled) {
>>                   selected_result = max_fixed16(method2, wp->y_tile_minimum);
>> +        } else if (DISPLAY_VER(display) >= 35) {
>> +                selected_result = method2;
>>           } else {
>>                   if ((wp->cpp * crtc_state->hw.pipe_mode.crtc_htotal /
>>                        wp->dbuf_block_size < 1) &&
>>