* [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 02/19] drm/i915: Extract South chicken " Uma Shankar
` (19 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
There are certain register definitions which are defined in i915_reg.h
which are exclusively needed by display. Move the same to display
headers to remove i915_reg.h includes from display. This is a step
towards making display independent of i915.
intel_clock_gating.c can include display header directly, since its
usage is planned to be re-factored and will be moved within display.
v3: Updated subject and commit message (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 10 ++++++++++
drivers/gpu/drm/i915/display/intel_pch_display.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 10 ----------
drivers/gpu/drm/i915/intel_clock_gating.c | 2 +-
4 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9e0d853f4b61..9f8fbfb2e115 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2021,6 +2021,16 @@
#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
+#define _TRANSA_CHICKEN2 0xf0064
+#define _TRANSB_CHICKEN2 0xf1064
+#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
+#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
+#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
+#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
+#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
+#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
+#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
+
#define PCH_DP_B _MMIO(0xe4100)
#define PCH_DP_C _MMIO(0xe4200)
#define PCH_DP_D _MMIO(0xe4300)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index 16619f7be5f8..69c7952a1413 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -6,7 +6,6 @@
#include <drm/drm_print.h>
#include "g4x_dp.h"
-#include "i915_reg.h"
#include "intel_crt.h"
#include "intel_crt_regs.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f928db78a3fa..f65f50bf44ba 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,16 +1023,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-#define _TRANSA_CHICKEN2 0xf0064
-#define _TRANSB_CHICKEN2 0xf1064
-#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
-#define TRANS_CHICKEN2_TIMING_OVERRIDE REG_BIT(31)
-#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED REG_BIT(29)
-#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK REG_GENMASK(28, 27)
-#define TRANS_CHICKEN2_FRAME_START_DELAY(x) REG_FIELD_PREP(TRANS_CHICKEN2_FRAME_START_DELAY_MASK, (x)) /* 0-3 */
-#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER REG_BIT(26)
-#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH REG_BIT(25)
-
#define SOUTH_CHICKEN1 _MMIO(0xc2000)
#define FDIA_PHASE_SYNC_SHIFT_OVR 19
#define FDIA_PHASE_SYNC_SHIFT_EN 18
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 7336934bb934..4e18d5a22112 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -30,7 +30,7 @@
#include "display/i9xx_plane_regs.h"
#include "display/intel_display.h"
#include "display/intel_display_core.h"
-
+#include "display/intel_display_regs.h"
#include "gt/intel_engine_regs.h"
#include "gt/intel_gt.h"
#include "gt/intel_gt_mcr.h"
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 02/19] drm/i915: Extract South chicken registers from i915_reg.h to display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
2026-01-29 21:13 ` [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 03/19] drm/i915: Extract display interrupt definitions Uma Shankar
` (18 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Extract South Chicken registers from i915_reg.h to display header.
This allows intel_pch_refclk.c not to include i915_reg.h
v3: Drop whitespace changes, commit header updated (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 27 +++++++++++++++++++
.../gpu/drm/i915/display/intel_pch_refclk.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 27 -------------------
3 files changed, 27 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 9f8fbfb2e115..db428e10d441 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2864,6 +2864,33 @@ enum skl_power_gate {
#define SFUSE_STRAP_DDIC_DETECTED (1 << 1)
#define SFUSE_STRAP_DDID_DETECTED (1 << 0)
+#define SOUTH_CHICKEN1 _MMIO(0xc2000)
+#define FDIA_PHASE_SYNC_SHIFT_OVR 19
+#define FDIA_PHASE_SYNC_SHIFT_EN 18
+#define INVERT_DDIE_HPD REG_BIT(28)
+#define INVERT_DDID_HPD_MTP REG_BIT(27)
+#define INVERT_TC4_HPD REG_BIT(26)
+#define INVERT_TC3_HPD REG_BIT(25)
+#define INVERT_TC2_HPD REG_BIT(24)
+#define INVERT_TC1_HPD REG_BIT(23)
+#define INVERT_DDID_HPD (1 << 18)
+#define INVERT_DDIC_HPD (1 << 17)
+#define INVERT_DDIB_HPD (1 << 16)
+#define INVERT_DDIA_HPD (1 << 15)
+#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
+#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
+#define FDI_BC_BIFURCATION_SELECT (1 << 12)
+#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
+#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
+#define SBCLK_RUN_REFCLK_DIS (1 << 7)
+#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
+#define SPT_PWM_GRANULARITY (1 << 0)
+#define SOUTH_CHICKEN2 _MMIO(0xc2004)
+#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
+#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
+#define LPT_PWM_GRANULARITY (1 << 5)
+#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
+
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_pch_refclk.c b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
index 9a89bb6dcf65..5f88663ef5e8 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_refclk.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_refclk.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f65f50bf44ba..c2efa50f080d 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1023,33 +1023,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-#define SOUTH_CHICKEN1 _MMIO(0xc2000)
-#define FDIA_PHASE_SYNC_SHIFT_OVR 19
-#define FDIA_PHASE_SYNC_SHIFT_EN 18
-#define INVERT_DDIE_HPD REG_BIT(28)
-#define INVERT_DDID_HPD_MTP REG_BIT(27)
-#define INVERT_TC4_HPD REG_BIT(26)
-#define INVERT_TC3_HPD REG_BIT(25)
-#define INVERT_TC2_HPD REG_BIT(24)
-#define INVERT_TC1_HPD REG_BIT(23)
-#define INVERT_DDID_HPD (1 << 18)
-#define INVERT_DDIC_HPD (1 << 17)
-#define INVERT_DDIB_HPD (1 << 16)
-#define INVERT_DDIA_HPD (1 << 15)
-#define FDI_PHASE_SYNC_OVR(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
-#define FDI_PHASE_SYNC_EN(pipe) (1 << (FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
-#define FDI_BC_BIFURCATION_SELECT (1 << 12)
-#define CHASSIS_CLK_REQ_DURATION_MASK (0xf << 8)
-#define CHASSIS_CLK_REQ_DURATION(x) ((x) << 8)
-#define SBCLK_RUN_REFCLK_DIS (1 << 7)
-#define ICP_SECOND_PPS_IO_SELECT REG_BIT(2)
-#define SPT_PWM_GRANULARITY (1 << 0)
-#define SOUTH_CHICKEN2 _MMIO(0xc2004)
-#define FDI_MPHY_IOSFSB_RESET_STATUS (1 << 13)
-#define FDI_MPHY_IOSFSB_RESET_CTL (1 << 12)
-#define LPT_PWM_GRANULARITY (1 << 5)
-#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
-
#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 03/19] drm/i915: Extract display interrupt definitions
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
2026-01-29 21:13 ` [v3 01/19] drm/i915: Extract display registers from i915_reg.h to display Uma Shankar
2026-01-29 21:13 ` [v3 02/19] drm/i915: Extract South chicken " Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display Uma Shankar
` (17 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Extract DE Interrupt registers from i915_reg.h to display header.
This allows intel_display_rps.c not to include i915_reg.h
v2: Update commit message (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 33 +++++++++++++++++++
.../gpu/drm/i915/display/intel_display_rps.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 33 -------------------
3 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index db428e10d441..d496e0ddd910 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1333,6 +1333,39 @@
GEN8_DE_PORT_IER, \
GEN8_DE_PORT_IIR)
+/* interrupts */
+#define DE_MASTER_IRQ_CONTROL (1 << 31)
+#define DE_SPRITEB_FLIP_DONE (1 << 29)
+#define DE_SPRITEA_FLIP_DONE (1 << 28)
+#define DE_PLANEB_FLIP_DONE (1 << 27)
+#define DE_PLANEA_FLIP_DONE (1 << 26)
+#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
+#define DE_PCU_EVENT (1 << 25)
+#define DE_GTT_FAULT (1 << 24)
+#define DE_POISON (1 << 23)
+#define DE_PERFORM_COUNTER (1 << 22)
+#define DE_PCH_EVENT (1 << 21)
+#define DE_AUX_CHANNEL_A (1 << 20)
+#define DE_DP_A_HOTPLUG (1 << 19)
+#define DE_GSE (1 << 18)
+#define DE_PIPEB_VBLANK (1 << 15)
+#define DE_PIPEB_EVEN_FIELD (1 << 14)
+#define DE_PIPEB_ODD_FIELD (1 << 13)
+#define DE_PIPEB_LINE_COMPARE (1 << 12)
+#define DE_PIPEB_VSYNC (1 << 11)
+#define DE_PIPEB_CRC_DONE (1 << 10)
+#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
+#define DE_PIPEA_VBLANK (1 << 7)
+#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
+#define DE_PIPEA_EVEN_FIELD (1 << 6)
+#define DE_PIPEA_ODD_FIELD (1 << 5)
+#define DE_PIPEA_LINE_COMPARE (1 << 4)
+#define DE_PIPEA_VSYNC (1 << 3)
+#define DE_PIPEA_CRC_DONE (1 << 2)
+#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
+#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
+#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
+
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/display/intel_display_rps.c b/drivers/gpu/drm/i915/display/intel_display_rps.c
index e77811396474..bf00266dae4b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_rps.c
+++ b/drivers/gpu/drm/i915/display/intel_display_rps.c
@@ -8,8 +8,8 @@
#include <drm/drm_crtc.h>
#include <drm/drm_vblank.h>
-#include "i915_reg.h"
#include "intel_display_core.h"
+#include "intel_display_regs.h"
#include "intel_display_irq.h"
#include "intel_display_rps.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c2efa50f080d..3f4203a69bcd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -805,39 +805,6 @@
#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
#define MMIO_TIMEOUT_US(us) ((us) << 0)
-/* interrupts */
-#define DE_MASTER_IRQ_CONTROL (1 << 31)
-#define DE_SPRITEB_FLIP_DONE (1 << 29)
-#define DE_SPRITEA_FLIP_DONE (1 << 28)
-#define DE_PLANEB_FLIP_DONE (1 << 27)
-#define DE_PLANEA_FLIP_DONE (1 << 26)
-#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
-#define DE_PCU_EVENT (1 << 25)
-#define DE_GTT_FAULT (1 << 24)
-#define DE_POISON (1 << 23)
-#define DE_PERFORM_COUNTER (1 << 22)
-#define DE_PCH_EVENT (1 << 21)
-#define DE_AUX_CHANNEL_A (1 << 20)
-#define DE_DP_A_HOTPLUG (1 << 19)
-#define DE_GSE (1 << 18)
-#define DE_PIPEB_VBLANK (1 << 15)
-#define DE_PIPEB_EVEN_FIELD (1 << 14)
-#define DE_PIPEB_ODD_FIELD (1 << 13)
-#define DE_PIPEB_LINE_COMPARE (1 << 12)
-#define DE_PIPEB_VSYNC (1 << 11)
-#define DE_PIPEB_CRC_DONE (1 << 10)
-#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
-#define DE_PIPEA_VBLANK (1 << 7)
-#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8 * (pipe)))
-#define DE_PIPEA_EVEN_FIELD (1 << 6)
-#define DE_PIPEA_ODD_FIELD (1 << 5)
-#define DE_PIPEA_LINE_COMPARE (1 << 4)
-#define DE_PIPEA_VSYNC (1 << 3)
-#define DE_PIPEA_CRC_DONE (1 << 2)
-#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8 * (pipe)))
-#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
-#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
-
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (2 preceding siblings ...)
2026-01-29 21:13 ` [v3 03/19] drm/i915: Extract display interrupt definitions Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
` (16 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move DSPCLK_GATE_D register definition to display header.
This allows intel_gmbus.c not to include i915_reg.h.
v3: Update commit header and message (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 50 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_gmbus.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 50 -------------------
3 files changed, 50 insertions(+), 51 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index d496e0ddd910..f90d52f7e5be 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -160,6 +160,47 @@
#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
+#define DSPCLK_GATE_D _MMIO(0x6200)
+#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
+# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
+# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
+# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
+# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
+# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
+# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
+# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
+# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
+# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
+# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
+# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
+# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
+# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
+# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
+# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
+# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
+# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
+# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
+# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
+# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
+# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
+# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
+# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
+# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
+# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
+# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
+# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
+# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
+# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
+/*
+ * This bit must be set on the 830 to prevent hangs when turning off the
+ * overlay scaler.
+ */
+# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
+# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
+# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
+# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
+# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
+
/* Additional CHV pll/phy registers */
#define DPIO_PHY_STATUS _MMIO(VLV_DISPLAY_BASE + 0x6240)
#define DPLL_PORTD_READY_MASK (0xf)
@@ -2924,6 +2965,15 @@ enum skl_power_gate {
#define LPT_PWM_GRANULARITY (1 << 5)
#define DPLS_EDP_PPS_FIX_DIS (1 << 0)
+#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
+#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
+#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
+#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
+#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
+#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
+#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
+#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
+
/* Gen4+ Timestamp and Pipe Frame time stamp registers */
#define GEN4_TIMESTAMP _MMIO(0x2358)
#define ILK_TIMESTAMP_HI _MMIO(0x70070)
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 2caff677600c..81b6c6991323 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -35,7 +35,6 @@
#include <drm/drm_print.h>
#include <drm/display/drm_hdcp_helper.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_regs.h"
#include "intel_display_types.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 3f4203a69bcd..26e5504dbc67 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -613,47 +613,6 @@
#define DSTATE_GFX_CLOCK_GATING (1 << 1)
#define DSTATE_DOT_CLOCK_GATING (1 << 0)
-#define DSPCLK_GATE_D _MMIO(0x6200)
-#define VLV_DSPCLK_GATE_D _MMIO(VLV_DISPLAY_BASE + 0x6200)
-# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
-# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
-# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
-# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
-# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
-# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
-# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
-# define PNV_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 24) /* pnv */
-# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
-# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
-# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
-# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
-# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
-# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
-# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
-# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
-# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
-# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
-# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
-# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
-# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
-# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
-# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
-# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
-# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
-# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
-# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
-# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
-# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
-/*
- * This bit must be set on the 830 to prevent hangs when turning off the
- * overlay scaler.
- */
-# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
-# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
-# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
-# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
-# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
-
#define RENCLK_GATE_D1 _MMIO(0x6204)
# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
@@ -990,15 +949,6 @@
#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-#define SOUTH_DSPCLK_GATE_D _MMIO(0xc2020)
-#define PCH_GMBUSUNIT_CLOCK_GATE_DISABLE (1 << 31)
-#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1 << 30)
-#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1 << 29)
-#define PCH_DPMGUNIT_CLOCK_GATE_DISABLE (1 << 15)
-#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1 << 14)
-#define CNP_PWM_CGE_GATING_DISABLE (1 << 13)
-#define PCH_LP_PARTITION_LEVEL_DISABLE (1 << 12)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (3 preceding siblings ...)
2026-01-29 21:13 ` [v3 04/19] drm/i915: Extract DSPCLK_GATE_D from i915_reg to display Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:00 ` Jani Nikula
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
` (15 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
There are certain register definitions which are commonly shared
by i915, xe and display. Extract the same to a common header to
avoid duplication.
Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
free from including i915_reg.h.
v2: Make the header granular and per feature (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 101 +------------------
include/drm/intel/intel_pcode.h | 108 +++++++++++++++++++++
3 files changed, 110 insertions(+), 101 deletions(-)
create mode 100644 include/drm/intel/intel_pcode.h
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 9217050a76e0..606256027264 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -27,9 +27,9 @@
#include <drm/drm_fixed.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
#include "hsw_ips.h"
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_cdclk.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 26e5504dbc67..c7361e82a0c6 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -25,6 +25,7 @@
#ifndef _I915_REG_H_
#define _I915_REG_H_
+#include <drm/intel/intel_pcode.h>
#include "i915_reg_defs.h"
#include "display/intel_display_reg_defs.h"
@@ -957,106 +958,6 @@
#define EDRAM_WAYS_IDX(cap) (((cap) >> 5) & 0x7)
#define EDRAM_SETS_IDX(cap) (((cap) >> 8) & 0x3)
-#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
-#define GEN6_PCODE_READY (1 << 31)
-#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
-#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
-#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
-#define GEN6_PCODE_ERROR_MASK 0xFF
-#define GEN6_PCODE_SUCCESS 0x0
-#define GEN6_PCODE_ILLEGAL_CMD 0x1
-#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
-#define GEN6_PCODE_TIMEOUT 0x3
-#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
-#define GEN7_PCODE_TIMEOUT 0x2
-#define GEN7_PCODE_ILLEGAL_DATA 0x3
-#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
-#define GEN11_PCODE_LOCKED 0x6
-#define GEN11_PCODE_REJECTED 0x11
-#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
-#define GEN6_PCODE_WRITE_RC6VIDS 0x4
-#define GEN6_PCODE_READ_RC6VIDS 0x5
-#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
-#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
-#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
-#define GEN9_PCODE_READ_MEM_LATENCY 0x6
-#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
-#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
-#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
-#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
-#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
-#define SKL_PCODE_CDCLK_CONTROL 0x7
-#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
-#define SKL_CDCLK_READY_FOR_CHANGE 0x1
-#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
-#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
-#define GEN6_READ_OC_PARAMS 0xc
-#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
-#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
-#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
-#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
-#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
-#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
-#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
-#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
-#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
-#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
-#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
-#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
-#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
-#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
-#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
- ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
- (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
- (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
-#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
-#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
-#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
-#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
-#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
-#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
-#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
-#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
-#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
-#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
-#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
-#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
-#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
-#define GEN6_PCODE_READ_D_COMP 0x10
-#define GEN6_PCODE_WRITE_D_COMP 0x11
-#define ICL_PCODE_EXIT_TCCOLD 0x12
-#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
-#define DISPLAY_IPS_CONTROL 0x19
-#define TGL_PCODE_TCCOLD 0x26
-#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
-#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
-#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
- /* See also IPS_CTL */
-#define IPS_PCODE_CONTROL (1 << 30)
-#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
-#define GEN9_PCODE_SAGV_CONTROL 0x21
-#define GEN9_SAGV_DISABLE 0x0
-#define GEN9_SAGV_IS_DISABLED 0x1
-#define GEN9_SAGV_ENABLE 0x3
-#define DG1_PCODE_STATUS 0x7E
-#define DG1_UNCORE_GET_INIT_STATUS 0x0
-#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
-#define PCODE_POWER_SETUP 0x7C
-#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
-#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
-#define POWER_SETUP_I1_WATTS REG_BIT(31)
-#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
-#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
-#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
-#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
-#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
-/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
-#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
-#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
-/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
-/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
-#define PCODE_MBOX_DOMAIN_NONE 0x0
-#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
#define GEN6_PCODE_DATA _MMIO(0x138128)
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
new file mode 100644
index 000000000000..8e9a574c87d9
--- /dev/null
+++ b/include/drm/intel/intel_pcode.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_COMMON_REG_H_
+#define _INTEL_GMD_COMMON_REG_H_
+
+#define GEN6_PCODE_MAILBOX _MMIO(0x138124)
+#define GEN6_PCODE_READY (1 << 31)
+#define GEN6_PCODE_MB_PARAM2 REG_GENMASK(23, 16)
+#define GEN6_PCODE_MB_PARAM1 REG_GENMASK(15, 8)
+#define GEN6_PCODE_MB_COMMAND REG_GENMASK(7, 0)
+#define GEN6_PCODE_ERROR_MASK 0xFF
+#define GEN6_PCODE_SUCCESS 0x0
+#define GEN6_PCODE_ILLEGAL_CMD 0x1
+#define GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x2
+#define GEN6_PCODE_TIMEOUT 0x3
+#define GEN6_PCODE_UNIMPLEMENTED_CMD 0xFF
+#define GEN7_PCODE_TIMEOUT 0x2
+#define GEN7_PCODE_ILLEGAL_DATA 0x3
+#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
+#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
+#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
+#define GEN6_PCODE_WRITE_RC6VIDS 0x4
+#define GEN6_PCODE_READ_RC6VIDS 0x5
+#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
+#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
+#define BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ 0x18
+#define GEN9_PCODE_READ_MEM_LATENCY 0x6
+#define GEN9_MEM_LATENCY_LEVEL_3_7_MASK REG_GENMASK(31, 24)
+#define GEN9_MEM_LATENCY_LEVEL_2_6_MASK REG_GENMASK(23, 16)
+#define GEN9_MEM_LATENCY_LEVEL_1_5_MASK REG_GENMASK(15, 8)
+#define GEN9_MEM_LATENCY_LEVEL_0_4_MASK REG_GENMASK(7, 0)
+#define SKL_PCODE_LOAD_HDCP_KEYS 0x5
+#define SKL_PCODE_CDCLK_CONTROL 0x7
+#define SKL_CDCLK_PREPARE_FOR_CHANGE 0x3
+#define SKL_CDCLK_READY_FOR_CHANGE 0x1
+#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
+#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
+#define GEN6_READ_OC_PARAMS 0xc
+#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
+#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
+#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ADL_PCODE_MEM_SS_READ_PSF_GV_INFO ((0) | (0x2 << 8))
+#define DISPLAY_TO_PCODE_CDCLK_MAX 0x28D
+#define DISPLAY_TO_PCODE_VOLTAGE_MASK REG_GENMASK(1, 0)
+#define DISPLAY_TO_PCODE_VOLTAGE_MAX DISPLAY_TO_PCODE_VOLTAGE_MASK
+#define DISPLAY_TO_PCODE_CDCLK_VALID REG_BIT(27)
+#define DISPLAY_TO_PCODE_PIPE_COUNT_VALID REG_BIT(31)
+#define DISPLAY_TO_PCODE_CDCLK_MASK REG_GENMASK(25, 16)
+#define DISPLAY_TO_PCODE_PIPE_COUNT_MASK REG_GENMASK(30, 28)
+#define DISPLAY_TO_PCODE_CDCLK(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_CDCLK_MASK, (x))
+#define DISPLAY_TO_PCODE_PIPE_COUNT(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_PIPE_COUNT_MASK, (x))
+#define DISPLAY_TO_PCODE_VOLTAGE(x) REG_FIELD_PREP(DISPLAY_TO_PCODE_VOLTAGE_MASK, (x))
+#define DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, num_pipes, voltage_level) \
+ ((DISPLAY_TO_PCODE_CDCLK(cdclk)) | \
+ (DISPLAY_TO_PCODE_PIPE_COUNT(num_pipes)) | \
+ (DISPLAY_TO_PCODE_VOLTAGE(voltage_level)))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
+#define ICL_PCODE_REP_QGV_MASK REG_GENMASK(1, 0)
+#define ICL_PCODE_REP_QGV_SAFE REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 0)
+#define ICL_PCODE_REP_QGV_POLL REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 1)
+#define ICL_PCODE_REP_QGV_REJECTED REG_FIELD_PREP(ICL_PCODE_REP_QGV_MASK, 2)
+#define ADLS_PCODE_REP_PSF_MASK REG_GENMASK(3, 2)
+#define ADLS_PCODE_REP_PSF_SAFE REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 0)
+#define ADLS_PCODE_REP_PSF_POLL REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 1)
+#define ADLS_PCODE_REP_PSF_REJECTED REG_FIELD_PREP(ADLS_PCODE_REP_PSF_MASK, 2)
+#define ICL_PCODE_REQ_QGV_PT_MASK REG_GENMASK(7, 0)
+#define ICL_PCODE_REQ_QGV_PT(x) REG_FIELD_PREP(ICL_PCODE_REQ_QGV_PT_MASK, (x))
+#define ADLS_PCODE_REQ_PSF_PT_MASK REG_GENMASK(10, 8)
+#define ADLS_PCODE_REQ_PSF_PT(x) REG_FIELD_PREP(ADLS_PCODE_REQ_PSF_PT_MASK, (x))
+#define GEN6_PCODE_READ_D_COMP 0x10
+#define GEN6_PCODE_WRITE_D_COMP 0x11
+#define ICL_PCODE_EXIT_TCCOLD 0x12
+#define HSW_PCODE_DE_WRITE_FREQ_REQ 0x17
+#define DISPLAY_IPS_CONTROL 0x19
+#define TGL_PCODE_TCCOLD 0x26
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED REG_BIT(0)
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ 0
+#define TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ REG_BIT(0)
+/* See also IPS_CTL */
+#define IPS_PCODE_CONTROL (1 << 30)
+#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
+#define GEN9_PCODE_SAGV_CONTROL 0x21
+#define GEN9_SAGV_DISABLE 0x0
+#define GEN9_SAGV_IS_DISABLED 0x1
+#define GEN9_SAGV_ENABLE 0x3
+#define DG1_PCODE_STATUS 0x7E
+#define DG1_UNCORE_GET_INIT_STATUS 0x0
+#define DG1_UNCORE_INIT_STATUS_COMPLETE 0x1
+#define PCODE_POWER_SETUP 0x7C
+#define POWER_SETUP_SUBCOMMAND_READ_I1 0x4
+#define POWER_SETUP_SUBCOMMAND_WRITE_I1 0x5
+#define POWER_SETUP_I1_WATTS REG_BIT(31)
+#define POWER_SETUP_I1_SHIFT 6 /* 10.6 fixed point format */
+#define POWER_SETUP_I1_DATA_MASK REG_GENMASK(15, 0)
+#define POWER_SETUP_SUBCOMMAND_G8_ENABLE 0x6
+#define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US 0x23
+#define XEHP_PCODE_FREQUENCY_CONFIG 0x6e /* pvc */
+/* XEHP_PCODE_FREQUENCY_CONFIG sub-commands (param1) */
+#define PCODE_MBOX_FC_SC_READ_FUSED_P0 0x0
+#define PCODE_MBOX_FC_SC_READ_FUSED_PN 0x1
+/* PCODE_MBOX_DOMAIN_* - mailbox domain IDs */
+/* XEHP_PCODE_FREQUENCY_CONFIG param2 */
+#define PCODE_MBOX_DOMAIN_NONE 0x0
+#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
+
+#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
@ 2026-02-03 12:00 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:00 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> There are certain register definitions which are commonly shared
> by i915, xe and display. Extract the same to a common header to
> avoid duplication.
>
> Move GEN6_PCODE_MAILBOX to common pcode header to make intel_cdclk.c
> free from including i915_reg.h.
>
> v2: Make the header granular and per feature (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cdclk.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 101 +------------------
> include/drm/intel/intel_pcode.h | 108 +++++++++++++++++++++
> 3 files changed, 110 insertions(+), 101 deletions(-)
> create mode 100644 include/drm/intel/intel_pcode.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 9217050a76e0..606256027264 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -27,9 +27,9 @@
>
> #include <drm/drm_fixed.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> #include "hsw_ips.h"
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_audio.h"
> #include "intel_cdclk.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 26e5504dbc67..c7361e82a0c6 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -25,6 +25,7 @@
> #ifndef _I915_REG_H_
> #define _I915_REG_H_
>
> +#include <drm/intel/intel_pcode.h>
I was thinking it would be better to include this only where needed, not
from i915_reg.h. It also improves granularity.
> diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
> new file mode 100644
> index 000000000000..8e9a574c87d9
> --- /dev/null
> +++ b/include/drm/intel/intel_pcode.h
Maybe call it intel_pcode_regs.h to emphasize it's only about registers?
> @@ -0,0 +1,108 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_COMMON_REG_H_
> +#define _INTEL_GMD_COMMON_REG_H_
Please adjust this too.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (4 preceding siblings ...)
2026-01-29 21:13 ` [v3 05/19] drm/{i915, xe}: Extract pcode definitions to common header Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:06 ` Jani Nikula
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
` (14 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header,
this helps intel_display_device.c free from i915_reg.h dependency.
v2: Move GMD_ID_DISPLAY to display header instead of common (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++----
drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ----
3 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 471f236c9ddf..d449528bfc7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -10,7 +10,6 @@
#include <drm/drm_print.h>
#include <drm/intel/pciids.h>
-#include "i915_reg.h"
#include "intel_cx0_phy_regs.h"
#include "intel_de.h"
#include "intel_display.h"
@@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
return NULL;
}
- gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
- gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
- gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
+ gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val);
+ gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val);
+ gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val);
for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
if (gmd_id.ver == gmdid_display_map[i].ver &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index f90d52f7e5be..0d7788db4a7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -6,6 +6,9 @@
#include "intel_display_reg_defs.h"
+#define GU_CNTL_PROTECTED _MMIO(0x10100C)
+#define DEPRESENT REG_BIT(9)
+
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
@@ -1626,6 +1629,11 @@
#define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
#define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
+#define GMD_ID_DISPLAY _MMIO(0x510a0)
+#define GMD_ID_DISPLAY_ARCH_MASK REG_GENMASK(31, 22)
+#define GMD_ID_DISPLAY_RELEASE_MASK REG_GENMASK(21, 14)
+#define GMD_ID_DISPLAY_STEP REG_GENMASK(5, 0)
+
#define XE2LPD_DE_CAP _MMIO(0x41100)
#define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
#define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index c7361e82a0c6..4341308c3b2b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -117,9 +117,6 @@
* #define GEN8_BAR _MMIO(0xb888)
*/
-#define GU_CNTL_PROTECTED _MMIO(0x10100C)
-#define DEPRESENT REG_BIT(9)
-
#define GU_CNTL _MMIO(0x101010)
#define LMEM_INIT REG_BIT(7)
#define DRIVERFLR REG_BIT(31)
@@ -926,7 +923,6 @@
#define MASK_WAKEMEM REG_BIT(13)
#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
-#define GMD_ID_DISPLAY _MMIO(0x510a0)
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
@ 2026-02-03 12:06 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:06 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GU_CNTL_PROTECTED and GMD_ID_DISPLAY to common header,
> this helps intel_display_device.c free from i915_reg.h dependency.
>
> v2: Move GMD_ID_DISPLAY to display header instead of common (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_device.c | 7 +++----
> drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ----
> 3 files changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
> index 471f236c9ddf..d449528bfc7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.c
> @@ -10,7 +10,6 @@
> #include <drm/drm_print.h>
> #include <drm/intel/pciids.h>
>
> -#include "i915_reg.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_de.h"
> #include "intel_display.h"
> @@ -1539,9 +1538,9 @@ probe_gmdid_display(struct intel_display *display, struct intel_display_ip_ver *
> return NULL;
> }
>
> - gmd_id.ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
> - gmd_id.rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
> - gmd_id.step = REG_FIELD_GET(GMD_ID_STEP, val);
> + gmd_id.ver = REG_FIELD_GET(GMD_ID_DISPLAY_ARCH_MASK, val);
> + gmd_id.rel = REG_FIELD_GET(GMD_ID_DISPLAY_RELEASE_MASK, val);
> + gmd_id.step = REG_FIELD_GET(GMD_ID_DISPLAY_STEP, val);
>
> for (i = 0; i < ARRAY_SIZE(gmdid_display_map); i++) {
> if (gmd_id.ver == gmdid_display_map[i].ver &&
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index f90d52f7e5be..0d7788db4a7f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -6,6 +6,9 @@
>
> #include "intel_display_reg_defs.h"
>
> +#define GU_CNTL_PROTECTED _MMIO(0x10100C)
> +#define DEPRESENT REG_BIT(9)
> +
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> @@ -1626,6 +1629,11 @@
> #define GLK_DFSM_DISPLAY_DSC_DISABLE (1 << 7)
> #define XE2LPD_DFSM_DBUF_OVERLAP_DISABLE (1 << 3)
>
> +#define GMD_ID_DISPLAY _MMIO(0x510a0)
> +#define GMD_ID_DISPLAY_ARCH_MASK REG_GENMASK(31, 22)
> +#define GMD_ID_DISPLAY_RELEASE_MASK REG_GENMASK(21, 14)
> +#define GMD_ID_DISPLAY_STEP REG_GENMASK(5, 0)
> +
> #define XE2LPD_DE_CAP _MMIO(0x41100)
> #define XE2LPD_DE_CAP_3DLUT_MASK REG_GENMASK(31, 30)
> #define XE2LPD_DE_CAP_DSC_MASK REG_GENMASK(29, 28)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c7361e82a0c6..4341308c3b2b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -117,9 +117,6 @@
> * #define GEN8_BAR _MMIO(0xb888)
> */
>
> -#define GU_CNTL_PROTECTED _MMIO(0x10100C)
> -#define DEPRESENT REG_BIT(9)
> -
> #define GU_CNTL _MMIO(0x101010)
> #define LMEM_INIT REG_BIT(7)
> #define DRIVERFLR REG_BIT(31)
> @@ -926,7 +923,6 @@
> #define MASK_WAKEMEM REG_BIT(13)
> #define DDI_CLOCK_REG_ACCESS REG_BIT(7)
>
> -#define GMD_ID_DISPLAY _MMIO(0x510a0)
> #define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
> #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> #define GMD_ID_STEP REG_GENMASK(5, 0)
I guess these could now go next to
#define GMD_ID_GRAPHICS _MMIO(0xd8c)
#define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c)
in gt/intel_gt_regs.h, but can be a follow-up too.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (5 preceding siblings ...)
2026-01-29 21:13 ` [v3 06/19] drm/i915: Remove i915_reg.h from intel_display_device.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 11:50 ` Jani Nikula
2026-01-29 21:13 ` [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c Uma Shankar
` (13 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make intel_dram.c free from including i915_reg.h.
v2: Move mem config register to newly added pcode header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_dram.c | 2 +-
drivers/gpu/drm/i915/i915_reg.h | 6 ------
include/drm/intel/intel_pcode.h | 6 ++++++
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
index 3b9879714ea9..3366e18f594e 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -7,8 +7,8 @@
#include <drm/drm_managed.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_display_core.h"
#include "intel_display_utils.h"
#include "intel_dram.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4341308c3b2b..bc466d8c8c60 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1010,12 +1010,6 @@
#define OROM_OFFSET _MMIO(0x1020c0)
#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
-#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
-#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
-#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
-#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
-#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
-
#define MTL_MEDIA_GSI_BASE 0x380000
#endif /* _I915_REG_H_ */
diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
index 8e9a574c87d9..f6f894ba9b20 100644
--- a/include/drm/intel/intel_pcode.h
+++ b/include/drm/intel/intel_pcode.h
@@ -105,4 +105,10 @@
#define PCODE_MBOX_DOMAIN_NONE 0x0
#define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
+#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
+#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
+#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
+#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
+#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
+
#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
@ 2026-02-03 11:50 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 11:50 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_dram.c free from including i915_reg.h.
>
> v2: Move mem config register to newly added pcode header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dram.c | 2 +-
> drivers/gpu/drm/i915/i915_reg.h | 6 ------
> include/drm/intel/intel_pcode.h | 6 ++++++
> 3 files changed, 7 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dram.c b/drivers/gpu/drm/i915/display/intel_dram.c
> index 3b9879714ea9..3366e18f594e 100644
> --- a/drivers/gpu/drm/i915/display/intel_dram.c
> +++ b/drivers/gpu/drm/i915/display/intel_dram.c
> @@ -7,8 +7,8 @@
>
> #include <drm/drm_managed.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_display_core.h"
> #include "intel_display_utils.h"
> #include "intel_dram.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4341308c3b2b..bc466d8c8c60 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1010,12 +1010,6 @@
> #define OROM_OFFSET _MMIO(0x1020c0)
> #define OROM_OFFSET_MASK REG_GENMASK(20, 16)
>
> -#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> -#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
> -#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
> -#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> -#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
> -
> #define MTL_MEDIA_GSI_BASE 0x380000
>
> #endif /* _I915_REG_H_ */
> diff --git a/include/drm/intel/intel_pcode.h b/include/drm/intel/intel_pcode.h
> index 8e9a574c87d9..f6f894ba9b20 100644
> --- a/include/drm/intel/intel_pcode.h
> +++ b/include/drm/intel/intel_pcode.h
> @@ -105,4 +105,10 @@
> #define PCODE_MBOX_DOMAIN_NONE 0x0
> #define PCODE_MBOX_DOMAIN_MEDIAFF 0x3
>
> +#define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700)
> +#define XE3P_ECC_IMPACTING_DE REG_BIT(12)
> +#define MTL_N_OF_ENABLED_QGV_POINTS_MASK REG_GENMASK(11, 8)
> +#define MTL_N_OF_POPULATED_CH_MASK REG_GENMASK(7, 4)
> +#define MTL_DDR_TYPE_MASK REG_GENMASK(3, 0)
This isn't related to pcode, and this is only used in display. Why here?
BR,
Jani.
> +
> #endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (6 preceding siblings ...)
2026-01-29 21:13 ` [v3 07/19] drm/i915: Remove i915_reg.h from intel_dram.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
` (12 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move CHICKEN_PIPESL_1 register definition to display header.
This allows intel_display.c free of i915_reg.h include.
v3: Fix commit header (Jani)
v2: Drop common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 1 -
.../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 22 ------------------
3 files changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7491e00e3858..b7d4ac7e5ff9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -50,7 +50,6 @@
#include "g4x_hdmi.h"
#include "hsw_ips.h"
#include "i915_config.h"
-#include "i915_reg.h"
#include "i9xx_plane.h"
#include "i9xx_plane_regs.h"
#include "i9xx_wm.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 0d7788db4a7f..706024c2a463 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1543,6 +1543,29 @@
#define CHICKEN_FBC_STRIDE_MASK REG_GENMASK(12, 0)
#define CHICKEN_FBC_STRIDE(x) REG_FIELD_PREP(CHICKEN_FBC_STRIDE_MASK, (x))
+#define _CHICKEN_PIPESL_1_A 0x420b0
+#define _CHICKEN_PIPESL_1_B 0x420b4
+#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
+#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
+#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
+#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
+#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
+#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
+#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
+#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
+#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
+#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
+#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
+#define HSW_FBCQ_DIS REG_BIT(22)
+#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
+#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
+#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
+#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
+#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
+#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
+#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
+#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
+
#define _CHICKEN_TRANS_A 0x420c0
#define _CHICKEN_TRANS_B 0x420c4
#define _CHICKEN_TRANS_C 0x420c8
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bc466d8c8c60..10928e8406dc 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -879,28 +879,6 @@
#define CHICKEN_PAR2_1 _MMIO(0x42090)
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-#define _CHICKEN_PIPESL_1_A 0x420b0
-#define _CHICKEN_PIPESL_1_B 0x420b4
-#define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
-#define HSW_PRI_STRETCH_MAX_MASK REG_GENMASK(28, 27)
-#define HSW_PRI_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 0)
-#define HSW_PRI_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 1)
-#define HSW_PRI_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 2)
-#define HSW_PRI_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_PRI_STRETCH_MAX_MASK, 3)
-#define HSW_SPR_STRETCH_MAX_MASK REG_GENMASK(26, 25)
-#define HSW_SPR_STRETCH_MAX_X8 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 0)
-#define HSW_SPR_STRETCH_MAX_X4 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 1)
-#define HSW_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 2)
-#define HSW_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(HSW_SPR_STRETCH_MAX_MASK, 3)
-#define HSW_FBCQ_DIS REG_BIT(22)
-#define HSW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(15) /* hsw */
-#define SKL_PSR_MASK_PLANE_FLIP REG_BIT(11) /* skl+ */
-#define SKL_PLANE1_STRETCH_MAX_MASK REG_GENMASK(1, 0)
-#define SKL_PLANE1_STRETCH_MAX_X8 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 0)
-#define SKL_PLANE1_STRETCH_MAX_X4 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 1)
-#define SKL_PLANE1_STRETCH_MAX_X2 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 2)
-#define SKL_PLANE1_STRETCH_MAX_X1 REG_FIELD_PREP(SKL_PLANE1_STRETCH_MAX_MASK, 3)
-#define BDW_UNMASK_VBL_TO_REGS_IN_SRD REG_BIT(0) /* bdw */
#define DISP_ARB_CTL _MMIO(0x45000)
#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (7 preceding siblings ...)
2026-01-29 21:13 ` [v3 08/19] drm/i915: Remove i915_reg.h from intel_display.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:39 ` Jani Nikula
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
` (11 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GEN2_ISR and some interrupt definitions to common header.
This removes dependency of i915_reg.h from intel_overlay.c.
v2: Create a separate file for common interrupts (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 +
.../gpu/drm/i915/display/intel_display_regs.h | 2 +
drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
.../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
drivers/gpu/drm/i915/i915_irq.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 37 ----------------
include/drm/intel/intel_gmd_interrupt.h | 43 +++++++++++++++++++
8 files changed, 50 insertions(+), 38 deletions(-)
create mode 100644 include/drm/intel/intel_gmd_interrupt.h
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 0a71840041de..31c78dc3d63b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -5,6 +5,7 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "i915_reg.h"
#include "icl_dsi_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 706024c2a463..40538910cb09 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -94,6 +94,8 @@
#define VLV_ERROR_PAGE_TABLE (1 << 4)
#define VLV_ERROR_CLAIM (1 << 0)
+#define GEN2_ISR _MMIO(0x20ac)
+
#define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
#define _MBUS_ABOX0_CTL 0x45038
diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 88eb7ae5765c..3a45836b8373 100644
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -28,6 +28,7 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_object_frontbuffer.h"
@@ -37,7 +38,6 @@
#include "gt/intel_ring.h"
#include "i915_drv.h"
-#include "i915_reg.h"
#include "intel_color_regs.h"
#include "intel_de.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index ac527d878820..998dea65fcff 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -5,6 +5,7 @@
#include <drm/drm_managed.h>
#include <drm/intel/intel-gtt.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gem/i915_gem_internal.h"
#include "gem/i915_gem_lmem.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 8314a4b0505e..7391c9b2ceb5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -4,6 +4,7 @@
*/
#include <drm/drm_cache.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gem/i915_gem_internal.h"
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 3fe978d4ea53..2acdd739335f 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -34,6 +34,7 @@
#include <drm/drm_drv.h>
#include <drm/drm_print.h>
#include <drm/intel/display_parent_interface.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/intel_display_irq.h"
#include "display/intel_hotplug.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 10928e8406dc..22b68ddfa7b4 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -365,7 +365,6 @@
#define GEN2_IER _MMIO(0x20a0)
#define GEN2_IIR _MMIO(0x20a4)
#define GEN2_IMR _MMIO(0x20a8)
-#define GEN2_ISR _MMIO(0x20ac)
#define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
GEN2_IER, \
@@ -522,42 +521,6 @@
/* These are all the "old" interrupts */
#define ILK_BSD_USER_INTERRUPT (1 << 5)
-#define I915_PM_INTERRUPT (1 << 31)
-#define I915_ISP_INTERRUPT (1 << 22)
-#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
-#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
-#define I915_MIPIC_INTERRUPT (1 << 19)
-#define I915_MIPIA_INTERRUPT (1 << 18)
-#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
-#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
-#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
-#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
-#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
-#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
-#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
-#define I915_HWB_OOM_INTERRUPT (1 << 13)
-#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
-#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
-#define I915_MISC_INTERRUPT (1 << 11)
-#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
-#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
-#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
-#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
-#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
-#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
-#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
-#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
-#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
-#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
-#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
-#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
-#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
-#define I915_DEBUG_INTERRUPT (1 << 2)
-#define I915_WINVALID_INTERRUPT (1 << 1)
-#define I915_USER_INTERRUPT (1 << 1)
-#define I915_ASLE_INTERRUPT (1 << 0)
-#define I915_BSD_USER_INTERRUPT (1 << 25)
-
#define GEN6_BSD_RNCID _MMIO(0x12198)
#define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
diff --git a/include/drm/intel/intel_gmd_interrupt.h b/include/drm/intel/intel_gmd_interrupt.h
new file mode 100644
index 000000000000..eae0acade16a
--- /dev/null
+++ b/include/drm/intel/intel_gmd_interrupt.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_INTERRUPT_H_
+#define _INTEL_GMD_INTERRUPT_H_
+
+#define I915_PM_INTERRUPT (1 << 31)
+#define I915_ISP_INTERRUPT (1 << 22)
+#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
+#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
+#define I915_MIPIC_INTERRUPT (1 << 19)
+#define I915_MIPIA_INTERRUPT (1 << 18)
+#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
+#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
+#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
+#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
+#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
+#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
+#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
+#define I915_HWB_OOM_INTERRUPT (1 << 13)
+#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
+#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
+#define I915_MISC_INTERRUPT (1 << 11)
+#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
+#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
+#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
+#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
+#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
+#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
+#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
+#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
+#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
+#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
+#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
+#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
+#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
+#define I915_DEBUG_INTERRUPT (1 << 2)
+#define I915_WINVALID_INTERRUPT (1 << 1)
+#define I915_USER_INTERRUPT (1 << 1)
+#define I915_ASLE_INTERRUPT (1 << 0)
+#define I915_BSD_USER_INTERRUPT (1 << 25)
+
+#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
@ 2026-02-03 12:39 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:39 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN2_ISR and some interrupt definitions to common header.
> This removes dependency of i915_reg.h from intel_overlay.c.
>
> v2: Create a separate file for common interrupts (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_irq.c | 1 +
> .../gpu/drm/i915/display/intel_display_regs.h | 2 +
> drivers/gpu/drm/i915/display/intel_overlay.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
> .../gpu/drm/i915/gt/intel_ring_submission.c | 1 +
> drivers/gpu/drm/i915/i915_irq.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 37 ----------------
> include/drm/intel/intel_gmd_interrupt.h | 43 +++++++++++++++++++
> 8 files changed, 50 insertions(+), 38 deletions(-)
> create mode 100644 include/drm/intel/intel_gmd_interrupt.h
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index 0a71840041de..31c78dc3d63b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -5,6 +5,7 @@
>
> #include <drm/drm_print.h>
> #include <drm/drm_vblank.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "i915_reg.h"
> #include "icl_dsi_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 706024c2a463..40538910cb09 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -94,6 +94,8 @@
> #define VLV_ERROR_PAGE_TABLE (1 << 4)
> #define VLV_ERROR_CLAIM (1 << 0)
>
> +#define GEN2_ISR _MMIO(0x20ac)
> +
> #define VLV_ERROR_REGS I915_ERROR_REGS(VLV_EMR, VLV_EIR)
>
> #define _MBUS_ABOX0_CTL 0x45038
> diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
> index 88eb7ae5765c..3a45836b8373 100644
> --- a/drivers/gpu/drm/i915/display/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/display/intel_overlay.c
> @@ -28,6 +28,7 @@
>
> #include <drm/drm_fourcc.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_object_frontbuffer.h"
> @@ -37,7 +38,6 @@
> #include "gt/intel_ring.h"
>
> #include "i915_drv.h"
> -#include "i915_reg.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index ac527d878820..998dea65fcff 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -5,6 +5,7 @@
>
> #include <drm/drm_managed.h>
> #include <drm/intel/intel-gtt.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "gem/i915_gem_internal.h"
> #include "gem/i915_gem_lmem.h"
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 8314a4b0505e..7391c9b2ceb5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -4,6 +4,7 @@
> */
>
> #include <drm/drm_cache.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "gem/i915_gem_internal.h"
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index 3fe978d4ea53..2acdd739335f 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -34,6 +34,7 @@
> #include <drm/drm_drv.h>
> #include <drm/drm_print.h>
> #include <drm/intel/display_parent_interface.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
>
> #include "display/intel_display_irq.h"
> #include "display/intel_hotplug.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 10928e8406dc..22b68ddfa7b4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -365,7 +365,6 @@
> #define GEN2_IER _MMIO(0x20a0)
> #define GEN2_IIR _MMIO(0x20a4)
> #define GEN2_IMR _MMIO(0x20a8)
> -#define GEN2_ISR _MMIO(0x20ac)
>
> #define GEN2_IRQ_REGS I915_IRQ_REGS(GEN2_IMR, \
> GEN2_IER, \
> @@ -522,42 +521,6 @@
> /* These are all the "old" interrupts */
> #define ILK_BSD_USER_INTERRUPT (1 << 5)
>
> -#define I915_PM_INTERRUPT (1 << 31)
> -#define I915_ISP_INTERRUPT (1 << 22)
> -#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
> -#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
> -#define I915_MIPIC_INTERRUPT (1 << 19)
> -#define I915_MIPIA_INTERRUPT (1 << 18)
> -#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
> -#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
> -#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
> -#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
> -#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
> -#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
> -#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
> -#define I915_HWB_OOM_INTERRUPT (1 << 13)
> -#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
> -#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
> -#define I915_MISC_INTERRUPT (1 << 11)
> -#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
> -#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
> -#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
> -#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
> -#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
> -#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
> -#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
> -#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
> -#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
> -#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
> -#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
> -#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
> -#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
> -#define I915_DEBUG_INTERRUPT (1 << 2)
> -#define I915_WINVALID_INTERRUPT (1 << 1)
> -#define I915_USER_INTERRUPT (1 << 1)
> -#define I915_ASLE_INTERRUPT (1 << 0)
> -#define I915_BSD_USER_INTERRUPT (1 << 25)
> -
> #define GEN6_BSD_RNCID _MMIO(0x12198)
>
> #define GEN7_FF_THREAD_MODE _MMIO(0x20a0)
> diff --git a/include/drm/intel/intel_gmd_interrupt.h b/include/drm/intel/intel_gmd_interrupt.h
> new file mode 100644
> index 000000000000..eae0acade16a
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_interrupt.h
Here too I think I'd name this *_regs.h.
Other than that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> @@ -0,0 +1,43 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_INTERRUPT_H_
> +#define _INTEL_GMD_INTERRUPT_H_
> +
> +#define I915_PM_INTERRUPT (1 << 31)
> +#define I915_ISP_INTERRUPT (1 << 22)
> +#define I915_LPE_PIPE_B_INTERRUPT (1 << 21)
> +#define I915_LPE_PIPE_A_INTERRUPT (1 << 20)
> +#define I915_MIPIC_INTERRUPT (1 << 19)
> +#define I915_MIPIA_INTERRUPT (1 << 18)
> +#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 18)
> +#define I915_DISPLAY_PORT_INTERRUPT (1 << 17)
> +#define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1 << 16)
> +#define I915_MASTER_ERROR_INTERRUPT (1 << 15)
> +#define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1 << 14)
> +#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1 << 14) /* p-state */
> +#define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1 << 13)
> +#define I915_HWB_OOM_INTERRUPT (1 << 13)
> +#define I915_LPE_PIPE_C_INTERRUPT (1 << 12)
> +#define I915_SYNC_STATUS_INTERRUPT (1 << 12)
> +#define I915_MISC_INTERRUPT (1 << 11)
> +#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1 << 11)
> +#define I915_DISPLAY_PIPE_C_VBLANK_INTERRUPT (1 << 10)
> +#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1 << 10)
> +#define I915_DISPLAY_PIPE_C_EVENT_INTERRUPT (1 << 9)
> +#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1 << 9)
> +#define I915_DISPLAY_PIPE_C_DPBM_INTERRUPT (1 << 8)
> +#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1 << 8)
> +#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1 << 7)
> +#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1 << 6)
> +#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1 << 5)
> +#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1 << 4)
> +#define I915_DISPLAY_PIPE_A_DPBM_INTERRUPT (1 << 3)
> +#define I915_DISPLAY_PIPE_B_DPBM_INTERRUPT (1 << 2)
> +#define I915_DEBUG_INTERRUPT (1 << 2)
> +#define I915_WINVALID_INTERRUPT (1 << 1)
> +#define I915_USER_INTERRUPT (1 << 1)
> +#define I915_ASLE_INTERRUPT (1 << 0)
> +#define I915_BSD_USER_INTERRUPT (1 << 25)
> +
> +#endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (8 preceding siblings ...)
2026-01-29 21:13 ` [v3 09/19] drm/i915: Remove i915_reg.h from intel_overlay.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:40 ` Jani Nikula
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
` (10 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move DE_IRQ_REGS to display header to make g4x_dp.c
free from i915_reg.h dependency. These registers are
only used by display and gvt.
v2: Move DE interrupt regs from common to display header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
.../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 15 ---------------
3 files changed, 17 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 4cb753177fd8..017c6dd8f9f6 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -8,9 +8,9 @@
#include <linux/string_helpers.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "g4x_dp.h"
-#include "i915_reg.h"
#include "intel_audio.h"
#include "intel_backlight.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 40538910cb09..0164dcbb709f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1049,6 +1049,15 @@
#define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
#define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
+#define DEISR _MMIO(0x44000)
+#define DEIMR _MMIO(0x44004)
+#define DEIIR _MMIO(0x44008)
+#define DEIER _MMIO(0x4400c)
+
+#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
+ DEIER, \
+ DEIIR)
+
#define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
#define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
@@ -1792,6 +1801,13 @@
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
+/* PCH */
+
+#define SDEISR _MMIO(0xc4000)
+#define SDEIMR _MMIO(0xc4004)
+#define SDEIIR _MMIO(0xc4008)
+#define SDEIER _MMIO(0xc400c)
+
#define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
SDEIER, \
SDEIIR)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 22b68ddfa7b4..6cb72e6e9086 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -728,15 +728,6 @@
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
-#define DEISR _MMIO(0x44000)
-#define DEIMR _MMIO(0x44004)
-#define DEIIR _MMIO(0x44008)
-#define DEIER _MMIO(0x4400c)
-
-#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
- DEIER, \
- DEIIR)
-
#define GTISR _MMIO(0x44010)
#define GTIMR _MMIO(0x44014)
#define GTIIR _MMIO(0x44018)
@@ -868,12 +859,6 @@
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
-/* PCH */
-
-#define SDEISR _MMIO(0xc4000)
-#define SDEIMR _MMIO(0xc4004)
-#define SDEIIR _MMIO(0xc4008)
-#define SDEIER _MMIO(0xc400c)
/* Icelake PPS_DATA and _ECC DIP Registers.
* These are available for transcoders B,C and eDP.
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
@ 2026-02-03 12:40 ` Jani Nikula
2026-02-05 7:29 ` Shankar, Uma
0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:40 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move DE_IRQ_REGS to display header to make g4x_dp.c
> free from i915_reg.h dependency. These registers are
> only used by display and gvt.
>
> v2: Move DE interrupt regs from common to display header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> .../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 15 ---------------
> 3 files changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 4cb753177fd8..017c6dd8f9f6 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -8,9 +8,9 @@
> #include <linux/string_helpers.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_interrupt.h>
How's this required in this patch? Nothing's being moved there in this
patch?
BR,
Jani.
>
> #include "g4x_dp.h"
> -#include "i915_reg.h"
> #include "intel_audio.h"
> #include "intel_backlight.h"
> #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 40538910cb09..0164dcbb709f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -1049,6 +1049,15 @@
> #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4)
> #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
>
> +#define DEISR _MMIO(0x44000)
> +#define DEIMR _MMIO(0x44004)
> +#define DEIIR _MMIO(0x44008)
> +#define DEIER _MMIO(0x4400c)
> +
> +#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> + DEIER, \
> + DEIIR)
> +
> #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> @@ -1792,6 +1801,13 @@
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
>
> +/* PCH */
> +
> +#define SDEISR _MMIO(0xc4000)
> +#define SDEIMR _MMIO(0xc4004)
> +#define SDEIIR _MMIO(0xc4008)
> +#define SDEIER _MMIO(0xc400c)
> +
> #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
> SDEIER, \
> SDEIIR)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 22b68ddfa7b4..6cb72e6e9086 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -728,15 +728,6 @@
> #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
> #define MASTER_INTERRUPT_ENABLE (1 << 31)
>
> -#define DEISR _MMIO(0x44000)
> -#define DEIMR _MMIO(0x44004)
> -#define DEIIR _MMIO(0x44008)
> -#define DEIER _MMIO(0x4400c)
> -
> -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> - DEIER, \
> - DEIIR)
> -
> #define GTISR _MMIO(0x44010)
> #define GTIMR _MMIO(0x44014)
> #define GTIIR _MMIO(0x44018)
> @@ -868,12 +859,6 @@
> #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> #define GMD_ID_STEP REG_GENMASK(5, 0)
>
> -/* PCH */
> -
> -#define SDEISR _MMIO(0xc4000)
> -#define SDEIMR _MMIO(0xc4004)
> -#define SDEIIR _MMIO(0xc4008)
> -#define SDEIER _MMIO(0xc400c)
>
> /* Icelake PPS_DATA and _ECC DIP Registers.
> * These are available for transcoders B,C and eDP.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
2026-02-03 12:40 ` Jani Nikula
@ 2026-02-05 7:29 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:29 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:10 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move DE_IRQ_REGS to display header to make g4x_dp.c free from
> > i915_reg.h dependency. These registers are only used by display and
> > gvt.
> >
> > v2: Move DE interrupt regs from common to display header (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/g4x_dp.c | 2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 15 ---------------
> > 3 files changed, 17 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c
> > b/drivers/gpu/drm/i915/display/g4x_dp.c
> > index 4cb753177fd8..017c6dd8f9f6 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> > @@ -8,9 +8,9 @@
> > #include <linux/string_helpers.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_interrupt.h>
>
> How's this required in this patch? Nothing's being moved there in this patch?
Yeah, this got left over during cleanup. Thanks for pointing out.
Will fix it.
Regards,
Uma Shankar
> BR,
> Jani.
>
> >
> > #include "g4x_dp.h"
> > -#include "i915_reg.h"
> > #include "intel_audio.h"
> > #include "intel_backlight.h"
> > #include "intel_connector.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 40538910cb09..0164dcbb709f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -1049,6 +1049,15 @@
> > #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) +
> 0x72414 + (i) * 4)
> > #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4)
> >
> > +#define DEISR _MMIO(0x44000)
> > +#define DEIMR _MMIO(0x44004)
> > +#define DEIIR _MMIO(0x44008)
> > +#define DEIER _MMIO(0x4400c)
> > +
> > +#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> > + DEIER, \
> > + DEIIR)
> > +
> > #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030)
> > #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
> > #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */
> > @@ -1792,6 +1801,13 @@
> >
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \
> >
> SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1))
> >
> > +/* PCH */
> > +
> > +#define SDEISR _MMIO(0xc4000)
> > +#define SDEIMR _MMIO(0xc4004)
> > +#define SDEIIR _MMIO(0xc4008)
> > +#define SDEIER _MMIO(0xc400c)
> > +
> > #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \
> > SDEIER, \
> > SDEIIR)
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 22b68ddfa7b4..6cb72e6e9086
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -728,15 +728,6 @@
> > #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master
> IER */
> > #define MASTER_INTERRUPT_ENABLE (1 << 31)
> >
> > -#define DEISR _MMIO(0x44000)
> > -#define DEIMR _MMIO(0x44004)
> > -#define DEIIR _MMIO(0x44008)
> > -#define DEIER _MMIO(0x4400c)
> > -
> > -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \
> > - DEIER, \
> > - DEIIR)
> > -
> > #define GTISR _MMIO(0x44010)
> > #define GTIMR _MMIO(0x44014)
> > #define GTIIR _MMIO(0x44018)
> > @@ -868,12 +859,6 @@
> > #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
> > #define GMD_ID_STEP REG_GENMASK(5, 0)
> >
> > -/* PCH */
> > -
> > -#define SDEISR _MMIO(0xc4000)
> > -#define SDEIMR _MMIO(0xc4004)
> > -#define SDEIIR _MMIO(0xc4008)
> > -#define SDEIER _MMIO(0xc400c)
> >
> > /* Icelake PPS_DATA and _ECC DIP Registers.
> > * These are available for transcoders B,C and eDP.
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (9 preceding siblings ...)
2026-01-29 21:13 ` [v3 10/19] drm/i915: Remove i915_reg.h from g4x_dp.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:42 ` Jani Nikula
2026-02-03 16:27 ` Ville Syrjälä
2026-01-29 21:13 ` [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
` (9 subsequent siblings)
20 siblings, 2 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move FW_BLC_SELF to common header to make i9xx_wm.c
free from i915_reg.h include. Introduce a common
intel_gmd_misc_regs.h to define common miscellaneous
register definitions across graphics and display.
v2: Introdue a common misc header for GMD
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
.../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
4 files changed, 30 insertions(+), 21 deletions(-)
create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 39dfceb438ae..24f898efa9dd 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -6,8 +6,8 @@
#include <linux/iopoll.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
-#include "i915_reg.h"
#include "i9xx_wm.h"
#include "i9xx_wm_regs.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 0164dcbb709f..680020e590cb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -4,6 +4,7 @@
#ifndef __INTEL_DISPLAY_REGS_H__
#define __INTEL_DISPLAY_REGS_H__
+#include <drm/intel/intel_gmd_misc_regs.h>
#include "intel_display_reg_defs.h"
#define GU_CNTL_PROTECTED _MMIO(0x10100C)
@@ -3119,6 +3120,11 @@ enum skl_power_gate {
#define MTL_TRAS_MASK REG_GENMASK(16, 8)
#define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
-
+#define FW_BLC _MMIO(0x20d8)
+#define FW_BLC2 _MMIO(0x20dc)
+#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
+#define FW_BLC_SELF_EN_MASK REG_BIT(31)
+#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
+#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
#endif /* __INTEL_DISPLAY_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cb72e6e9086..b4b749e52b5b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -26,6 +26,7 @@
#define _I915_REG_H_
#include <drm/intel/intel_pcode.h>
+#include <drm/intel/intel_gmd_misc_regs.h>
#include "i915_reg_defs.h"
#include "display/intel_display_reg_defs.h"
@@ -394,24 +395,10 @@
#define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
-#define INSTPM _MMIO(0x20c0)
-#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
-#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
- will not assert AGPBUSY# and will only
- be delivered when out of C3. */
-#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
-#define INSTPM_TLB_INVALIDATE (1 << 9)
-#define INSTPM_SYNC_FLUSH (1 << 5)
#define MEM_MODE _MMIO(0x20cc)
#define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
#define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
#define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
-#define FW_BLC _MMIO(0x20d8)
-#define FW_BLC2 _MMIO(0x20dc)
-#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
-#define FW_BLC_SELF_EN_MASK REG_BIT(31)
-#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
-#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
#define MM_BURST_LENGTH 0x00700000
#define MM_FIFO_WATERMARK 0x0001F000
#define LM_BURST_LENGTH 0x00000700
@@ -834,11 +821,6 @@
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-#define DISP_ARB_CTL _MMIO(0x45000)
-#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
-#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
-#define DISP_FBC_WM_DIS REG_BIT(15)
-
#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
new file mode 100644
index 000000000000..377f4e383699
--- /dev/null
+++ b/include/drm/intel/intel_gmd_misc_regs.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2026 Intel Corporation */
+
+#ifndef _INTEL_GMD_MISC_REG_H_
+#define _INTEL_GMD_MISC_REG_H_
+
+#define DISP_ARB_CTL _MMIO(0x45000)
+#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
+#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
+#define DISP_FBC_WM_DIS REG_BIT(15)
+
+#define INSTPM _MMIO(0x20c0)
+#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
+#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
+ will not assert AGPBUSY# and will only
+ be delivered when out of C3. */
+#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
+#define INSTPM_TLB_INVALIDATE (1 << 9)
+#define INSTPM_SYNC_FLUSH (1 << 5)
+
+#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
@ 2026-02-03 12:42 ` Jani Nikula
2026-02-05 7:31 ` Shankar, Uma
2026-02-03 16:27 ` Ville Syrjälä
1 sibling, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:42 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move FW_BLC_SELF to common header to make i9xx_wm.c
> free from i915_reg.h include. Introduce a common
> intel_gmd_misc_regs.h to define common miscellaneous
> register definitions across graphics and display.
>
> v2: Introdue a common misc header for GMD
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> 4 files changed, 30 insertions(+), 21 deletions(-)
> create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 39dfceb438ae..24f898efa9dd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "i9xx_wm_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 0164dcbb709f..680020e590cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -4,6 +4,7 @@
> #ifndef __INTEL_DISPLAY_REGS_H__
> #define __INTEL_DISPLAY_REGS_H__
>
> +#include <drm/intel/intel_gmd_misc_regs.h>
Please only include where needed.
> #include "intel_display_reg_defs.h"
>
> #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
>
> -
> +#define FW_BLC _MMIO(0x20d8)
> +#define FW_BLC2 _MMIO(0x20dc)
> +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
>
> #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6cb72e6e9086..b4b749e52b5b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -26,6 +26,7 @@
> #define _I915_REG_H_
>
> #include <drm/intel/intel_pcode.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
Please only include where needed.
> #include "i915_reg_defs.h"
> #include "display/intel_display_reg_defs.h"
>
> @@ -394,24 +395,10 @@
>
> #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
>
> -#define INSTPM _MMIO(0x20c0)
> -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> - will not assert AGPBUSY# and will only
> - be delivered when out of C3. */
> -#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> -#define INSTPM_TLB_INVALIDATE (1 << 9)
> -#define INSTPM_SYNC_FLUSH (1 << 5)
> #define MEM_MODE _MMIO(0x20cc)
> #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
> #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> -#define FW_BLC _MMIO(0x20d8)
> -#define FW_BLC2 _MMIO(0x20dc)
> -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> #define MM_BURST_LENGTH 0x00700000
> #define MM_FIFO_WATERMARK 0x0001F000
> #define LM_BURST_LENGTH 0x00000700
> @@ -834,11 +821,6 @@
> #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
>
>
> -#define DISP_ARB_CTL _MMIO(0x45000)
> -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> -#define DISP_FBC_WM_DIS REG_BIT(15)
> -
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
> new file mode 100644
> index 000000000000..377f4e383699
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_misc_regs.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_MISC_REG_H_
> +#define _INTEL_GMD_MISC_REG_H_
Should be REGS_H to match the file name.
> +
> +#define DISP_ARB_CTL _MMIO(0x45000)
> +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> +#define DISP_FBC_WM_DIS REG_BIT(15)
> +
> +#define INSTPM _MMIO(0x20c0)
> +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> + will not assert AGPBUSY# and will only
> + be delivered when out of C3. */
> +#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> +#define INSTPM_TLB_INVALIDATE (1 << 9)
> +#define INSTPM_SYNC_FLUSH (1 << 5)
> +
> +#endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread* RE: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-02-03 12:42 ` Jani Nikula
@ 2026-02-05 7:31 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:31 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:12 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Move FW_BLC_SELF to common header to make i9xx_wm.c free from
> > i915_reg.h include. Introduce a common intel_gmd_misc_regs.h to define
> > common miscellaneous register definitions across graphics and display.
> >
> > v2: Introdue a common misc header for GMD
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> > include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> > 4 files changed, 30 insertions(+), 21 deletions(-) create mode
> > 100644 include/drm/intel/intel_gmd_misc_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > index 39dfceb438ae..24f898efa9dd 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_wm.h"
> > #include "i9xx_wm_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 0164dcbb709f..680020e590cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -4,6 +4,7 @@
> > #ifndef __INTEL_DISPLAY_REGS_H__
> > #define __INTEL_DISPLAY_REGS_H__
> >
> > +#include <drm/intel/intel_gmd_misc_regs.h>
>
> Please only include where needed.
Sure, will update.
> > #include "intel_display_reg_defs.h"
> >
> > #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> > @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> > #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> >
> > -
> > +#define FW_BLC _MMIO(0x20d8)
> > +#define FW_BLC2 _MMIO(0x20dc)
> > +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> >
> > #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6cb72e6e9086..b4b749e52b5b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -26,6 +26,7 @@
> > #define _I915_REG_H_
> >
> > #include <drm/intel/intel_pcode.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
>
> Please only include where needed.
Will do.
> > #include "i915_reg_defs.h"
> > #include "display/intel_display_reg_defs.h"
> >
> > @@ -394,24 +395,10 @@
> >
> > #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
> >
> > -#define INSTPM _MMIO(0x20c0)
> > -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > - will not assert AGPBUSY# and will only
> > - be delivered when out of C3. */
> > -#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > -#define INSTPM_TLB_INVALIDATE (1 << 9)
> > -#define INSTPM_SYNC_FLUSH (1 << 5)
> > #define MEM_MODE _MMIO(0x20cc)
> > #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> > #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845
> only */
> > #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> > -#define FW_BLC _MMIO(0x20d8)
> > -#define FW_BLC2 _MMIO(0x20dc)
> > -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> > #define MM_BURST_LENGTH 0x00700000
> > #define MM_FIFO_WATERMARK 0x0001F000
> > #define LM_BURST_LENGTH 0x00000700
> > @@ -834,11 +821,6 @@
> > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
> REG_BIT(14)
> >
> >
> > -#define DISP_ARB_CTL _MMIO(0x45000)
> > -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > -#define DISP_FBC_WM_DIS REG_BIT(15)
> > -
> > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> > #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> > #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> > diff --git a/include/drm/intel/intel_gmd_misc_regs.h
> > b/include/drm/intel/intel_gmd_misc_regs.h
> > new file mode 100644
> > index 000000000000..377f4e383699
> > --- /dev/null
> > +++ b/include/drm/intel/intel_gmd_misc_regs.h
> > @@ -0,0 +1,21 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/* Copyright © 2026 Intel Corporation */
> > +
> > +#ifndef _INTEL_GMD_MISC_REG_H_
> > +#define _INTEL_GMD_MISC_REG_H_
>
> Should be REGS_H to match the file name.
Sure, will fix.
Regards,
Uma Shankar
> > +
> > +#define DISP_ARB_CTL _MMIO(0x45000)
> > +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > +#define DISP_FBC_WM_DIS REG_BIT(15)
> > +
> > +#define INSTPM _MMIO(0x20c0)
> > +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > + will not assert AGPBUSY# and will only
> > + be delivered when out of C3. */
> > +#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > +#define INSTPM_TLB_INVALIDATE (1 << 9)
> > +#define INSTPM_SYNC_FLUSH (1 << 5)
> > +
> > +#endif
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
2026-02-03 12:42 ` Jani Nikula
@ 2026-02-03 16:27 ` Ville Syrjälä
2026-02-05 7:36 ` Shankar, Uma
1 sibling, 1 reply; 41+ messages in thread
From: Ville Syrjälä @ 2026-02-03 16:27 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, intel-xe, jani.nikula
On Fri, Jan 30, 2026 at 02:43:50AM +0530, Uma Shankar wrote:
> Move FW_BLC_SELF to common header to make i9xx_wm.c
> free from i915_reg.h include. Introduce a common
> intel_gmd_misc_regs.h to define common miscellaneous
> register definitions across graphics and display.
>
> v2: Introdue a common misc header for GMD
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> 4 files changed, 30 insertions(+), 21 deletions(-)
> create mode 100644 include/drm/intel/intel_gmd_misc_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 39dfceb438ae..24f898efa9dd 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "i9xx_wm_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 0164dcbb709f..680020e590cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -4,6 +4,7 @@
> #ifndef __INTEL_DISPLAY_REGS_H__
> #define __INTEL_DISPLAY_REGS_H__
>
> +#include <drm/intel/intel_gmd_misc_regs.h>
> #include "intel_display_reg_defs.h"
>
> #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
>
> -
> +#define FW_BLC _MMIO(0x20d8)
> +#define FW_BLC2 _MMIO(0x20dc)
> +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
>
> #endif /* __INTEL_DISPLAY_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 6cb72e6e9086..b4b749e52b5b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -26,6 +26,7 @@
> #define _I915_REG_H_
>
> #include <drm/intel/intel_pcode.h>
> +#include <drm/intel/intel_gmd_misc_regs.h>
> #include "i915_reg_defs.h"
> #include "display/intel_display_reg_defs.h"
>
> @@ -394,24 +395,10 @@
>
> #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
>
> -#define INSTPM _MMIO(0x20c0)
> -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> - will not assert AGPBUSY# and will only
> - be delivered when out of C3. */
> -#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> -#define INSTPM_TLB_INVALIDATE (1 << 9)
> -#define INSTPM_SYNC_FLUSH (1 << 5)
> #define MEM_MODE _MMIO(0x20cc)
> #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845 only */
> #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> -#define FW_BLC _MMIO(0x20d8)
> -#define FW_BLC2 _MMIO(0x20dc)
> -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> #define MM_BURST_LENGTH 0x00700000
> #define MM_FIFO_WATERMARK 0x0001F000
> #define LM_BURST_LENGTH 0x00000700
> @@ -834,11 +821,6 @@
> #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
>
>
> -#define DISP_ARB_CTL _MMIO(0x45000)
> -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> -#define DISP_FBC_WM_DIS REG_BIT(15)
> -
> #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> diff --git a/include/drm/intel/intel_gmd_misc_regs.h b/include/drm/intel/intel_gmd_misc_regs.h
> new file mode 100644
> index 000000000000..377f4e383699
> --- /dev/null
> +++ b/include/drm/intel/intel_gmd_misc_regs.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2026 Intel Corporation */
> +
> +#ifndef _INTEL_GMD_MISC_REG_H_
> +#define _INTEL_GMD_MISC_REG_H_
What is a "GMD"?
> +
> +#define DISP_ARB_CTL _MMIO(0x45000)
> +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> +#define DISP_FBC_WM_DIS REG_BIT(15)
That's just a regular display register. I suspect most of the
other registers relatd to the arbiter/etc. are in
intel_display_regs.h
> +
> +#define INSTPM _MMIO(0x20c0)
> +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled, pending interrupts
> + will not assert AGPBUSY# and will only
> + be delivered when out of C3. */
> +#define INSTPM_FORCE_ORDERING (1 << 7) /* GEN6+ */
> +#define INSTPM_TLB_INVALIDATE (1 << 9)
> +#define INSTPM_SYNC_FLUSH (1 << 5)
This is not even a display register.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 41+ messages in thread* RE: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
2026-02-03 16:27 ` Ville Syrjälä
@ 2026-02-05 7:36 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:36 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Nikula, Jani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 3, 2026 9:57 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c
>
> On Fri, Jan 30, 2026 at 02:43:50AM +0530, Uma Shankar wrote:
> > Move FW_BLC_SELF to common header to make i9xx_wm.c free from
> > i915_reg.h include. Introduce a common intel_gmd_misc_regs.h to define
> > common miscellaneous register definitions across graphics and display.
> >
> > v2: Introdue a common misc header for GMD
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/i9xx_wm.c | 2 +-
> > .../gpu/drm/i915/display/intel_display_regs.h | 8 ++++++-
> > drivers/gpu/drm/i915/i915_reg.h | 20 +-----------------
> > include/drm/intel/intel_gmd_misc_regs.h | 21 +++++++++++++++++++
> > 4 files changed, 30 insertions(+), 21 deletions(-) create mode
> > 100644 include/drm/intel/intel_gmd_misc_regs.h
> >
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > index 39dfceb438ae..24f898efa9dd 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_wm.h"
> > #include "i9xx_wm_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 0164dcbb709f..680020e590cb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -4,6 +4,7 @@
> > #ifndef __INTEL_DISPLAY_REGS_H__
> > #define __INTEL_DISPLAY_REGS_H__
> >
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> > #include "intel_display_reg_defs.h"
> >
> > #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> > @@ -3119,6 +3120,11 @@ enum skl_power_gate {
> > #define MTL_TRAS_MASK REG_GENMASK(16, 8)
> > #define MTL_TRDPRE_MASK REG_GENMASK(7, 0)
> >
> > -
> > +#define FW_BLC _MMIO(0x20d8)
> > +#define FW_BLC2 _MMIO(0x20dc)
> > +#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > +#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > +#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > +#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> >
> > #endif /* __INTEL_DISPLAY_REGS_H__ */ diff --git
> > a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 6cb72e6e9086..b4b749e52b5b 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -26,6 +26,7 @@
> > #define _I915_REG_H_
> >
> > #include <drm/intel/intel_pcode.h>
> > +#include <drm/intel/intel_gmd_misc_regs.h>
> > #include "i915_reg_defs.h"
> > #include "display/intel_display_reg_defs.h"
> >
> > @@ -394,24 +395,10 @@
> >
> > #define GEN2_ERROR_REGS I915_ERROR_REGS(EMR, EIR)
> >
> > -#define INSTPM _MMIO(0x20c0)
> > -#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > -#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > - will not assert AGPBUSY# and will only
> > - be delivered when out of C3. */
> > -#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > -#define INSTPM_TLB_INVALIDATE (1 << 9)
> > -#define INSTPM_SYNC_FLUSH (1 << 5)
> > #define MEM_MODE _MMIO(0x20cc)
> > #define MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1 << 3) /* 830 only */
> > #define MEM_DISPLAY_A_TRICKLE_FEED_DISABLE (1 << 2) /* 830/845
> only */
> > #define MEM_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2) /* 85x only */
> > -#define FW_BLC _MMIO(0x20d8)
> > -#define FW_BLC2 _MMIO(0x20dc)
> > -#define FW_BLC_SELF _MMIO(0x20e0) /* 915+ only */
> > -#define FW_BLC_SELF_EN_MASK REG_BIT(31)
> > -#define FW_BLC_SELF_FIFO_MASK REG_BIT(16) /* 945 only */
> > -#define FW_BLC_SELF_EN REG_BIT(15) /* 945 only */
> > #define MM_BURST_LENGTH 0x00700000
> > #define MM_FIFO_WATERMARK 0x0001F000
> > #define LM_BURST_LENGTH 0x00000700
> > @@ -834,11 +821,6 @@
> > #define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT
> REG_BIT(14)
> >
> >
> > -#define DISP_ARB_CTL _MMIO(0x45000)
> > -#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > -#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > -#define DISP_FBC_WM_DIS REG_BIT(15)
> > -
> > #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
> > #define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
> > #define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
> > diff --git a/include/drm/intel/intel_gmd_misc_regs.h
> > b/include/drm/intel/intel_gmd_misc_regs.h
> > new file mode 100644
> > index 000000000000..377f4e383699
> > --- /dev/null
> > +++ b/include/drm/intel/intel_gmd_misc_regs.h
> > @@ -0,0 +1,21 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/* Copyright © 2026 Intel Corporation */
> > +
> > +#ifndef _INTEL_GMD_MISC_REG_H_
> > +#define _INTEL_GMD_MISC_REG_H_
>
> What is a "GMD"?
For all common ones, I have used Graphics Media Display (GMD) as referred by
bspec as well.
> > +
> > +#define DISP_ARB_CTL _MMIO(0x45000)
> > +#define DISP_FBC_MEMORY_WAKE REG_BIT(31)
> > +#define DISP_TILE_SURFACE_SWIZZLING REG_BIT(13)
> > +#define DISP_FBC_WM_DIS REG_BIT(15)
>
> That's just a regular display register. I suspect most of the other registers relatd to
> the arbiter/etc. are in intel_display_regs.h
Yeah I also thought so, but this is used by intel_ggtt_fencing.c. Hence had to keep it
in the common header.
> > +
> > +#define INSTPM _MMIO(0x20c0)
> > +#define INSTPM_SELF_EN (1 << 12) /* 915GM only */
> > +#define INSTPM_AGPBUSY_INT_EN (1 << 11) /* gen3: when disabled,
> pending interrupts
> > + will not assert AGPBUSY# and will only
> > + be delivered when out of C3. */
> > +#define INSTPM_FORCE_ORDERING (1 << 7) /*
> GEN6+ */
> > +#define INSTPM_TLB_INVALIDATE (1 << 9)
> > +#define INSTPM_SYNC_FLUSH (1 << 5)
>
> This is not even a display register.
Yeah, but this is being used in intel_display_debugfs and in i9xx_wm.c.
So had to keep in a common header.
Regards,
Uma Shankar
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (10 preceding siblings ...)
2026-01-29 21:13 ` [v3 11/19] drm/i915: Remove i915_reg.h from i9xx_wm.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
` (8 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move TRANS_CHICKEN1 reg to display header to make g4x_hdmi.c
free from i915_reg.h dependency.
v2: Remove from common header in include and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 1 -
drivers/gpu/drm/i915/display/intel_display_regs.h | 12 ++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 12 ------------
3 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 8b22447e8e23..5fe5067c4237 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -8,7 +8,6 @@
#include <drm/drm_print.h>
#include "g4x_hdmi.h"
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_audio.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 680020e590cb..5679a83ff19b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -2145,6 +2145,18 @@
#define TRANS_BPC_6 REG_FIELD_PREP(TRANS_BPC_MASK, 2)
#define TRANS_BPC_12 REG_FIELD_PREP(TRANS_BPC_MASK, 3)
+/* Icelake PPS_DATA and _ECC DIP Registers.
+ * These are available for transcoders B,C and eDP.
+ * Adding the _A so as to reuse the _MMIO_TRANS2
+ * definition, with which it offsets to the right location.
+ */
+
+#define _TRANSA_CHICKEN1 0xf0060
+#define _TRANSB_CHICKEN1 0xf1060
+#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
+#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
+#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
+
#define _TRANSA_CHICKEN2 0xf0064
#define _TRANSB_CHICKEN2 0xf1064
#define TRANS_CHICKEN2(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4b749e52b5b..635726f01e9a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -842,18 +842,6 @@
#define GMD_ID_STEP REG_GENMASK(5, 0)
-/* Icelake PPS_DATA and _ECC DIP Registers.
- * These are available for transcoders B,C and eDP.
- * Adding the _A so as to reuse the _MMIO_TRANS2
- * definition, with which it offsets to the right location.
- */
-
-#define _TRANSA_CHICKEN1 0xf0060
-#define _TRANSB_CHICKEN1 0xf1060
-#define TRANS_CHICKEN1(pipe) _MMIO_PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
-#define TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE REG_BIT(10)
-#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE REG_BIT(4)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (11 preceding siblings ...)
2026-01-29 21:13 ` [v3 12/19] drm/{i915, xe}: Remove i915_reg.h from g4x_hdmi.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 16:22 ` Ville Syrjälä
2026-01-29 21:13 ` [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c Uma Shankar
` (7 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make intel_rom.c free from including i915_reg.h.
v3: Update patch header
v2: Use display header instead of gmd common include (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
drivers/gpu/drm/i915/display/intel_rom.c | 3 +--
drivers/gpu/drm/i915/i915_reg.h | 8 --------
3 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 5679a83ff19b..3707c5999ffb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -10,6 +10,14 @@
#define GU_CNTL_PROTECTED _MMIO(0x10100C)
#define DEPRESENT REG_BIT(9)
+#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
+#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
+#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
+#define SPI_STATIC_REGIONS _MMIO(0x102090)
+#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
+#define OROM_OFFSET _MMIO(0x1020c0)
+#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
+
#define _GEN7_PIPEA_DE_LOAD_SL 0x70068
#define _GEN7_PIPEB_DE_LOAD_SL 0x71068
#define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
index c8f615315310..d7de53acaba9 100644
--- a/drivers/gpu/drm/i915/display/intel_rom.c
+++ b/drivers/gpu/drm/i915/display/intel_rom.c
@@ -7,10 +7,9 @@
#include <drm/drm_device.h>
-#include "i915_reg.h"
-
#include "intel_rom.h"
#include "intel_uncore.h"
+#include "intel_display_regs.h"
struct intel_rom {
/* for PCI ROM */
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 635726f01e9a..f896ece3b568 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -898,14 +898,6 @@
#define SGGI_DIS REG_BIT(15)
#define SGR_DIS REG_BIT(13)
-#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
-#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
-#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
-#define SPI_STATIC_REGIONS _MMIO(0x102090)
-#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
-#define OROM_OFFSET _MMIO(0x1020c0)
-#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
-
#define MTL_MEDIA_GSI_BASE 0x380000
#endif /* _I915_REG_H_ */
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
@ 2026-02-03 16:22 ` Ville Syrjälä
2026-02-05 7:38 ` Shankar, Uma
0 siblings, 1 reply; 41+ messages in thread
From: Ville Syrjälä @ 2026-02-03 16:22 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, intel-xe, jani.nikula
On Fri, Jan 30, 2026 at 02:43:52AM +0530, Uma Shankar wrote:
> Make intel_rom.c free from including i915_reg.h.
>
> v3: Update patch header
>
> v2: Use display header instead of gmd common include (Jani)
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
> drivers/gpu/drm/i915/display/intel_rom.c | 3 +--
> drivers/gpu/drm/i915/i915_reg.h | 8 --------
> 3 files changed, 9 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 5679a83ff19b..3707c5999ffb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -10,6 +10,14 @@
> #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> #define DEPRESENT REG_BIT(9)
>
> +#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> +#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> +#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> +#define SPI_STATIC_REGIONS _MMIO(0x102090)
> +#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
> +#define OROM_OFFSET _MMIO(0x1020c0)
> +#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
Those don't look like display registers to me. Should probably
live in some more specific header.
> +
> #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL)
> diff --git a/drivers/gpu/drm/i915/display/intel_rom.c b/drivers/gpu/drm/i915/display/intel_rom.c
> index c8f615315310..d7de53acaba9 100644
> --- a/drivers/gpu/drm/i915/display/intel_rom.c
> +++ b/drivers/gpu/drm/i915/display/intel_rom.c
> @@ -7,10 +7,9 @@
>
> #include <drm/drm_device.h>
>
> -#include "i915_reg.h"
> -
> #include "intel_rom.h"
> #include "intel_uncore.h"
> +#include "intel_display_regs.h"
>
> struct intel_rom {
> /* for PCI ROM */
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 635726f01e9a..f896ece3b568 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -898,14 +898,6 @@
> #define SGGI_DIS REG_BIT(15)
> #define SGR_DIS REG_BIT(13)
>
> -#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> -#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> -#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> -#define SPI_STATIC_REGIONS _MMIO(0x102090)
> -#define OPTIONROM_SPI_REGIONID_MASK REG_GENMASK(7, 0)
> -#define OROM_OFFSET _MMIO(0x1020c0)
> -#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
> -
> #define MTL_MEDIA_GSI_BASE 0x380000
>
> #endif /* _I915_REG_H_ */
> --
> 2.50.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 41+ messages in thread* RE: [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
2026-02-03 16:22 ` Ville Syrjälä
@ 2026-02-05 7:38 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:38 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Nikula, Jani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 3, 2026 9:52 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c
>
> On Fri, Jan 30, 2026 at 02:43:52AM +0530, Uma Shankar wrote:
> > Make intel_rom.c free from including i915_reg.h.
> >
> > v3: Update patch header
> >
> > v2: Use display header instead of gmd common include (Jani)
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_regs.h | 8 ++++++++
> > drivers/gpu/drm/i915/display/intel_rom.c | 3 +--
> > drivers/gpu/drm/i915/i915_reg.h | 8 --------
> > 3 files changed, 9 insertions(+), 10 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 5679a83ff19b..3707c5999ffb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -10,6 +10,14 @@
> > #define GU_CNTL_PROTECTED _MMIO(0x10100C)
> > #define DEPRESENT REG_BIT(9)
> >
> > +#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> > +#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> > +#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> > +#define SPI_STATIC_REGIONS _MMIO(0x102090)
> > +#define OPTIONROM_SPI_REGIONID_MASK
> REG_GENMASK(7, 0)
> > +#define OROM_OFFSET _MMIO(0x1020c0)
> > +#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
>
> Those don't look like display registers to me. Should probably live in some more
> specific header.
Sure, will create a new file intel_oprom_regs.h to keep these out of display header.
Hope this is fine.
Regards,
Uma Shankar
> > +
> > #define _GEN7_PIPEA_DE_LOAD_SL 0x70068
> > #define _GEN7_PIPEB_DE_LOAD_SL 0x71068
> > #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe,
> > _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) diff --git
> > a/drivers/gpu/drm/i915/display/intel_rom.c
> > b/drivers/gpu/drm/i915/display/intel_rom.c
> > index c8f615315310..d7de53acaba9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_rom.c
> > +++ b/drivers/gpu/drm/i915/display/intel_rom.c
> > @@ -7,10 +7,9 @@
> >
> > #include <drm/drm_device.h>
> >
> > -#include "i915_reg.h"
> > -
> > #include "intel_rom.h"
> > #include "intel_uncore.h"
> > +#include "intel_display_regs.h"
> >
> > struct intel_rom {
> > /* for PCI ROM */
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 635726f01e9a..f896ece3b568
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -898,14 +898,6 @@
> > #define SGGI_DIS REG_BIT(15)
> > #define SGR_DIS REG_BIT(13)
> >
> > -#define PRIMARY_SPI_TRIGGER _MMIO(0x102040)
> > -#define PRIMARY_SPI_ADDRESS _MMIO(0x102080)
> > -#define PRIMARY_SPI_REGIONID _MMIO(0x102084)
> > -#define SPI_STATIC_REGIONS _MMIO(0x102090)
> > -#define OPTIONROM_SPI_REGIONID_MASK
> REG_GENMASK(7, 0)
> > -#define OROM_OFFSET _MMIO(0x1020c0)
> > -#define OROM_OFFSET_MASK REG_GENMASK(20, 16)
> > -
> > #define MTL_MEDIA_GSI_BASE 0x380000
> >
> > #endif /* _I915_REG_H_ */
> > --
> > 2.50.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (12 preceding siblings ...)
2026-01-29 21:13 ` [v3 13/19] drm/i915: Remove i915_reg.h from intel_rom.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
` (6 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move some chicken registers to display header to make
intel_psr.c free from including i915_reg.h.
v3: Update commit header
v2: Use display header instead of gmd common include (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 26 +++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 28 -------------------
3 files changed, 26 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 3707c5999ffb..23626ee2d4ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -366,6 +366,32 @@
#define OGAMC1 _MMIO(0x30020)
#define OGAMC0 _MMIO(0x30024)
+#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
+#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
+#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
+#define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
+#define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
+#define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
+#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \
+ _LATENCY_REPORTING_REMOVED_PIPE_A, \
+ _LATENCY_REPORTING_REMOVED_PIPE_B, \
+ _LATENCY_REPORTING_REMOVED_PIPE_C, \
+ _LATENCY_REPORTING_REMOVED_PIPE_D)
+#define ICL_DELAY_PMRSP REG_BIT(22)
+#define DISABLE_FLR_SRC REG_BIT(15)
+#define MASK_WAKEMEM REG_BIT(13)
+#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
+
+#define CHICKEN_PAR1_1 _MMIO(0x42080)
+#define IGNORE_KVMR_PIPE_A REG_BIT(23)
+#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
+#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
+#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
+#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
+#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
+#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
+#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
+
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
#define DG2_DPFC_GATING_DIS REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 62208ffc5101..bde7dbfe15a8 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -29,7 +29,6 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
-#include "i915_reg.h"
#include "intel_alpm.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f896ece3b568..b23ac1b8f495 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -807,41 +807,13 @@
#define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE REG_BIT(5)
#define CHICKEN3_DGMG_DONE_FIX_DISABLE REG_BIT(2)
-#define CHICKEN_PAR1_1 _MMIO(0x42080)
-#define IGNORE_KVMR_PIPE_A REG_BIT(23)
-#define KBL_ARB_FILL_SPARE_22 REG_BIT(22)
-#define DIS_RAM_BYPASS_PSR2_MAN_TRACK REG_BIT(16)
-#define SKL_DE_COMPRESSED_HASH_MODE REG_BIT(15)
-#define HSW_MASK_VBL_TO_PIPE_IN_SRD REG_BIT(15) /* hsw/bdw */
-#define FORCE_ARB_IDLE_PLANES REG_BIT(14)
-#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
-#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
-
#define CHICKEN_PAR2_1 _MMIO(0x42090)
#define KVM_CONFIG_CHANGE_NOTIFICATION_SELECT REG_BIT(14)
-
-#define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430)
-#define _LATENCY_REPORTING_REMOVED_PIPE_D REG_BIT(31)
-#define SKL_SELECT_ALTERNATE_DC_EXIT REG_BIT(30)
-#define _LATENCY_REPORTING_REMOVED_PIPE_C REG_BIT(25)
-#define _LATENCY_REPORTING_REMOVED_PIPE_B REG_BIT(24)
-#define _LATENCY_REPORTING_REMOVED_PIPE_A REG_BIT(23)
-#define LATENCY_REPORTING_REMOVED(pipe) _PICK((pipe), \
- _LATENCY_REPORTING_REMOVED_PIPE_A, \
- _LATENCY_REPORTING_REMOVED_PIPE_B, \
- _LATENCY_REPORTING_REMOVED_PIPE_C, \
- _LATENCY_REPORTING_REMOVED_PIPE_D)
-#define ICL_DELAY_PMRSP REG_BIT(22)
-#define DISABLE_FLR_SRC REG_BIT(15)
-#define MASK_WAKEMEM REG_BIT(13)
-#define DDI_CLOCK_REG_ACCESS REG_BIT(7)
-
#define GMD_ID_ARCH_MASK REG_GENMASK(31, 22)
#define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14)
#define GMD_ID_STEP REG_GENMASK(5, 0)
-
#define VLV_PMWGICZ _MMIO(0x1300a4)
#define HSW_EDRAM_CAP _MMIO(0x120010)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (13 preceding siblings ...)
2026-01-29 21:13 ` [v3 14/19] drm/i915: Remove i915_reg.h from intel_psr.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:47 ` Jani Nikula
2026-01-29 21:13 ` [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c Uma Shankar
` (5 subsequent siblings)
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
free from including i915_reg.h.
v2: Move GEN7_ERR_INT regs to display header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
.../drm/i915/display/intel_fifo_underrun.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 23 -------------------
3 files changed, 23 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 23626ee2d4ce..ab2ef267c9ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -91,6 +91,29 @@
#define DERRMR_PIPEC_VBLANK (1 << 21)
#define DERRMR_PIPEC_HBLANK (1 << 22)
+#define GEN7_ERR_INT _MMIO(0x44040)
+#define ERR_INT_POISON (1 << 31)
+#define ERR_INT_INVALID_GTT_PTE (1 << 29)
+#define ERR_INT_INVALID_PTE_DATA (1 << 28)
+#define ERR_INT_SPRITE_C_FAULT (1 << 23)
+#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
+#define ERR_INT_CURSOR_C_FAULT (1 << 21)
+#define ERR_INT_SPRITE_B_FAULT (1 << 20)
+#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
+#define ERR_INT_CURSOR_B_FAULT (1 << 18)
+#define ERR_INT_SPRITE_A_FAULT (1 << 17)
+#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
+#define ERR_INT_CURSOR_A_FAULT (1 << 15)
+#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
+#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
+#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
+#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
+#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
+#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
+#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
+#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
+#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
+
#define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
VLV_IER, \
VLV_IIR)
diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
index b413b3e871d8..bf047180def9 100644
--- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
@@ -29,7 +29,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b23ac1b8f495..611ae5861450 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -327,29 +327,6 @@
#define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
#define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
-#define GEN7_ERR_INT _MMIO(0x44040)
-#define ERR_INT_POISON (1 << 31)
-#define ERR_INT_INVALID_GTT_PTE (1 << 29)
-#define ERR_INT_INVALID_PTE_DATA (1 << 28)
-#define ERR_INT_SPRITE_C_FAULT (1 << 23)
-#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
-#define ERR_INT_CURSOR_C_FAULT (1 << 21)
-#define ERR_INT_SPRITE_B_FAULT (1 << 20)
-#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
-#define ERR_INT_CURSOR_B_FAULT (1 << 18)
-#define ERR_INT_SPRITE_A_FAULT (1 << 17)
-#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
-#define ERR_INT_CURSOR_A_FAULT (1 << 15)
-#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
-#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
-#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
-#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
-#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
-#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
-#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
-#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
-#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
-
#define FPGA_DBG _MMIO(0x42300)
#define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
@ 2026-02-03 12:47 ` Jani Nikula
0 siblings, 0 replies; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:47 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Move GEN7_ERR_INT reg to common header to make intel_fifo_underrun.c
> free from including i915_reg.h.
>
> v2: Move GEN7_ERR_INT regs to display header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_display_regs.h | 23 +++++++++++++++++++
> .../drm/i915/display/intel_fifo_underrun.c | 1 -
> drivers/gpu/drm/i915/i915_reg.h | 23 -------------------
> 3 files changed, 23 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 23626ee2d4ce..ab2ef267c9ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -91,6 +91,29 @@
> #define DERRMR_PIPEC_VBLANK (1 << 21)
> #define DERRMR_PIPEC_HBLANK (1 << 22)
>
> +#define GEN7_ERR_INT _MMIO(0x44040)
> +#define ERR_INT_POISON (1 << 31)
> +#define ERR_INT_INVALID_GTT_PTE (1 << 29)
> +#define ERR_INT_INVALID_PTE_DATA (1 << 28)
> +#define ERR_INT_SPRITE_C_FAULT (1 << 23)
> +#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
> +#define ERR_INT_CURSOR_C_FAULT (1 << 21)
> +#define ERR_INT_SPRITE_B_FAULT (1 << 20)
> +#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
> +#define ERR_INT_CURSOR_B_FAULT (1 << 18)
> +#define ERR_INT_SPRITE_A_FAULT (1 << 17)
> +#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
> +#define ERR_INT_CURSOR_A_FAULT (1 << 15)
> +#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
> +#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
> +#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
> +#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
> +#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
> +#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
> +#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
> +#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
> +#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
> +
> #define VLV_IRQ_REGS I915_IRQ_REGS(VLV_IMR, \
> VLV_IER, \
> VLV_IIR)
> diff --git a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> index b413b3e871d8..bf047180def9 100644
> --- a/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> +++ b/drivers/gpu/drm/i915/display/intel_fifo_underrun.c
> @@ -29,7 +29,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b23ac1b8f495..611ae5861450 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -327,29 +327,6 @@
> #define GEN7_MEDIA_MAX_REQ_COUNT _MMIO(0x4070)
> #define GEN7_GFX_MAX_REQ_COUNT _MMIO(0x4074)
>
> -#define GEN7_ERR_INT _MMIO(0x44040)
> -#define ERR_INT_POISON (1 << 31)
> -#define ERR_INT_INVALID_GTT_PTE (1 << 29)
> -#define ERR_INT_INVALID_PTE_DATA (1 << 28)
> -#define ERR_INT_SPRITE_C_FAULT (1 << 23)
> -#define ERR_INT_PRIMARY_C_FAULT (1 << 22)
> -#define ERR_INT_CURSOR_C_FAULT (1 << 21)
> -#define ERR_INT_SPRITE_B_FAULT (1 << 20)
> -#define ERR_INT_PRIMARY_B_FAULT (1 << 19)
> -#define ERR_INT_CURSOR_B_FAULT (1 << 18)
> -#define ERR_INT_SPRITE_A_FAULT (1 << 17)
> -#define ERR_INT_PRIMARY_A_FAULT (1 << 16)
> -#define ERR_INT_CURSOR_A_FAULT (1 << 15)
> -#define ERR_INT_MMIO_UNCLAIMED (1 << 13)
> -#define ERR_INT_PIPE_CRC_DONE_C (1 << 8)
> -#define ERR_INT_FIFO_UNDERRUN_C (1 << 6)
> -#define ERR_INT_PIPE_CRC_DONE_B (1 << 5)
> -#define ERR_INT_FIFO_UNDERRUN_B (1 << 3)
> -#define ERR_INT_PIPE_CRC_DONE_A (1 << 2)
> -#define ERR_INT_PIPE_CRC_DONE(pipe) (1 << (2 + (pipe) * 3))
> -#define ERR_INT_FIFO_UNDERRUN_A (1 << 0)
> -#define ERR_INT_FIFO_UNDERRUN(pipe) (1 << ((pipe) * 3))
> -
> #define FPGA_DBG _MMIO(0x42300)
> #define FPGA_DBG_RM_NOCLAIM REG_BIT(31)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (14 preceding siblings ...)
2026-01-29 21:13 ` [v3 15/19] drm/i915: Remove i915_reg.h from intel_fifo_underrun.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
` (4 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move VLV_IRQ_REGS to common header for interrupt to make
intel_display_irq.c free from including i915_reg.h.
v2: Move interrupt to dedicated header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
.../gpu/drm/i915/display/intel_display_irq.c | 1 -
.../gpu/drm/i915/display/intel_display_regs.h | 5 ++
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
drivers/gpu/drm/i915/gt/intel_rc6.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/gvt/interrupt.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 52 -------------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 2 +
drivers/gpu/drm/i915/vlv_suspend.c | 1 +
include/drm/intel/intel_gmd_interrupt.h | 49 +++++++++++++++++
11 files changed, 63 insertions(+), 53 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 31c78dc3d63b..5d80f0f4779c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -7,7 +7,6 @@
#include <drm/drm_vblank.h>
#include <drm/intel/intel_gmd_interrupt.h>
-#include "i915_reg.h"
#include "icl_dsi_regs.h"
#include "intel_crtc.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index ab2ef267c9ce..4a9b7560ce8c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -1479,6 +1479,11 @@
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8 * (pipe)))
+/* Display Internal Timeout Register */
+#define RM_TIMEOUT _MMIO(0x42060)
+#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
+#define MMIO_TIMEOUT_US(us) ((us) << 0)
+
#define GEN8_DE_MISC_ISR _MMIO(0x44460)
#define GEN8_DE_MISC_IMR _MMIO(0x44464)
#define GEN8_DE_MISC_IIR _MMIO(0x44468)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index 75e802e10be2..702d8558aa69 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -5,6 +5,8 @@
#include <linux/sched/clock.h>
+#include <drm/intel/intel_gmd_interrupt.h>
+
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 286d49ecc449..dfda675f633a 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -7,6 +7,7 @@
#include <linux/string_helpers.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/vlv_clock.h"
#include "gem/i915_gem_region.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6f860c320afc..28541b0c7cb9 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -40,6 +40,7 @@
#include <drm/display/drm_dp.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/bxt_dpio_phy_regs.h"
#include "display/i9xx_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/interrupt.c b/drivers/gpu/drm/i915/gvt/interrupt.c
index 91d22b1c62e2..92c4e2762032 100644
--- a/drivers/gpu/drm/i915/gvt/interrupt.c
+++ b/drivers/gpu/drm/i915/gvt/interrupt.c
@@ -32,6 +32,7 @@
#include <linux/eventfd.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 611ae5861450..9cd7fce09ebe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -337,9 +337,6 @@
#define VLV_GU_CTL0 _MMIO(VLV_DISPLAY_BASE + 0x2030)
#define VLV_GU_CTL1 _MMIO(VLV_DISPLAY_BASE + 0x2034)
-#define SCPD0 _MMIO(0x209c) /* 915+ only */
-#define SCPD_FBC_IGNORE_3D (1 << 6)
-#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
#define GEN2_IER _MMIO(0x20a0)
#define GEN2_IIR _MMIO(0x20a4)
#define GEN2_IMR _MMIO(0x20a8)
@@ -352,13 +349,6 @@
#define GINT_DIS (1 << 22)
#define GCFG_DIS (1 << 8)
#define VLV_GUNIT_CLOCK_GATE2 _MMIO(VLV_DISPLAY_BASE + 0x2064)
-#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
-#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
-#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
-#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
-#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
-#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
-#define VLV_PCBR_ADDR_SHIFT 12
#define EIR _MMIO(0x20b0)
#define EMR _MMIO(0x20b4)
@@ -684,11 +674,6 @@
#define PCH_3DCGDIS1 _MMIO(0x46024)
# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
-/* Display Internal Timeout Register */
-#define RM_TIMEOUT _MMIO(0x42060)
-#define RM_TIMEOUT_REG_CAPTURE _MMIO(0x420E0)
-#define MMIO_TIMEOUT_US(us) ((us) << 0)
-
#define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */
#define MASTER_INTERRUPT_ENABLE (1 << 31)
@@ -701,24 +686,6 @@
GTIER, \
GTIIR)
-#define GEN8_MASTER_IRQ _MMIO(0x44200)
-#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
-#define GEN8_PCU_IRQ (1 << 30)
-#define GEN8_DE_PCH_IRQ (1 << 23)
-#define GEN8_DE_MISC_IRQ (1 << 22)
-#define GEN8_DE_PORT_IRQ (1 << 20)
-#define GEN8_DE_PIPE_C_IRQ (1 << 18)
-#define GEN8_DE_PIPE_B_IRQ (1 << 17)
-#define GEN8_DE_PIPE_A_IRQ (1 << 16)
-#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
-#define GEN8_GT_VECS_IRQ (1 << 6)
-#define GEN8_GT_GUC_IRQ (1 << 5)
-#define GEN8_GT_PM_IRQ (1 << 4)
-#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
-#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
-#define GEN8_GT_BCS_IRQ (1 << 1)
-#define GEN8_GT_RCS_IRQ (1 << 0)
-
#define GEN8_GT_ISR(which) _MMIO(0x44300 + (0x10 * (which)))
#define GEN8_GT_IMR(which) _MMIO(0x44304 + (0x10 * (which)))
#define GEN8_GT_IIR(which) _MMIO(0x44308 + (0x10 * (which)))
@@ -744,25 +711,6 @@
GEN8_PCU_IER, \
GEN8_PCU_IIR)
-#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
-#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
-#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
-#define GEN11_GU_MISC_IER _MMIO(0x444fc)
-#define GEN11_GU_MISC_GSE (1 << 27)
-
-#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
- GEN11_GU_MISC_IER, \
- GEN11_GU_MISC_IIR)
-
-#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
-#define GEN11_MASTER_IRQ (1 << 31)
-#define GEN11_PCU_IRQ (1 << 30)
-#define GEN11_GU_MISC_IRQ (1 << 29)
-#define GEN11_DISPLAY_IRQ (1 << 16)
-#define GEN11_GT_DW_IRQ(x) (1 << (x))
-#define GEN11_GT_DW1_IRQ (1 << 1)
-#define GEN11_GT_DW0_IRQ (1 << 0)
-
#define DG1_MSTR_TILE_INTR _MMIO(0x190008)
#define DG1_MSTR_IRQ REG_BIT(31)
#define DG1_MSTR_TILE(t) REG_BIT(t)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 4e18d5a22112..627185c6d110 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -26,6 +26,7 @@
*/
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "display/i9xx_plane_regs.h"
#include "display/intel_display.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index c0154fd77fc9..b20d4eb0bfd2 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -3,6 +3,8 @@
* Copyright © 2020 Intel Corporation
*/
+#include <drm/intel/intel_gmd_interrupt.h>
+
#include "display/bxt_dpio_phy_regs.h"
#include "display/i9xx_plane_regs.h"
#include "display/i9xx_wm_regs.h"
diff --git a/drivers/gpu/drm/i915/vlv_suspend.c b/drivers/gpu/drm/i915/vlv_suspend.c
index bace7b38329b..e350f588cec1 100644
--- a/drivers/gpu/drm/i915/vlv_suspend.c
+++ b/drivers/gpu/drm/i915/vlv_suspend.c
@@ -7,6 +7,7 @@
#include <linux/kernel.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_gmd_interrupt.h>
#include "gt/intel_gt_regs.h"
diff --git a/include/drm/intel/intel_gmd_interrupt.h b/include/drm/intel/intel_gmd_interrupt.h
index eae0acade16a..5c77b0aa96a2 100644
--- a/include/drm/intel/intel_gmd_interrupt.h
+++ b/include/drm/intel/intel_gmd_interrupt.h
@@ -40,4 +40,53 @@
#define I915_ASLE_INTERRUPT (1 << 0)
#define I915_BSD_USER_INTERRUPT (1 << 25)
+#define GEN8_MASTER_IRQ _MMIO(0x44200)
+#define GEN8_MASTER_IRQ_CONTROL (1 << 31)
+#define GEN8_PCU_IRQ (1 << 30)
+#define GEN8_DE_PCH_IRQ (1 << 23)
+#define GEN8_DE_MISC_IRQ (1 << 22)
+#define GEN8_DE_PORT_IRQ (1 << 20)
+#define GEN8_DE_PIPE_C_IRQ (1 << 18)
+#define GEN8_DE_PIPE_B_IRQ (1 << 17)
+#define GEN8_DE_PIPE_A_IRQ (1 << 16)
+#define GEN8_DE_PIPE_IRQ(pipe) (1 << (16 + (pipe)))
+#define GEN8_GT_VECS_IRQ (1 << 6)
+#define GEN8_GT_GUC_IRQ (1 << 5)
+#define GEN8_GT_PM_IRQ (1 << 4)
+#define GEN8_GT_VCS1_IRQ (1 << 3) /* NB: VCS2 in bspec! */
+#define GEN8_GT_VCS0_IRQ (1 << 2) /* NB: VCS1 in bpsec! */
+#define GEN8_GT_BCS_IRQ (1 << 1)
+#define GEN8_GT_RCS_IRQ (1 << 0)
+
+#define GEN11_GU_MISC_ISR _MMIO(0x444f0)
+#define GEN11_GU_MISC_IMR _MMIO(0x444f4)
+#define GEN11_GU_MISC_IIR _MMIO(0x444f8)
+#define GEN11_GU_MISC_IER _MMIO(0x444fc)
+#define GEN11_GU_MISC_GSE (1 << 27)
+
+#define GEN11_GU_MISC_IRQ_REGS I915_IRQ_REGS(GEN11_GU_MISC_IMR, \
+ GEN11_GU_MISC_IER, \
+ GEN11_GU_MISC_IIR)
+
+#define GEN11_GFX_MSTR_IRQ _MMIO(0x190010)
+#define GEN11_MASTER_IRQ (1 << 31)
+#define GEN11_PCU_IRQ (1 << 30)
+#define GEN11_GU_MISC_IRQ (1 << 29)
+#define GEN11_DISPLAY_IRQ (1 << 16)
+#define GEN11_GT_DW_IRQ(x) (1 << (x))
+#define GEN11_GT_DW1_IRQ (1 << 1)
+#define GEN11_GT_DW0_IRQ (1 << 0)
+
+#define SCPD0 _MMIO(0x209c) /* 915+ only */
+#define SCPD_FBC_IGNORE_3D (1 << 6)
+#define CSTATE_RENDER_CLOCK_GATE_DISABLE (1 << 5)
+
+#define VLV_IIR_RW _MMIO(VLV_DISPLAY_BASE + 0x2084)
+#define VLV_IER _MMIO(VLV_DISPLAY_BASE + 0x20a0)
+#define VLV_IIR _MMIO(VLV_DISPLAY_BASE + 0x20a4)
+#define VLV_IMR _MMIO(VLV_DISPLAY_BASE + 0x20a8)
+#define VLV_ISR _MMIO(VLV_DISPLAY_BASE + 0x20ac)
+#define VLV_PCBR _MMIO(VLV_DISPLAY_BASE + 0x2120)
+#define VLV_PCBR_ADDR_SHIFT 12
+
#endif
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (15 preceding siblings ...)
2026-01-29 21:13 ` [v3 16/19] drm/i915: Remove i915_reg.h from intel_display_irq.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:49 ` Jani Nikula
2026-02-03 16:34 ` Ville Syrjälä
2026-01-29 21:13 ` [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
` (3 subsequent siblings)
20 siblings, 2 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make intel_display_power_well.c free from including i915_reg.h.
v2: Include specific pcode header, drop common header (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
drivers/gpu/drm/i915/i915_reg.h | 3 ---
3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 6f9bc6f9615e..f98de1baa63d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -6,8 +6,8 @@
#include <linux/iopoll.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_backlight_regs.h"
#include "intel_combo_phy.h"
#include "intel_combo_phy_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4a9b7560ce8c..758749c5c322 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -359,6 +359,8 @@
#define FW_CSPWRDWNEN (1 << 15)
#define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
+/* Disable display A/B trickle feed */
+#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
#define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
#define CDCLK_FREQ_SHIFT 4
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9cd7fce09ebe..e4fc61dcd384 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -428,9 +428,6 @@
#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
-/* Disable display A/B trickle feed */
-#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
-
/* Set display plane priority */
#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
@ 2026-02-03 12:49 ` Jani Nikula
2026-02-05 7:40 ` Shankar, Uma
2026-02-03 16:34 ` Ville Syrjälä
1 sibling, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:49 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make intel_display_power_well.c free from including i915_reg.h.
>
> v2: Include specific pcode header, drop common header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 6f9bc6f9615e..f98de1baa63d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
Hmm, nothing's being moved there in this patch, so this change feels
unrelated.
BR,
Jani.
>
> -#include "i915_reg.h"
> #include "intel_backlight_regs.h"
> #include "intel_combo_phy.h"
> #include "intel_combo_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4a9b7560ce8c..758749c5c322 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -359,6 +359,8 @@
> #define FW_CSPWRDWNEN (1 << 15)
>
> #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> +/* Disable display A/B trickle feed */
> +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
>
> #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
> #define CDCLK_FREQ_SHIFT 4
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9cd7fce09ebe..e4fc61dcd384 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -428,9 +428,6 @@
> #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
> #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
>
> -/* Disable display A/B trickle feed */
> -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> -
> /* Set display plane priority */
> #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
> #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-02-03 12:49 ` Jani Nikula
@ 2026-02-05 7:40 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:40 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:19 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 17/19] drm/i915: Remove i915_reg.h from
> intel_display_power_well.c
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make intel_display_power_well.c free from including i915_reg.h.
> >
> > v2: Include specific pcode header, drop common header (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 3 ---
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 6f9bc6f9615e..f98de1baa63d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
>
> Hmm, nothing's being moved there in this patch, so this change feels unrelated.
Yeah, this got missed. Thanks Jani for spotting it.
Will fix.
Regards,
Uma Shankar
> BR,
> Jani.
>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_combo_phy.h"
> > #include "intel_combo_phy_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4a9b7560ce8c..758749c5c322 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -359,6 +359,8 @@
> > #define FW_CSPWRDWNEN (1 << 15)
> >
> > #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> > +/* Disable display A/B trickle feed */
> > +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> >
> > #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE +
> 0x6508)
> > #define CDCLK_FREQ_SHIFT 4
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 9cd7fce09ebe..e4fc61dcd384
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -428,9 +428,6 @@
> > #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /*
> default */
> > #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
> >
> > -/* Disable display A/B trickle feed */
> > -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> > -
> > /* Set display plane priority */
> > #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display
> A > display B */
> > #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display
> B > display A */
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* Re: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
2026-02-03 12:49 ` Jani Nikula
@ 2026-02-03 16:34 ` Ville Syrjälä
2026-02-05 7:44 ` Shankar, Uma
1 sibling, 1 reply; 41+ messages in thread
From: Ville Syrjälä @ 2026-02-03 16:34 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx, intel-xe, jani.nikula
On Fri, Jan 30, 2026 at 02:43:56AM +0530, Uma Shankar wrote:
> Make intel_display_power_well.c free from including i915_reg.h.
>
> v2: Include specific pcode header, drop common header (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> drivers/gpu/drm/i915/i915_reg.h | 3 ---
> 3 files changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 6f9bc6f9615e..f98de1baa63d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -6,8 +6,8 @@
> #include <linux/iopoll.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_backlight_regs.h"
> #include "intel_combo_phy.h"
> #include "intel_combo_phy_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4a9b7560ce8c..758749c5c322 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -359,6 +359,8 @@
> #define FW_CSPWRDWNEN (1 << 15)
>
> #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> +/* Disable display A/B trickle feed */
> +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
>
> #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE + 0x6508)
> #define CDCLK_FREQ_SHIFT 4
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9cd7fce09ebe..e4fc61dcd384 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -428,9 +428,6 @@
> #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
> #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
>
> -/* Disable display A/B trickle feed */
> -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> -
Instead of confusing where this bit lives on most platforms
(MI_ARB_STATE) we should probably just add a separate defition
for the VLV bit (since it has a separate register offset definition
as well).
> /* Set display plane priority */
> #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
> #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
> --
> 2.50.1
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* RE: [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c
2026-02-03 16:34 ` Ville Syrjälä
@ 2026-02-05 7:44 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:44 UTC (permalink / raw)
To: Ville Syrjälä
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Nikula, Jani
> -----Original Message-----
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Sent: Tuesday, February 3, 2026 10:05 PM
> To: Shankar, Uma <uma.shankar@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Nikula, Jani
> <jani.nikula@intel.com>
> Subject: Re: [v3 17/19] drm/i915: Remove i915_reg.h from
> intel_display_power_well.c
>
> On Fri, Jan 30, 2026 at 02:43:56AM +0530, Uma Shankar wrote:
> > Make intel_display_power_well.c free from including i915_reg.h.
> >
> > v2: Include specific pcode header, drop common header (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_regs.h | 2 ++
> > drivers/gpu/drm/i915/i915_reg.h | 3 ---
> > 3 files changed, 3 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 6f9bc6f9615e..f98de1baa63d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -6,8 +6,8 @@
> > #include <linux/iopoll.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_combo_phy.h"
> > #include "intel_combo_phy_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > index 4a9b7560ce8c..758749c5c322 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> > @@ -359,6 +359,8 @@
> > #define FW_CSPWRDWNEN (1 << 15)
> >
> > #define MI_ARB_VLV _MMIO(VLV_DISPLAY_BASE + 0x6504)
> > +/* Disable display A/B trickle feed */
> > +#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> >
> > #define CZCLK_CDCLK_FREQ_RATIO _MMIO(VLV_DISPLAY_BASE +
> 0x6508)
> > #define CDCLK_FREQ_SHIFT 4
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 9cd7fce09ebe..e4fc61dcd384
> > 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -428,9 +428,6 @@
> > #define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /*
> default */
> > #define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
> >
> > -/* Disable display A/B trickle feed */
> > -#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
> > -
>
> Instead of confusing where this bit lives on most platforms
> (MI_ARB_STATE) we should probably just add a separate defition for the VLV bit
> (since it has a separate register offset definition as well).
Sure, will fix it.
Regards,
Uma Shankar
> > /* Set display plane priority */
> > #define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display
> A > display B */
> > #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display
> B > display A */
> > --
> > 2.50.1
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (16 preceding siblings ...)
2026-01-29 21:13 ` [v3 17/19] drm/i915: Remove i915_reg.h from intel_display_power_well.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
` (2 subsequent siblings)
20 siblings, 0 replies; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Move GEN9_CLKGATE_DIS_0 reg to display header to make
intel_modeset_setup.c free from i915_reg.h include.
v2: Remove from gmd common header and use display_regs.h (Jani)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_regs.h | 14 ++++++++++++++
drivers/gpu/drm/i915/display/intel_modeset_setup.c | 1 -
drivers/gpu/drm/i915/i915_reg.h | 14 --------------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 758749c5c322..ba1fb4c392e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -417,6 +417,20 @@
#define SKL_EDP_PSR_FIX_RDWRAP REG_BIT(3)
#define IGNORE_PSR2_HW_TRACKING REG_BIT(1)
+/*
+ * GEN9 clock gating regs
+ */
+#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
+#define DARBF_GATING_DIS REG_BIT(27)
+#define DMG_GATING_DIS REG_BIT(21)
+#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
+#define PWM2_GATING_DIS REG_BIT(14)
+#define PWM1_GATING_DIS REG_BIT(13)
+
+#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
+#define TGL_VRH_GATING_DIS REG_BIT(31)
+#define DPT_GATING_DIS REG_BIT(22)
+
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
#define BXT_GMBUS_GATING_DIS (1 << 14)
#define DG2_DPFC_GATING_DIS REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/intel_modeset_setup.c b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
index d10cbf69a5f8..9b0becee221c 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_setup.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_setup.c
@@ -11,7 +11,6 @@
#include <drm/drm_print.h>
#include <drm/drm_vblank.h>
-#include "i915_reg.h"
#include "i9xx_wm.h"
#include "intel_atomic.h"
#include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e4fc61dcd384..c360843a2e35 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -629,20 +629,6 @@
#define VLV_CLK_CTL2 _MMIO(0x101104)
#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
-/*
- * GEN9 clock gating regs
- */
-#define GEN9_CLKGATE_DIS_0 _MMIO(0x46530)
-#define DARBF_GATING_DIS REG_BIT(27)
-#define DMG_GATING_DIS REG_BIT(21)
-#define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe))
-#define PWM2_GATING_DIS REG_BIT(14)
-#define PWM1_GATING_DIS REG_BIT(13)
-
-#define GEN9_CLKGATE_DIS_3 _MMIO(0x46538)
-#define TGL_VRH_GATING_DIS REG_BIT(31)
-#define DPT_GATING_DIS REG_BIT(22)
-
#define VLV_DPFLIPSTAT _MMIO(VLV_DISPLAY_BASE + 0x70028)
#define PIPEB_LINE_COMPARE_INT_EN REG_BIT(29)
#define PIPEB_HLINE_INT_EN REG_BIT(28)
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (17 preceding siblings ...)
2026-01-29 21:13 ` [v3 18/19] drm/i915: Remove i915_reg.h from intel_modeset_setup.c Uma Shankar
@ 2026-01-29 21:13 ` Uma Shankar
2026-02-03 12:50 ` Jani Nikula
2026-01-29 22:13 ` ✓ i915.CI.BAT: success for Make Display free from i915_reg.h (rev3) Patchwork
2026-01-30 7:21 ` ✗ i915.CI.Full: failure " Patchwork
20 siblings, 1 reply; 41+ messages in thread
From: Uma Shankar @ 2026-01-29 21:13 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula, ville.syrjala, Uma Shankar
Make display files free from including i915_reg.h.
v2: Include modular per component headers (Jani)
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
drivers/gpu/drm/i915/display/intel_backlight.c | 1 -
drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
drivers/gpu/drm/i915/display/intel_casf.c | 1 -
drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
drivers/gpu/drm/i915/display/intel_display_wa.c | 1 -
drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
drivers/gpu/drm/i915/display/intel_pps.c | 1 -
drivers/gpu/drm/i915/display/intel_tc.c | 1 -
drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
19 files changed, 5 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 0caaea2e64e1..5697fa4eb11f 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -6,9 +6,9 @@
#include <linux/debugfs.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
#include "hsw_ips.h"
-#include "i915_reg.h"
#include "intel_color_regs.h"
#include "intel_de.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index b1fecf178906..9c16753a1f3b 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,7 +10,6 @@
#include <drm/drm_fourcc.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "i9xx_plane.h"
#include "i9xx_plane_regs.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c8e0333706c1..7cf511a6c0f9 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,7 +34,6 @@
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
-#include "i915_reg.h"
#include "icl_dsi.h"
#include "icl_dsi_regs.h"
#include "intel_atomic.h"
diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index a68fdbd2acb9..34e95f05936e 100644
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -12,7 +12,6 @@
#include <drm/drm_file.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_backlight.h"
#include "intel_backlight_regs.h"
#include "intel_connector.h"
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 8d84445c69f1..71149d8bcd73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -5,8 +5,8 @@
#include <drm/drm_atomic_state_helper.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_bw.h"
#include "intel_crtc.h"
#include "intel_display_core.h"
diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
index 0fe4398a1a4e..b167af31de5b 100644
--- a/drivers/gpu/drm/i915/display/intel_casf.c
+++ b/drivers/gpu/drm/i915/display/intel_casf.c
@@ -3,7 +3,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_casf.h"
#include "intel_casf_regs.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index d8739e2bb004..3f0c9c7fd5f8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -34,7 +34,6 @@
#include <drm/drm_print.h>
#include <drm/drm_privacy_screen_consumer.h>
-#include "i915_reg.h"
#include "icl_dsi.h"
#include "intel_alpm.h"
#include "intel_audio.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
index aba13e8a9051..1ce28a31affb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
+++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
@@ -15,7 +15,6 @@
#include <drm/drm_print.h>
#include "hsw_ips.h"
-#include "i915_reg.h"
#include "i9xx_wm_regs.h"
#include "intel_alpm.h"
#include "intel_bo.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 06adf6afbec0..a6e9f1c8d2dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -7,8 +7,8 @@
#include <linux/string_helpers.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_backlight_regs.h"
#include "intel_cdclk.h"
#include "intel_clock_gating.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 2eb4af62d556..d9788a979561 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_core.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 1182bc9a2e6d..8df06b993890 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -29,7 +29,6 @@
#include <drm/drm_file.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_crtc.h"
#include "intel_de.h"
#include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index 5bb0090dd5ed..24ce8a7842c7 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -8,7 +8,6 @@
#include <drm/drm_fixed.h>
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index b7479ced7871..6110a582437c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -17,8 +17,8 @@
#include <drm/display/drm_hdcp_helper.h>
#include <drm/drm_print.h>
#include <drm/intel/i915_component.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "intel_connector.h"
#include "intel_de.h"
#include "intel_display_jiffies.h"
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 82c39e4ffa37..8865cb2ac569 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_irq.h"
#include "intel_display_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index 04f63bdd0b87..1df23447fd84 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -5,7 +5,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index b217ec7aa758..2d799af73bb7 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -9,7 +9,6 @@
#include <drm/drm_print.h>
#include "g4x_dp.h"
-#include "i915_reg.h"
#include "intel_de.h"
#include "intel_display_jiffies.h"
#include "intel_display_power_well.h"
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 064f572bbc85..78ed9c58a72f 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -7,7 +7,6 @@
#include <drm/drm_print.h>
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index b41da10f0f85..9efb94b4cbdb 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -7,8 +7,8 @@
#include <drm/drm_blend.h>
#include <drm/drm_print.h>
+#include <drm/intel/intel_pcode.h>
-#include "i915_reg.h"
#include "i9xx_wm.h"
#include "intel_atomic.h"
#include "intel_bw.h"
diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
index d705af3bf8ba..67f0082d3a69 100644
--- a/drivers/gpu/drm/i915/display/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
@@ -33,7 +33,6 @@
#include <drm/drm_print.h>
#include <drm/drm_probe_helper.h>
-#include "i915_reg.h"
#include "intel_atomic.h"
#include "intel_backlight.h"
#include "intel_connector.h"
--
2.50.1
^ permalink raw reply related [flat|nested] 41+ messages in thread* Re: [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
@ 2026-02-03 12:50 ` Jani Nikula
2026-02-05 7:48 ` Shankar, Uma
0 siblings, 1 reply; 41+ messages in thread
From: Jani Nikula @ 2026-02-03 12:50 UTC (permalink / raw)
To: Uma Shankar, intel-gfx, intel-xe; +Cc: ville.syrjala, Uma Shankar
On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> Make display files free from including i915_reg.h.
>
> v2: Include modular per component headers (Jani)
>
> Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
> drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
> drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
> drivers/gpu/drm/i915/display/intel_backlight.c | 1 -
> drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
> drivers/gpu/drm/i915/display/intel_casf.c | 1 -
> drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
> drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
> drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display_wa.c | 1 -
> drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
> drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
> drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
> drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
> drivers/gpu/drm/i915/display/intel_pps.c | 1 -
> drivers/gpu/drm/i915/display/intel_tc.c | 1 -
> drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
> 19 files changed, 5 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index 0caaea2e64e1..5697fa4eb11f 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -6,9 +6,9 @@
> #include <linux/debugfs.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
Nothing's being added there in this patch, so this feels
unrelated. Ditto below.
I think it'll lead to a better overall series if intel_pcode.h (or
intel_pcode_regs.h) isn't included in i915_reg.h but rather everywhere
it's needed.
BR,
Jani.
>
> #include "hsw_ips.h"
> -#include "i915_reg.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index b1fecf178906..9c16753a1f3b 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -10,7 +10,6 @@
> #include <drm/drm_fourcc.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "i9xx_plane.h"
> #include "i9xx_plane_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c8e0333706c1..7cf511a6c0f9 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,7 +34,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>
> -#include "i915_reg.h"
> #include "icl_dsi.h"
> #include "icl_dsi_regs.h"
> #include "intel_atomic.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
> index a68fdbd2acb9..34e95f05936e 100644
> --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> @@ -12,7 +12,6 @@
> #include <drm/drm_file.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_backlight.h"
> #include "intel_backlight_regs.h"
> #include "intel_connector.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 8d84445c69f1..71149d8bcd73 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -5,8 +5,8 @@
>
> #include <drm/drm_atomic_state_helper.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_bw.h"
> #include "intel_crtc.h"
> #include "intel_display_core.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_casf.c b/drivers/gpu/drm/i915/display/intel_casf.c
> index 0fe4398a1a4e..b167af31de5b 100644
> --- a/drivers/gpu/drm/i915/display/intel_casf.c
> +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> @@ -3,7 +3,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_casf.h"
> #include "intel_casf_regs.h"
> #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index d8739e2bb004..3f0c9c7fd5f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -34,7 +34,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_privacy_screen_consumer.h>
>
> -#include "i915_reg.h"
> #include "icl_dsi.h"
> #include "intel_alpm.h"
> #include "intel_audio.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> index aba13e8a9051..1ce28a31affb 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> @@ -15,7 +15,6 @@
> #include <drm/drm_print.h>
>
> #include "hsw_ips.h"
> -#include "i915_reg.h"
> #include "i9xx_wm_regs.h"
> #include "intel_alpm.h"
> #include "intel_bo.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 06adf6afbec0..a6e9f1c8d2dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -7,8 +7,8 @@
> #include <linux/string_helpers.h>
>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_backlight_regs.h"
> #include "intel_cdclk.h"
> #include "intel_clock_gating.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
> index 2eb4af62d556..d9788a979561 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> @@ -5,7 +5,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_core.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 1182bc9a2e6d..8df06b993890 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -29,7 +29,6 @@
> #include <drm/drm_file.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_crtc.h"
> #include "intel_de.h"
> #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index 5bb0090dd5ed..24ce8a7842c7 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -8,7 +8,6 @@
> #include <drm/drm_fixed.h>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_crtc.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index b7479ced7871..6110a582437c 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -17,8 +17,8 @@
> #include <drm/display/drm_hdcp_helper.h>
> #include <drm/drm_print.h>
> #include <drm/intel/i915_component.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "intel_connector.h"
> #include "intel_de.h"
> #include "intel_display_jiffies.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 82c39e4ffa37..8865cb2ac569 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -5,7 +5,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_irq.h"
> #include "intel_display_regs.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> index 04f63bdd0b87..1df23447fd84 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> @@ -5,7 +5,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_cx0_phy.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
> index b217ec7aa758..2d799af73bb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -9,7 +9,6 @@
> #include <drm/drm_print.h>
>
> #include "g4x_dp.h"
> -#include "i915_reg.h"
> #include "intel_de.h"
> #include "intel_display_jiffies.h"
> #include "intel_display_power_well.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 064f572bbc85..78ed9c58a72f 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -7,7 +7,6 @@
>
> #include <drm/drm_print.h>
>
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_cx0_phy_regs.h"
> #include "intel_ddi.h"
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
> index b41da10f0f85..9efb94b4cbdb 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -7,8 +7,8 @@
>
> #include <drm/drm_blend.h>
> #include <drm/drm_print.h>
> +#include <drm/intel/intel_pcode.h>
>
> -#include "i915_reg.h"
> #include "i9xx_wm.h"
> #include "intel_atomic.h"
> #include "intel_bw.h"
> diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c b/drivers/gpu/drm/i915/display/vlv_dsi.c
> index d705af3bf8ba..67f0082d3a69 100644
> --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> @@ -33,7 +33,6 @@
> #include <drm/drm_print.h>
> #include <drm/drm_probe_helper.h>
>
> -#include "i915_reg.h"
> #include "intel_atomic.h"
> #include "intel_backlight.h"
> #include "intel_connector.h"
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread* RE: [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
2026-02-03 12:50 ` Jani Nikula
@ 2026-02-05 7:48 ` Shankar, Uma
0 siblings, 0 replies; 41+ messages in thread
From: Shankar, Uma @ 2026-02-05 7:48 UTC (permalink / raw)
To: Nikula, Jani, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com
> -----Original Message-----
> From: Nikula, Jani <jani.nikula@intel.com>
> Sent: Tuesday, February 3, 2026 6:21 PM
> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org;
> intel-xe@lists.freedesktop.org
> Cc: ville.syrjala@linux.intel.com; Shankar, Uma <uma.shankar@intel.com>
> Subject: Re: [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display
>
> On Fri, 30 Jan 2026, Uma Shankar <uma.shankar@intel.com> wrote:
> > Make display files free from including i915_reg.h.
> >
> > v2: Include modular per component headers (Jani)
> >
> > Signed-off-by: Uma Shankar <uma.shankar@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/hsw_ips.c | 2 +-
> > drivers/gpu/drm/i915/display/i9xx_plane.c | 1 -
> > drivers/gpu/drm/i915/display/icl_dsi.c | 1 -
> > drivers/gpu/drm/i915/display/intel_backlight.c | 1 -
> > drivers/gpu/drm/i915/display/intel_bw.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_casf.c | 1 -
> > drivers/gpu/drm/i915/display/intel_ddi.c | 1 -
> > drivers/gpu/drm/i915/display/intel_display_debugfs.c | 1 -
> > drivers/gpu/drm/i915/display/intel_display_power.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_display_wa.c | 1 -
> > drivers/gpu/drm/i915/display/intel_dmc.c | 1 -
> > drivers/gpu/drm/i915/display/intel_fdi.c | 1 -
> > drivers/gpu/drm/i915/display/intel_hdcp.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 1 -
> > drivers/gpu/drm/i915/display/intel_lt_phy.c | 1 -
> > drivers/gpu/drm/i915/display/intel_pps.c | 1 -
> > drivers/gpu/drm/i915/display/intel_tc.c | 1 -
> > drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
> > drivers/gpu/drm/i915/display/vlv_dsi.c | 1 -
> > 19 files changed, 5 insertions(+), 19 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c
> > b/drivers/gpu/drm/i915/display/hsw_ips.c
> > index 0caaea2e64e1..5697fa4eb11f 100644
> > --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> > +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> > @@ -6,9 +6,9 @@
> > #include <linux/debugfs.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
>
> Nothing's being added there in this patch, so this feels unrelated. Ditto below.
>
> I think it'll lead to a better overall series if intel_pcode.h (or
> intel_pcode_regs.h) isn't included in i915_reg.h but rather everywhere it's needed.
Yes Jani, will fix this and have it included only where needed.
Regards,
Uma Shankar
> BR,
> Jani.
>
>
> >
> > #include "hsw_ips.h"
> > -#include "i915_reg.h"
> > #include "intel_color_regs.h"
> > #include "intel_de.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > index b1fecf178906..9c16753a1f3b 100644
> > --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> > +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> > @@ -10,7 +10,6 @@
> > #include <drm/drm_fourcc.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_plane.h"
> > #include "i9xx_plane_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> > b/drivers/gpu/drm/i915/display/icl_dsi.c
> > index c8e0333706c1..7cf511a6c0f9 100644
> > --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> > @@ -34,7 +34,6 @@
> > #include <drm/drm_print.h>
> > #include <drm/drm_probe_helper.h>
> >
> > -#include "i915_reg.h"
> > #include "icl_dsi.h"
> > #include "icl_dsi_regs.h"
> > #include "intel_atomic.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c
> > b/drivers/gpu/drm/i915/display/intel_backlight.c
> > index a68fdbd2acb9..34e95f05936e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_backlight.c
> > +++ b/drivers/gpu/drm/i915/display/intel_backlight.c
> > @@ -12,7 +12,6 @@
> > #include <drm/drm_file.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_connector.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 8d84445c69f1..71149d8bcd73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -5,8 +5,8 @@
> >
> > #include <drm/drm_atomic_state_helper.h> #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_bw.h"
> > #include "intel_crtc.h"
> > #include "intel_display_core.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_casf.c
> > b/drivers/gpu/drm/i915/display/intel_casf.c
> > index 0fe4398a1a4e..b167af31de5b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_casf.c
> > +++ b/drivers/gpu/drm/i915/display/intel_casf.c
> > @@ -3,7 +3,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_casf.h"
> > #include "intel_casf_regs.h"
> > #include "intel_de.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > index d8739e2bb004..3f0c9c7fd5f8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > @@ -34,7 +34,6 @@
> > #include <drm/drm_print.h>
> > #include <drm/drm_privacy_screen_consumer.h>
> >
> > -#include "i915_reg.h"
> > #include "icl_dsi.h"
> > #include "intel_alpm.h"
> > #include "intel_audio.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > index aba13e8a9051..1ce28a31affb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_debugfs.c
> > @@ -15,7 +15,6 @@
> > #include <drm/drm_print.h>
> >
> > #include "hsw_ips.h"
> > -#include "i915_reg.h"
> > #include "i9xx_wm_regs.h"
> > #include "intel_alpm.h"
> > #include "intel_bo.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> > b/drivers/gpu/drm/i915/display/intel_display_power.c
> > index 06adf6afbec0..a6e9f1c8d2dc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> > @@ -7,8 +7,8 @@
> > #include <linux/string_helpers.h>
> >
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_backlight_regs.h"
> > #include "intel_cdclk.h"
> > #include "intel_clock_gating.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > index 2eb4af62d556..d9788a979561 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
> > @@ -5,7 +5,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_core.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 1182bc9a2e6d..8df06b993890 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -29,7 +29,6 @@
> > #include <drm/drm_file.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_crtc.h"
> > #include "intel_de.h"
> > #include "intel_display_power_well.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c
> > b/drivers/gpu/drm/i915/display/intel_fdi.c
> > index 5bb0090dd5ed..24ce8a7842c7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > @@ -8,7 +8,6 @@
> > #include <drm/drm_fixed.h>
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_atomic.h"
> > #include "intel_crtc.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > index b7479ced7871..6110a582437c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> > @@ -17,8 +17,8 @@
> > #include <drm/display/drm_hdcp_helper.h> #include <drm/drm_print.h>
> > #include <drm/intel/i915_component.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_connector.h"
> > #include "intel_de.h"
> > #include "intel_display_jiffies.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > index 82c39e4ffa37..8865cb2ac569 100644
> > --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> > @@ -5,7 +5,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_irq.h"
> > #include "intel_display_regs.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > index 04f63bdd0b87..1df23447fd84 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
> > @@ -5,7 +5,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_cx0_phy.h"
> > #include "intel_cx0_phy_regs.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> > b/drivers/gpu/drm/i915/display/intel_pps.c
> > index b217ec7aa758..2d799af73bb7 100644
> > --- a/drivers/gpu/drm/i915/display/intel_pps.c
> > +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> > @@ -9,7 +9,6 @@
> > #include <drm/drm_print.h>
> >
> > #include "g4x_dp.h"
> > -#include "i915_reg.h"
> > #include "intel_de.h"
> > #include "intel_display_jiffies.h"
> > #include "intel_display_power_well.h"
> > diff --git a/drivers/gpu/drm/i915/display/intel_tc.c
> > b/drivers/gpu/drm/i915/display/intel_tc.c
> > index 064f572bbc85..78ed9c58a72f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_tc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> > @@ -7,7 +7,6 @@
> >
> > #include <drm/drm_print.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_atomic.h"
> > #include "intel_cx0_phy_regs.h"
> > #include "intel_ddi.h"
> > diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> > b/drivers/gpu/drm/i915/display/skl_watermark.c
> > index b41da10f0f85..9efb94b4cbdb 100644
> > --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> > +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> > @@ -7,8 +7,8 @@
> >
> > #include <drm/drm_blend.h>
> > #include <drm/drm_print.h>
> > +#include <drm/intel/intel_pcode.h>
> >
> > -#include "i915_reg.h"
> > #include "i9xx_wm.h"
> > #include "intel_atomic.h"
> > #include "intel_bw.h"
> > diff --git a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > index d705af3bf8ba..67f0082d3a69 100644
> > --- a/drivers/gpu/drm/i915/display/vlv_dsi.c
> > +++ b/drivers/gpu/drm/i915/display/vlv_dsi.c
> > @@ -33,7 +33,6 @@
> > #include <drm/drm_print.h>
> > #include <drm/drm_probe_helper.h>
> >
> > -#include "i915_reg.h"
> > #include "intel_atomic.h"
> > #include "intel_backlight.h"
> > #include "intel_connector.h"
>
> --
> Jani Nikula, Intel
^ permalink raw reply [flat|nested] 41+ messages in thread
* ✓ i915.CI.BAT: success for Make Display free from i915_reg.h (rev3)
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (18 preceding siblings ...)
2026-01-29 21:13 ` [v3 19/19] drm/{i915, xe}: Remove i915_reg.h from display Uma Shankar
@ 2026-01-29 22:13 ` Patchwork
2026-01-30 7:21 ` ✗ i915.CI.Full: failure " Patchwork
20 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2026-01-29 22:13 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5443 bytes --]
== Series Details ==
Series: Make Display free from i915_reg.h (rev3)
URL : https://patchwork.freedesktop.org/series/159131/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_17907 -> Patchwork_159131v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/index.html
Participating hosts (42 -> 40)
------------------------------
Additional (1): bat-adls-6
Missing (3): bat-dg2-13 fi-glk-j4005 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_159131v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adls-6: NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_tiled_pread_basic:
- bat-adls-6: NOTRUN -> [SKIP][2] ([i915#3282])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@gem_tiled_pread_basic.html
* igt@i915_selftest@live@workarounds:
- bat-dg2-14: [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/bat-dg2-14/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-dg2-14/igt@i915_selftest@live@workarounds.html
* igt@intel_hwmon@hwmon-read:
- bat-adls-6: NOTRUN -> [SKIP][5] ([i915#7707]) +1 other test skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@intel_hwmon@hwmon-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-adls-6: NOTRUN -> [SKIP][6] ([i915#4103]) +1 other test skip
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_dsc@dsc-basic:
- bat-adls-6: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#3840])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adls-6: NOTRUN -> [SKIP][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pm_backlight@basic-brightness:
- bat-adls-6: NOTRUN -> [SKIP][9] ([i915#5354])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-adls-6: NOTRUN -> [SKIP][10] ([i915#1072] / [i915#9732]) +3 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-adls-6: NOTRUN -> [SKIP][11] ([i915#3555])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-adls-6: NOTRUN -> [SKIP][12] ([i915#3291]) +2 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-adls-6/igt@prime_vgem@basic-fence-read.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-arlh-3: [DMESG-FAIL][13] ([i915#12061]) -> [PASS][14] +1 other test pass
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/bat-arlh-3/igt@i915_selftest@live@workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-arlh-3/igt@i915_selftest@live@workarounds.html
- bat-dg2-9: [DMESG-FAIL][15] ([i915#12061]) -> [PASS][16] +1 other test pass
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/bat-dg2-9/igt@i915_selftest@live@workarounds.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/bat-dg2-9/igt@i915_selftest@live@workarounds.html
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
Build changes
-------------
* Linux: CI_DRM_17907 -> Patchwork_159131v3
CI-20190529: 20190529
CI_DRM_17907: bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8725: 8725
Patchwork_159131v3: bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/index.html
[-- Attachment #2: Type: text/html, Size: 6567 bytes --]
^ permalink raw reply [flat|nested] 41+ messages in thread* ✗ i915.CI.Full: failure for Make Display free from i915_reg.h (rev3)
2026-01-29 21:13 [v3 00/19] Make Display free from i915_reg.h Uma Shankar
` (19 preceding siblings ...)
2026-01-29 22:13 ` ✓ i915.CI.BAT: success for Make Display free from i915_reg.h (rev3) Patchwork
@ 2026-01-30 7:21 ` Patchwork
20 siblings, 0 replies; 41+ messages in thread
From: Patchwork @ 2026-01-30 7:21 UTC (permalink / raw)
To: Uma Shankar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 115940 bytes --]
== Series Details ==
Series: Make Display free from i915_reg.h (rev3)
URL : https://patchwork.freedesktop.org/series/159131/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_17907_full -> Patchwork_159131v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_159131v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_159131v3_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_159131v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_eio@in-flight-internal-1us:
- shard-mtlp: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-mtlp-6/igt@gem_eio@in-flight-internal-1us.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-mtlp-2/igt@gem_eio@in-flight-internal-1us.html
* igt@gem_exec_suspend@basic-s3:
- shard-tglu-1: NOTRUN -> [ABORT][3] +1 other test abort
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@gem_exec_suspend@basic-s3.html
* igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-1-size-128:
- shard-rkl: NOTRUN -> [FAIL][4] +1 other test fail
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-1-size-128.html
* igt@kms_plane_cursor@viewport:
- shard-tglu-1: NOTRUN -> [FAIL][5] +3 other tests fail
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane_cursor@viewport.html
Known issues
------------
Here are the changes found in Patchwork_159131v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance:
- shard-rkl: NOTRUN -> [DMESG-WARN][6] ([i915#15095]) +1 other test dmesg-warn
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@drm_buddy@drm_buddy@drm_test_buddy_fragmentation_performance.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-tglu: NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@suspend-resume:
- shard-dg2: [PASS][8] -> [INCOMPLETE][9] ([i915#13356]) +1 other test incomplete
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@gem_ccs@suspend-resume.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-1/igt@gem_ccs@suspend-resume.html
- shard-tglu: NOTRUN -> [SKIP][10] ([i915#9323])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@gem_ccs@suspend-resume.html
* igt@gem_create@create-ext-set-pat:
- shard-tglu-1: NOTRUN -> [SKIP][11] ([i915#8562])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_sseu@engines:
- shard-tglu-1: NOTRUN -> [SKIP][12] ([i915#280])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@gem_ctx_sseu@engines.html
* igt@gem_ctx_sseu@mmap-args:
- shard-rkl: NOTRUN -> [SKIP][13] ([i915#280])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@gem_ctx_sseu@mmap-args.html
* igt@gem_exec_balancer@parallel-keep-in-fence:
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#4525])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@gem_exec_balancer@parallel-keep-in-fence.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-tglu: NOTRUN -> [SKIP][15] ([i915#4525])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-rkl: NOTRUN -> [SKIP][16] ([i915#3281]) +3 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_lmem_swapping@heavy-random:
- shard-glk: NOTRUN -> [SKIP][17] ([i915#4613]) +4 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk6/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@heavy-verify-random:
- shard-tglu: NOTRUN -> [SKIP][18] ([i915#4613]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@gem_lmem_swapping@heavy-verify-random.html
* igt@gem_lmem_swapping@parallel-random-verify:
- shard-tglu-1: NOTRUN -> [SKIP][19] ([i915#4613]) +1 other test skip
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#4613]) +2 other tests skip
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_pxp@hw-rejects-pxp-buffer:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#13717])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@gem_pxp@hw-rejects-pxp-buffer.html
* igt@gem_pxp@hw-rejects-pxp-context:
- shard-tglu: NOTRUN -> [SKIP][22] ([i915#13398])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@gem_pxp@hw-rejects-pxp-context.html
* igt@gem_set_tiling_vs_pwrite:
- shard-rkl: NOTRUN -> [SKIP][23] ([i915#3282]) +2 other tests skip
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@gem_set_tiling_vs_pwrite.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#3297] / [i915#3323])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-rkl: NOTRUN -> [SKIP][25] ([i915#3297])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@unsync-unmap-after-close:
- shard-tglu-1: NOTRUN -> [SKIP][26] ([i915#3297])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume:
- shard-glk: [PASS][27] -> [INCOMPLETE][28] ([i915#13356] / [i915#14586])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-glk5/igt@gem_workarounds@suspend-resume.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk1/igt@gem_workarounds@suspend-resume.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglu-1: NOTRUN -> [SKIP][29] ([i915#2527] / [i915#2856])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@bb-start-param:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#2527]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@gen9_exec_parse@bb-start-param.html
* igt@gen9_exec_parse@shadow-peek:
- shard-tglu: NOTRUN -> [SKIP][31] ([i915#2527] / [i915#2856]) +2 other tests skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_module_load@fault-injection:
- shard-glk10: NOTRUN -> [ABORT][32] ([i915#15342] / [i915#15481])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@i915_module_load@fault-injection.html
* igt@i915_module_load@fault-injection@i915_driver_hw_probe:
- shard-glk10: NOTRUN -> [ABORT][33] ([i915#15481])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@i915_module_load@fault-injection@i915_driver_hw_probe.html
* igt@i915_module_load@fault-injection@intel_connector_register:
- shard-glk10: NOTRUN -> [DMESG-WARN][34] ([i915#15342])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@i915_module_load@fault-injection@intel_connector_register.html
* igt@i915_module_load@fault-injection@intel_gt_init-enodev:
- shard-glk10: NOTRUN -> [SKIP][35] +46 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@i915_module_load@fault-injection@intel_gt_init-enodev.html
* igt@i915_pm_freq_api@freq-reset:
- shard-rkl: NOTRUN -> [SKIP][36] ([i915#8399])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@i915_pm_freq_api@freq-reset.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-tglu: NOTRUN -> [SKIP][37] ([i915#6590]) +1 other test skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-tglu: NOTRUN -> [SKIP][38] ([i915#14498])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [PASS][39] -> [ABORT][40] ([i915#15131])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-1/igt@i915_suspend@basic-s3-without-i915.html
- shard-glk: NOTRUN -> [INCOMPLETE][41] ([i915#4817])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk5/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_async_flips@async-flip-suspend-resume:
- shard-dg2: [PASS][42] -> [FAIL][43] ([i915#15285])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-1/igt@kms_async_flips@async-flip-suspend-resume.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@kms_async_flips@async-flip-suspend-resume.html
* igt@kms_async_flips@async-flip-suspend-resume@pipe-b-dp-3:
- shard-dg2: NOTRUN -> [FAIL][44] ([i915#15285])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@kms_async_flips@async-flip-suspend-resume@pipe-b-dp-3.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-tglu-1: NOTRUN -> [SKIP][45] ([i915#5286]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip:
- shard-rkl: NOTRUN -> [SKIP][46] ([i915#5286]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-tglu: NOTRUN -> [SKIP][47] ([i915#5286]) +2 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#3638])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-0:
- shard-dg1: [PASS][49] -> [DMESG-WARN][50] ([i915#4423]) +1 other test dmesg-warn
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-17/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-18/igt@kms_big_fb@y-tiled-64bpp-rotate-0.html
* igt@kms_big_fb@yf-tiled-addfb-size-overflow:
- shard-rkl: NOTRUN -> [SKIP][51] +8 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_big_fb@yf-tiled-addfb-size-overflow.html
* igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
- shard-tglu: NOTRUN -> [SKIP][53] ([i915#12313]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#6095]) +55 other tests skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs@pipe-c-hdmi-a-3.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][55] ([i915#10307] / [i915#6095]) +108 other tests skip
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][56] ([i915#6095]) +24 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html
* igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#14098] / [i915#6095]) +42 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-ccs:
- shard-glk: NOTRUN -> [INCOMPLETE][58] ([i915#15582]) +1 other test incomplete
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk6/igt@kms_ccs@crc-primary-suspend-y-tiled-ccs.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc:
- shard-rkl: [PASS][59] -> [INCOMPLETE][60] ([i915#15582])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [INCOMPLETE][61] ([i915#15582])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-a-hdmi-a-2.html
* igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
- shard-tglu-1: NOTRUN -> [SKIP][62] ([i915#6095]) +29 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-tglu-1: NOTRUN -> [SKIP][63] ([i915#12313]) +1 other test skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
- shard-rkl: NOTRUN -> [SKIP][64] ([i915#12313])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#6095]) +75 other tests skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_ccs@random-ccs-data-y-tiled-ccs@pipe-b-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][66] ([i915#6095]) +207 other tests skip
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#13781]) +3 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-3/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-3.html
* igt@kms_cdclk@plane-scaling:
- shard-tglu: NOTRUN -> [SKIP][68] ([i915#3742])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][69] ([i915#13783]) +3 other tests skip
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-1/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
- shard-tglu: NOTRUN -> [SKIP][70] ([i915#11151] / [i915#7828]) +2 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_edid@hdmi-mode-timings:
- shard-rkl: NOTRUN -> [SKIP][71] ([i915#11151] / [i915#7828]) +3 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_chamelium_edid@hdmi-mode-timings.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-tglu-1: NOTRUN -> [SKIP][72] ([i915#11151] / [i915#7828]) +4 other tests skip
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_color@deep-color:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#12655] / [i915#3555])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_color@deep-color.html
* igt@kms_content_protection@atomic-dpms@pipe-a-dp-3:
- shard-dg2: NOTRUN -> [FAIL][74] ([i915#7173])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@kms_content_protection@atomic-dpms@pipe-a-dp-3.html
* igt@kms_content_protection@atomic-hdcp14:
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#6944])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_content_protection@atomic-hdcp14.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: NOTRUN -> [SKIP][76] ([i915#15330] / [i915#3116])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@dp-mst-type-1-suspend-resume:
- shard-tglu-1: NOTRUN -> [SKIP][77] ([i915#15330])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html
* igt@kms_content_protection@mei-interface:
- shard-tglu-1: NOTRUN -> [SKIP][78] ([i915#6944] / [i915#9424])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@uevent-hdcp14:
- shard-tglu: NOTRUN -> [SKIP][79] ([i915#6944]) +1 other test skip
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_content_protection@uevent-hdcp14.html
* igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1:
- shard-tglu: [PASS][80] -> [FAIL][81] ([i915#13566]) +1 other test fail
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-64x21@pipe-a-hdmi-a-1.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#13049]) +1 other test skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-tglu: NOTRUN -> [SKIP][83] ([i915#13049]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [FAIL][84] ([i915#13566]) +3 other tests fail
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-1.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- shard-tglu: NOTRUN -> [SKIP][85] ([i915#4103]) +1 other test skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size:
- shard-tglu-1: NOTRUN -> [SKIP][86] +30 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_cursor_legacy@cursorb-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#9067])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html
* igt@kms_display_modes@extended-mode-basic:
- shard-tglu-1: NOTRUN -> [SKIP][88] ([i915#13691])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_display_modes@extended-mode-basic.html
* igt@kms_dp_aux_dev:
- shard-dg2: [PASS][89] -> [SKIP][90] ([i915#1257])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@kms_dp_aux_dev.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@kms_dp_aux_dev.html
- shard-tglu-1: NOTRUN -> [SKIP][91] ([i915#1257])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_dp_aux_dev.html
* igt@kms_dp_linktrain_fallback@dsc-fallback:
- shard-tglu-1: NOTRUN -> [SKIP][92] ([i915#13707])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_dp_linktrain_fallback@dsc-fallback.html
* igt@kms_dsc@dsc-with-formats:
- shard-tglu-1: NOTRUN -> [SKIP][93] ([i915#3555] / [i915#3840])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#3555] / [i915#3840])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@dp-mst:
- shard-tglu-1: NOTRUN -> [SKIP][95] ([i915#9337])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr2:
- shard-tglu: NOTRUN -> [SKIP][96] ([i915#658])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-absolute-wf_vblank:
- shard-rkl: NOTRUN -> [SKIP][97] ([i915#9934]) +2 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_flip@2x-absolute-wf_vblank.html
* igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][98] ([i915#9934])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_flip@2x-flip-vs-dpms-on-nop-interruptible.html
* igt@kms_flip@2x-flip-vs-panning-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: NOTRUN -> [INCOMPLETE][99] ([i915#12314]) +1 other test incomplete
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk5/igt@kms_flip@2x-flip-vs-panning-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1:
- shard-snb: [PASS][100] -> [TIMEOUT][101] ([i915#14033]) +1 other test timeout
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-snb7/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-snb4/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
- shard-tglu-1: NOTRUN -> [SKIP][102] ([i915#3637] / [i915#9934]) +5 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-tglu: NOTRUN -> [SKIP][103] ([i915#3637] / [i915#9934]) +1 other test skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3:
- shard-dg2: [PASS][104] -> [FAIL][105] ([i915#13027]) +1 other test fail
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-3/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-6/igt@kms_flip@flip-vs-expired-vblank@a-hdmi-a3.html
* igt@kms_flip@flip-vs-suspend:
- shard-glk10: NOTRUN -> [INCOMPLETE][106] ([i915#12745] / [i915#4839])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
- shard-glk10: NOTRUN -> [INCOMPLETE][107] ([i915#12745])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-tglu-1: NOTRUN -> [SKIP][108] ([i915#2587] / [i915#2672] / [i915#3555])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode:
- shard-tglu-1: NOTRUN -> [SKIP][109] ([i915#2587] / [i915#2672])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
- shard-rkl: NOTRUN -> [SKIP][110] ([i915#2672] / [i915#3555])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#2672])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
- shard-tglu: NOTRUN -> [SKIP][112] ([i915#2672] / [i915#3555]) +2 other tests skip
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][113] ([i915#2587] / [i915#2672]) +2 other tests skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][114] +28 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-rkl: NOTRUN -> [INCOMPLETE][115] ([i915#10056])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-suspend.html
- shard-glk: NOTRUN -> [INCOMPLETE][116] ([i915#10056])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk5/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-rkl: NOTRUN -> [SKIP][117] ([i915#5439])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
- shard-rkl: NOTRUN -> [SKIP][118] ([i915#15102]) +1 other test skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
- shard-rkl: NOTRUN -> [SKIP][119] ([i915#15102] / [i915#3023]) +11 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-glk: NOTRUN -> [SKIP][120] +269 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff:
- shard-rkl: NOTRUN -> [SKIP][121] ([i915#1825]) +10 other tests skip
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt:
- shard-tglu-1: NOTRUN -> [SKIP][122] ([i915#15574]) +2 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-tglu-1: NOTRUN -> [SKIP][123] ([i915#15102]) +10 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
- shard-tglu-1: NOTRUN -> [SKIP][124] ([i915#5439])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-tglu: NOTRUN -> [SKIP][125] ([i915#9766])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu:
- shard-tglu: NOTRUN -> [SKIP][126] ([i915#15102]) +7 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
* igt@kms_hdr@static-swap:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#3555] / [i915#8228]) +1 other test skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_hdr@static-swap.html
* igt@kms_hdr@static-toggle:
- shard-dg2: [PASS][128] -> [SKIP][129] ([i915#3555] / [i915#8228])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@kms_hdr@static-toggle.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@kms_hdr@static-toggle.html
- shard-tglu: NOTRUN -> [SKIP][130] ([i915#3555] / [i915#8228])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_hdr@static-toggle.html
* igt@kms_hdr@static-toggle-dpms:
- shard-rkl: [PASS][131] -> [SKIP][132] ([i915#3555] / [i915#8228])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@kms_hdr@static-toggle-dpms.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@basic-big-joiner:
- shard-tglu: NOTRUN -> [SKIP][133] ([i915#15460])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_joiner@basic-big-joiner.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-rkl: NOTRUN -> [SKIP][134] ([i915#15459])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_joiner@basic-force-ultra-joiner:
- shard-tglu-1: NOTRUN -> [SKIP][135] ([i915#15458])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_joiner@basic-force-ultra-joiner.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-tglu: NOTRUN -> [SKIP][136] ([i915#1839])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5:
- shard-rkl: NOTRUN -> [SKIP][137] ([i915#15608] / [i915#8825]) +3 other tests skip
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_plane@pixel-format-4-tiled-bmg-ccs-modifier@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier@pipe-b-plane-5:
- shard-tglu-1: NOTRUN -> [SKIP][138] ([i915#15608]) +25 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier@pipe-b-plane-7:
- shard-tglu-1: NOTRUN -> [SKIP][139] ([i915#15608] / [i915#8825]) +3 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-dg2-rc-ccs-cc-modifier@pipe-b-plane-7.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
- shard-tglu-1: NOTRUN -> [SKIP][140] ([i915#15608] / [i915#15609] / [i915#8825]) +1 other test skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-b-plane-0:
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#15608]) +9 other tests skip
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier@pipe-b-plane-0.html
* igt@kms_plane@pixel-format-x-tiled-modifier-source-clamping@pipe-b-plane-7:
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#15609]) +1 other test skip
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_plane@pixel-format-x-tiled-modifier-source-clamping@pipe-b-plane-7.html
* igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping@pipe-a-plane-7:
- shard-tglu-1: NOTRUN -> [SKIP][143] ([i915#15609]) +3 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-modifier-source-clamping@pipe-a-plane-7.html
* igt@kms_plane@pixel-format-yf-tiled-ccs-modifier:
- shard-tglu: NOTRUN -> [SKIP][144] ([i915#15608] / [i915#8825]) +1 other test skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html
* igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping@pipe-b-plane-7:
- shard-tglu-1: NOTRUN -> [SKIP][145] ([i915#15609] / [i915#8825]) +1 other test skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier-source-clamping@pipe-b-plane-7.html
* igt@kms_plane@pixel-format-yf-tiled-ccs-modifier@pipe-b-plane-3:
- shard-tglu: NOTRUN -> [SKIP][146] ([i915#15608]) +6 other tests skip
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier@pipe-b-plane-3.html
* igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-1-size-64:
- shard-rkl: NOTRUN -> [FAIL][147] ([i915#15530])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_plane_cursor@overlay@pipe-a-hdmi-a-1-size-64.html
* igt@kms_plane_multiple@2x-tiling-yf:
- shard-tglu: NOTRUN -> [SKIP][148] ([i915#13958])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_plane_multiple@2x-tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size:
- shard-rkl: [PASS][149] -> [SKIP][150] ([i915#6953])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@kms_plane_scaling@intel-max-src-size.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_plane_scaling@intel-max-src-size.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
- shard-tglu-1: NOTRUN -> [SKIP][151] ([i915#15329] / [i915#3555])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b:
- shard-tglu-1: NOTRUN -> [SKIP][152] ([i915#15329]) +3 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b.html
* igt@kms_pm_dc@dc6-psr:
- shard-rkl: NOTRUN -> [SKIP][153] ([i915#9685]) +1 other test skip
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-tglu: NOTRUN -> [SKIP][154] ([i915#15073])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-dg2: [PASS][155] -> [SKIP][156] ([i915#15073])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-4/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-3/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-rkl: [PASS][157] -> [SKIP][158] ([i915#15073])
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@kms_pm_rpm@modeset-non-lpsp.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-tglu-1: NOTRUN -> [SKIP][159] ([i915#15073])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@system-suspend-idle:
- shard-rkl: [PASS][160] -> [INCOMPLETE][161] ([i915#14419])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_pm_rpm@system-suspend-idle.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_pm_rpm@system-suspend-idle.html
* igt@kms_prime@basic-crc-hybrid:
- shard-rkl: NOTRUN -> [SKIP][162] ([i915#6524])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_prime@basic-crc-hybrid.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
- shard-glk: NOTRUN -> [SKIP][163] ([i915#11520]) +5 other tests skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk9/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-tglu: NOTRUN -> [SKIP][164] ([i915#11520]) +2 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
- shard-glk10: NOTRUN -> [SKIP][165] ([i915#11520]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk10/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
- shard-tglu-1: NOTRUN -> [SKIP][166] ([i915#11520]) +4 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#11520]) +2 other tests skip
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-p010:
- shard-tglu: NOTRUN -> [SKIP][168] ([i915#9683])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr@fbc-pr-suspend:
- shard-rkl: NOTRUN -> [SKIP][169] ([i915#1072] / [i915#9732]) +7 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_psr@fbc-pr-suspend.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-tglu-1: NOTRUN -> [SKIP][170] ([i915#9732]) +10 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-tglu: NOTRUN -> [SKIP][171] ([i915#9732]) +9 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-4/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
- shard-tglu-1: NOTRUN -> [SKIP][172] ([i915#5289])
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
- shard-rkl: NOTRUN -> [SKIP][173] ([i915#5289])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
* igt@kms_scaling_modes@scaling-mode-full:
- shard-tglu: NOTRUN -> [SKIP][174] ([i915#3555]) +3 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-9/igt@kms_scaling_modes@scaling-mode-full.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-rkl: NOTRUN -> [SKIP][175] ([i915#3555])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_vblank@ts-continuation-suspend:
- shard-glk: NOTRUN -> [INCOMPLETE][176] ([i915#12276]) +1 other test incomplete
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk9/igt@kms_vblank@ts-continuation-suspend.html
* igt@kms_vrr@flip-dpms:
- shard-tglu-1: NOTRUN -> [SKIP][177] ([i915#3555]) +3 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@kms_vrr@flip-dpms.html
* igt@kms_vrr@flip-suspend:
- shard-rkl: NOTRUN -> [SKIP][178] ([i915#15243] / [i915#3555])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_vrr@flip-suspend.html
* igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
- shard-tglu-1: NOTRUN -> [FAIL][179] ([i915#12910])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3:
- shard-rkl: [INCOMPLETE][180] ([i915#13356]) -> [PASS][181] +1 other test pass
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_ctx_isolation@preservation-s3.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@gem_ctx_isolation@preservation-s3.html
* igt@gem_eio@in-flight-immediate:
- shard-rkl: [ABORT][182] -> [PASS][183]
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-3/igt@gem_eio@in-flight-immediate.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-4/igt@gem_eio@in-flight-immediate.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [ABORT][184] ([i915#5566]) -> [PASS][185]
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-glk5/igt@gen9_exec_parse@allowed-all.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_module_load@load:
- shard-dg1: ([PASS][186], [PASS][187], [PASS][188], [PASS][189], [PASS][190], [PASS][191], [PASS][192], [PASS][193], [PASS][194], [PASS][195], [PASS][196], [PASS][197], [PASS][198], [PASS][199], [PASS][200], [PASS][201], [PASS][202], [PASS][203], [PASS][204], [PASS][205], [PASS][206], [PASS][207], [PASS][208], [SKIP][209]) ([i915#14785]) -> ([PASS][210], [PASS][211], [PASS][212], [PASS][213], [PASS][214], [PASS][215], [PASS][216], [PASS][217], [PASS][218], [PASS][219], [PASS][220], [PASS][221], [PASS][222], [PASS][223], [PASS][224], [PASS][225], [PASS][226], [PASS][227], [PASS][228], [PASS][229], [PASS][230], [PASS][231], [PASS][232], [PASS][233], [PASS][234])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-17/igt@i915_module_load@load.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-13/igt@i915_module_load@load.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-18/igt@i915_module_load@load.html
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-14/igt@i915_module_load@load.html
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-17/igt@i915_module_load@load.html
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-17/igt@i915_module_load@load.html
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@i915_module_load@load.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-18/igt@i915_module_load@load.html
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@i915_module_load@load.html
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-13/igt@i915_module_load@load.html
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-18/igt@i915_module_load@load.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@i915_module_load@load.html
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-12/igt@i915_module_load@load.html
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@i915_module_load@load.html
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-14/igt@i915_module_load@load.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-12/igt@i915_module_load@load.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-14/igt@i915_module_load@load.html
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-17/igt@i915_module_load@load.html
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@i915_module_load@load.html
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-18/igt@i915_module_load@load.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-18/igt@i915_module_load@load.html
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-13/igt@i915_module_load@load.html
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-12/igt@i915_module_load@load.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-14/igt@i915_module_load@load.html
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-12/igt@i915_module_load@load.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-16/igt@i915_module_load@load.html
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-17/igt@i915_module_load@load.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@i915_module_load@load.html
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@i915_module_load@load.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-16/igt@i915_module_load@load.html
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-14/igt@i915_module_load@load.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-17/igt@i915_module_load@load.html
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-18/igt@i915_module_load@load.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@i915_module_load@load.html
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-12/igt@i915_module_load@load.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-17/igt@i915_module_load@load.html
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@i915_module_load@load.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-16/igt@i915_module_load@load.html
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@i915_module_load@load.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-12/igt@i915_module_load@load.html
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-14/igt@i915_module_load@load.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-17/igt@i915_module_load@load.html
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-18/igt@i915_module_load@load.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-14/igt@i915_module_load@load.html
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-18/igt@i915_module_load@load.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-14/igt@i915_module_load@load.html
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-12/igt@i915_module_load@load.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-13/igt@i915_module_load@load.html
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-18/igt@i915_module_load@load.html
- shard-dg2: ([PASS][235], [PASS][236], [PASS][237], [PASS][238], [PASS][239], [PASS][240], [PASS][241], [PASS][242], [PASS][243], [PASS][244], [PASS][245], [PASS][246], [PASS][247], [PASS][248], [PASS][249], [PASS][250], [PASS][251], [PASS][252], [PASS][253], [PASS][254], [PASS][255], [PASS][256], [SKIP][257], [PASS][258]) ([i915#14785]) -> ([PASS][259], [PASS][260], [PASS][261], [PASS][262], [PASS][263], [PASS][264], [PASS][265], [PASS][266], [PASS][267], [PASS][268], [PASS][269], [PASS][270], [PASS][271], [PASS][272], [PASS][273], [PASS][274], [PASS][275], [PASS][276], [PASS][277], [PASS][278], [PASS][279], [PASS][280], [PASS][281], [PASS][282], [PASS][283])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-5/igt@i915_module_load@load.html
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-6/igt@i915_module_load@load.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-1/igt@i915_module_load@load.html
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-8/igt@i915_module_load@load.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-5/igt@i915_module_load@load.html
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-4/igt@i915_module_load@load.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-8/igt@i915_module_load@load.html
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@i915_module_load@load.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-3/igt@i915_module_load@load.html
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-6/igt@i915_module_load@load.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-7/igt@i915_module_load@load.html
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-7/igt@i915_module_load@load.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-3/igt@i915_module_load@load.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-1/igt@i915_module_load@load.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-5/igt@i915_module_load@load.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@i915_module_load@load.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-6/igt@i915_module_load@load.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-7/igt@i915_module_load@load.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-4/igt@i915_module_load@load.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-4/igt@i915_module_load@load.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-1/igt@i915_module_load@load.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@i915_module_load@load.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-8/igt@i915_module_load@load.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-3/igt@i915_module_load@load.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-1/igt@i915_module_load@load.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@i915_module_load@load.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-8/igt@i915_module_load@load.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-4/igt@i915_module_load@load.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@i915_module_load@load.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-7/igt@i915_module_load@load.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-6/igt@i915_module_load@load.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@i915_module_load@load.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-3/igt@i915_module_load@load.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-3/igt@i915_module_load@load.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-7/igt@i915_module_load@load.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-6/igt@i915_module_load@load.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-4/igt@i915_module_load@load.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-3/igt@i915_module_load@load.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-6/igt@i915_module_load@load.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-7/igt@i915_module_load@load.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-4/igt@i915_module_load@load.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-8/igt@i915_module_load@load.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@i915_module_load@load.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@i915_module_load@load.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-3/igt@i915_module_load@load.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@i915_module_load@load.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-8/igt@i915_module_load@load.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-7/igt@i915_module_load@load.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-1/igt@i915_module_load@load.html
- shard-rkl: ([PASS][284], [PASS][285], [PASS][286], [PASS][287], [PASS][288], [PASS][289], [PASS][290], [PASS][291], [PASS][292], [PASS][293], [PASS][294], [PASS][295], [PASS][296], [PASS][297], [PASS][298], [PASS][299], [PASS][300], [PASS][301], [PASS][302], [PASS][303], [PASS][304], [SKIP][305], [PASS][306], [PASS][307]) ([i915#14785]) -> ([PASS][308], [PASS][309], [PASS][310], [PASS][311], [PASS][312], [PASS][313], [PASS][314], [PASS][315], [PASS][316], [PASS][317], [PASS][318], [PASS][319], [PASS][320], [PASS][321], [PASS][322], [PASS][323], [PASS][324], [PASS][325], [PASS][326], [PASS][327], [PASS][328], [PASS][329], [PASS][330], [PASS][331])
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@i915_module_load@load.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-8/igt@i915_module_load@load.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@i915_module_load@load.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-3/igt@i915_module_load@load.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@i915_module_load@load.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@i915_module_load@load.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-3/igt@i915_module_load@load.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@i915_module_load@load.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-8/igt@i915_module_load@load.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-3/igt@i915_module_load@load.html
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-8/igt@i915_module_load@load.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-3/igt@i915_module_load@load.html
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@i915_module_load@load.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@i915_module_load@load.html
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@i915_module_load@load.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-2/igt@i915_module_load@load.html
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@i915_module_load@load.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@i915_module_load@load.html
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@i915_module_load@load.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-2/igt@i915_module_load@load.html
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@i915_module_load@load.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@i915_module_load@load.html
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@i915_module_load@load.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@i915_module_load@load.html
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@i915_module_load@load.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@i915_module_load@load.html
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-4/igt@i915_module_load@load.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@i915_module_load@load.html
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@i915_module_load@load.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@i915_module_load@load.html
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@i915_module_load@load.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@i915_module_load@load.html
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@i915_module_load@load.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@i915_module_load@load.html
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@i915_module_load@load.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-4/igt@i915_module_load@load.html
[320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@i915_module_load@load.html
[321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@i915_module_load@load.html
[322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@i915_module_load@load.html
[323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@i915_module_load@load.html
[324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@i915_module_load@load.html
[325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@i915_module_load@load.html
[326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-4/igt@i915_module_load@load.html
[327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@i915_module_load@load.html
[328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@i915_module_load@load.html
[329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@i915_module_load@load.html
[330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@i915_module_load@load.html
[331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@i915_module_load@load.html
* igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
- shard-dg2: [FAIL][332] ([i915#5956]) -> [PASS][333] +1 other test pass
[332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-3/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
[333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2:
- shard-rkl: [INCOMPLETE][334] ([i915#15582]) -> [PASS][335] +1 other test pass
[334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
[335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-rkl: [ABORT][336] ([i915#15132]) -> [PASS][337]
[336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@kms_fbcon_fbt@fbc-suspend.html
[337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-dg2: [FAIL][338] ([i915#15389] / [i915#6880]) -> [PASS][339]
[338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
[339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_hdr@static-toggle:
- shard-rkl: [SKIP][340] ([i915#3555] / [i915#8228]) -> [PASS][341] +1 other test pass
[340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_hdr@static-toggle.html
[341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_hdr@static-toggle.html
* igt@kms_joiner@basic-force-big-joiner:
- shard-dg2: [SKIP][342] ([i915#15459]) -> [PASS][343]
[342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-1/igt@kms_joiner@basic-force-big-joiner.html
[343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@kms_joiner@basic-force-big-joiner.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][344] ([i915#15073]) -> [PASS][345] +2 other tests pass
[344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@i2c:
- shard-dg1: [DMESG-WARN][346] ([i915#4423]) -> [PASS][347]
[346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@kms_pm_rpm@i2c.html
[347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-17/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg1: [SKIP][348] ([i915#15073]) -> [PASS][349]
[348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp.html
[349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-12/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@perf_pmu@rc6-suspend:
- shard-rkl: [INCOMPLETE][350] ([i915#13520]) -> [PASS][351]
[350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@perf_pmu@rc6-suspend.html
[351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-5/igt@perf_pmu@rc6-suspend.html
#### Warnings ####
* igt@gem_ccs@block-multicopy-inplace:
- shard-rkl: [SKIP][352] ([i915#3555] / [i915#9323]) -> [SKIP][353] ([i915#14544] / [i915#3555] / [i915#9323])
[352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@gem_ccs@block-multicopy-inplace.html
[353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_close_race@multigpu-basic-process:
- shard-rkl: [SKIP][354] ([i915#14544] / [i915#7697]) -> [SKIP][355] ([i915#7697])
[354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_close_race@multigpu-basic-process.html
[355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-rkl: [SKIP][356] ([i915#14544] / [i915#6334]) -> [SKIP][357] ([i915#6334]) +1 other test skip
[356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_exec_capture@capture-invisible@smem0.html
[357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_capture@capture-recoverable:
- shard-rkl: [SKIP][358] ([i915#14544] / [i915#6344]) -> [SKIP][359] ([i915#6344])
[358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_exec_capture@capture-recoverable.html
[359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@gem_exec_capture@capture-recoverable.html
* igt@gem_exec_reloc@basic-write-read-noreloc:
- shard-rkl: [SKIP][360] ([i915#14544] / [i915#3281]) -> [SKIP][361] ([i915#3281]) +3 other tests skip
[360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_exec_reloc@basic-write-read-noreloc.html
[361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@gem_exec_reloc@basic-write-read-noreloc.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-rkl: [SKIP][362] ([i915#3281]) -> [SKIP][363] ([i915#14544] / [i915#3281]) +3 other tests skip
[362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@gem_exec_reloc@basic-write-wc-noreloc.html
[363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_exec_schedule@semaphore-power:
- shard-rkl: [SKIP][364] ([i915#7276]) -> [SKIP][365] ([i915#14544] / [i915#7276])
[364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@gem_exec_schedule@semaphore-power.html
[365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_exec_schedule@semaphore-power.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs:
- shard-rkl: [SKIP][366] ([i915#4613]) -> [SKIP][367] ([i915#14544] / [i915#4613]) +3 other tests skip
[366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
[367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random-ccs.html
* igt@gem_lmem_swapping@massive:
- shard-rkl: [SKIP][368] ([i915#14544] / [i915#4613]) -> [SKIP][369] ([i915#4613])
[368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_lmem_swapping@massive.html
[369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@gem_lmem_swapping@massive.html
* igt@gem_media_vme:
- shard-rkl: [SKIP][370] ([i915#14544] / [i915#284]) -> [SKIP][371] ([i915#284])
[370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_media_vme.html
[371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@gem_media_vme.html
* igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
- shard-rkl: [SKIP][372] ([i915#3282]) -> [SKIP][373] ([i915#14544] / [i915#3282]) +2 other tests skip
[372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
[373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
* igt@gem_pread@snoop:
- shard-rkl: [SKIP][374] ([i915#14544] / [i915#3282]) -> [SKIP][375] ([i915#3282]) +2 other tests skip
[374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_pread@snoop.html
[375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@gem_pread@snoop.html
* igt@gem_softpin@evict-snoop:
- shard-rkl: [SKIP][376] -> [SKIP][377] ([i915#14544]) +5 other tests skip
[376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@gem_softpin@evict-snoop.html
[377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_softpin@evict-snoop.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: [SKIP][378] ([i915#3297]) -> [SKIP][379] ([i915#14544] / [i915#3297])
[378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@gem_userptr_blits@create-destroy-unsync.html
[379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-rkl: [SKIP][380] ([i915#14544] / [i915#3297]) -> [SKIP][381] ([i915#3297])
[380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gem_userptr_blits@unsync-unmap.html
[381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@gem_userptr_blits@unsync-unmap.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-rkl: [SKIP][382] ([i915#14544] / [i915#2527]) -> [SKIP][383] ([i915#2527]) +1 other test skip
[382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@gen9_exec_parse@batch-zero-length.html
[383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@gen9_exec_parse@batch-zero-length.html
* igt@gen9_exec_parse@shadow-peek:
- shard-rkl: [SKIP][384] ([i915#2527]) -> [SKIP][385] ([i915#14544] / [i915#2527]) +2 other tests skip
[384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@gen9_exec_parse@shadow-peek.html
[385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@gen9_exec_parse@shadow-peek.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-rkl: [SKIP][386] ([i915#6590]) -> [SKIP][387] ([i915#14544] / [i915#6590]) +1 other test skip
[386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@i915_pm_freq_mult@media-freq@gt0.html
[387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-rkl: [SKIP][388] ([i915#14544] / [i915#1769] / [i915#3555]) -> [SKIP][389] ([i915#1769] / [i915#3555])
[388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
[389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-rkl: [SKIP][390] ([i915#5286]) -> [SKIP][391] ([i915#14544] / [i915#5286]) +1 other test skip
[390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
[391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
- shard-rkl: [SKIP][392] ([i915#14544] / [i915#5286]) -> [SKIP][393] ([i915#5286]) +2 other tests skip
[392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
[393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
* igt@kms_big_fb@linear-64bpp-rotate-270:
- shard-rkl: [SKIP][394] ([i915#3638]) -> [SKIP][395] ([i915#14544] / [i915#3638])
[394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_big_fb@linear-64bpp-rotate-270.html
[395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_big_fb@linear-64bpp-rotate-270.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-dg1: [SKIP][396] ([i915#3638] / [i915#4423]) -> [SKIP][397] ([i915#3638])
[396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@kms_big_fb@linear-64bpp-rotate-90.html
[397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-14/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180:
- shard-rkl: [SKIP][398] ([i915#14544]) -> [SKIP][399] +3 other tests skip
[398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
[399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180.html
* igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
- shard-rkl: [SKIP][400] ([i915#12313]) -> [SKIP][401] ([i915#12313] / [i915#14544])
[400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
[401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html
* igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs:
- shard-rkl: [SKIP][402] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][403] ([i915#14098] / [i915#6095]) +6 other tests skip
[402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
[403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_ccs@crc-primary-basic-y-tiled-gen12-mc-ccs.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: [SKIP][404] ([i915#14544] / [i915#6095]) -> [SKIP][405] ([i915#6095]) +5 other tests skip
[404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html
[405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs:
- shard-rkl: [SKIP][406] ([i915#14098] / [i915#6095]) -> [SKIP][407] ([i915#14098] / [i915#14544] / [i915#6095]) +15 other tests skip
[406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
[407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: [SKIP][408] ([i915#6095]) -> [SKIP][409] ([i915#14544] / [i915#6095]) +15 other tests skip
[408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
[409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: [SKIP][410] ([i915#3742]) -> [SKIP][411] ([i915#14544] / [i915#3742])
[410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@kms_cdclk@plane-scaling.html
[411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_cdclk@plane-scaling.html
* igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
- shard-rkl: [SKIP][412] ([i915#11151] / [i915#7828]) -> [SKIP][413] ([i915#11151] / [i915#14544] / [i915#7828]) +2 other tests skip
[412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
[413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html
* igt@kms_chamelium_edid@vga-edid-read:
- shard-rkl: [SKIP][414] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][415] ([i915#11151] / [i915#7828]) +1 other test skip
[414]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_chamelium_edid@vga-edid-read.html
[415]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_chamelium_edid@vga-edid-read.html
* igt@kms_content_protection@atomic:
- shard-rkl: [SKIP][416] ([i915#6944] / [i915#7118] / [i915#9424]) -> [SKIP][417] ([i915#14544] / [i915#6944] / [i915#7118] / [i915#9424])
[416]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_content_protection@atomic.html
[417]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg2: [SKIP][418] ([i915#6944] / [i915#7118] / [i915#9424]) -> [FAIL][419] ([i915#7173])
[418]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-4/igt@kms_content_protection@atomic-dpms.html
[419]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@atomic-dpms-hdcp14:
- shard-dg2: [FAIL][420] ([i915#7173]) -> [SKIP][421] ([i915#6944])
[420]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-11/igt@kms_content_protection@atomic-dpms-hdcp14.html
[421]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-5/igt@kms_content_protection@atomic-dpms-hdcp14.html
- shard-rkl: [SKIP][422] ([i915#6944]) -> [SKIP][423] ([i915#14544] / [i915#6944])
[422]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_content_protection@atomic-dpms-hdcp14.html
[423]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_content_protection@atomic-dpms-hdcp14.html
* igt@kms_cursor_crc@cursor-random-max-size:
- shard-rkl: [SKIP][424] ([i915#14544] / [i915#3555]) -> [SKIP][425] ([i915#3555])
[424]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_cursor_crc@cursor-random-max-size.html
[425]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_cursor_crc@cursor-random-max-size.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-rkl: [SKIP][426] ([i915#3555]) -> [SKIP][427] ([i915#14544] / [i915#3555]) +5 other tests skip
[426]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
[427]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-rkl: [SKIP][428] ([i915#4103]) -> [SKIP][429] ([i915#14544] / [i915#4103])
[428]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
[429]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
- shard-rkl: [SKIP][430] ([i915#14544] / [i915#4103]) -> [SKIP][431] ([i915#4103])
[430]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
[431]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html
* igt@kms_dp_link_training@uhbr-mst:
- shard-rkl: [SKIP][432] ([i915#13748]) -> [SKIP][433] ([i915#13748] / [i915#14544])
[432]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_dp_link_training@uhbr-mst.html
[433]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_dp_link_training@uhbr-mst.html
* igt@kms_dsc@dsc-basic:
- shard-rkl: [SKIP][434] ([i915#14544] / [i915#3555] / [i915#3840]) -> [SKIP][435] ([i915#3555] / [i915#3840]) +1 other test skip
[434]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_dsc@dsc-basic.html
[435]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_dsc@dsc-basic.html
* igt@kms_dsc@dsc-fractional-bpp:
- shard-rkl: [SKIP][436] ([i915#3840]) -> [SKIP][437] ([i915#14544] / [i915#3840])
[436]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_dsc@dsc-fractional-bpp.html
[437]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_dsc@dsc-fractional-bpp.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-rkl: [SKIP][438] ([i915#3555] / [i915#3840]) -> [SKIP][439] ([i915#14544] / [i915#3555] / [i915#3840])
[438]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-5/igt@kms_dsc@dsc-with-output-formats.html
[439]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@psr2:
- shard-rkl: [SKIP][440] ([i915#658]) -> [SKIP][441] ([i915#14544] / [i915#658])
[440]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_feature_discovery@psr2.html
[441]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-dpms:
- shard-rkl: [SKIP][442] ([i915#14544] / [i915#9934]) -> [SKIP][443] ([i915#9934]) +3 other tests skip
[442]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_flip@2x-flip-vs-dpms.html
[443]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_flip@2x-flip-vs-dpms.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-rkl: [SKIP][444] ([i915#9934]) -> [SKIP][445] ([i915#14544] / [i915#9934]) +4 other tests skip
[444]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_flip@2x-plain-flip-interruptible.html
[445]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
- shard-rkl: [SKIP][446] ([i915#14544] / [i915#2672]) -> [SKIP][447] ([i915#2672]) +2 other tests skip
[446]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
[447]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling:
- shard-rkl: [SKIP][448] ([i915#14544] / [i915#2672] / [i915#3555]) -> [SKIP][449] ([i915#2672] / [i915#3555]) +2 other tests skip
[448]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html
[449]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
- shard-rkl: [SKIP][450] ([i915#14544] / [i915#1825]) -> [SKIP][451] ([i915#1825]) +7 other tests skip
[450]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
[451]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-cpu:
- shard-rkl: [SKIP][452] ([i915#14544] / [i915#15574]) -> [SKIP][453] ([i915#15574])
[452]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-cpu.html
[453]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_frontbuffer_tracking@fbc-abgr161616f-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
- shard-rkl: [SKIP][454] ([i915#15102]) -> [SKIP][455] ([i915#14544] / [i915#15102])
[454]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html
[455]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render:
- shard-rkl: [SKIP][456] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][457] ([i915#15102] / [i915#3023]) +3 other tests skip
[456]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
[457]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][458] ([i915#15102] / [i915#3458]) -> [SKIP][459] ([i915#10433] / [i915#15102] / [i915#3458]) +1 other test skip
[458]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
[459]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-rte:
- shard-dg2: [SKIP][460] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][461] ([i915#15102] / [i915#3458])
[460]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
[461]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-1p-rte.html
* igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render:
- shard-rkl: [SKIP][462] ([i915#15574]) -> [SKIP][463] ([i915#14544] / [i915#15574])
[462]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html
[463]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-abgr161616f-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-rkl: [SKIP][464] ([i915#15102] / [i915#3023]) -> [SKIP][465] ([i915#14544] / [i915#15102] / [i915#3023]) +6 other tests skip
[464]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
[465]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu:
- shard-rkl: [SKIP][466] ([i915#14544] / [i915#15102]) -> [SKIP][467] ([i915#15102]) +1 other test skip
[466]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html
[467]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: [SKIP][468] ([i915#1825]) -> [SKIP][469] ([i915#14544] / [i915#1825]) +16 other tests skip
[468]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
[469]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_hdr@brightness-with-hdr:
- shard-rkl: [SKIP][470] ([i915#13331] / [i915#14544]) -> [SKIP][471] ([i915#1187] / [i915#12713])
[470]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_hdr@brightness-with-hdr.html
[471]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_hdr@brightness-with-hdr.html
- shard-tglu: [SKIP][472] ([i915#1187] / [i915#12713]) -> [SKIP][473] ([i915#12713])
[472]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-tglu-2/igt@kms_hdr@brightness-with-hdr.html
[473]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-tglu-3/igt@kms_hdr@brightness-with-hdr.html
* igt@kms_pipe_stress@stress-xrgb8888-4tiled:
- shard-rkl: [SKIP][474] ([i915#14712]) -> [SKIP][475] ([i915#14544] / [i915#14712])
[474]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
[475]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_pipe_stress@stress-xrgb8888-4tiled.html
* igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
- shard-rkl: [SKIP][476] ([i915#14544] / [i915#15608] / [i915#8825]) -> [SKIP][477] ([i915#15608] / [i915#8825]) +3 other tests skip
[476]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html
[477]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html
* igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier@pipe-a-plane-0:
- shard-rkl: [SKIP][478] ([i915#14544] / [i915#15608]) -> [SKIP][479] ([i915#15608]) +2 other tests skip
[478]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier@pipe-a-plane-0.html
[479]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier@pipe-a-plane-0.html
* igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping:
- shard-rkl: [SKIP][480] ([i915#15608] / [i915#15609] / [i915#8825]) -> [SKIP][481] ([i915#14544] / [i915#15608] / [i915#15609] / [i915#8825])
[480]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
[481]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping@pipe-a-plane-0:
- shard-rkl: [SKIP][482] ([i915#15608]) -> [SKIP][483] ([i915#14544] / [i915#15608]) +1 other test skip
[482]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping@pipe-a-plane-0.html
[483]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping@pipe-a-plane-0.html
* igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping@pipe-b-plane-5:
- shard-rkl: [SKIP][484] ([i915#15609] / [i915#8825]) -> [SKIP][485] ([i915#14544] / [i915#15609] / [i915#8825])
[484]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping@pipe-b-plane-5.html
[485]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-ccs-modifier-source-clamping@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping:
- shard-rkl: [SKIP][486] ([i915#14544] / [i915#15608] / [i915#15609] / [i915#8825]) -> [SKIP][487] ([i915#15608] / [i915#15609] / [i915#8825])
[486]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html
[487]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping.html
* igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping@pipe-b-plane-5:
- shard-rkl: [SKIP][488] ([i915#14544] / [i915#15609] / [i915#8825]) -> [SKIP][489] ([i915#15609] / [i915#8825])
[488]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping@pipe-b-plane-5.html
[489]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-2/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier-source-clamping@pipe-b-plane-5.html
* igt@kms_plane@pixel-format-yf-tiled-ccs-modifier:
- shard-rkl: [SKIP][490] ([i915#15608] / [i915#8825]) -> [SKIP][491] ([i915#14544] / [i915#15608] / [i915#8825]) +1 other test skip
[490]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html
[491]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_plane@pixel-format-yf-tiled-ccs-modifier.html
* igt@kms_pm_backlight@brightness-with-dpms:
- shard-rkl: [SKIP][492] ([i915#12343] / [i915#14544]) -> [SKIP][493] ([i915#12343])
[492]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html
[493]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_pm_backlight@brightness-with-dpms.html
* igt@kms_pm_lpsp@kms-lpsp:
- shard-rkl: [SKIP][494] ([i915#9340]) -> [SKIP][495] ([i915#3828])
[494]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
[495]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-8/igt@kms_pm_lpsp@kms-lpsp.html
- shard-dg1: [SKIP][496] ([i915#3828]) -> [SKIP][497] ([i915#9340])
[496]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-14/igt@kms_pm_lpsp@kms-lpsp.html
[497]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-12/igt@kms_pm_lpsp@kms-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [SKIP][498] ([i915#15073]) -> [SKIP][499] ([i915#14544] / [i915#15073])
[498]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-4/igt@kms_pm_rpm@modeset-lpsp-stress.html
[499]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf:
- shard-rkl: [SKIP][500] ([i915#11520] / [i915#14544]) -> [SKIP][501] ([i915#11520]) +1 other test skip
[500]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
[501]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_psr2_sf@pr-cursor-plane-move-continuous-exceed-fully-sf.html
* igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
- shard-rkl: [SKIP][502] ([i915#11520]) -> [SKIP][503] ([i915#11520] / [i915#14544]) +4 other tests skip
[502]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
[503]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
* igt@kms_psr@psr-sprite-plane-move:
- shard-rkl: [SKIP][504] ([i915#1072] / [i915#9732]) -> [SKIP][505] ([i915#1072] / [i915#14544] / [i915#9732]) +7 other tests skip
[504]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_psr@psr-sprite-plane-move.html
[505]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_psr@psr-sprite-plane-move.html
* igt@kms_psr@psr2-sprite-mmap-cpu:
- shard-rkl: [SKIP][506] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][507] ([i915#1072] / [i915#9732]) +10 other tests skip
[506]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_psr@psr2-sprite-mmap-cpu.html
[507]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-3/igt@kms_psr@psr2-sprite-mmap-cpu.html
* igt@kms_vrr@flip-basic:
- shard-rkl: [SKIP][508] ([i915#15243] / [i915#3555]) -> [SKIP][509] ([i915#14544] / [i915#15243] / [i915#3555])
[508]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-7/igt@kms_vrr@flip-basic.html
[509]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-6/igt@kms_vrr@flip-basic.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-dg1: [SKIP][510] ([i915#4423] / [i915#9906]) -> [SKIP][511] ([i915#9906])
[510]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg1-16/igt@kms_vrr@seamless-rr-switch-drrs.html
[511]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg1-14/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-rkl: [SKIP][512] ([i915#14544] / [i915#9906]) -> [SKIP][513] ([i915#9906])
[512]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-virtual.html
[513]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@kms_vrr@seamless-rr-switch-virtual.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [FAIL][514] ([i915#3089]) -> [FAIL][515] ([i915#9100]) +1 other test fail
[514]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-dg2-8/igt@perf@non-zero-reason@0-rcs0.html
[515]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-dg2-7/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf@unprivileged-single-ctx-counters:
- shard-rkl: [SKIP][516] ([i915#14544] / [i915#2433]) -> [SKIP][517] ([i915#2433])
[516]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@perf@unprivileged-single-ctx-counters.html
[517]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@perf@unprivileged-single-ctx-counters.html
* igt@perf_pmu@rc6-suspend:
- shard-glk: [INCOMPLETE][518] ([i915#13356]) -> [INCOMPLETE][519] ([i915#13356] / [i915#14242])
[518]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-glk6/igt@perf_pmu@rc6-suspend.html
[519]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-glk5/igt@perf_pmu@rc6-suspend.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: [SKIP][520] ([i915#14544] / [i915#3708]) -> [SKIP][521] ([i915#3708])
[520]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@prime_vgem@fence-write-hang.html
[521]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@prime_vgem@fence-write-hang.html
* igt@sriov_basic@bind-unbind-vf:
- shard-rkl: [SKIP][522] ([i915#14544] / [i915#9917]) -> [SKIP][523] ([i915#9917])
[522]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17907/shard-rkl-6/igt@sriov_basic@bind-unbind-vf.html
[523]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/shard-rkl-7/igt@sriov_basic@bind-unbind-vf.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
[i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
[i915#1187]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1187
[i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
[i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
[i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
[i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
[i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
[i915#12655]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12655
[i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
[i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
[i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
[i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
[i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
[i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
[i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
[i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
[i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
[i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
[i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
[i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
[i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
[i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
[i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
[i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
[i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
[i915#14033]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14033
[i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
[i915#14242]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14242
[i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
[i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
[i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
[i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
[i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
[i915#14785]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14785
[i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
[i915#15095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15095
[i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
[i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
[i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
[i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
[i915#15285]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15285
[i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
[i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
[i915#15342]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15342
[i915#15389]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15389
[i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
[i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
[i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
[i915#15481]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15481
[i915#15530]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15530
[i915#15574]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15574
[i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
[i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
[i915#15609]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15609
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3089]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3089
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
[i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
[i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
[i915#7276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7276
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8825
[i915#9067]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9067
[i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_17907 -> Patchwork_159131v3
CI-20190529: 20190529
CI_DRM_17907: bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8725: 8725
Patchwork_159131v3: bd9c2b8a3a5b7bd8c38108929bfabd7a40dc922b @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159131v3/index.html
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