[Intel-gfx] [PATCH 00/13] drm/i915: Load LUTs with DSB

[Intel-gfx] [PATCH 00/13] drm/i915: Load LUTs with DSB

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Restore DSB usage for lodaing the LUTs, and do so
properly during vblank to avoid tearing. And also
included are some improvements to aid in analyzing
DSB issues.

There is one undocumented (afaik) hw issue with
the legacy LUT that I still need to report to the
hw folks. But I have already included what seems
like an effective workaround.

Ville Syrjälä (13):
  drm/i915/dsb: Define more DSB registers
  drm/i915/dsb: Pimp debug/error prints
  drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()
  drm/i915/dsb: Introduce intel_dsb_finish()
  drm/i915/dsb: Dump the DSB command buffer when DSB fails
  drm/i915/dsb: Allow vblank synchronized DSB execution
  drm/i915/dsb: Nuke the DSB debug
  drm/i915/dsb: Skip DSB command buffer setup if we have no LUTs
  drm/i915/dsb: Don't use DSB to load the LUTs during full modeset
  drm/i915/dsb: Load LUTs using the DSB during vblank
  drm/i915/dsb: Write each legacy LUT entry twice with DSB
  drm/i915/dsb: Load LUTs with the DSB
  drm/i915: Do state check for color management changes

 drivers/gpu/drm/i915/display/intel_color.c    | 46 ++++++++++--
 drivers/gpu/drm/i915/display/intel_color.h    |  2 +
 drivers/gpu/drm/i915/display/intel_crtc.c     |  4 +-
 drivers/gpu/drm/i915/display/intel_display.c  |  3 +
 drivers/gpu/drm/i915/display/intel_dsb.c      | 70 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_dsb.h      |  5 +-
 .../drm/i915/display/intel_modeset_verify.c   |  2 +
 drivers/gpu/drm/i915/i915_reg.h               | 50 ++++++++++++-
 8 files changed, 156 insertions(+), 26 deletions(-)

-- 
2.38.2

[Intel-gfx] [PATCH 01/13] drm/i915/dsb: Define more DSB registers

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add definitions for more DSB registers. Less annoying spec
trawling when working on the DSB code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bad36a67d873..ea2722fdaa41 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8105,8 +8105,54 @@ enum skl_power_gate {
 #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x0)
 #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x4)
 #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x8)
-#define   DSB_ENABLE			(1 << 31)
-#define   DSB_STATUS_BUSY		(1 << 0)
+#define   DSB_ENABLE			REG_BIT(31)
+#define   DSB_BUF_REITERATE		REG_BIT(29)
+#define   DSB_WAIT_FOR_VBLANK		REG_BIT(28)
+#define   DSB_WAIT_FOR_LINE_IN		REG_BIT(27)
+#define   DSB_HALT			REG_BIT(16)
+#define   DSB_NON_POSTED		REG_BIT(8)
+#define   DSB_STATUS_BUSY		REG_BIT(0)
+#define DSB_MMIOCTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
+#define   DSB_MMIO_DEAD_CLOCKS_ENABLE	REG_BIT(31)
+#define   DSB_MMIO_DEAD_CLOCKS_COUNT_MASK	REG_GENMASK(15, 8)
+#define   DSB_MMIO_DEAD_CLOCKS_COUNT(x)	REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))
+#define   DSB_MMIO_CYCLES_MASK		REG_GENMASK(7, 0)
+#define   DSB_MMIO_CYCLES(x)		REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))
+#define DSB_POLLFUNC(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
+#define   DSB_POLL_ENABLE		REG_BIT(31)
+#define   DSB_POLL_WAIT_MASK		REG_GENMASK(30, 23)
+#define   DSB_POLL_WAIT(x)		REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */
+#define   DSB_POLL_COUNT_MASK		REG_GENMASK(22, 15)
+#define   DSB_POLL_COUNT(x)		REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))
+#define DSB_DEBUG(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x14)
+#define DSB_POLLMASK(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
+#define DSB_STATUS(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x24)
+#define DSB_INTERRUPT(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
+#define   DSB_ATS_FAULT_INT_EN		REG_BIT(20)
+#define   DSB_GTT_FAULT_INT_EN		REG_BIT(19)
+#define   DSB_RSPTIMEOUT_INT_EN		REG_BIT(18)
+#define   DSB_POLL_ERR_INT_EN		REG_BIT(17)
+#define   DSB_PROG_INT_EN		REG_BIT(16)
+#define   DSB_ATS_FAULT_INT_STATUS	REG_BIT(4)
+#define   DSB_GTT_FAULT_INT_STATUS	REG_BIT(3)
+#define   DSB_RSPTIMEOUT_INT_STATUS	REG_BIT(2)
+#define   DSB_POLL_ERR_INT_STATUS	REG_BIT(1)
+#define   DSB_PROG_INT_STATUS		REG_BIT(0)
+#define DSB_CURRENT_HEAD(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
+#define DSB_RM_TIMEOUT(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x30)
+#define   DSB_RM_CLAIM_TIMEOUT		REG_BIT(31)
+#define   DSB_RM_READY_TIMEOUT		REG_BIT(30)
+#define   DSB_RM_CLAIM_TIMEOUT_COUNT_MASK	REG_GENMASK(23, 16)
+#define   DSB_RM_CLAIM_TIMEOUT_COUNT(x)	REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */
+#define   DSB_RM_READY_TIMEOUT_VALUE_MASK	REG_GENMASK(15, 0)
+#define   DSB_RM_READY_TIMEOUT_VALUE(x)	REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
+#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
+#define DSB_PMCTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
+#define DSB_PMCTRL_2(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
+#define DSB_PF_LN_LOWER(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x40)
+#define DSB_PF_LN_UPPER(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x44)
+#define DSB_BUFRPT_CNT(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x48)
+#define DSB_CHICKEN(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
 
 #define CLKREQ_POLICY			_MMIO(0x101038)
 #define  CLKREQ_POLICY_MEM_UP_OVRD	REG_BIT(1)
-- 
2.38.2

Re: [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Define more DSB registers

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 01/13] drm/i915/dsb: Define more DSB registers
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Add definitions for more DSB registers. Less annoying spec trawling when
> working on the DSB code.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

The register definition as per bspec and looks good to me.
Some do not have any usage currently. Leaving it your discretion to merge the patch

Reviewed-by: Animesh Manna <animesh.manna@intel.com> 

> ---
>  drivers/gpu/drm/i915/i915_reg.h | 50 +++++++++++++++++++++++++++++++-
> -
>  1 file changed, 48 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h index bad36a67d873..ea2722fdaa41
> 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8105,8 +8105,54 @@ enum skl_power_gate {
>  #define DSB_HEAD(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x0)
>  #define DSB_TAIL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x4)
>  #define DSB_CTRL(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x8)
> -#define   DSB_ENABLE			(1 << 31)
> -#define   DSB_STATUS_BUSY		(1 << 0)
> +#define   DSB_ENABLE			REG_BIT(31)
> +#define   DSB_BUF_REITERATE		REG_BIT(29)
> +#define   DSB_WAIT_FOR_VBLANK		REG_BIT(28)
> +#define   DSB_WAIT_FOR_LINE_IN		REG_BIT(27)
> +#define   DSB_HALT			REG_BIT(16)
> +#define   DSB_NON_POSTED		REG_BIT(8)
> +#define   DSB_STATUS_BUSY		REG_BIT(0)
> +#define DSB_MMIOCTRL(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0xc)
> +#define   DSB_MMIO_DEAD_CLOCKS_ENABLE	REG_BIT(31)
> +#define   DSB_MMIO_DEAD_CLOCKS_COUNT_MASK	REG_GENMASK(15, 8)
> +#define   DSB_MMIO_DEAD_CLOCKS_COUNT(x)
> 	REG_FIELD_PREP(DSB_MMIO_DEAD_CLOCK_COUNT_MASK, (x))
> +#define   DSB_MMIO_CYCLES_MASK		REG_GENMASK(7, 0)
> +#define   DSB_MMIO_CYCLES(x)
> 	REG_FIELD_PREP(DSB_MMIO_CYCLES_MASK, (x))
> +#define DSB_POLLFUNC(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x10)
> +#define   DSB_POLL_ENABLE		REG_BIT(31)
> +#define   DSB_POLL_WAIT_MASK		REG_GENMASK(30, 23)
> +#define   DSB_POLL_WAIT(x)
> 	REG_FIELD_PREP(DSB_POLL_WAIT_MASK, (x)) /* usec */
> +#define   DSB_POLL_COUNT_MASK		REG_GENMASK(22, 15)
> +#define   DSB_POLL_COUNT(x)
> 	REG_FIELD_PREP(DSB_POLL_COUNT_MASK, (x))
> +#define DSB_DEBUG(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x14)
> +#define DSB_POLLMASK(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x1c)
> +#define DSB_STATUS(pipe, id)		_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x24)
> +#define DSB_INTERRUPT(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x28)
> +#define   DSB_ATS_FAULT_INT_EN		REG_BIT(20)
> +#define   DSB_GTT_FAULT_INT_EN		REG_BIT(19)
> +#define   DSB_RSPTIMEOUT_INT_EN		REG_BIT(18)
> +#define   DSB_POLL_ERR_INT_EN		REG_BIT(17)
> +#define   DSB_PROG_INT_EN		REG_BIT(16)
> +#define   DSB_ATS_FAULT_INT_STATUS	REG_BIT(4)
> +#define   DSB_GTT_FAULT_INT_STATUS	REG_BIT(3)
> +#define   DSB_RSPTIMEOUT_INT_STATUS	REG_BIT(2)
> +#define   DSB_POLL_ERR_INT_STATUS	REG_BIT(1)
> +#define   DSB_PROG_INT_STATUS		REG_BIT(0)
> +#define DSB_CURRENT_HEAD(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x2c)
> +#define DSB_RM_TIMEOUT(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x30)
> +#define   DSB_RM_CLAIM_TIMEOUT		REG_BIT(31)
> +#define   DSB_RM_READY_TIMEOUT		REG_BIT(30)
> +#define   DSB_RM_CLAIM_TIMEOUT_COUNT_MASK	REG_GENMASK(23,
> 16)
> +#define   DSB_RM_CLAIM_TIMEOUT_COUNT(x)
> 	REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /*
> clocks */
> +#define   DSB_RM_READY_TIMEOUT_VALUE_MASK	REG_GENMASK(15, 0)
> +#define   DSB_RM_READY_TIMEOUT_VALUE(x)
> 	REG_FIELD_PREP(DSB_RM_READY_TIMEOUT_VALUE, (x)) /* usec */
> +#define DSB_RMTIMEOUTREG_CAPTURE(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x34)
> +#define DSB_PMCTRL(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x38)
> +#define DSB_PMCTRL_2(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0x3c)
> +#define DSB_PF_LN_LOWER(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x40)
> +#define DSB_PF_LN_UPPER(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x44)
> +#define DSB_BUFRPT_CNT(pipe, id)	_MMIO(DSBSL_INSTANCE(pipe, id) +
> 0x48)
> +#define DSB_CHICKEN(pipe, id)
> 	_MMIO(DSBSL_INSTANCE(pipe, id) + 0xf0)
> 
>  #define CLKREQ_POLICY			_MMIO(0x101038)
>  #define  CLKREQ_POLICY_MEM_UP_OVRD	REG_BIT(1)
> --
> 2.38.2

[Intel-gfx] [PATCH 02/13] drm/i915/dsb: Pimp debug/error prints

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Print the crtc/DSB id information to make it clear which DSB engine
we're talking about.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 96bc117fd6a0..f41146fc84d7 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -88,7 +88,8 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
 
 	/* each instruction is 2 dwords */
 	return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2,
-			 "DSB buffer overflow\n");
+			 "[CRTC:%d:%s] DSB %d buffer overflow\n",
+			 crtc->base.base.id, crtc->base.name, dsb->id);
 }
 
 static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
@@ -232,7 +233,8 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 		return;
 
 	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
-		drm_err(&dev_priv->drm, "DSB engine is busy.\n");
+		drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n",
+			crtc->base.base.id, crtc->base.name, dsb->id);
 		goto reset;
 	}
 
@@ -250,7 +252,8 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 
 	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
 		drm_err(&dev_priv->drm,
-			"Timed out waiting for DSB workload completion.\n");
+			"[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
+			crtc->base.base.id, crtc->base.name, dsb->id);
 
 reset:
 	dsb->free_pos = 0;
@@ -325,7 +328,8 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
 	kfree(dsb);
 out:
 	drm_info_once(&i915->drm,
-		      "DSB queue setup failed, will fallback to MMIO for display HW programming\n");
+		      "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to MMIO for display HW programming\n",
+		      crtc->base.base.id, crtc->base.name, DSB1);
 
 	return NULL;
 }
-- 
2.38.2

Re: [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Pimp debug/error prints

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:00 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 02/13] drm/i915/dsb: Pimp debug/error prints
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Print the crtc/DSB id information to make it clear which DSB engine we're
> talking about.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++----
>  1 file changed, 8 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 96bc117fd6a0..f41146fc84d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -88,7 +88,8 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
> 
>  	/* each instruction is 2 dwords */
>  	return !drm_WARN(&i915->drm, dsb->free_pos > dsb->size - 2,
> -			 "DSB buffer overflow\n");
> +			 "[CRTC:%d:%s] DSB %d buffer overflow\n",
> +			 crtc->base.base.id, crtc->base.name, dsb->id);
>  }
> 
>  static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe, @@
> -232,7 +233,8 @@ void intel_dsb_commit(struct intel_dsb *dsb)
>  		return;
> 
>  	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
> -		drm_err(&dev_priv->drm, "DSB engine is busy.\n");
> +		drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n",
> +			crtc->base.base.id, crtc->base.name, dsb->id);
>  		goto reset;
>  	}
> 
> @@ -250,7 +252,8 @@ void intel_dsb_commit(struct intel_dsb *dsb)
> 
>  	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
>  		drm_err(&dev_priv->drm,
> -			"Timed out waiting for DSB workload
> completion.\n");
> +			"[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
> +			crtc->base.base.id, crtc->base.name, dsb->id);
> 
>  reset:
>  	dsb->free_pos = 0;
> @@ -325,7 +328,8 @@ struct intel_dsb *intel_dsb_prepare(struct intel_crtc
> *crtc,
>  	kfree(dsb);
>  out:
>  	drm_info_once(&i915->drm,
> -		      "DSB queue setup failed, will fallback to MMIO for display
> HW programming\n");
> +		      "[CRTC:%d:%s] DSB %d queue setup failed, will fallback to
> MMIO for display HW programming\n",
> +		      crtc->base.base.id, crtc->base.name, DSB1);
> 
>  	return NULL;
>  }
> --
> 2.38.2

[Intel-gfx] [PATCH 03/13] drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Starting the DSB execution vs. waiting for it stop are two
totally different things. Split intel_dsb_wait() from
intel_dsb_commit() so that we can eventually allow the DSB
to execute asynchronously.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c |  4 +++-
 drivers/gpu/drm/i915/display/intel_dsb.c   | 11 +++++++++--
 drivers/gpu/drm/i915/display/intel_dsb.h   |  1 +
 3 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 8d97c299e657..5d99913429b9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1256,8 +1256,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 		break;
 	}
 
-	if (crtc_state->dsb)
+	if (crtc_state->dsb) {
 		intel_dsb_commit(crtc_state->dsb);
+		intel_dsb_wait(crtc_state->dsb);
+	}
 }
 
 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index f41146fc84d7..0b2faa33f204 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -235,7 +235,7 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
 		drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n",
 			crtc->base.base.id, crtc->base.name, dsb->id);
-		goto reset;
+		return;
 	}
 
 	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
@@ -249,13 +249,20 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 		    "DSB execution started - head 0x%x, tail 0x%x\n",
 		    i915_ggtt_offset(dsb->vma),
 		    i915_ggtt_offset(dsb->vma) + tail);
+}
+
+void intel_dsb_wait(struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
 
 	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
 		drm_err(&dev_priv->drm,
 			"[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
 			crtc->base.base.id, crtc->base.name, dsb->id);
 
-reset:
+	/* Attempt to reset it */
 	dsb->free_pos = 0;
 	dsb->ins_start_offset = 0;
 	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0);
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 05c221b6d0a4..7999199c2464 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -19,5 +19,6 @@ void intel_dsb_cleanup(struct intel_dsb *dsb);
 void intel_dsb_reg_write(struct intel_dsb *dsb,
 			 i915_reg_t reg, u32 val);
 void intel_dsb_commit(struct intel_dsb *dsb);
+void intel_dsb_wait(struct intel_dsb *dsb);
 
 #endif
-- 
2.38.2

Re: [Intel-gfx] [PATCH 03/13] drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 03/13] drm/i915/dsb: Split intel_dsb_wait() from
> intel_dsb_commit()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Starting the DSB execution vs. waiting for it stop are two totally different
> things. Split intel_dsb_wait() from
> intel_dsb_commit() so that we can eventually allow the DSB to execute
> asynchronously.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_color.c |  4 +++-
>  drivers/gpu/drm/i915/display/intel_dsb.c   | 11 +++++++++--
>  drivers/gpu/drm/i915/display/intel_dsb.h   |  1 +
>  3 files changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 8d97c299e657..5d99913429b9 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1256,8 +1256,10 @@ static void icl_load_luts(const struct
> intel_crtc_state *crtc_state)
>  		break;
>  	}
> 
> -	if (crtc_state->dsb)
> +	if (crtc_state->dsb) {
>  		intel_dsb_commit(crtc_state->dsb);
> +		intel_dsb_wait(crtc_state->dsb);
> +	}
>  }
> 
>  static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) diff --
> git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index f41146fc84d7..0b2faa33f204 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -235,7 +235,7 @@ void intel_dsb_commit(struct intel_dsb *dsb)
>  	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
>  		drm_err(&dev_priv->drm, "[CRTC:%d:%s] DSB %d is busy\n",
>  			crtc->base.base.id, crtc->base.name, dsb->id);
> -		goto reset;
> +		return;
>  	}
> 
>  	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), @@ -249,13
> +249,20 @@ void intel_dsb_commit(struct intel_dsb *dsb)
>  		    "DSB execution started - head 0x%x, tail 0x%x\n",
>  		    i915_ggtt_offset(dsb->vma),
>  		    i915_ggtt_offset(dsb->vma) + tail);
> +}
> +
> +void intel_dsb_wait(struct intel_dsb *dsb) {
> +	struct intel_crtc *crtc = dsb->crtc;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> 
>  	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
>  		drm_err(&dev_priv->drm,
>  			"[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
>  			crtc->base.base.id, crtc->base.name, dsb->id);
> 
> -reset:
> +	/* Attempt to reset it */
>  	dsb->free_pos = 0;
>  	dsb->ins_start_offset = 0;
>  	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id), 0); diff --git
> a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 05c221b6d0a4..7999199c2464 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -19,5 +19,6 @@ void intel_dsb_cleanup(struct intel_dsb *dsb);  void
> intel_dsb_reg_write(struct intel_dsb *dsb,
>  			 i915_reg_t reg, u32 val);
>  void intel_dsb_commit(struct intel_dsb *dsb);
> +void intel_dsb_wait(struct intel_dsb *dsb);
> 
>  #endif
> --
> 2.38.2

[Intel-gfx] [PATCH 04/13] drm/i915/dsb: Introduce intel_dsb_finish()

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Introduce a function to emits whatever commands we need
at the end of the DSB command buffer. For the moment we
only do the tail cacheline alignment there, but eventually
we might want eg. emit an interrupt.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c |  1 +
 drivers/gpu/drm/i915/display/intel_dsb.c   | 11 +++++++----
 drivers/gpu/drm/i915/display/intel_dsb.h   |  1 +
 3 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 5d99913429b9..6d6d300fa2df 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1257,6 +1257,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 	}
 
 	if (crtc_state->dsb) {
+		intel_dsb_finish(crtc_state->dsb);
 		intel_dsb_commit(crtc_state->dsb);
 		intel_dsb_wait(crtc_state->dsb);
 	}
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 0b2faa33f204..9e25b1345927 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -199,7 +199,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
 	}
 }
 
-static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
+static void intel_dsb_align_tail(struct intel_dsb *dsb)
 {
 	u32 aligned_tail, tail;
 
@@ -211,8 +211,11 @@ static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
 		       aligned_tail - tail);
 
 	dsb->free_pos = aligned_tail / 4;
+}
 
-	return aligned_tail;
+void intel_dsb_finish(struct intel_dsb *dsb)
+{
+	intel_dsb_align_tail(dsb);
 }
 
 /**
@@ -228,8 +231,8 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 	enum pipe pipe = crtc->pipe;
 	u32 tail;
 
-	tail = intel_dsb_align_tail(dsb);
-	if (tail == 0)
+	tail = dsb->free_pos * 4;
+	if (drm_WARN_ON(&dev_priv->drm, !IS_ALIGNED(tail, CACHELINE_BYTES)))
 		return;
 
 	if (is_dsb_busy(dev_priv, pipe, dsb->id)) {
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 7999199c2464..6b22499e8a5d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -15,6 +15,7 @@ struct intel_dsb;
 
 struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
 				    unsigned int max_cmds);
+void intel_dsb_finish(struct intel_dsb *dsb);
 void intel_dsb_cleanup(struct intel_dsb *dsb);
 void intel_dsb_reg_write(struct intel_dsb *dsb,
 			 i915_reg_t reg, u32 val);
-- 
2.38.2

Re: [Intel-gfx] [PATCH 04/13] drm/i915/dsb: Introduce intel_dsb_finish()

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 04/13] drm/i915/dsb: Introduce intel_dsb_finish()
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Introduce a function to emits whatever commands we need at the end of the
> DSB command buffer. For the moment we only do the tail cacheline
> alignment there, but eventually we might want eg. emit an interrupt.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_color.c |  1 +
>  drivers/gpu/drm/i915/display/intel_dsb.c   | 11 +++++++----
>  drivers/gpu/drm/i915/display/intel_dsb.h   |  1 +
>  3 files changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 5d99913429b9..6d6d300fa2df 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1257,6 +1257,7 @@ static void icl_load_luts(const struct
> intel_crtc_state *crtc_state)
>  	}
> 
>  	if (crtc_state->dsb) {
> +		intel_dsb_finish(crtc_state->dsb);
>  		intel_dsb_commit(crtc_state->dsb);
>  		intel_dsb_wait(crtc_state->dsb);
>  	}
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 0b2faa33f204..9e25b1345927 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -199,7 +199,7 @@ void intel_dsb_reg_write(struct intel_dsb *dsb,
>  	}
>  }
> 
> -static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
> +static void intel_dsb_align_tail(struct intel_dsb *dsb)
>  {
>  	u32 aligned_tail, tail;
> 
> @@ -211,8 +211,11 @@ static u32 intel_dsb_align_tail(struct intel_dsb *dsb)
>  		       aligned_tail - tail);
> 
>  	dsb->free_pos = aligned_tail / 4;
> +}
> 
> -	return aligned_tail;
> +void intel_dsb_finish(struct intel_dsb *dsb) {
> +	intel_dsb_align_tail(dsb);
>  }
> 
>  /**
> @@ -228,8 +231,8 @@ void intel_dsb_commit(struct intel_dsb *dsb)
>  	enum pipe pipe = crtc->pipe;
>  	u32 tail;
> 
> -	tail = intel_dsb_align_tail(dsb);
> -	if (tail == 0)
> +	tail = dsb->free_pos * 4;
> +	if (drm_WARN_ON(&dev_priv->drm, !IS_ALIGNED(tail,
> CACHELINE_BYTES)))
>  		return;
> 
>  	if (is_dsb_busy(dev_priv, pipe, dsb->id)) { diff --git
> a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 7999199c2464..6b22499e8a5d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -15,6 +15,7 @@ struct intel_dsb;
> 
>  struct intel_dsb *intel_dsb_prepare(struct intel_crtc *crtc,
>  				    unsigned int max_cmds);
> +void intel_dsb_finish(struct intel_dsb *dsb);
>  void intel_dsb_cleanup(struct intel_dsb *dsb);  void
> intel_dsb_reg_write(struct intel_dsb *dsb,
>  			 i915_reg_t reg, u32 val);
> --
> 2.38.2

[Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command buffer when DSB fails

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Dump the full DSB command buffers and head/tail pointers if the
the DSB hasn't completed its job in time.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 33 +++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 9e25b1345927..f454329b6901 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -92,6 +92,22 @@ static bool assert_dsb_has_room(struct intel_dsb *dsb)
 			 crtc->base.base.id, crtc->base.name, dsb->id);
 }
 
+static void intel_dsb_dump(struct intel_dsb *dsb)
+{
+	struct intel_crtc *crtc = dsb->crtc;
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	const u32 *buf = dsb->cmd_buf;
+	int i;
+
+	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n",
+		    crtc->base.base.id, crtc->base.name, dsb->id);
+	for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
+		drm_dbg_kms(&i915->drm,
+			    " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
+	drm_dbg_kms(&i915->drm, "}\n");
+}
+
 static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
 			enum dsb_id id)
 {
@@ -260,10 +276,21 @@ void intel_dsb_wait(struct intel_dsb *dsb)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 
-	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
+	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
+		u32 offset = i915_ggtt_offset(dsb->vma);
+
+		intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
+			       DSB_ENABLE | DSB_HALT);
+
 		drm_err(&dev_priv->drm,
-			"[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
-			crtc->base.base.id, crtc->base.name, dsb->id);
+			"[CRTC:%d:%s] DSB %d timed out waiting for idle (current head=0x%x, head=0x%x, tail=0x%x)\n",
+			crtc->base.base.id, crtc->base.name, dsb->id,
+			intel_de_read(dev_priv, DSB_CURRENT_HEAD(pipe, dsb->id)) - offset,
+			intel_de_read(dev_priv, DSB_HEAD(pipe, dsb->id)) - offset,
+			intel_de_read(dev_priv, DSB_TAIL(pipe, dsb->id)) - offset);
+
+		intel_dsb_dump(dsb);
+	}
 
 	/* Attempt to reset it */
 	dsb->free_pos = 0;
-- 
2.38.2

Re: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command buffer when DSB fails

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command
> buffer when DSB fails
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Dump the full DSB command buffers and head/tail pointers if the the DSB
> hasn't completed its job in time.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 33 +++++++++++++++++++++---
>  1 file changed, 30 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 9e25b1345927..f454329b6901 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -92,6 +92,22 @@ static bool assert_dsb_has_room(struct intel_dsb
> *dsb)
>  			 crtc->base.base.id, crtc->base.name, dsb->id);  }
> 
> +static void intel_dsb_dump(struct intel_dsb *dsb) {
> +	struct intel_crtc *crtc = dsb->crtc;
> +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> +	const u32 *buf = dsb->cmd_buf;
> +	int i;
> +
> +	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n",
> +		    crtc->base.base.id, crtc->base.name, dsb->id);
> +	for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
> +		drm_dbg_kms(&i915->drm,
> +			    " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
> +			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
> +	drm_dbg_kms(&i915->drm, "}\n");
> +}
> +
>  static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
>  			enum dsb_id id)
>  {
> @@ -260,10 +276,21 @@ void intel_dsb_wait(struct intel_dsb *dsb)
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
> 
> -	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
> +	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
> +		u32 offset = i915_ggtt_offset(dsb->vma);
> +
> +		intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
> +			       DSB_ENABLE | DSB_HALT);

One doubt - Why DSB_ENABLE bit is set here? Is setting DSB_HALT not sufficient.
Other than above the changes look good to me.

Regards,
Animesh

> +
>  		drm_err(&dev_priv->drm,
> -			"[CRTC:%d:%s] DSB %d timed out waiting for idle\n",
> -			crtc->base.base.id, crtc->base.name, dsb->id);
> +			"[CRTC:%d:%s] DSB %d timed out waiting for idle
> (current head=0x%x, head=0x%x, tail=0x%x)\n",
> +			crtc->base.base.id, crtc->base.name, dsb->id,
> +			intel_de_read(dev_priv, DSB_CURRENT_HEAD(pipe,
> dsb->id)) - offset,
> +			intel_de_read(dev_priv, DSB_HEAD(pipe, dsb->id)) -
> offset,
> +			intel_de_read(dev_priv, DSB_TAIL(pipe, dsb->id)) -
> offset);
> +
> +		intel_dsb_dump(dsb);
> +	}
> 
>  	/* Attempt to reset it */
>  	dsb->free_pos = 0;
> --
> 2.38.2

Re: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command buffer when DSB fails

[Ville Syrjälä]

On Thu, Feb 02, 2023 at 05:09:05PM +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Wednesday, January 18, 2023 10:01 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 05/13] drm/i915/dsb: Dump the DSB command
> > buffer when DSB fails
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Dump the full DSB command buffers and head/tail pointers if the the DSB
> > hasn't completed its job in time.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_dsb.c | 33 +++++++++++++++++++++---
> >  1 file changed, 30 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> > b/drivers/gpu/drm/i915/display/intel_dsb.c
> > index 9e25b1345927..f454329b6901 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> > @@ -92,6 +92,22 @@ static bool assert_dsb_has_room(struct intel_dsb
> > *dsb)
> >  			 crtc->base.base.id, crtc->base.name, dsb->id);  }
> > 
> > +static void intel_dsb_dump(struct intel_dsb *dsb) {
> > +	struct intel_crtc *crtc = dsb->crtc;
> > +	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > +	const u32 *buf = dsb->cmd_buf;
> > +	int i;
> > +
> > +	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] DSB %d commands {\n",
> > +		    crtc->base.base.id, crtc->base.name, dsb->id);
> > +	for (i = 0; i < ALIGN(dsb->free_pos, 64 / 4); i += 4)
> > +		drm_dbg_kms(&i915->drm,
> > +			    " 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
> > +			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
> > +	drm_dbg_kms(&i915->drm, "}\n");
> > +}
> > +
> >  static bool is_dsb_busy(struct drm_i915_private *i915, enum pipe pipe,
> >  			enum dsb_id id)
> >  {
> > @@ -260,10 +276,21 @@ void intel_dsb_wait(struct intel_dsb *dsb)
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	enum pipe pipe = crtc->pipe;
> > 
> > -	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1))
> > +	if (wait_for(!is_dsb_busy(dev_priv, pipe, dsb->id), 1)) {
> > +		u32 offset = i915_ggtt_offset(dsb->vma);
> > +
> > +		intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
> > +			       DSB_ENABLE | DSB_HALT);
> 
> One doubt - Why DSB_ENABLE bit is set here? Is setting DSB_HALT not sufficient.
> Other than above the changes look good to me.

Clearing the enable with would reset the DSB, so the halt would
seem superfluous in that case. And I *think* a reset does clear
DSB_CURRENT_HEAD so the debugs wouldn't provide any helpful data
in that case. I'll need to double check that I suppose, but at
least right now my DSB_CURRENT_HEAD does read zero while the DSB
isn't actively executing.

Though I suppose we could make do without the halt entirely and
just read the registers while the DSB might still be making
progress. Admittedly I suppose it still might be even with the
halt as I don't think the halt is instantaneous.

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 06/13] drm/i915/dsb: Allow vblank synchronized DSB execution

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Allow the caller to ask for the DSB commands to execute
during vblank.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 2 +-
 drivers/gpu/drm/i915/display/intel_dsb.c   | 4 +++-
 drivers/gpu/drm/i915/display/intel_dsb.h   | 3 ++-
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 6d6d300fa2df..162d671182e3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1258,7 +1258,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 
 	if (crtc_state->dsb) {
 		intel_dsb_finish(crtc_state->dsb);
-		intel_dsb_commit(crtc_state->dsb);
+		intel_dsb_commit(crtc_state->dsb, false);
 		intel_dsb_wait(crtc_state->dsb);
 	}
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index f454329b6901..43679090eceb 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -237,10 +237,11 @@ void intel_dsb_finish(struct intel_dsb *dsb)
 /**
  * intel_dsb_commit() - Trigger workload execution of DSB.
  * @dsb: DSB context
+ * @wait_for_vblank: wait for vblank before executing
  *
  * This function is used to do actual write to hardware using DSB.
  */
-void intel_dsb_commit(struct intel_dsb *dsb)
+void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
 {
 	struct intel_crtc *crtc = dsb->crtc;
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -258,6 +259,7 @@ void intel_dsb_commit(struct intel_dsb *dsb)
 	}
 
 	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
+		       (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
 		       DSB_ENABLE);
 	intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
 		       i915_ggtt_offset(dsb->vma));
diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h b/drivers/gpu/drm/i915/display/intel_dsb.h
index 6b22499e8a5d..b8148b47022d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.h
+++ b/drivers/gpu/drm/i915/display/intel_dsb.h
@@ -19,7 +19,8 @@ void intel_dsb_finish(struct intel_dsb *dsb);
 void intel_dsb_cleanup(struct intel_dsb *dsb);
 void intel_dsb_reg_write(struct intel_dsb *dsb,
 			 i915_reg_t reg, u32 val);
-void intel_dsb_commit(struct intel_dsb *dsb);
+void intel_dsb_commit(struct intel_dsb *dsb,
+		      bool wait_for_vblank);
 void intel_dsb_wait(struct intel_dsb *dsb);
 
 #endif
-- 
2.38.2

Re: [Intel-gfx] [PATCH 06/13] drm/i915/dsb: Allow vblank synchronized DSB execution

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 06/13] drm/i915/dsb: Allow vblank synchronized
> DSB execution
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Allow the caller to ask for the DSB commands to execute during vblank.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 2 +-
>  drivers/gpu/drm/i915/display/intel_dsb.c   | 4 +++-
>  drivers/gpu/drm/i915/display/intel_dsb.h   | 3 ++-
>  3 files changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 6d6d300fa2df..162d671182e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1258,7 +1258,7 @@ static void icl_load_luts(const struct
> intel_crtc_state *crtc_state)
> 
>  	if (crtc_state->dsb) {
>  		intel_dsb_finish(crtc_state->dsb);
> -		intel_dsb_commit(crtc_state->dsb);
> +		intel_dsb_commit(crtc_state->dsb, false);
>  		intel_dsb_wait(crtc_state->dsb);
>  	}
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index f454329b6901..43679090eceb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -237,10 +237,11 @@ void intel_dsb_finish(struct intel_dsb *dsb)
>  /**
>   * intel_dsb_commit() - Trigger workload execution of DSB.
>   * @dsb: DSB context
> + * @wait_for_vblank: wait for vblank before executing
>   *
>   * This function is used to do actual write to hardware using DSB.
>   */
> -void intel_dsb_commit(struct intel_dsb *dsb)
> +void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
>  {
>  	struct intel_crtc *crtc = dsb->crtc;
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); @@ -
> 258,6 +259,7 @@ void intel_dsb_commit(struct intel_dsb *dsb)
>  	}
> 
>  	intel_de_write(dev_priv, DSB_CTRL(pipe, dsb->id),
> +		       (wait_for_vblank ? DSB_WAIT_FOR_VBLANK : 0) |
>  		       DSB_ENABLE);
>  	intel_de_write(dev_priv, DSB_HEAD(pipe, dsb->id),
>  		       i915_ggtt_offset(dsb->vma));
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.h
> b/drivers/gpu/drm/i915/display/intel_dsb.h
> index 6b22499e8a5d..b8148b47022d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.h
> @@ -19,7 +19,8 @@ void intel_dsb_finish(struct intel_dsb *dsb);  void
> intel_dsb_cleanup(struct intel_dsb *dsb);  void intel_dsb_reg_write(struct
> intel_dsb *dsb,
>  			 i915_reg_t reg, u32 val);
> -void intel_dsb_commit(struct intel_dsb *dsb);
> +void intel_dsb_commit(struct intel_dsb *dsb,
> +		      bool wait_for_vblank);
>  void intel_dsb_wait(struct intel_dsb *dsb);
> 
>  #endif
> --
> 2.38.2

[Intel-gfx] [PATCH 07/13] drm/i915/dsb: Nuke the DSB debug

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We'll be wanting to start the DSB from the vblank evasion critical
section so printk()s are a big nono. Get rid if the debug print.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsb.c | 5 -----
 1 file changed, 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c
index 43679090eceb..96159d69bbff 100644
--- a/drivers/gpu/drm/i915/display/intel_dsb.c
+++ b/drivers/gpu/drm/i915/display/intel_dsb.c
@@ -265,11 +265,6 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool wait_for_vblank)
 		       i915_ggtt_offset(dsb->vma));
 	intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
 		       i915_ggtt_offset(dsb->vma) + tail);
-
-	drm_dbg_kms(&dev_priv->drm,
-		    "DSB execution started - head 0x%x, tail 0x%x\n",
-		    i915_ggtt_offset(dsb->vma),
-		    i915_ggtt_offset(dsb->vma) + tail);
 }
 
 void intel_dsb_wait(struct intel_dsb *dsb)
-- 
2.38.2

Re: [Intel-gfx] [PATCH 07/13] drm/i915/dsb: Nuke the DSB debug

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 07/13] drm/i915/dsb: Nuke the DSB debug
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We'll be wanting to start the DSB from the vblank evasion critical section so
> printk()s are a big nono. Get rid if the debug print.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dsb.c | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c
> b/drivers/gpu/drm/i915/display/intel_dsb.c
> index 43679090eceb..96159d69bbff 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsb.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsb.c
> @@ -265,11 +265,6 @@ void intel_dsb_commit(struct intel_dsb *dsb, bool
> wait_for_vblank)
>  		       i915_ggtt_offset(dsb->vma));
>  	intel_de_write(dev_priv, DSB_TAIL(pipe, dsb->id),
>  		       i915_ggtt_offset(dsb->vma) + tail);
> -
> -	drm_dbg_kms(&dev_priv->drm,
> -		    "DSB execution started - head 0x%x, tail 0x%x\n",
> -		    i915_ggtt_offset(dsb->vma),
> -		    i915_ggtt_offset(dsb->vma) + tail);
>  }
> 
>  void intel_dsb_wait(struct intel_dsb *dsb)
> --
> 2.38.2

[Intel-gfx] [PATCH 08/13] drm/i915/dsb: Skip DSB command buffer setup if we have no LUTs

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

If we have no LUTs to load there is no point in setting up
the DSB command buffer.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 162d671182e3..f4a527a3c265 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1383,6 +1383,9 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
 	/* FIXME DSB has issues loading LUTs, disable it for now */
 	return;
 
+	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
+		return;
+
 	crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
 }
 
-- 
2.38.2

Re: [Intel-gfx] [PATCH 08/13] drm/i915/dsb: Skip DSB command buffer setup if we have no LUTs

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 08/13] drm/i915/dsb: Skip DSB command buffer
> setup if we have no LUTs
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> If we have no LUTs to load there is no point in setting up the DSB command
> buffer.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 162d671182e3..f4a527a3c265 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1383,6 +1383,9 @@ void intel_color_prepare_commit(struct
> intel_crtc_state *crtc_state)
>  	/* FIXME DSB has issues loading LUTs, disable it for now */
>  	return;
> 
> +	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
> +		return;
> +
>  	crtc_state->dsb = intel_dsb_prepare(crtc, 1024);  }
> 
> --
> 2.38.2

[Intel-gfx] [PATCH 09/13] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Using the DSB for LUT loading during full modesets would require
some actual though. Let's just use mmio for the time being.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index f4a527a3c265..cab8dfd03853 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1383,6 +1383,10 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
 	/* FIXME DSB has issues loading LUTs, disable it for now */
 	return;
 
+	if (!crtc_state->hw.active ||
+	    intel_crtc_needs_modeset(crtc_state))
+		return;
+
 	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
 		return;
 
-- 
2.38.2

Re: [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Don't use DSB to load the
> LUTs during full modeset
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Using the DSB for LUT loading during full modesets would require some
> actual though. Let's just use mmio for the time being.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index f4a527a3c265..cab8dfd03853 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1383,6 +1383,10 @@ void intel_color_prepare_commit(struct
> intel_crtc_state *crtc_state)
>  	/* FIXME DSB has issues loading LUTs, disable it for now */
>  	return;
> 
> +	if (!crtc_state->hw.active ||
> +	    intel_crtc_needs_modeset(crtc_state))
> +		return;

Is it causing any issue ? Did not get the advantage of MMIO over DSB during modeset.

Regards,
Animesh

> +
>  	if (!crtc_state->pre_csc_lut && !crtc_state->post_csc_lut)
>  		return;
> 
> --
> 2.38.2

Re: [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Don't use DSB to load the LUTs during full modeset

[Ville Syrjälä]

On Fri, Feb 03, 2023 at 10:04:17AM +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Wednesday, January 18, 2023 10:01 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 09/13] drm/i915/dsb: Don't use DSB to load the
> > LUTs during full modeset
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Using the DSB for LUT loading during full modesets would require some
> > actual though. Let's just use mmio for the time being.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_color.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index f4a527a3c265..cab8dfd03853 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -1383,6 +1383,10 @@ void intel_color_prepare_commit(struct
> > intel_crtc_state *crtc_state)
> >  	/* FIXME DSB has issues loading LUTs, disable it for now */
> >  	return;
> > 
> > +	if (!crtc_state->hw.active ||
> > +	    intel_crtc_needs_modeset(crtc_state))
> > +		return;
> 
> Is it causing any issue ? Did not get the advantage of MMIO over DSB during modeset.

Integrating DSB usage into the modeset path would require actual
thought.

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 10/13] drm/i915/dsb: Load LUTs using the DSB during vblank

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Loading LUTs with the DSB outside of vblank doesn't really
work due to the palette anti-collision logic. Apparently the
DSB register writes don't get stalled like CPU mmio writes
do and instead we end up corrupting the LUT entries. Disabling
the anti-collision logic would allow us to successfully load
the LUT outside of vblank, but presumably that risks the LUT
reads from the scanout (temportarily) getting corrupted data
from the LUT instead.

The anti-collision logic isn't active during vblank so that
is when we can successfully load the LUT with the DSB. That is
what we want to do anyway to avoid tearing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c   | 30 ++++++++++++++++----
 drivers/gpu/drm/i915/display/intel_color.h   |  2 ++
 drivers/gpu/drm/i915/display/intel_crtc.c    |  4 ++-
 drivers/gpu/drm/i915/display/intel_display.c |  3 ++
 4 files changed, 32 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index cab8dfd03853..4c3344ee473e 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1255,12 +1255,6 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 		MISSING_CASE(crtc_state->gamma_mode);
 		break;
 	}
-
-	if (crtc_state->dsb) {
-		intel_dsb_finish(crtc_state->dsb);
-		intel_dsb_commit(crtc_state->dsb, false);
-		intel_dsb_wait(crtc_state->dsb);
-	}
 }
 
 static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color)
@@ -1358,6 +1352,9 @@ void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
+	if (crtc_state->dsb)
+		return;
+
 	i915->display.funcs.color->load_luts(crtc_state);
 }
 
@@ -1374,11 +1371,15 @@ void intel_color_commit_arm(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 
 	i915->display.funcs.color->color_commit_arm(crtc_state);
+
+	if (crtc_state->dsb)
+		intel_dsb_commit(crtc_state->dsb, true);
 }
 
 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
 	/* FIXME DSB has issues loading LUTs, disable it for now */
 	return;
@@ -1391,6 +1392,12 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
 		return;
 
 	crtc_state->dsb = intel_dsb_prepare(crtc, 1024);
+	if (!crtc_state->dsb)
+		return;
+
+	i915->display.funcs.color->load_luts(crtc_state);
+
+	intel_dsb_finish(crtc_state->dsb);
 }
 
 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
@@ -1402,6 +1409,17 @@ void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state)
 	crtc_state->dsb = NULL;
 }
 
+void intel_color_wait_commit(const struct intel_crtc_state *crtc_state)
+{
+	if (crtc_state->dsb)
+		intel_dsb_wait(crtc_state->dsb);
+}
+
+bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state)
+{
+	return crtc_state->dsb;
+}
+
 static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index d620b5b1e2a6..a478606a38d4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -19,6 +19,8 @@ void intel_color_crtc_init(struct intel_crtc *crtc);
 int intel_color_check(struct intel_crtc_state *crtc_state);
 void intel_color_prepare_commit(struct intel_crtc_state *crtc_state);
 void intel_color_cleanup_commit(struct intel_crtc_state *crtc_state);
+bool intel_color_uses_dsb(const struct intel_crtc_state *crtc_state);
+void intel_color_wait_commit(const struct intel_crtc_state *crtc_state);
 void intel_color_commit_noarm(const struct intel_crtc_state *crtc_state);
 void intel_color_commit_arm(const struct intel_crtc_state *crtc_state);
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 82be0fbe9934..764942c843fd 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -24,6 +24,7 @@
 #include "intel_display_trace.h"
 #include "intel_display_types.h"
 #include "intel_drrs.h"
+#include "intel_dsb.h"
 #include "intel_dsi.h"
 #include "intel_pipe_crc.h"
 #include "intel_psr.h"
@@ -387,7 +388,8 @@ static bool intel_crtc_needs_vblank_work(const struct intel_crtc_state *crtc_sta
 	return crtc_state->hw.active &&
 		!intel_crtc_needs_modeset(crtc_state) &&
 		!crtc_state->preload_luts &&
-		intel_crtc_needs_color_update(crtc_state);
+		intel_crtc_needs_color_update(crtc_state) &&
+		!intel_color_uses_dsb(crtc_state);
 }
 
 static void intel_crtc_vblank_work(struct kthread_work *base)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c38a54efedbe..a5f1a4698a78 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -80,6 +80,7 @@
 #include "intel_dpll_mgr.h"
 #include "intel_dpt.h"
 #include "intel_drrs.h"
+#include "intel_dsb.h"
 #include "intel_dsi.h"
 #include "intel_dvo.h"
 #include "intel_fb.h"
@@ -7482,6 +7483,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
 		if (new_crtc_state->do_async_flip)
 			intel_crtc_disable_flip_done(state, crtc);
+
+		intel_color_wait_commit(new_crtc_state);
 	}
 
 	/*
-- 
2.38.2

[Intel-gfx] [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry twice with DSB

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The DSB has problems loading the legacy LUT. Looks like
simply writing each LUT entry twice back-to-back is
sufficient workaround for this.

Curiously it doesn't even matter what data we provide for the
first write, the second write always seems to work 100%. So
this doesn't seem to be some kind of simple race where the data
gets latched before it's actually available on some bus (which
was my first hunch).

TODO: need to figure out what is the actual hw issue here

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 4c3344ee473e..8de2dc4b7904 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -860,9 +860,18 @@ static void ilk_load_lut_8(const struct intel_crtc_state *crtc_state,
 
 	lut = blob->data;
 
-	for (i = 0; i < 256; i++)
+	for (i = 0; i < 256; i++) {
+		/*
+		 * DSB fails to correctly load the legacy
+		 * LUT unless we write each entry twice.
+		 * It doesn't actually matter what data we
+		 * provide for the first write.
+		 */
+		if (crtc_state->dsb)
+			ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), 0);
 		ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
 			      i9xx_lut_8(&lut[i]));
+	}
 }
 
 static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
-- 
2.38.2

Re: [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry twice with DSB

[Manna, Animesh]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> Syrjala
> Sent: Wednesday, January 18, 2023 10:01 PM
> To: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry
> twice with DSB
> 
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The DSB has problems loading the legacy LUT. Looks like simply writing each
> LUT entry twice back-to-back is sufficient workaround for this.
> 
> Curiously it doesn't even matter what data we provide for the first write, the
> second write always seems to work 100%. So this doesn't seem to be some
> kind of simple race where the data gets latched before it's actually available
> on some bus (which was my first hunch).
> 
> TODO: need to figure out what is the actual hw issue here
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index 4c3344ee473e..8de2dc4b7904 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -860,9 +860,18 @@ static void ilk_load_lut_8(const struct
> intel_crtc_state *crtc_state,
> 
>  	lut = blob->data;
> 
> -	for (i = 0; i < 256; i++)
> +	for (i = 0; i < 256; i++) {
> +		/*
> +		 * DSB fails to correctly load the legacy
> +		 * LUT unless we write each entry twice.
> +		 * It doesn't actually matter what data we
> +		 * provide for the first write.
> +		 */

Is it confirmed by hardware team? Is there any difference with indexed register write and single register write.

Regards,
Animesh 

> +		if (crtc_state->dsb)
> +			ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i), 0);
>  		ilk_lut_write(crtc_state, LGC_PALETTE(pipe, i),
>  			      i9xx_lut_8(&lut[i]));
> +	}
>  }
> 
>  static void ilk_load_lut_10(const struct intel_crtc_state *crtc_state,
> --
> 2.38.2

Re: [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry twice with DSB

[Ville Syrjälä]

On Thu, Feb 02, 2023 at 07:05:27PM +0000, Manna, Animesh wrote:
> 
> 
> > -----Original Message-----
> > From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Wednesday, January 18, 2023 10:01 PM
> > To: intel-gfx@lists.freedesktop.org
> > Subject: [Intel-gfx] [PATCH 11/13] drm/i915/dsb: Write each legacy LUT entry
> > twice with DSB
> > 
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > The DSB has problems loading the legacy LUT. Looks like simply writing each
> > LUT entry twice back-to-back is sufficient workaround for this.
> > 
> > Curiously it doesn't even matter what data we provide for the first write, the
> > second write always seems to work 100%. So this doesn't seem to be some
> > kind of simple race where the data gets latched before it's actually available
> > on some bus (which was my first hunch).
> > 
> > TODO: need to figure out what is the actual hw issue here
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_color.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 4c3344ee473e..8de2dc4b7904 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -860,9 +860,18 @@ static void ilk_load_lut_8(const struct
> > intel_crtc_state *crtc_state,
> > 
> >  	lut = blob->data;
> > 
> > -	for (i = 0; i < 256; i++)
> > +	for (i = 0; i < 256; i++) {
> > +		/*
> > +		 * DSB fails to correctly load the legacy
> > +		 * LUT unless we write each entry twice.
> > +		 * It doesn't actually matter what data we
> > +		 * provide for the first write.
> > +		 */
> 
> Is it confirmed by hardware team?

Haven't filed the hsd yet on account of being busy debugging
other DSB issues. But I should do that soon.

> Is there any difference with indexed register write and single register write.

It doesn't matter what kind of write you use. I also tried all
various other tricks (eg. the non-posted write stuff, and just
slowing things down with other registers writes, etc.).

-- 
Ville Syrjälä
Intel

[Intel-gfx] [PATCH 12/13] drm/i915/dsb: Load LUTs with the DSB

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The known DSB vs. LUT issues (anti-collision logic, and
legacy LUT fails) have been dealt with. Use the DSB to
load the LUTs (except during full modesets).

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 8de2dc4b7904..a4103227d060 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1390,9 +1390,6 @@ void intel_color_prepare_commit(struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 
-	/* FIXME DSB has issues loading LUTs, disable it for now */
-	return;
-
 	if (!crtc_state->hw.active ||
 	    intel_crtc_needs_modeset(crtc_state))
 		return;
-- 
2.38.2

[Intel-gfx] [PATCH 13/13] drm/i915: Do state check for color management changes

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

In order to validate LUT programming more thoroughly let's
do a state check for all color management updates as well.

Not sure we really want this outside CI. It is rather heavy
and color management updates could become rather common
with all the HDR/etc. stuff happening. Maybe we should have
an extra knob for this that we could enable in CI?

v2: Skip for initial_commit to avoid FDI dotclock
    sanity checks/etc. tripping up

Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
index 842d70f0dfd2..9e4767e1b900 100644
--- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c
+++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c
@@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc,
 			       struct intel_crtc_state *new_crtc_state)
 {
 	if (!intel_crtc_needs_modeset(new_crtc_state) &&
+	    (!intel_crtc_needs_color_update(new_crtc_state) ||
+	     new_crtc_state->inherited) &&
 	    !intel_crtc_needs_fastset(new_crtc_state))
 		return;
 
-- 
2.38.2

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Load LUTs with DSB

[Patchwork]

== Series Details ==

Series: drm/i915: Load LUTs with DSB
URL   : https://patchwork.freedesktop.org/series/113042/
State : warning

== Summary ==

Error: dim checkpatch failed
dec4d3704799 drm/i915/dsb: Define more DSB registers
-:62: WARNING:LONG_LINE_COMMENT: line length of 105 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/i915_reg.h:8146:
+#define   DSB_RM_CLAIM_TIMEOUT_COUNT(x)	REG_FIELD_PREP(DSB_RM_CLAIM_TIMEOUT_COUNT_MASK, (x)) /* clocks */

total: 0 errors, 1 warnings, 0 checks, 56 lines checked
e9f5449ce908 drm/i915/dsb: Pimp debug/error prints
4f80d4562b76 drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()
819323e99297 drm/i915/dsb: Introduce intel_dsb_finish()
89414f294893 drm/i915/dsb: Dump the DSB command buffer when DSB fails
-:34: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:107:
+			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
 			                        ^

-:34: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:107:
+			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
 			                                  ^

-:34: CHECK:SPACING: spaces preferred around that '+' (ctx:VxV)
#34: FILE: drivers/gpu/drm/i915/display/intel_dsb.c:107:
+			    i * 4, buf[i], buf[i+1], buf[i+2], buf[i+3]);
 			                                            ^

total: 0 errors, 0 warnings, 3 checks, 46 lines checked
0f65ee332a2c drm/i915/dsb: Allow vblank synchronized DSB execution
99a9829d4bc3 drm/i915/dsb: Nuke the DSB debug
e65a662d0456 drm/i915/dsb: Skip DSB command buffer setup if we have no LUTs
9d1bb871a402 drm/i915/dsb: Don't use DSB to load the LUTs during full modeset
41fea74cedcf drm/i915/dsb: Load LUTs using the DSB during vblank
4f8f78ef5490 drm/i915/dsb: Write each legacy LUT entry twice with DSB
ed03d78bd2e1 drm/i915/dsb: Load LUTs with the DSB
a385a359081f drm/i915: Do state check for color management changes

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Load LUTs with DSB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7196 bytes --]

== Series Details ==

Series: drm/i915: Load LUTs with DSB
URL   : https://patchwork.freedesktop.org/series/113042/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12605 -> Patchwork_113042v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/index.html

Participating hosts (43 -> 43)
------------------------------

  Additional (1): fi-kbl-soraka 
  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_113042v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_gttfill@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][1] ([fdo#109271]) +15 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-kbl-soraka/igt@gem_exec_gttfill@basic.html
    - fi-pnv-d510:        [PASS][2] -> [FAIL][3] ([i915#7229])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@basic:
    - fi-kbl-soraka:      NOTRUN -> [SKIP][5] ([fdo#109271] / [i915#4613]) +3 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][6] ([i915#5334] / [i915#7872])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_pm:
    - fi-kbl-soraka:      NOTRUN -> [DMESG-FAIL][7] ([i915#1886])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@guc_multi_lrc:
    - fi-kbl-soraka:      NOTRUN -> [INCOMPLETE][8] ([i915#7640])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-kbl-soraka/igt@i915_selftest@live@guc_multi_lrc.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - fi-rkl-guc:         NOTRUN -> [SKIP][9] ([i915#7828])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-rkl-guc/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions:
    - fi-bsw-n3050:       [PASS][10] -> [FAIL][11] ([i915#6298])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@gt_heartbeat:
    - fi-apl-guc:         [DMESG-FAIL][12] ([i915#5334]) -> [PASS][13]
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@hangcheck:
    - fi-rkl-guc:         [INCOMPLETE][14] ([i915#4983]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-rkl-guc/igt@i915_selftest@live@hangcheck.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size:
    - fi-bsw-n3050:       [FAIL][16] ([i915#6298]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/fi-bsw-n3050/igt@kms_cursor_legacy@basic-busy-flip-before-cursor@atomic-transitions-varying-size.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-3:
    - {bat-dg2-11}:       [INCOMPLETE][18] -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-3.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/bat-dg2-11/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-3.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
  [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
  [i915#6298]: https://gitlab.freedesktop.org/drm/intel/issues/6298
  [i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
  [i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7640]: https://gitlab.freedesktop.org/drm/intel/issues/7640
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7834]: https://gitlab.freedesktop.org/drm/intel/issues/7834
  [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872


Build changes
-------------

  * Linux: CI_DRM_12605 -> Patchwork_113042v1

  CI-20190529: 20190529
  CI_DRM_12605: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7123: 2b29e8ac07fbcfadc48b9d60e4d736a6e3b289ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113042v1: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

241c82c5290a drm/i915: Do state check for color management changes
5924cc0c9183 drm/i915/dsb: Load LUTs with the DSB
381688363c15 drm/i915/dsb: Write each legacy LUT entry twice with DSB
64a66603d770 drm/i915/dsb: Load LUTs using the DSB during vblank
b04b04a402bc drm/i915/dsb: Don't use DSB to load the LUTs during full modeset
2acabd3ffdae drm/i915/dsb: Skip DSB command buffer setup if we have no LUTs
5863cea0971f drm/i915/dsb: Nuke the DSB debug
a9432408431e drm/i915/dsb: Allow vblank synchronized DSB execution
5e92572ee951 drm/i915/dsb: Dump the DSB command buffer when DSB fails
e2001c1b4a4f drm/i915/dsb: Introduce intel_dsb_finish()
b1a4a93019d5 drm/i915/dsb: Split intel_dsb_wait() from intel_dsb_commit()
0a378d82adba drm/i915/dsb: Pimp debug/error prints
5f891361b56d drm/i915/dsb: Define more DSB registers

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/index.html

[-- Attachment #2: Type: text/html, Size: 8200 bytes --]

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Load LUTs with DSB

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 16988 bytes --]

== Series Details ==

Series: drm/i915: Load LUTs with DSB
URL   : https://patchwork.freedesktop.org/series/113042/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12605_full -> Patchwork_113042v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/index.html

Participating hosts (12 -> 10)
------------------------------

  Missing    (2): pig-skl-6260u pig-kbl-iris 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_113042v1_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@kms_big_fb@x-tiled-8bpp-rotate-0:
    - {shard-dg1}:        [PASS][1] -> [DMESG-WARN][2] +6 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-dg1-17/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-dg1-17/igt@kms_big_fb@x-tiled-8bpp-rotate-0.html

  * igt@kms_color@ctm-0-75@pipe-a-hdmi-a-3:
    - {shard-dg1}:        NOTRUN -> [DMESG-WARN][3]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-dg1-19/igt@kms_color@ctm-0-75@pipe-a-hdmi-a-3.html

  * igt@kms_color@ctm-0-75@pipe-c-hdmi-a-3:
    - {shard-dg1}:        NOTRUN -> [DMESG-FAIL][4] +3 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-dg1-19/igt@kms_color@ctm-0-75@pipe-c-hdmi-a-3.html

  * igt@kms_color@legacy-gamma@pipe-c-hdmi-a-4:
    - {shard-dg1}:        [PASS][5] -> [DMESG-FAIL][6] +7 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-dg1-15/igt@kms_color@legacy-gamma@pipe-c-hdmi-a-4.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-dg1-16/igt@kms_color@legacy-gamma@pipe-c-hdmi-a-4.html

  * igt@kms_plane@pixel-format-source-clamping@pipe-a-planes:
    - {shard-dg1}:        [PASS][7] -> [INCOMPLETE][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-dg1-14/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-dg1-14/igt@kms_plane@pixel-format-source-clamping@pipe-a-planes.html

  
Known issues
------------

  Here are the changes found in Patchwork_113042v1_full that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@drm_fdinfo@virtual-idle:
    - {shard-rkl}:        [FAIL][9] ([i915#7742]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html

  * igt@gem_bad_reloc@negative-reloc-lut:
    - {shard-rkl}:        [SKIP][11] ([i915#3281]) -> [PASS][12] +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-3/igt@gem_bad_reloc@negative-reloc-lut.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-5/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_ctx_exec@basic-nohangcheck:
    - {shard-rkl}:        [FAIL][13] ([i915#6268]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html

  * igt@gem_exec_fair@basic-none-share@rcs0:
    - {shard-rkl}:        [FAIL][15] ([i915#2842]) -> [PASS][16] +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-2/igt@gem_exec_fair@basic-none-share@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-5/igt@gem_exec_fair@basic-none-share@rcs0.html

  * igt@gem_set_tiling_vs_pwrite:
    - {shard-rkl}:        [SKIP][17] ([i915#3282]) -> [PASS][18] +3 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-2/igt@gem_set_tiling_vs_pwrite.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-5/igt@gem_set_tiling_vs_pwrite.html

  * igt@gen9_exec_parse@bb-start-far:
    - {shard-rkl}:        [SKIP][19] ([i915#2527]) -> [PASS][20] +2 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-3/igt@gen9_exec_parse@bb-start-far.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-5/igt@gen9_exec_parse@bb-start-far.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-rkl}:        [WARN][21] ([i915#2681]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-glk:          [FAIL][23] ([i915#72]) -> [PASS][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-glk3/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][25] ([i915#79]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-glk6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
    - {shard-rkl}:        [SKIP][27] ([i915#1849] / [i915#4098]) -> [PASS][28] +5 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_pipe_crc_basic@bad-source:
    - {shard-rkl}:        [SKIP][29] ([i915#1845] / [i915#4098]) -> [PASS][30] +6 similar issues
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-1/igt@kms_pipe_crc_basic@bad-source.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-6/igt@kms_pipe_crc_basic@bad-source.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - {shard-rkl}:        [SKIP][31] ([i915#2436]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-rkl-3/igt@perf@gen8-unprivileged-single-ctx-counters.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@sysfs_timeslice_duration@timeout@vcs1:
    - {shard-dg1}:        [FAIL][33] ([i915#1755]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12605/shard-dg1-15/igt@sysfs_timeslice_duration@timeout@vcs1.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/shard-dg1-19/igt@sysfs_timeslice_duration@timeout@vcs1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109312]: https://bugs.freedesktop.org/show_bug.cgi?id=109312
  [fdo#109313]: https://bugs.freedesktop.org/show_bug.cgi?id=109313
  [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110542]: https://bugs.freedesktop.org/show_bug.cgi?id=110542
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
  [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
  [i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
  [i915#2436]: https://gitlab.freedesktop.org/drm/intel/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3639]: https://gitlab.freedesktop.org/drm/intel/issues/3639
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4387]: https://gitlab.freedesktop.org/drm/intel/issues/4387
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5507]: https://gitlab.freedesktop.org/drm/intel/issues/5507
  [i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6227]: https://gitlab.freedesktop.org/drm/intel/issues/6227
  [i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6247]: https://gitlab.freedesktop.org/drm/intel/issues/6247
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/intel/issues/6335
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7128]: https://gitlab.freedesktop.org/drm/intel/issues/7128
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#7294]: https://gitlab.freedesktop.org/drm/intel/issues/7294
  [i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707
  [i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79


Build changes
-------------

  * Linux: CI_DRM_12605 -> Patchwork_113042v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12605: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7123: 2b29e8ac07fbcfadc48b9d60e4d736a6e3b289ab @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_113042v1: 1e863b59056127f55822b29a8f0cabf476806979 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_113042v1/index.html

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