[PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Mohammed Thasleem]

Starting from MTl we don't have a platform agnostic way to validate DC6 state
due to dc6 counter has been removed to validate DC state.
Adding dc6_entry_counter at display dirver to validate dc6 state.

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
 drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
 3 files changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 554870d2494b..cc244617011f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -376,6 +376,7 @@ struct intel_display {
 	struct {
 		struct intel_dmc *dmc;
 		intel_wakeref_t wakeref;
+		u32 dc6_entry_counter;
 	} dmc;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f45a4f9ba23c..0eb178aa618d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
 	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
 
 	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
+
+	display->dmc.dc6_entry_counter++;
 }
 
 void bxt_enable_dc9(struct intel_display *display)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 221d3abda791..f51bd8e6011d 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	if (i915_mmio_reg_valid(dc6_reg))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   intel_de_read(display, dc6_reg));
+	seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
 
 	seq_printf(m, "program base: 0x%08x\n",
 		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
-- 
2.43.0

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Jani Nikula]

On Mon, 03 Feb 2025, Mohammed Thasleem <mohammed.thasleem@intel.com> wrote:
> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> due to dc6 counter has been removed to validate DC state.
> Adding dc6_entry_counter at display dirver to validate dc6 state.
>
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
>  3 files changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..cc244617011f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -376,6 +376,7 @@ struct intel_display {
>  	struct {
>  		struct intel_dmc *dmc;
>  		intel_wakeref_t wakeref;
> +		u32 dc6_entry_counter;
>  	} dmc;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index f45a4f9ba23c..0eb178aa618d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
>  	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
>  
>  	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> +
> +	display->dmc.dc6_entry_counter++;

This file has no business touching the guts of display->dmc.

BR,
Jani.


>  }
>  
>  void bxt_enable_dc9(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 221d3abda791..f51bd8e6011d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	if (i915_mmio_reg_valid(dc6_reg))
>  		seq_printf(m, "DC5 -> DC6 count: %d\n",
>  			   intel_de_read(display, dc6_reg));
> +	seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

-- 
Jani Nikula, Intel

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> due to dc6 counter has been removed to validate DC state.
> Adding dc6_entry_counter at display dirver to validate dc6 state.
> 
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
>  3 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..cc244617011f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -376,6 +376,7 @@ struct intel_display {
>  	struct {
>  		struct intel_dmc *dmc;
>  		intel_wakeref_t wakeref;
> +		u32 dc6_entry_counter;
>  	} dmc;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index f45a4f9ba23c..0eb178aa618d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
>  	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
>  
>  	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> +
> +	display->dmc.dc6_entry_counter++;

AFAIU the goal is to validate that the display HW can reach the DC6
power state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Based on the above, we'd need a DC6 residency counter maintained by the
driver which is incremented if the DC5 residency counter increments
while DC6 is enabled. The dc6_entry_counter in this patch is not enough
for this, since it doesn't take into account the DC5 residency. While
user space could check both dc6_entry_counter and the DC5 residency,
that check would be racy wrt. the driver enabling/disabling the DC6
state asynchronously.

I suppose the driver could take a snapshot of the DC5 residency counter
right after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency += dc5_residency_current - dc5_residency_start

The commit log would need a justification, something along the above
lines.

>  }
>  
>  void bxt_enable_dc9(struct intel_display *display)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 221d3abda791..f51bd8e6011d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	if (i915_mmio_reg_valid(dc6_reg))
>  		seq_printf(m, "DC5 -> DC6 count: %d\n",
>  			   intel_de_read(display, dc6_reg));
> +	seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> -- 
> 2.43.0
> 

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Gustavo Sousa]

Quoting Imre Deak (2025-02-03 09:43:38-03:00)
>On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
>> Starting from MTl we don't have a platform agnostic way to validate DC6 state
>> due to dc6 counter has been removed to validate DC state.
>> Adding dc6_entry_counter at display dirver to validate dc6 state.
>> 
>> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
>>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
>>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
>>  3 files changed, 4 insertions(+)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 554870d2494b..cc244617011f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -376,6 +376,7 @@ struct intel_display {
>>          struct {
>>                  struct intel_dmc *dmc;
>>                  intel_wakeref_t wakeref;
>> +                u32 dc6_entry_counter;
>>          } dmc;
>>  
>>          struct {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index f45a4f9ba23c..0eb178aa618d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
>>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
>>  
>>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
>> +
>> +        display->dmc.dc6_entry_counter++;
>
>AFAIU the goal is to validate that the display HW can reach the DC6
>power state. There is no HW DC6 residency counter (and there wasn't such
>a counter earlier either), so an alternative way is required. According
>to the HW team the display driver has programmed everything correctly in
>order to allow the DC6 power state if the DC5 power state is reached
>(indicated by the HW DC5 residency counter incrementing) and DC6 is
>enabled by the driver.

Yep. That's what I learned as well when looking into this stuff a while
ago.

>
>Based on the above, we'd need a DC6 residency counter maintained by the
>driver which is incremented if the DC5 residency counter increments
>while DC6 is enabled. The dc6_entry_counter in this patch is not enough
>for this, since it doesn't take into account the DC5 residency. While
>user space could check both dc6_entry_counter and the DC5 residency,
>that check would be racy wrt. the driver enabling/disabling the DC6
>state asynchronously.

I'm not sure doing a driver-maintained dc6 entry counter would be
something worth implementing. Even if we have successfully entered DC5
and, in theory, DC6 would follow if enabled, this would be a synthetic
counter and it could be masking some hardware bug that could be
preventing DC6.

On the IGT side, we could just skip if we are on a platform that does
not support DC6 counters, at least while we do not have a reliable
alternative way of checking for DC6.

It would be good if we could detect that PG0 was in fact disabled, which
I believe is a stronger indication of DC6.

--
Gustavo Sousa

>
>I suppose the driver could take a snapshot of the DC5 residency counter
>right after it enables DC6 (dc5_residency_start) and increment the SW
>DC6 residency counter right before it disables DC6 or when user space
>reads the DC6 counter. So the driver would update the counter at these
>two points in the following way:
>dc6_residency += dc5_residency_current - dc5_residency_start
>
>The commit log would need a justification, something along the above
>lines.
>
>>  }
>>  
>>  void bxt_enable_dc9(struct intel_display *display)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index 221d3abda791..f51bd8e6011d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>>          if (i915_mmio_reg_valid(dc6_reg))
>>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
>>                             intel_de_read(display, dc6_reg));
>> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
>>  
>>          seq_printf(m, "program base: 0x%08x\n",
>>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
>> -- 
>> 2.43.0
>>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> >> due to dc6 counter has been removed to validate DC state.
> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> >> 
> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> >>  3 files changed, 4 insertions(+)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index 554870d2494b..cc244617011f 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -376,6 +376,7 @@ struct intel_display {
> >>          struct {
> >>                  struct intel_dmc *dmc;
> >>                  intel_wakeref_t wakeref;
> >> +                u32 dc6_entry_counter;
> >>          } dmc;
> >>  
> >>          struct {
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> index f45a4f9ba23c..0eb178aa618d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> >>  
> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> >> +
> >> +        display->dmc.dc6_entry_counter++;
> >
> >AFAIU the goal is to validate that the display HW can reach the DC6
> >power state. There is no HW DC6 residency counter (and there wasn't such
> >a counter earlier either), so an alternative way is required. According
> >to the HW team the display driver has programmed everything correctly in
> >order to allow the DC6 power state if the DC5 power state is reached
> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> >enabled by the driver.
> 
> Yep. That's what I learned as well when looking into this stuff a while
> ago.
> 
> >Based on the above, we'd need a DC6 residency counter maintained by the
> >driver which is incremented if the DC5 residency counter increments
> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> >for this, since it doesn't take into account the DC5 residency. While
> >user space could check both dc6_entry_counter and the DC5 residency,
> >that check would be racy wrt. the driver enabling/disabling the DC6
> >state asynchronously.
> 
> I'm not sure doing a driver-maintained dc6 entry counter would be
> something worth implementing. Even if we have successfully entered DC5
> and, in theory, DC6 would follow if enabled, this would be a synthetic
> counter and it could be masking some hardware bug that could be
> preventing DC6.

According to the HW team the DC5 residency counter incrementing while
DC6 is enabled is a guarantee that the display is configured correctly
to allow the HW entering DC6 at all times. IOW this is the HW team's
suggestion to validate DC6 at the moment.

> On the IGT side, we could just skip if we are on a platform that does
> not support DC6 counters, at least while we do not have a reliable
> alternative way of checking for DC6.

I think IGT would need to validate DC6 in the above way suggested by the
HW team.

> It would be good if we could detect that PG0 was in fact disabled, which
> I believe is a stronger indication of DC6.

It would be good to have a HW DC6 residency counter, but there isn't one
at the moment. Other ways may have a dependency on other, non-display HW
blocks, for instance in case of shared clock/voltage resources, the
display functionality validation shouldn't be affected by these HW
blocks.

> --
> Gustavo Sousa
> 
> >
> >I suppose the driver could take a snapshot of the DC5 residency counter
> >right after it enables DC6 (dc5_residency_start) and increment the SW
> >DC6 residency counter right before it disables DC6 or when user space
> >reads the DC6 counter. So the driver would update the counter at these
> >two points in the following way:
> >dc6_residency += dc5_residency_current - dc5_residency_start
> >
> >The commit log would need a justification, something along the above
> >lines.
> >
> >>  }
> >>  
> >>  void bxt_enable_dc9(struct intel_display *display)
> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> index 221d3abda791..f51bd8e6011d 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >>          if (i915_mmio_reg_valid(dc6_reg))
> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> >>                             intel_de_read(display, dc6_reg));
> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> >>  
> >>          seq_printf(m, "program base: 0x%08x\n",
> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> >> -- 
> >> 2.43.0
> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Gustavo Sousa]

Quoting Imre Deak (2025-02-03 11:26:19-03:00)
>On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
>> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
>> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
>> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
>> >> due to dc6 counter has been removed to validate DC state.
>> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
>> >> 
>> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>> >> ---
>> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
>> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
>> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
>> >>  3 files changed, 4 insertions(+)
>> >> 
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> index 554870d2494b..cc244617011f 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> @@ -376,6 +376,7 @@ struct intel_display {
>> >>          struct {
>> >>                  struct intel_dmc *dmc;
>> >>                  intel_wakeref_t wakeref;
>> >> +                u32 dc6_entry_counter;
>> >>          } dmc;
>> >>  
>> >>          struct {
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> >> index f45a4f9ba23c..0eb178aa618d 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
>> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
>> >>  
>> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
>> >> +
>> >> +        display->dmc.dc6_entry_counter++;
>> >
>> >AFAIU the goal is to validate that the display HW can reach the DC6
>> >power state. There is no HW DC6 residency counter (and there wasn't such
>> >a counter earlier either), so an alternative way is required. According
>> >to the HW team the display driver has programmed everything correctly in
>> >order to allow the DC6 power state if the DC5 power state is reached
>> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
>> >enabled by the driver.
>> 
>> Yep. That's what I learned as well when looking into this stuff a while
>> ago.
>> 
>> >Based on the above, we'd need a DC6 residency counter maintained by the
>> >driver which is incremented if the DC5 residency counter increments

By the way, the counter that we currently have in our driver is the one
incremented by the DMC. I was meaning to send a patch for the residency
counter maintained by the hardware, but have not yet... In theory, that
one should be more accurate, but would require us to enable and disable
that counter as the IGT test starts and finishes.

>> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
>> >for this, since it doesn't take into account the DC5 residency. While
>> >user space could check both dc6_entry_counter and the DC5 residency,
>> >that check would be racy wrt. the driver enabling/disabling the DC6
>> >state asynchronously.
>> 
>> I'm not sure doing a driver-maintained dc6 entry counter would be
>> something worth implementing. Even if we have successfully entered DC5
>> and, in theory, DC6 would follow if enabled, this would be a synthetic
>> counter and it could be masking some hardware bug that could be
>> preventing DC6.
>
>According to the HW team the DC5 residency counter incrementing while
>DC6 is enabled is a guarantee that the display is configured correctly
>to allow the HW entering DC6 at all times. IOW this is the HW team's
>suggestion to validate DC6 at the moment.
>
>> On the IGT side, we could just skip if we are on a platform that does
>> not support DC6 counters, at least while we do not have a reliable
>> alternative way of checking for DC6.
>
>I think IGT would need to validate DC6 in the above way suggested by the
>HW team.

I'm still inclined to think that we should defer DC6 checking for when
we actually have a way to verify it. The way suggested above sounds
like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.

In that case, just checking for DC5 should be enough for the time
being...

I won't object further if we do the other way though.

>
>> It would be good if we could detect that PG0 was in fact disabled, which
>> I believe is a stronger indication of DC6.
>
>It would be good to have a HW DC6 residency counter, but there isn't one
>at the moment. Other ways may have a dependency on other, non-display HW
>blocks, for instance in case of shared clock/voltage resources, the
>display functionality validation shouldn't be affected by these HW
>blocks.

As far as I understand by reading the docs, DC6 is DC5 with PG0
disabled. That's why my suggestion above.

--
Gustavo Sousa

>
>> --
>> Gustavo Sousa
>> 
>> >
>> >I suppose the driver could take a snapshot of the DC5 residency counter
>> >right after it enables DC6 (dc5_residency_start) and increment the SW
>> >DC6 residency counter right before it disables DC6 or when user space
>> >reads the DC6 counter. So the driver would update the counter at these
>> >two points in the following way:
>> >dc6_residency += dc5_residency_current - dc5_residency_start
>> >
>> >The commit log would need a justification, something along the above
>> >lines.
>> >
>> >>  }
>> >>  
>> >>  void bxt_enable_dc9(struct intel_display *display)
>> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> index 221d3abda791..f51bd8e6011d 100644
>> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>> >>          if (i915_mmio_reg_valid(dc6_reg))
>> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
>> >>                             intel_de_read(display, dc6_reg));
>> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
>> >>  
>> >>          seq_printf(m, "program base: 0x%08x\n",
>> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
>> >> -- 
>> >> 2.43.0
>> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> >> >> due to dc6 counter has been removed to validate DC state.
> >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> >> >> 
> >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> >> >> ---
> >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> >> >>  3 files changed, 4 insertions(+)
> >> >> 
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> index 554870d2494b..cc244617011f 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> @@ -376,6 +376,7 @@ struct intel_display {
> >> >>          struct {
> >> >>                  struct intel_dmc *dmc;
> >> >>                  intel_wakeref_t wakeref;
> >> >> +                u32 dc6_entry_counter;
> >> >>          } dmc;
> >> >>  
> >> >>          struct {
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> >> index f45a4f9ba23c..0eb178aa618d 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> >> >>  
> >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> >> >> +
> >> >> +        display->dmc.dc6_entry_counter++;
> >> >
> >> >AFAIU the goal is to validate that the display HW can reach the DC6
> >> >power state. There is no HW DC6 residency counter (and there wasn't such
> >> >a counter earlier either), so an alternative way is required. According
> >> >to the HW team the display driver has programmed everything correctly in
> >> >order to allow the DC6 power state if the DC5 power state is reached
> >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> >> >enabled by the driver.
> >> 
> >> Yep. That's what I learned as well when looking into this stuff a while
> >> ago.
> >> 
> >> >Based on the above, we'd need a DC6 residency counter maintained by the
> >> >driver which is incremented if the DC5 residency counter increments
> 
> By the way, the counter that we currently have in our driver is the one
> incremented by the DMC. I was meaning to send a patch for the residency
> counter maintained by the hardware, but have not yet... In theory, that
> one should be more accurate, but would require us to enable and disable
> that counter as the IGT test starts and finishes.
> 
> >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> >> >for this, since it doesn't take into account the DC5 residency. While
> >> >user space could check both dc6_entry_counter and the DC5 residency,
> >> >that check would be racy wrt. the driver enabling/disabling the DC6
> >> >state asynchronously.
> >> 
> >> I'm not sure doing a driver-maintained dc6 entry counter would be
> >> something worth implementing. Even if we have successfully entered DC5
> >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> >> counter and it could be masking some hardware bug that could be
> >> preventing DC6.
> >
> >According to the HW team the DC5 residency counter incrementing while
> >DC6 is enabled is a guarantee that the display is configured correctly
> >to allow the HW entering DC6 at all times. IOW this is the HW team's
> >suggestion to validate DC6 at the moment.
> >
> >> On the IGT side, we could just skip if we are on a platform that does
> >> not support DC6 counters, at least while we do not have a reliable
> >> alternative way of checking for DC6.
> >
> >I think IGT would need to validate DC6 in the above way suggested by the
> >HW team.
> 
> I'm still inclined to think that we should defer DC6 checking for when
> we actually have a way to verify it. The way suggested above sounds
> like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> 
> In that case, just checking for DC5 should be enough for the time
> being...

That's not the same as DC5 incrementing while DC6 is enabled.

> I won't object further if we do the other way though.
> 
> >
> >> It would be good if we could detect that PG0 was in fact disabled, which
> >> I believe is a stronger indication of DC6.
> >
> >It would be good to have a HW DC6 residency counter, but there isn't one
> >at the moment. Other ways may have a dependency on other, non-display HW
> >blocks, for instance in case of shared clock/voltage resources, the
> >display functionality validation shouldn't be affected by these HW
> >blocks.
> 
> As far as I understand by reading the docs, DC6 is DC5 with PG0
> disabled. That's why my suggestion above.
> 
> --
> Gustavo Sousa
> 
> >
> >> --
> >> Gustavo Sousa
> >> 
> >> >
> >> >I suppose the driver could take a snapshot of the DC5 residency counter
> >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> >> >DC6 residency counter right before it disables DC6 or when user space
> >> >reads the DC6 counter. So the driver would update the counter at these
> >> >two points in the following way:
> >> >dc6_residency += dc5_residency_current - dc5_residency_start
> >> >
> >> >The commit log would need a justification, something along the above
> >> >lines.
> >> >
> >> >>  }
> >> >>  
> >> >>  void bxt_enable_dc9(struct intel_display *display)
> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> >> index 221d3abda791..f51bd8e6011d 100644
> >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >> >>          if (i915_mmio_reg_valid(dc6_reg))
> >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> >> >>                             intel_de_read(display, dc6_reg));
> >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> >> >>  
> >> >>          seq_printf(m, "program base: 0x%08x\n",
> >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> >> >> -- 
> >> >> 2.43.0
> >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Rodrigo Vivi]

On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > >> >> due to dc6 counter has been removed to validate DC state.
> > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > >> >> 
> > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > >> >> ---
> > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > >> >>  3 files changed, 4 insertions(+)
> > >> >> 
> > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > >> >> index 554870d2494b..cc244617011f 100644
> > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > >> >>          struct {
> > >> >>                  struct intel_dmc *dmc;
> > >> >>                  intel_wakeref_t wakeref;
> > >> >> +                u32 dc6_entry_counter;
> > >> >>          } dmc;
> > >> >>  
> > >> >>          struct {
> > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > >> >>  
> > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > >> >> +
> > >> >> +        display->dmc.dc6_entry_counter++;
> > >> >
> > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > >> >a counter earlier either), so an alternative way is required. According
> > >> >to the HW team the display driver has programmed everything correctly in
> > >> >order to allow the DC6 power state if the DC5 power state is reached
> > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > >> >enabled by the driver.
> > >> 
> > >> Yep. That's what I learned as well when looking into this stuff a while
> > >> ago.
> > >> 
> > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > >> >driver which is incremented if the DC5 residency counter increments
> > 
> > By the way, the counter that we currently have in our driver is the one
> > incremented by the DMC. I was meaning to send a patch for the residency
> > counter maintained by the hardware, but have not yet... In theory, that
> > one should be more accurate, but would require us to enable and disable
> > that counter as the IGT test starts and finishes.
> > 
> > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > >> >for this, since it doesn't take into account the DC5 residency. While
> > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > >> >state asynchronously.
> > >> 
> > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > >> something worth implementing. Even if we have successfully entered DC5
> > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > >> counter and it could be masking some hardware bug that could be
> > >> preventing DC6.
> > >
> > >According to the HW team the DC5 residency counter incrementing while
> > >DC6 is enabled is a guarantee that the display is configured correctly
> > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > >suggestion to validate DC6 at the moment.
> > >
> > >> On the IGT side, we could just skip if we are on a platform that does
> > >> not support DC6 counters, at least while we do not have a reliable
> > >> alternative way of checking for DC6.
> > >
> > >I think IGT would need to validate DC6 in the above way suggested by the
> > >HW team.
> > 
> > I'm still inclined to think that we should defer DC6 checking for when
> > we actually have a way to verify it. The way suggested above sounds
> > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > 
> > In that case, just checking for DC5 should be enough for the time
> > being...
> 
> That's not the same as DC5 incrementing while DC6 is enabled.
> 
> > I won't object further if we do the other way though.
> > 
> > >
> > >> It would be good if we could detect that PG0 was in fact disabled, which
> > >> I believe is a stronger indication of DC6.
> > >
> > >It would be good to have a HW DC6 residency counter, but there isn't one
> > >at the moment. Other ways may have a dependency on other, non-display HW
> > >blocks, for instance in case of shared clock/voltage resources, the
> > >display functionality validation shouldn't be affected by these HW
> > >blocks.
> > 
> > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > disabled. That's why my suggestion above.
> > 
> > --
> > Gustavo Sousa
> > 
> > >
> > >> --
> > >> Gustavo Sousa
> > >> 
> > >> >
> > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > >> >DC6 residency counter right before it disables DC6 or when user space
> > >> >reads the DC6 counter. So the driver would update the counter at these
> > >> >two points in the following way:
> > >> >dc6_residency += dc5_residency_current - dc5_residency_start

Hmm I don't have a good feeling about this.

I prefer that we are clear to the userspace(IGT) that is an extra flag
and not to pretend that we have a residency counter.

So, we either are clear that we are counting the entries, or having
a flag that tells that we are allowing dc6. Which btw, could be done
by IGT checking DC6_EN bit directly, no?!

> > >> >
> > >> >The commit log would need a justification, something along the above
> > >> >lines.
> > >> >
> > >> >>  }
> > >> >>  
> > >> >>  void bxt_enable_dc9(struct intel_display *display)
> > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > >> >> index 221d3abda791..f51bd8e6011d 100644
> > >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> > >> >>          if (i915_mmio_reg_valid(dc6_reg))
> > >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> > >> >>                             intel_de_read(display, dc6_reg));
> > >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> > >> >>  
> > >> >>          seq_printf(m, "program base: 0x%08x\n",
> > >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > >> >> -- 
> > >> >> 2.43.0
> > >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Rodrigo Vivi]

On Mon, Feb 03, 2025 at 11:23:23AM +0200, Jani Nikula wrote:
> On Mon, 03 Feb 2025, Mohammed Thasleem <mohammed.thasleem@intel.com> wrote:
> > Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > due to dc6 counter has been removed to validate DC state.
> > Adding dc6_entry_counter at display dirver to validate dc6 state.
> >
> > Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> >  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> >  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> >  3 files changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 554870d2494b..cc244617011f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -376,6 +376,7 @@ struct intel_display {
> >  	struct {
> >  		struct intel_dmc *dmc;
> >  		intel_wakeref_t wakeref;
> > +		u32 dc6_entry_counter;
> >  	} dmc;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index f45a4f9ba23c..0eb178aa618d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> >  	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> >  
> >  	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > +
> > +	display->dmc.dc6_entry_counter++;
> 
> This file has no business touching the guts of display->dmc.

my bad... I might have suggested that because here we are covering
something up for DMC :)

But yet, maybe better another place of i915_display.

> 
> BR,
> Jani.
> 
> 
> >  }
> >  
> >  void bxt_enable_dc9(struct intel_display *display)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 221d3abda791..f51bd8e6011d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >  	if (i915_mmio_reg_valid(dc6_reg))
> >  		seq_printf(m, "DC5 -> DC6 count: %d\n",
> >  			   intel_de_read(display, dc6_reg));
> > +	seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> >  
> >  	seq_printf(m, "program base: 0x%08x\n",
> >  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> 
> -- 
> Jani Nikula, Intel

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 10:45:58AM -0500, Rodrigo Vivi wrote:
> On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> > On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > > >> >> due to dc6 counter has been removed to validate DC state.
> > > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > > >> >> 
> > > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > > >> >> ---
> > > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > > >> >>  3 files changed, 4 insertions(+)
> > > >> >> 
> > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > >> >> index 554870d2494b..cc244617011f 100644
> > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > > >> >>          struct {
> > > >> >>                  struct intel_dmc *dmc;
> > > >> >>                  intel_wakeref_t wakeref;
> > > >> >> +                u32 dc6_entry_counter;
> > > >> >>          } dmc;
> > > >> >>  
> > > >> >>          struct {
> > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > > >> >>  
> > > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > > >> >> +
> > > >> >> +        display->dmc.dc6_entry_counter++;
> > > >> >
> > > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > > >> >a counter earlier either), so an alternative way is required. According
> > > >> >to the HW team the display driver has programmed everything correctly in
> > > >> >order to allow the DC6 power state if the DC5 power state is reached
> > > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > > >> >enabled by the driver.
> > > >> 
> > > >> Yep. That's what I learned as well when looking into this stuff a while
> > > >> ago.
> > > >> 
> > > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > > >> >driver which is incremented if the DC5 residency counter increments
> > > 
> > > By the way, the counter that we currently have in our driver is the one
> > > incremented by the DMC. I was meaning to send a patch for the residency
> > > counter maintained by the hardware, but have not yet... In theory, that
> > > one should be more accurate, but would require us to enable and disable
> > > that counter as the IGT test starts and finishes.
> > > 
> > > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > > >> >for this, since it doesn't take into account the DC5 residency. While
> > > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > > >> >state asynchronously.
> > > >> 
> > > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > > >> something worth implementing. Even if we have successfully entered DC5
> > > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > > >> counter and it could be masking some hardware bug that could be
> > > >> preventing DC6.
> > > >
> > > >According to the HW team the DC5 residency counter incrementing while
> > > >DC6 is enabled is a guarantee that the display is configured correctly
> > > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > > >suggestion to validate DC6 at the moment.
> > > >
> > > >> On the IGT side, we could just skip if we are on a platform that does
> > > >> not support DC6 counters, at least while we do not have a reliable
> > > >> alternative way of checking for DC6.
> > > >
> > > >I think IGT would need to validate DC6 in the above way suggested by the
> > > >HW team.
> > > 
> > > I'm still inclined to think that we should defer DC6 checking for when
> > > we actually have a way to verify it. The way suggested above sounds
> > > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > > 
> > > In that case, just checking for DC5 should be enough for the time
> > > being...
> > 
> > That's not the same as DC5 incrementing while DC6 is enabled.
> > 
> > > I won't object further if we do the other way though.
> > > 
> > > >
> > > >> It would be good if we could detect that PG0 was in fact disabled, which
> > > >> I believe is a stronger indication of DC6.
> > > >
> > > >It would be good to have a HW DC6 residency counter, but there isn't one
> > > >at the moment. Other ways may have a dependency on other, non-display HW
> > > >blocks, for instance in case of shared clock/voltage resources, the
> > > >display functionality validation shouldn't be affected by these HW
> > > >blocks.
> > > 
> > > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > > disabled. That's why my suggestion above.
> > > 
> > > --
> > > Gustavo Sousa
> > > 
> > > >
> > > >> --
> > > >> Gustavo Sousa
> > > >> 
> > > >> >
> > > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > > >> >DC6 residency counter right before it disables DC6 or when user space
> > > >> >reads the DC6 counter. So the driver would update the counter at these
> > > >> >two points in the following way:
> > > >> >dc6_residency += dc5_residency_current - dc5_residency_start
> 
> Hmm I don't have a good feeling about this.
> 
> I prefer that we are clear to the userspace(IGT) that is an extra flag
> and not to pretend that we have a residency counter.
> 
> So, we either are clear that we are counting the entries, or having
> a flag that tells that we are allowing dc6. Which btw, could be done
> by IGT checking DC6_EN bit directly, no?!

A DC6 enabled check alone would be not enough and checking it from user
space along with the DC5 counter would be racy as described above. I see
this working by the driver tracking the DC6 enabled flag + the DC5
counter in the above way; it could be exposed to user space with a
suitable name, eg. dc6_allowed_time.

> > > >> >The commit log would need a justification, something along the above
> > > >> >lines.
> > > >> >
> > > >> >>  }
> > > >> >>  
> > > >> >>  void bxt_enable_dc9(struct intel_display *display)
> > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > >> >> index 221d3abda791..f51bd8e6011d 100644
> > > >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> > > >> >>          if (i915_mmio_reg_valid(dc6_reg))
> > > >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > >> >>                             intel_de_read(display, dc6_reg));
> > > >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> > > >> >>  
> > > >> >>          seq_printf(m, "program base: 0x%08x\n",
> > > >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > > >> >> -- 
> > > >> >> 2.43.0
> > > >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Rodrigo Vivi]

On Mon, Feb 03, 2025 at 06:01:25PM +0200, Imre Deak wrote:
> On Mon, Feb 03, 2025 at 10:45:58AM -0500, Rodrigo Vivi wrote:
> > On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> > > On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > > > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > > > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > > > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > > > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > > > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > > > >> >> due to dc6 counter has been removed to validate DC state.
> > > > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > > > >> >>
> > > > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > > > >> >> ---
> > > > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > > > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > > > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > > > >> >>  3 files changed, 4 insertions(+)
> > > > >> >>
> > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > >> >> index 554870d2494b..cc244617011f 100644
> > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > > > >> >>          struct {
> > > > >> >>                  struct intel_dmc *dmc;
> > > > >> >>                  intel_wakeref_t wakeref;
> > > > >> >> +                u32 dc6_entry_counter;
> > > > >> >>          } dmc;
> > > > >> >>
> > > > >> >>          struct {
> > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > > > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > > > >> >>
> > > > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > > > >> >> +
> > > > >> >> +        display->dmc.dc6_entry_counter++;
> > > > >> >
> > > > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > > > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > > > >> >a counter earlier either), so an alternative way is required. According
> > > > >> >to the HW team the display driver has programmed everything correctly in
> > > > >> >order to allow the DC6 power state if the DC5 power state is reached
> > > > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > > > >> >enabled by the driver.
> > > > >>
> > > > >> Yep. That's what I learned as well when looking into this stuff a while
> > > > >> ago.
> > > > >>
> > > > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > > > >> >driver which is incremented if the DC5 residency counter increments
> > > >
> > > > By the way, the counter that we currently have in our driver is the one
> > > > incremented by the DMC. I was meaning to send a patch for the residency
> > > > counter maintained by the hardware, but have not yet... In theory, that
> > > > one should be more accurate, but would require us to enable and disable
> > > > that counter as the IGT test starts and finishes.
> > > >
> > > > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > > > >> >for this, since it doesn't take into account the DC5 residency. While
> > > > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > > > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > > > >> >state asynchronously.
> > > > >>
> > > > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > > > >> something worth implementing. Even if we have successfully entered DC5
> > > > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > > > >> counter and it could be masking some hardware bug that could be
> > > > >> preventing DC6.
> > > > >
> > > > >According to the HW team the DC5 residency counter incrementing while
> > > > >DC6 is enabled is a guarantee that the display is configured correctly
> > > > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > > > >suggestion to validate DC6 at the moment.
> > > > >
> > > > >> On the IGT side, we could just skip if we are on a platform that does
> > > > >> not support DC6 counters, at least while we do not have a reliable
> > > > >> alternative way of checking for DC6.
> > > > >
> > > > >I think IGT would need to validate DC6 in the above way suggested by the
> > > > >HW team.
> > > >
> > > > I'm still inclined to think that we should defer DC6 checking for when
> > > > we actually have a way to verify it. The way suggested above sounds
> > > > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > > >
> > > > In that case, just checking for DC5 should be enough for the time
> > > > being...
> > >
> > > That's not the same as DC5 incrementing while DC6 is enabled.
> > >
> > > > I won't object further if we do the other way though.
> > > >
> > > > >
> > > > >> It would be good if we could detect that PG0 was in fact disabled, which
> > > > >> I believe is a stronger indication of DC6.
> > > > >
> > > > >It would be good to have a HW DC6 residency counter, but there isn't one
> > > > >at the moment. Other ways may have a dependency on other, non-display HW
> > > > >blocks, for instance in case of shared clock/voltage resources, the
> > > > >display functionality validation shouldn't be affected by these HW
> > > > >blocks.
> > > >
> > > > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > > > disabled. That's why my suggestion above.
> > > >
> > > > --
> > > > Gustavo Sousa
> > > >
> > > > >
> > > > >> --
> > > > >> Gustavo Sousa
> > > > >>
> > > > >> >
> > > > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > > > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > > > >> >DC6 residency counter right before it disables DC6 or when user space
> > > > >> >reads the DC6 counter. So the driver would update the counter at these
> > > > >> >two points in the following way:
> > > > >> >dc6_residency += dc5_residency_current - dc5_residency_start
> >
> > Hmm I don't have a good feeling about this.
> >
> > I prefer that we are clear to the userspace(IGT) that is an extra flag
> > and not to pretend that we have a residency counter.
> >
> > So, we either are clear that we are counting the entries, or having
> > a flag that tells that we are allowing dc6. Which btw, could be done
> > by IGT checking DC6_EN bit directly, no?!
>
> A DC6 enabled check alone would be not enough and checking it from user
> space along with the DC5 counter would be racy as described above. I see
> this working by the driver tracking the DC6 enabled flag + the DC5
> counter in the above way; it could be exposed to user space with a
> suitable name, eg. dc6_allowed_time.

Right, the name and new entry in the debugfs file would make this
better because we wouldn't be pretending 'residency', specially
with no guarantee that it would enter.

However I'd like to keep things simple. Stepping back to see
what the use case from the test are trying to really
accomplish:

  * SUBTEST: dc6-dpms
  * Description: Validate display engine entry to DC6 state while all connectors's
  *              DPMS property set to OFF
  *
  * SUBTEST: dc6-psr
  * Description: This test validates display engine entry to DC6 state while PSR is active
  * Functionality: pm_dc, psr1

Of course, we already know that it is impossible to validate
that the display engine itself entered that. But we can
at least validate that our driver is allowing that condition.

This is with fake residency, with the allowed_time, but also
with the simple counter that Mohammed added, or also just
by checking the register directly...

 _MMIO(0x45504) & 0x3 == 2 // in idle scenario described above should be enough imho

>
> > > > >> >The commit log would need a justification, something along the above
> > > > >> >lines.
> > > > >> >
> > > > >> >>  }
> > > > >> >>
> > > > >> >>  void bxt_enable_dc9(struct intel_display *display)
> > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > >> >> index 221d3abda791..f51bd8e6011d 100644
> > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> > > > >> >>          if (i915_mmio_reg_valid(dc6_reg))
> > > > >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > > >> >>                             intel_de_read(display, dc6_reg));
> > > > >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> > > > >> >>
> > > > >> >>          seq_printf(m, "program base: 0x%08x\n",
> > > > >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > > > >> >> --
> > > > >> >> 2.43.0
> > > > >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 11:12:34AM -0500, Rodrigo Vivi wrote:
> On Mon, Feb 03, 2025 at 06:01:25PM +0200, Imre Deak wrote:
> > On Mon, Feb 03, 2025 at 10:45:58AM -0500, Rodrigo Vivi wrote:
> > > On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> > > > On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > > > > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > > > > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > > > > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > > > > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > > > > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > > > > >> >> due to dc6 counter has been removed to validate DC state.
> > > > > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > > > > >> >>
> > > > > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > > > > >> >> ---
> > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > > > > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > > > > >> >>  3 files changed, 4 insertions(+)
> > > > > >> >>
> > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > >> >> index 554870d2494b..cc244617011f 100644
> > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > > > > >> >>          struct {
> > > > > >> >>                  struct intel_dmc *dmc;
> > > > > >> >>                  intel_wakeref_t wakeref;
> > > > > >> >> +                u32 dc6_entry_counter;
> > > > > >> >>          } dmc;
> > > > > >> >>
> > > > > >> >>          struct {
> > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > > > > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > > > > >> >>
> > > > > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > > > > >> >> +
> > > > > >> >> +        display->dmc.dc6_entry_counter++;
> > > > > >> >
> > > > > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > > > > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > > > > >> >a counter earlier either), so an alternative way is required. According
> > > > > >> >to the HW team the display driver has programmed everything correctly in
> > > > > >> >order to allow the DC6 power state if the DC5 power state is reached
> > > > > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > > > > >> >enabled by the driver.
> > > > > >>
> > > > > >> Yep. That's what I learned as well when looking into this stuff a while
> > > > > >> ago.
> > > > > >>
> > > > > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > > > > >> >driver which is incremented if the DC5 residency counter increments
> > > > >
> > > > > By the way, the counter that we currently have in our driver is the one
> > > > > incremented by the DMC. I was meaning to send a patch for the residency
> > > > > counter maintained by the hardware, but have not yet... In theory, that
> > > > > one should be more accurate, but would require us to enable and disable
> > > > > that counter as the IGT test starts and finishes.
> > > > >
> > > > > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > > > > >> >for this, since it doesn't take into account the DC5 residency. While
> > > > > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > > > > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > > > > >> >state asynchronously.
> > > > > >>
> > > > > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > > > > >> something worth implementing. Even if we have successfully entered DC5
> > > > > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > > > > >> counter and it could be masking some hardware bug that could be
> > > > > >> preventing DC6.
> > > > > >
> > > > > >According to the HW team the DC5 residency counter incrementing while
> > > > > >DC6 is enabled is a guarantee that the display is configured correctly
> > > > > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > > > > >suggestion to validate DC6 at the moment.
> > > > > >
> > > > > >> On the IGT side, we could just skip if we are on a platform that does
> > > > > >> not support DC6 counters, at least while we do not have a reliable
> > > > > >> alternative way of checking for DC6.
> > > > > >
> > > > > >I think IGT would need to validate DC6 in the above way suggested by the
> > > > > >HW team.
> > > > >
> > > > > I'm still inclined to think that we should defer DC6 checking for when
> > > > > we actually have a way to verify it. The way suggested above sounds
> > > > > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > > > >
> > > > > In that case, just checking for DC5 should be enough for the time
> > > > > being...
> > > >
> > > > That's not the same as DC5 incrementing while DC6 is enabled.
> > > >
> > > > > I won't object further if we do the other way though.
> > > > >
> > > > > >
> > > > > >> It would be good if we could detect that PG0 was in fact disabled, which
> > > > > >> I believe is a stronger indication of DC6.
> > > > > >
> > > > > >It would be good to have a HW DC6 residency counter, but there isn't one
> > > > > >at the moment. Other ways may have a dependency on other, non-display HW
> > > > > >blocks, for instance in case of shared clock/voltage resources, the
> > > > > >display functionality validation shouldn't be affected by these HW
> > > > > >blocks.
> > > > >
> > > > > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > > > > disabled. That's why my suggestion above.
> > > > >
> > > > > --
> > > > > Gustavo Sousa
> > > > >
> > > > > >
> > > > > >> --
> > > > > >> Gustavo Sousa
> > > > > >>
> > > > > >> >
> > > > > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > > > > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > > > > >> >DC6 residency counter right before it disables DC6 or when user space
> > > > > >> >reads the DC6 counter. So the driver would update the counter at these
> > > > > >> >two points in the following way:
> > > > > >> >dc6_residency += dc5_residency_current - dc5_residency_start
> > >
> > > Hmm I don't have a good feeling about this.
> > >
> > > I prefer that we are clear to the userspace(IGT) that is an extra flag
> > > and not to pretend that we have a residency counter.
> > >
> > > So, we either are clear that we are counting the entries, or having
> > > a flag that tells that we are allowing dc6. Which btw, could be done
> > > by IGT checking DC6_EN bit directly, no?!
> >
> > A DC6 enabled check alone would be not enough and checking it from user
> > space along with the DC5 counter would be racy as described above. I see
> > this working by the driver tracking the DC6 enabled flag + the DC5
> > counter in the above way; it could be exposed to user space with a
> > suitable name, eg. dc6_allowed_time.
> 
> Right, the name and new entry in the debugfs file would make this
> better because we wouldn't be pretending 'residency', specially
> with no guarantee that it would enter.
> 
> However I'd like to keep things simple. Stepping back to see
> what the use case from the test are trying to really
> accomplish:
> 
>   * SUBTEST: dc6-dpms
>   * Description: Validate display engine entry to DC6 state while all connectors's
>   *              DPMS property set to OFF
>   *
>   * SUBTEST: dc6-psr
>   * Description: This test validates display engine entry to DC6 state while PSR is active
>   * Functionality: pm_dc, psr1
> 
> Of course, we already know that it is impossible to validate
> that the display engine itself entered that. But we can
> at least validate that our driver is allowing that condition.
> 
> This is with fake residency, with the allowed_time, but also
> with the simple counter that Mohammed added, or also just
> by checking the register directly...
> 
>  _MMIO(0x45504) & 0x3 == 2 // in idle scenario described above should be enough imho

The driver enabling DC6 is not an enough condition for DC6 being allowed
from the display side. Some display clock gating etc. configuration by
the driver could be blocking it. According to the HW team, DC5 being
entered while DC6 is enabled is a guarantee that DC6 is allowed from the
display side - i.e. the driver has configured everything correctly for
that.

> > > > > >> >The commit log would need a justification, something along the above
> > > > > >> >lines.
> > > > > >> >
> > > > > >> >>  }
> > > > > >> >>
> > > > > >> >>  void bxt_enable_dc9(struct intel_display *display)
> > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > >> >> index 221d3abda791..f51bd8e6011d 100644
> > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> > > > > >> >>          if (i915_mmio_reg_valid(dc6_reg))
> > > > > >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > > > >> >>                             intel_de_read(display, dc6_reg));
> > > > > >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> > > > > >> >>
> > > > > >> >>          seq_printf(m, "program base: 0x%08x\n",
> > > > > >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > > > > >> >> --
> > > > > >> >> 2.43.0
> > > > > >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Gustavo Sousa]

Quoting Imre Deak (2025-02-03 12:14:10-03:00)
>On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
>> Quoting Imre Deak (2025-02-03 11:26:19-03:00)
>> >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
>> >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
>> >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
>> >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
>> >> >> due to dc6 counter has been removed to validate DC state.
>> >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
>> >> >> 
>> >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>> >> >> ---
>> >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
>> >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
>> >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
>> >> >>  3 files changed, 4 insertions(+)
>> >> >> 
>> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> >> index 554870d2494b..cc244617011f 100644
>> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> >> >> @@ -376,6 +376,7 @@ struct intel_display {
>> >> >>          struct {
>> >> >>                  struct intel_dmc *dmc;
>> >> >>                  intel_wakeref_t wakeref;
>> >> >> +                u32 dc6_entry_counter;
>> >> >>          } dmc;
>> >> >>  
>> >> >>          struct {
>> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> >> >> index f45a4f9ba23c..0eb178aa618d 100644
>> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
>> >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
>> >> >>  
>> >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
>> >> >> +
>> >> >> +        display->dmc.dc6_entry_counter++;
>> >> >
>> >> >AFAIU the goal is to validate that the display HW can reach the DC6
>> >> >power state. There is no HW DC6 residency counter (and there wasn't such
>> >> >a counter earlier either), so an alternative way is required. According
>> >> >to the HW team the display driver has programmed everything correctly in
>> >> >order to allow the DC6 power state if the DC5 power state is reached
>> >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
>> >> >enabled by the driver.
>> >> 
>> >> Yep. That's what I learned as well when looking into this stuff a while
>> >> ago.
>> >> 
>> >> >Based on the above, we'd need a DC6 residency counter maintained by the
>> >> >driver which is incremented if the DC5 residency counter increments
>> 
>> By the way, the counter that we currently have in our driver is the one
>> incremented by the DMC. I was meaning to send a patch for the residency
>> counter maintained by the hardware, but have not yet... In theory, that
>> one should be more accurate, but would require us to enable and disable
>> that counter as the IGT test starts and finishes.
>> 
>> >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
>> >> >for this, since it doesn't take into account the DC5 residency. While
>> >> >user space could check both dc6_entry_counter and the DC5 residency,
>> >> >that check would be racy wrt. the driver enabling/disabling the DC6
>> >> >state asynchronously.
>> >> 
>> >> I'm not sure doing a driver-maintained dc6 entry counter would be
>> >> something worth implementing. Even if we have successfully entered DC5
>> >> and, in theory, DC6 would follow if enabled, this would be a synthetic
>> >> counter and it could be masking some hardware bug that could be
>> >> preventing DC6.
>> >
>> >According to the HW team the DC5 residency counter incrementing while
>> >DC6 is enabled is a guarantee that the display is configured correctly
>> >to allow the HW entering DC6 at all times. IOW this is the HW team's
>> >suggestion to validate DC6 at the moment.
>> >
>> >> On the IGT side, we could just skip if we are on a platform that does
>> >> not support DC6 counters, at least while we do not have a reliable
>> >> alternative way of checking for DC6.
>> >
>> >I think IGT would need to validate DC6 in the above way suggested by the
>> >HW team.
>> 
>> I'm still inclined to think that we should defer DC6 checking for when
>> we actually have a way to verify it. The way suggested above sounds
>> like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
>> 
>> In that case, just checking for DC5 should be enough for the time
>> being...
>
>That's not the same as DC5 incrementing while DC6 is enabled.

Ah, I see.

You mean that, with DC6 enabled, hardware/firmware flows for DC5 might
be different, right?

Yeah, that would make sense. In that case, maybe a flag (or counter)
from driver that we got into DC5 with DC6 enabled would be helpful
indeed.

--
Gustavo Sousa

>
>> I won't object further if we do the other way though.
>> 
>> >
>> >> It would be good if we could detect that PG0 was in fact disabled, which
>> >> I believe is a stronger indication of DC6.
>> >
>> >It would be good to have a HW DC6 residency counter, but there isn't one
>> >at the moment. Other ways may have a dependency on other, non-display HW
>> >blocks, for instance in case of shared clock/voltage resources, the
>> >display functionality validation shouldn't be affected by these HW
>> >blocks.
>> 
>> As far as I understand by reading the docs, DC6 is DC5 with PG0
>> disabled. That's why my suggestion above.
>> 
>> --
>> Gustavo Sousa
>> 
>> >
>> >> --
>> >> Gustavo Sousa
>> >> 
>> >> >
>> >> >I suppose the driver could take a snapshot of the DC5 residency counter
>> >> >right after it enables DC6 (dc5_residency_start) and increment the SW
>> >> >DC6 residency counter right before it disables DC6 or when user space
>> >> >reads the DC6 counter. So the driver would update the counter at these
>> >> >two points in the following way:
>> >> >dc6_residency += dc5_residency_current - dc5_residency_start
>> >> >
>> >> >The commit log would need a justification, something along the above
>> >> >lines.
>> >> >
>> >> >>  }
>> >> >>  
>> >> >>  void bxt_enable_dc9(struct intel_display *display)
>> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> >> index 221d3abda791..f51bd8e6011d 100644
>> >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>> >> >>          if (i915_mmio_reg_valid(dc6_reg))
>> >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
>> >> >>                             intel_de_read(display, dc6_reg));
>> >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
>> >> >>  
>> >> >>          seq_printf(m, "program base: 0x%08x\n",
>> >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
>> >> >> -- 
>> >> >> 2.43.0
>> >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Rodrigo Vivi]

On Mon, Feb 03, 2025 at 06:27:17PM +0200, Imre Deak wrote:
> On Mon, Feb 03, 2025 at 11:12:34AM -0500, Rodrigo Vivi wrote:
> > On Mon, Feb 03, 2025 at 06:01:25PM +0200, Imre Deak wrote:
> > > On Mon, Feb 03, 2025 at 10:45:58AM -0500, Rodrigo Vivi wrote:
> > > > On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> > > > > On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > > > > > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > > > > > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > > > > > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > > > > > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > > > > > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > > > > > >> >> due to dc6 counter has been removed to validate DC state.
> > > > > > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > > > > > >> >>
> > > > > > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > > > > > >> >> ---
> > > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > > > > > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > > > > > >> >>  3 files changed, 4 insertions(+)
> > > > > > >> >>
> > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > >> >> index 554870d2494b..cc244617011f 100644
> > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > > > > > >> >>          struct {
> > > > > > >> >>                  struct intel_dmc *dmc;
> > > > > > >> >>                  intel_wakeref_t wakeref;
> > > > > > >> >> +                u32 dc6_entry_counter;
> > > > > > >> >>          } dmc;
> > > > > > >> >>
> > > > > > >> >>          struct {
> > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > > > > > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > > > > > >> >>
> > > > > > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > > > > > >> >> +
> > > > > > >> >> +        display->dmc.dc6_entry_counter++;
> > > > > > >> >
> > > > > > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > > > > > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > > > > > >> >a counter earlier either), so an alternative way is required. According
> > > > > > >> >to the HW team the display driver has programmed everything correctly in
> > > > > > >> >order to allow the DC6 power state if the DC5 power state is reached
> > > > > > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > > > > > >> >enabled by the driver.
> > > > > > >>
> > > > > > >> Yep. That's what I learned as well when looking into this stuff a while
> > > > > > >> ago.
> > > > > > >>
> > > > > > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > > > > > >> >driver which is incremented if the DC5 residency counter increments
> > > > > >
> > > > > > By the way, the counter that we currently have in our driver is the one
> > > > > > incremented by the DMC. I was meaning to send a patch for the residency
> > > > > > counter maintained by the hardware, but have not yet... In theory, that
> > > > > > one should be more accurate, but would require us to enable and disable
> > > > > > that counter as the IGT test starts and finishes.
> > > > > >
> > > > > > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > > > > > >> >for this, since it doesn't take into account the DC5 residency. While
> > > > > > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > > > > > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > > > > > >> >state asynchronously.
> > > > > > >>
> > > > > > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > > > > > >> something worth implementing. Even if we have successfully entered DC5
> > > > > > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > > > > > >> counter and it could be masking some hardware bug that could be
> > > > > > >> preventing DC6.
> > > > > > >
> > > > > > >According to the HW team the DC5 residency counter incrementing while
> > > > > > >DC6 is enabled is a guarantee that the display is configured correctly
> > > > > > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > > > > > >suggestion to validate DC6 at the moment.
> > > > > > >
> > > > > > >> On the IGT side, we could just skip if we are on a platform that does
> > > > > > >> not support DC6 counters, at least while we do not have a reliable
> > > > > > >> alternative way of checking for DC6.
> > > > > > >
> > > > > > >I think IGT would need to validate DC6 in the above way suggested by the
> > > > > > >HW team.
> > > > > >
> > > > > > I'm still inclined to think that we should defer DC6 checking for when
> > > > > > we actually have a way to verify it. The way suggested above sounds
> > > > > > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > > > > >
> > > > > > In that case, just checking for DC5 should be enough for the time
> > > > > > being...
> > > > >
> > > > > That's not the same as DC5 incrementing while DC6 is enabled.
> > > > >
> > > > > > I won't object further if we do the other way though.
> > > > > >
> > > > > > >
> > > > > > >> It would be good if we could detect that PG0 was in fact disabled, which
> > > > > > >> I believe is a stronger indication of DC6.
> > > > > > >
> > > > > > >It would be good to have a HW DC6 residency counter, but there isn't one
> > > > > > >at the moment. Other ways may have a dependency on other, non-display HW
> > > > > > >blocks, for instance in case of shared clock/voltage resources, the
> > > > > > >display functionality validation shouldn't be affected by these HW
> > > > > > >blocks.
> > > > > >
> > > > > > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > > > > > disabled. That's why my suggestion above.
> > > > > >
> > > > > > --
> > > > > > Gustavo Sousa
> > > > > >
> > > > > > >
> > > > > > >> --
> > > > > > >> Gustavo Sousa
> > > > > > >>
> > > > > > >> >
> > > > > > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > > > > > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > > > > > >> >DC6 residency counter right before it disables DC6 or when user space
> > > > > > >> >reads the DC6 counter. So the driver would update the counter at these
> > > > > > >> >two points in the following way:
> > > > > > >> >dc6_residency += dc5_residency_current - dc5_residency_start
> > > >
> > > > Hmm I don't have a good feeling about this.
> > > >
> > > > I prefer that we are clear to the userspace(IGT) that is an extra flag
> > > > and not to pretend that we have a residency counter.
> > > >
> > > > So, we either are clear that we are counting the entries, or having
> > > > a flag that tells that we are allowing dc6. Which btw, could be done
> > > > by IGT checking DC6_EN bit directly, no?!
> > >
> > > A DC6 enabled check alone would be not enough and checking it from user
> > > space along with the DC5 counter would be racy as described above. I see
> > > this working by the driver tracking the DC6 enabled flag + the DC5
> > > counter in the above way; it could be exposed to user space with a
> > > suitable name, eg. dc6_allowed_time.
> > 
> > Right, the name and new entry in the debugfs file would make this
> > better because we wouldn't be pretending 'residency', specially
> > with no guarantee that it would enter.
> > 
> > However I'd like to keep things simple. Stepping back to see
> > what the use case from the test are trying to really
> > accomplish:
> > 
> >   * SUBTEST: dc6-dpms
> >   * Description: Validate display engine entry to DC6 state while all connectors's
> >   *              DPMS property set to OFF
> >   *
> >   * SUBTEST: dc6-psr
> >   * Description: This test validates display engine entry to DC6 state while PSR is active
> >   * Functionality: pm_dc, psr1
> > 
> > Of course, we already know that it is impossible to validate
> > that the display engine itself entered that. But we can
> > at least validate that our driver is allowing that condition.
> > 
> > This is with fake residency, with the allowed_time, but also
> > with the simple counter that Mohammed added, or also just
> > by checking the register directly...
> > 
> >  _MMIO(0x45504) & 0x3 == 2 // in idle scenario described above should be enough imho
> 
> The driver enabling DC6 is not an enough condition for DC6 being allowed
> from the display side. Some display clock gating etc. configuration by
> the driver could be blocking it. According to the HW team, DC5 being
> entered while DC6 is enabled is a guarantee that DC6 is allowed from the
> display side - i.e. the driver has configured everything correctly for
> that.

Fair enough. So IGT test case would check directly if DC5 counter is
increasing and DC6 is allowed.

Something as simple as this in the kernel code would tell that
DC6 is enabled:


--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
                seq_printf(m, "DC5 -> DC6 count: %d\n",
                           intel_de_read(display, dc6_reg));
 
+       seq_printf(m, "DC6 allowed: %s\n", str_yes_no((intel_de_read(display,
+                                                                   DC_STATE_EN)
+                                                     & 0x3) == 2));
+

and

$ cat i915_dmc_info
[snip]
DC3 -> DC5 count: 286
DC5 -> DC6 count: 0
DC6 allowed: yes
[snip]

$ cat i915_dmc_info
[snip]
DC3 -> DC5 count: 292
DC5 -> DC6 count: 0
DC6 allowed: yes
[snip]

Thoughts?

> 
> > > > > > >> >The commit log would need a justification, something along the above
> > > > > > >> >lines.
> > > > > > >> >
> > > > > > >> >>  }
> > > > > > >> >>
> > > > > > >> >>  void bxt_enable_dc9(struct intel_display *display)
> > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > > >> >> index 221d3abda791..f51bd8e6011d 100644
> > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > > >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> > > > > > >> >>          if (i915_mmio_reg_valid(dc6_reg))
> > > > > > >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > > > > >> >>                             intel_de_read(display, dc6_reg));
> > > > > > >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> > > > > > >> >>
> > > > > > >> >>          seq_printf(m, "program base: 0x%08x\n",
> > > > > > >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > > > > > >> >> --
> > > > > > >> >> 2.43.0
> > > > > > >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 01:37:17PM -0300, Gustavo Sousa wrote:
> Quoting Imre Deak (2025-02-03 12:14:10-03:00)
> >On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> >> Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> >> >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> >> >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> >> >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> >> >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> >> >> >> due to dc6 counter has been removed to validate DC state.
> >> >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> >> >> >> 
> >> >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> >> >> >> ---
> >> >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> >> >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> >> >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> >> >> >>  3 files changed, 4 insertions(+)
> >> >> >> 
> >> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> >> index 554870d2494b..cc244617011f 100644
> >> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> >> >> @@ -376,6 +376,7 @@ struct intel_display {
> >> >> >>          struct {
> >> >> >>                  struct intel_dmc *dmc;
> >> >> >>                  intel_wakeref_t wakeref;
> >> >> >> +                u32 dc6_entry_counter;
> >> >> >>          } dmc;
> >> >> >>  
> >> >> >>          struct {
> >> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> >> >> index f45a4f9ba23c..0eb178aa618d 100644
> >> >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> >> >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> >> >> >>  
> >> >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> >> >> >> +
> >> >> >> +        display->dmc.dc6_entry_counter++;
> >> >> >
> >> >> >AFAIU the goal is to validate that the display HW can reach the DC6
> >> >> >power state. There is no HW DC6 residency counter (and there wasn't such
> >> >> >a counter earlier either), so an alternative way is required. According
> >> >> >to the HW team the display driver has programmed everything correctly in
> >> >> >order to allow the DC6 power state if the DC5 power state is reached
> >> >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> >> >> >enabled by the driver.
> >> >> 
> >> >> Yep. That's what I learned as well when looking into this stuff a while
> >> >> ago.
> >> >> 
> >> >> >Based on the above, we'd need a DC6 residency counter maintained by the
> >> >> >driver which is incremented if the DC5 residency counter increments
> >> 
> >> By the way, the counter that we currently have in our driver is the one
> >> incremented by the DMC. I was meaning to send a patch for the residency
> >> counter maintained by the hardware, but have not yet... In theory, that
> >> one should be more accurate, but would require us to enable and disable
> >> that counter as the IGT test starts and finishes.
> >> 
> >> >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> >> >> >for this, since it doesn't take into account the DC5 residency. While
> >> >> >user space could check both dc6_entry_counter and the DC5 residency,
> >> >> >that check would be racy wrt. the driver enabling/disabling the DC6
> >> >> >state asynchronously.
> >> >> 
> >> >> I'm not sure doing a driver-maintained dc6 entry counter would be
> >> >> something worth implementing. Even if we have successfully entered DC5
> >> >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> >> >> counter and it could be masking some hardware bug that could be
> >> >> preventing DC6.
> >> >
> >> >According to the HW team the DC5 residency counter incrementing while
> >> >DC6 is enabled is a guarantee that the display is configured correctly
> >> >to allow the HW entering DC6 at all times. IOW this is the HW team's
> >> >suggestion to validate DC6 at the moment.
> >> >
> >> >> On the IGT side, we could just skip if we are on a platform that does
> >> >> not support DC6 counters, at least while we do not have a reliable
> >> >> alternative way of checking for DC6.
> >> >
> >> >I think IGT would need to validate DC6 in the above way suggested by the
> >> >HW team.
> >> 
> >> I'm still inclined to think that we should defer DC6 checking for when
> >> we actually have a way to verify it. The way suggested above sounds
> >> like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> >> 
> >> In that case, just checking for DC5 should be enough for the time
> >> being...
> >
> >That's not the same as DC5 incrementing while DC6 is enabled.
> 
> Ah, I see.
> 
> You mean that, with DC6 enabled, hardware/firmware flows for DC5 might
> be different, right?

Yes, that's possible, or some driver configuration while the driver
keeps DC6 enabled would block both DC5 and DC6.

> Yeah, that would make sense. In that case, maybe a flag (or counter)
> from driver that we got into DC5 with DC6 enabled would be helpful
> indeed.
> 
> --
> Gustavo Sousa
> 
> >
> >> I won't object further if we do the other way though.
> >> 
> >> >
> >> >> It would be good if we could detect that PG0 was in fact disabled, which
> >> >> I believe is a stronger indication of DC6.
> >> >
> >> >It would be good to have a HW DC6 residency counter, but there isn't one
> >> >at the moment. Other ways may have a dependency on other, non-display HW
> >> >blocks, for instance in case of shared clock/voltage resources, the
> >> >display functionality validation shouldn't be affected by these HW
> >> >blocks.
> >> 
> >> As far as I understand by reading the docs, DC6 is DC5 with PG0
> >> disabled. That's why my suggestion above.
> >> 
> >> --
> >> Gustavo Sousa
> >> 
> >> >
> >> >> --
> >> >> Gustavo Sousa
> >> >> 
> >> >> >
> >> >> >I suppose the driver could take a snapshot of the DC5 residency counter
> >> >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> >> >> >DC6 residency counter right before it disables DC6 or when user space
> >> >> >reads the DC6 counter. So the driver would update the counter at these
> >> >> >two points in the following way:
> >> >> >dc6_residency += dc5_residency_current - dc5_residency_start
> >> >> >
> >> >> >The commit log would need a justification, something along the above
> >> >> >lines.
> >> >> >
> >> >> >>  }
> >> >> >>  
> >> >> >>  void bxt_enable_dc9(struct intel_display *display)
> >> >> >> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> >> >> index 221d3abda791..f51bd8e6011d 100644
> >> >> >> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >> >> >> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> >> >> @@ -1293,6 +1293,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >> >> >>          if (i915_mmio_reg_valid(dc6_reg))
> >> >> >>                  seq_printf(m, "DC5 -> DC6 count: %d\n",
> >> >> >>                             intel_de_read(display, dc6_reg));
> >> >> >> +        seq_printf(m, "DC6 entry count: %d\n", display->dmc.dc6_entry_counter);
> >> >> >>  
> >> >> >>          seq_printf(m, "program base: 0x%08x\n",
> >> >> >>                     intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> >> >> >> -- 
> >> >> >> 2.43.0
> >> >> >>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 11:42:11AM -0500, Rodrigo Vivi wrote:
> On Mon, Feb 03, 2025 at 06:27:17PM +0200, Imre Deak wrote:
> > On Mon, Feb 03, 2025 at 11:12:34AM -0500, Rodrigo Vivi wrote:
> > > On Mon, Feb 03, 2025 at 06:01:25PM +0200, Imre Deak wrote:
> > > > On Mon, Feb 03, 2025 at 10:45:58AM -0500, Rodrigo Vivi wrote:
> > > > > On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> > > > > > On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > > > > > > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > > > > > > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > > > > > > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > > > > > > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > > > > > > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > > > > > > >> >> due to dc6 counter has been removed to validate DC state.
> > > > > > > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > > > > > > >> >>
> > > > > > > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > > > > > > >> >> ---
> > > > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > > > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > > > > > > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > > > > > > >> >>  3 files changed, 4 insertions(+)
> > > > > > > >> >>
> > > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > > >> >> index 554870d2494b..cc244617011f 100644
> > > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > > > > > > >> >>          struct {
> > > > > > > >> >>                  struct intel_dmc *dmc;
> > > > > > > >> >>                  intel_wakeref_t wakeref;
> > > > > > > >> >> +                u32 dc6_entry_counter;
> > > > > > > >> >>          } dmc;
> > > > > > > >> >>
> > > > > > > >> >>          struct {
> > > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > > > > > > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > > > > > > >> >>
> > > > > > > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > > > > > > >> >> +
> > > > > > > >> >> +        display->dmc.dc6_entry_counter++;
> > > > > > > >> >
> > > > > > > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > > > > > > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > > > > > > >> >a counter earlier either), so an alternative way is required. According
> > > > > > > >> >to the HW team the display driver has programmed everything correctly in
> > > > > > > >> >order to allow the DC6 power state if the DC5 power state is reached
> > > > > > > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > > > > > > >> >enabled by the driver.
> > > > > > > >>
> > > > > > > >> Yep. That's what I learned as well when looking into this stuff a while
> > > > > > > >> ago.
> > > > > > > >>
> > > > > > > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > > > > > > >> >driver which is incremented if the DC5 residency counter increments
> > > > > > >
> > > > > > > By the way, the counter that we currently have in our driver is the one
> > > > > > > incremented by the DMC. I was meaning to send a patch for the residency
> > > > > > > counter maintained by the hardware, but have not yet... In theory, that
> > > > > > > one should be more accurate, but would require us to enable and disable
> > > > > > > that counter as the IGT test starts and finishes.
> > > > > > >
> > > > > > > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > > > > > > >> >for this, since it doesn't take into account the DC5 residency. While
> > > > > > > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > > > > > > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > > > > > > >> >state asynchronously.
> > > > > > > >>
> > > > > > > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > > > > > > >> something worth implementing. Even if we have successfully entered DC5
> > > > > > > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > > > > > > >> counter and it could be masking some hardware bug that could be
> > > > > > > >> preventing DC6.
> > > > > > > >
> > > > > > > >According to the HW team the DC5 residency counter incrementing while
> > > > > > > >DC6 is enabled is a guarantee that the display is configured correctly
> > > > > > > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > > > > > > >suggestion to validate DC6 at the moment.
> > > > > > > >
> > > > > > > >> On the IGT side, we could just skip if we are on a platform that does
> > > > > > > >> not support DC6 counters, at least while we do not have a reliable
> > > > > > > >> alternative way of checking for DC6.
> > > > > > > >
> > > > > > > >I think IGT would need to validate DC6 in the above way suggested by the
> > > > > > > >HW team.
> > > > > > >
> > > > > > > I'm still inclined to think that we should defer DC6 checking for when
> > > > > > > we actually have a way to verify it. The way suggested above sounds
> > > > > > > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > > > > > >
> > > > > > > In that case, just checking for DC5 should be enough for the time
> > > > > > > being...
> > > > > >
> > > > > > That's not the same as DC5 incrementing while DC6 is enabled.
> > > > > >
> > > > > > > I won't object further if we do the other way though.
> > > > > > >
> > > > > > > >
> > > > > > > >> It would be good if we could detect that PG0 was in fact disabled, which
> > > > > > > >> I believe is a stronger indication of DC6.
> > > > > > > >
> > > > > > > >It would be good to have a HW DC6 residency counter, but there isn't one
> > > > > > > >at the moment. Other ways may have a dependency on other, non-display HW
> > > > > > > >blocks, for instance in case of shared clock/voltage resources, the
> > > > > > > >display functionality validation shouldn't be affected by these HW
> > > > > > > >blocks.
> > > > > > >
> > > > > > > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > > > > > > disabled. That's why my suggestion above.
> > > > > > >
> > > > > > > --
> > > > > > > Gustavo Sousa
> > > > > > >
> > > > > > > >
> > > > > > > >> --
> > > > > > > >> Gustavo Sousa
> > > > > > > >>
> > > > > > > >> >
> > > > > > > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > > > > > > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > > > > > > >> >DC6 residency counter right before it disables DC6 or when user space
> > > > > > > >> >reads the DC6 counter. So the driver would update the counter at these
> > > > > > > >> >two points in the following way:
> > > > > > > >> >dc6_residency += dc5_residency_current - dc5_residency_start
> > > > >
> > > > > Hmm I don't have a good feeling about this.
> > > > >
> > > > > I prefer that we are clear to the userspace(IGT) that is an extra flag
> > > > > and not to pretend that we have a residency counter.
> > > > >
> > > > > So, we either are clear that we are counting the entries, or having
> > > > > a flag that tells that we are allowing dc6. Which btw, could be done
> > > > > by IGT checking DC6_EN bit directly, no?!
> > > >
> > > > A DC6 enabled check alone would be not enough and checking it from user
> > > > space along with the DC5 counter would be racy as described above. I see
> > > > this working by the driver tracking the DC6 enabled flag + the DC5
> > > > counter in the above way; it could be exposed to user space with a
> > > > suitable name, eg. dc6_allowed_time.
> > > 
> > > Right, the name and new entry in the debugfs file would make this
> > > better because we wouldn't be pretending 'residency', specially
> > > with no guarantee that it would enter.
> > > 
> > > However I'd like to keep things simple. Stepping back to see
> > > what the use case from the test are trying to really
> > > accomplish:
> > > 
> > >   * SUBTEST: dc6-dpms
> > >   * Description: Validate display engine entry to DC6 state while all connectors's
> > >   *              DPMS property set to OFF
> > >   *
> > >   * SUBTEST: dc6-psr
> > >   * Description: This test validates display engine entry to DC6 state while PSR is active
> > >   * Functionality: pm_dc, psr1
> > > 
> > > Of course, we already know that it is impossible to validate
> > > that the display engine itself entered that. But we can
> > > at least validate that our driver is allowing that condition.
> > > 
> > > This is with fake residency, with the allowed_time, but also
> > > with the simple counter that Mohammed added, or also just
> > > by checking the register directly...
> > > 
> > >  _MMIO(0x45504) & 0x3 == 2 // in idle scenario described above should be enough imho
> > 
> > The driver enabling DC6 is not an enough condition for DC6 being allowed
> > from the display side. Some display clock gating etc. configuration by
> > the driver could be blocking it. According to the HW team, DC5 being
> > entered while DC6 is enabled is a guarantee that DC6 is allowed from the
> > display side - i.e. the driver has configured everything correctly for
> > that.
> 
> Fair enough. So IGT test case would check directly if DC5 counter is
> increasing and DC6 is allowed.
> 
> Something as simple as this in the kernel code would tell that
> DC6 is enabled:
> 
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>                 seq_printf(m, "DC5 -> DC6 count: %d\n",
>                            intel_de_read(display, dc6_reg));
>  
> +       seq_printf(m, "DC6 allowed: %s\n", str_yes_no((intel_de_read(display,
> +                                                                   DC_STATE_EN)
> +                                                     & 0x3) == 2));
> +
> 
> and
> 
> $ cat i915_dmc_info
> [snip]
> DC3 -> DC5 count: 286
> DC5 -> DC6 count: 0
> DC6 allowed: yes
> [snip]
> 
> $ cat i915_dmc_info
> [snip]
> DC3 -> DC5 count: 292
> DC5 -> DC6 count: 0
> DC6 allowed: yes
> [snip]
> 
> Thoughts?

The DC5 increment could've happened while DC6 was disabled by the driver.

--Imre

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Add debugfs for dc6 counter

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter
URL   : https://patchwork.freedesktop.org/series/144240/
State : warning

== Summary ==

Error: dim checkpatch failed
ac35a2baaed3 drm/i915/dmc: Add debugfs for dc6 counter
-:6: WARNING:COMMIT_LOG_LONG_LINE: Prefer a maximum 75 chars per line (possible unwrapped commit description?)
#6: 
Starting from MTl we don't have a platform agnostic way to validate DC6 state

total: 0 errors, 1 warnings, 0 checks, 22 lines checked

✗ Fi.CI.SPARSE: warning for drm/i915/dmc: Add debugfs for dc6 counter

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter
URL   : https://patchwork.freedesktop.org/series/144240/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Rodrigo Vivi]

On Mon, Feb 03, 2025 at 06:51:17PM +0200, Imre Deak wrote:
> On Mon, Feb 03, 2025 at 11:42:11AM -0500, Rodrigo Vivi wrote:
> > On Mon, Feb 03, 2025 at 06:27:17PM +0200, Imre Deak wrote:
> > > On Mon, Feb 03, 2025 at 11:12:34AM -0500, Rodrigo Vivi wrote:
> > > > On Mon, Feb 03, 2025 at 06:01:25PM +0200, Imre Deak wrote:
> > > > > On Mon, Feb 03, 2025 at 10:45:58AM -0500, Rodrigo Vivi wrote:
> > > > > > On Mon, Feb 03, 2025 at 05:14:10PM +0200, Imre Deak wrote:
> > > > > > > On Mon, Feb 03, 2025 at 11:59:59AM -0300, Gustavo Sousa wrote:
> > > > > > > > Quoting Imre Deak (2025-02-03 11:26:19-03:00)
> > > > > > > > >On Mon, Feb 03, 2025 at 10:39:54AM -0300, Gustavo Sousa wrote:
> > > > > > > > >> Quoting Imre Deak (2025-02-03 09:43:38-03:00)
> > > > > > > > >> >On Mon, Feb 03, 2025 at 02:26:13PM +0530, Mohammed Thasleem wrote:
> > > > > > > > >> >> Starting from MTl we don't have a platform agnostic way to validate DC6 state
> > > > > > > > >> >> due to dc6 counter has been removed to validate DC state.
> > > > > > > > >> >> Adding dc6_entry_counter at display dirver to validate dc6 state.
> > > > > > > > >> >>
> > > > > > > > >> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > > > > > > > >> >> ---
> > > > > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_core.h       | 1 +
> > > > > > > > >> >>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 2 ++
> > > > > > > > >> >>  drivers/gpu/drm/i915/display/intel_dmc.c                | 1 +
> > > > > > > > >> >>  3 files changed, 4 insertions(+)
> > > > > > > > >> >>
> > > > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > > > >> >> index 554870d2494b..cc244617011f 100644
> > > > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > > > > > > > >> >> @@ -376,6 +376,7 @@ struct intel_display {
> > > > > > > > >> >>          struct {
> > > > > > > > >> >>                  struct intel_dmc *dmc;
> > > > > > > > >> >>                  intel_wakeref_t wakeref;
> > > > > > > > >> >> +                u32 dc6_entry_counter;
> > > > > > > > >> >>          } dmc;
> > > > > > > > >> >>
> > > > > > > > >> >>          struct {
> > > > > > > > >> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > > > >> >> index f45a4f9ba23c..0eb178aa618d 100644
> > > > > > > > >> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > > > >> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > > > > > > > >> >> @@ -869,6 +869,8 @@ void skl_enable_dc6(struct intel_display *display)
> > > > > > > > >> >>          intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC6);
> > > > > > > > >> >>
> > > > > > > > >> >>          gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC6);
> > > > > > > > >> >> +
> > > > > > > > >> >> +        display->dmc.dc6_entry_counter++;
> > > > > > > > >> >
> > > > > > > > >> >AFAIU the goal is to validate that the display HW can reach the DC6
> > > > > > > > >> >power state. There is no HW DC6 residency counter (and there wasn't such
> > > > > > > > >> >a counter earlier either), so an alternative way is required. According
> > > > > > > > >> >to the HW team the display driver has programmed everything correctly in
> > > > > > > > >> >order to allow the DC6 power state if the DC5 power state is reached
> > > > > > > > >> >(indicated by the HW DC5 residency counter incrementing) and DC6 is
> > > > > > > > >> >enabled by the driver.
> > > > > > > > >>
> > > > > > > > >> Yep. That's what I learned as well when looking into this stuff a while
> > > > > > > > >> ago.
> > > > > > > > >>
> > > > > > > > >> >Based on the above, we'd need a DC6 residency counter maintained by the
> > > > > > > > >> >driver which is incremented if the DC5 residency counter increments
> > > > > > > >
> > > > > > > > By the way, the counter that we currently have in our driver is the one
> > > > > > > > incremented by the DMC. I was meaning to send a patch for the residency
> > > > > > > > counter maintained by the hardware, but have not yet... In theory, that
> > > > > > > > one should be more accurate, but would require us to enable and disable
> > > > > > > > that counter as the IGT test starts and finishes.
> > > > > > > >
> > > > > > > > >> >while DC6 is enabled. The dc6_entry_counter in this patch is not enough
> > > > > > > > >> >for this, since it doesn't take into account the DC5 residency. While
> > > > > > > > >> >user space could check both dc6_entry_counter and the DC5 residency,
> > > > > > > > >> >that check would be racy wrt. the driver enabling/disabling the DC6
> > > > > > > > >> >state asynchronously.
> > > > > > > > >>
> > > > > > > > >> I'm not sure doing a driver-maintained dc6 entry counter would be
> > > > > > > > >> something worth implementing. Even if we have successfully entered DC5
> > > > > > > > >> and, in theory, DC6 would follow if enabled, this would be a synthetic
> > > > > > > > >> counter and it could be masking some hardware bug that could be
> > > > > > > > >> preventing DC6.
> > > > > > > > >
> > > > > > > > >According to the HW team the DC5 residency counter incrementing while
> > > > > > > > >DC6 is enabled is a guarantee that the display is configured correctly
> > > > > > > > >to allow the HW entering DC6 at all times. IOW this is the HW team's
> > > > > > > > >suggestion to validate DC6 at the moment.
> > > > > > > > >
> > > > > > > > >> On the IGT side, we could just skip if we are on a platform that does
> > > > > > > > >> not support DC6 counters, at least while we do not have a reliable
> > > > > > > > >> alternative way of checking for DC6.
> > > > > > > > >
> > > > > > > > >I think IGT would need to validate DC6 in the above way suggested by the
> > > > > > > > >HW team.
> > > > > > > >
> > > > > > > > I'm still inclined to think that we should defer DC6 checking for when
> > > > > > > > we actually have a way to verify it. The way suggested above sounds
> > > > > > > > like: *trust* that DC6 is reached when DC5 is reached with DC6 enabled.
> > > > > > > >
> > > > > > > > In that case, just checking for DC5 should be enough for the time
> > > > > > > > being...
> > > > > > >
> > > > > > > That's not the same as DC5 incrementing while DC6 is enabled.
> > > > > > >
> > > > > > > > I won't object further if we do the other way though.
> > > > > > > >
> > > > > > > > >
> > > > > > > > >> It would be good if we could detect that PG0 was in fact disabled, which
> > > > > > > > >> I believe is a stronger indication of DC6.
> > > > > > > > >
> > > > > > > > >It would be good to have a HW DC6 residency counter, but there isn't one
> > > > > > > > >at the moment. Other ways may have a dependency on other, non-display HW
> > > > > > > > >blocks, for instance in case of shared clock/voltage resources, the
> > > > > > > > >display functionality validation shouldn't be affected by these HW
> > > > > > > > >blocks.
> > > > > > > >
> > > > > > > > As far as I understand by reading the docs, DC6 is DC5 with PG0
> > > > > > > > disabled. That's why my suggestion above.
> > > > > > > >
> > > > > > > > --
> > > > > > > > Gustavo Sousa
> > > > > > > >
> > > > > > > > >
> > > > > > > > >> --
> > > > > > > > >> Gustavo Sousa
> > > > > > > > >>
> > > > > > > > >> >
> > > > > > > > >> >I suppose the driver could take a snapshot of the DC5 residency counter
> > > > > > > > >> >right after it enables DC6 (dc5_residency_start) and increment the SW
> > > > > > > > >> >DC6 residency counter right before it disables DC6 or when user space
> > > > > > > > >> >reads the DC6 counter. So the driver would update the counter at these
> > > > > > > > >> >two points in the following way:
> > > > > > > > >> >dc6_residency += dc5_residency_current - dc5_residency_start
> > > > > >
> > > > > > Hmm I don't have a good feeling about this.
> > > > > >
> > > > > > I prefer that we are clear to the userspace(IGT) that is an extra flag
> > > > > > and not to pretend that we have a residency counter.
> > > > > >
> > > > > > So, we either are clear that we are counting the entries, or having
> > > > > > a flag that tells that we are allowing dc6. Which btw, could be done
> > > > > > by IGT checking DC6_EN bit directly, no?!
> > > > >
> > > > > A DC6 enabled check alone would be not enough and checking it from user
> > > > > space along with the DC5 counter would be racy as described above. I see
> > > > > this working by the driver tracking the DC6 enabled flag + the DC5
> > > > > counter in the above way; it could be exposed to user space with a
> > > > > suitable name, eg. dc6_allowed_time.
> > > > 
> > > > Right, the name and new entry in the debugfs file would make this
> > > > better because we wouldn't be pretending 'residency', specially
> > > > with no guarantee that it would enter.
> > > > 
> > > > However I'd like to keep things simple. Stepping back to see
> > > > what the use case from the test are trying to really
> > > > accomplish:
> > > > 
> > > >   * SUBTEST: dc6-dpms
> > > >   * Description: Validate display engine entry to DC6 state while all connectors's
> > > >   *              DPMS property set to OFF
> > > >   *
> > > >   * SUBTEST: dc6-psr
> > > >   * Description: This test validates display engine entry to DC6 state while PSR is active
> > > >   * Functionality: pm_dc, psr1
> > > > 
> > > > Of course, we already know that it is impossible to validate
> > > > that the display engine itself entered that. But we can
> > > > at least validate that our driver is allowing that condition.
> > > > 
> > > > This is with fake residency, with the allowed_time, but also
> > > > with the simple counter that Mohammed added, or also just
> > > > by checking the register directly...
> > > > 
> > > >  _MMIO(0x45504) & 0x3 == 2 // in idle scenario described above should be enough imho
> > > 
> > > The driver enabling DC6 is not an enough condition for DC6 being allowed
> > > from the display side. Some display clock gating etc. configuration by
> > > the driver could be blocking it. According to the HW team, DC5 being
> > > entered while DC6 is enabled is a guarantee that DC6 is allowed from the
> > > display side - i.e. the driver has configured everything correctly for
> > > that.
> > 
> > Fair enough. So IGT test case would check directly if DC5 counter is
> > increasing and DC6 is allowed.
> > 
> > Something as simple as this in the kernel code would tell that
> > DC6 is enabled:
> > 
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
> >                            intel_de_read(display, dc6_reg));
> >  
> > +       seq_printf(m, "DC6 allowed: %s\n", str_yes_no((intel_de_read(display,
> > +                                                                   DC_STATE_EN)
> > +                                                     & 0x3) == 2));
> > +
> > 
> > and
> > 
> > $ cat i915_dmc_info
> > [snip]
> > DC3 -> DC5 count: 286
> > DC5 -> DC6 count: 0
> > DC6 allowed: yes
> > [snip]
> > 
> > $ cat i915_dmc_info
> > [snip]
> > DC3 -> DC5 count: 292
> > DC5 -> DC6 count: 0
> > DC6 allowed: yes
> > [snip]
> > 
> > Thoughts?
> 
> The DC5 increment could've happened while DC6 was disabled by the driver.

Yes, it could... in general the dc6 bit would be zero, but right, there's
a possible race.

But should we complicate things when we know that on the test case itself
we are in full control of the modeset?! From the test perspective I believe
this would be more than enough without complicating things.

But well, if you really believe that we need to go further in the driver
to cover that it is fine by me.

But just to ensure that we are in the same page, could you please open
up a bit more of your idea on when to increase the dc5 sw counters
in a way that we would ensure that we don't have race and that we
get the dc6 allowed counter correctly?

Btw, while doing this experiment I noticed that the debugfs and test
also doesn't call that residency anyway and it is just count. So
perhaps with your idea we don't need to change the debugfs interface.

> 
> --Imre
> 

✓ i915.CI.BAT: success for drm/i915/dmc: Add debugfs for dc6 counter

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3120 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter
URL   : https://patchwork.freedesktop.org/series/144240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16054 -> Patchwork_144240v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_144240v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - bat-adls-6:         [PASS][1] -> [FAIL][2] ([i915#13401])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/bat-adls-6/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/bat-adls-6/igt@i915_pm_rpm@module-reload.html
    - bat-rpls-4:         [PASS][3] -> [FAIL][4] ([i915#13401])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/bat-rpls-4/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [PASS][5] -> [DMESG-FAIL][6] ([i915#12061]) +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/bat-arls-5/igt@i915_selftest@live@workarounds.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][7] -> [SKIP][8] ([i915#9197]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-6:         [DMESG-FAIL][9] ([i915#12061]) -> [PASS][10] +1 other test pass
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13401]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13401
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16054 -> Patchwork_144240v1

  CI-20190529: 20190529
  CI_DRM_16054: 907133c4b6b53621c4e90697c1cc85ccef3f5711 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8220: 8220
  Patchwork_144240v1: 907133c4b6b53621c4e90697c1cc85ccef3f5711 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/index.html

[-- Attachment #2: Type: text/html, Size: 3954 bytes --]

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
> > > > [...]
> > > >
> > > > The driver enabling DC6 is not an enough condition for DC6 being allowed
> > > > from the display side. Some display clock gating etc. configuration by
> > > > the driver could be blocking it. According to the HW team, DC5 being
> > > > entered while DC6 is enabled is a guarantee that DC6 is allowed from the
> > > > display side - i.e. the driver has configured everything correctly for
> > > > that.
> > > 
> > > Fair enough. So IGT test case would check directly if DC5 counter is
> > > increasing and DC6 is allowed.
> > > 
> > > Something as simple as this in the kernel code would tell that
> > > DC6 is enabled:
> > > 
> > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > @@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
> > >                            intel_de_read(display, dc6_reg));
> > >  
> > > +       seq_printf(m, "DC6 allowed: %s\n", str_yes_no((intel_de_read(display,
> > > +                                                                   DC_STATE_EN)
> > > +                                                     & 0x3) == 2));
> > > +
> > > 
> > > and
> > > 
> > > $ cat i915_dmc_info
> > > [snip]
> > > DC3 -> DC5 count: 286
> > > DC5 -> DC6 count: 0
> > > DC6 allowed: yes
> > > [snip]
> > > 
> > > $ cat i915_dmc_info
> > > [snip]
> > > DC3 -> DC5 count: 292
> > > DC5 -> DC6 count: 0
> > > DC6 allowed: yes
> > > [snip]
> > > 
> > > Thoughts?
> > 
> > The DC5 increment could've happened while DC6 was disabled by the driver.
> 
> Yes, it could... in general the dc6 bit would be zero, but right, there's
> a possible race.
> 
> But should we complicate things when we know that on the test case itself
> we are in full control of the modeset?! From the test perspective I believe
> this would be more than enough without complicating things.

Imo having a counter which works based on the condition that guarantees the
display to allow DC6, would help later in debugging.

> But well, if you really believe that we need to go further in the driver
> to cover that it is fine by me.
> 
> But just to ensure that we are in the same page, could you please open
> up a bit more of your idea on when to increase the dc5 sw counters
> in a way that we would ensure that we don't have race and that we
> get the dc6 allowed counter correctly?

Something like the following:

1. Right after the driver sets DC6_EN, it stores the DC5 HW counter's
   current value:
   dc5_start = dc5_current
2. Right before the driver clears DC6_EN, it updates the DC6 allowed
   counter:
   dc6_allowed += dc5_current - dc5_start
   dc5_start = dc5_current
3. When userspace reads the counters via debugfs the driver first
   updates dc6_allowed the same way as 2. did if DC6_EN is set.

> Btw, while doing this experiment I noticed that the debugfs and test
> also doesn't call that residency anyway and it is just count. So
> perhaps with your idea we don't need to change the debugfs interface.

✗ i915.CI.Full: failure for drm/i915/dmc: Add debugfs for dc6 counter

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 98093 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16054_full -> Patchwork_144240v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_hangman@gt-error-state-capture@vcs1:
    - shard-mtlp:         [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-mtlp-2/igt@i915_hangman@gt-error-state-capture@vcs1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-7/igt@i915_hangman@gt-error-state-capture@vcs1.html

  
Known issues
------------

  Here are the changes found in Patchwork_144240v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-tglu-1:       NOTRUN -> [SKIP][3] ([i915#11078])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@device_reset@unbind-cold-reset-rebind.html
    - shard-dg2:          NOTRUN -> [SKIP][4] ([i915#11078])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@device_reset@unbind-reset-rebind:
    - shard-tglu:         [PASS][5] -> [ABORT][6] ([i915#12817] / [i915#5507])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-tglu-5/igt@device_reset@unbind-reset-rebind.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-7/igt@device_reset@unbind-reset-rebind.html

  * igt@drm_fdinfo@virtual-busy:
    - shard-dg2:          NOTRUN -> [SKIP][7] ([i915#8414])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@drm_fdinfo@virtual-busy.html

  * igt@gem_caching@writes:
    - shard-mtlp:         NOTRUN -> [SKIP][8] ([i915#4873])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@gem_caching@writes.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-dg1:          NOTRUN -> [SKIP][9] ([i915#3555] / [i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#13008])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][11] ([i915#9323]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@gem_ccs@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg1:          NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-tglu:         NOTRUN -> [SKIP][13] ([i915#6335])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-2/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg1:          NOTRUN -> [SKIP][14] ([i915#8555])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@gem_ctx_persistence@heartbeat-stop.html
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#8555])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_ctx_persistence@legacy-engines-hostile-preempt:
    - shard-snb:          NOTRUN -> [SKIP][16] ([i915#1099])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-snb2/igt@gem_ctx_persistence@legacy-engines-hostile-preempt.html

  * igt@gem_ctx_sseu@engines:
    - shard-dg1:          NOTRUN -> [SKIP][17] ([i915#280]) +1 other test skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-dg2:          NOTRUN -> [SKIP][18] ([i915#280])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@gem_ctx_sseu@invalid-args.html
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#280])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-5/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_eio@hibernate:
    - shard-dg1:          NOTRUN -> [ABORT][20] ([i915#7975])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@gem_eio@hibernate.html

  * igt@gem_eio@wait-1us:
    - shard-mtlp:         [PASS][21] -> [ABORT][22] ([i915#13193]) +3 other tests abort
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-mtlp-8/igt@gem_eio@wait-1us.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-7/igt@gem_eio@wait-1us.html

  * igt@gem_exec_balancer@bonded-semaphore:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#4812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gem_exec_balancer@bonded-semaphore.html

  * igt@gem_exec_balancer@parallel-balancer:
    - shard-tglu-1:       NOTRUN -> [SKIP][24] ([i915#4525]) +1 other test skip
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@gem_exec_balancer@parallel-balancer.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-tglu:         NOTRUN -> [SKIP][25] ([i915#4525]) +1 other test skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#4525]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_big@single:
    - shard-tglu:         NOTRUN -> [ABORT][27] ([i915#11713])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-2/igt@gem_exec_big@single.html

  * igt@gem_exec_capture@capture-invisible:
    - shard-tglu-1:       NOTRUN -> [SKIP][28] ([i915#6334]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@gem_exec_capture@capture-invisible.html

  * igt@gem_exec_fence@submit:
    - shard-dg1:          NOTRUN -> [SKIP][29] ([i915#4812]) +5 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@gem_exec_fence@submit.html

  * igt@gem_exec_flush@basic-uc-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#3539])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_exec_flush@basic-uc-prw-default.html

  * igt@gem_exec_flush@basic-uc-rw-default:
    - shard-dg2:          NOTRUN -> [SKIP][31] ([i915#3539] / [i915#4852])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gem_exec_flush@basic-uc-rw-default.html

  * igt@gem_exec_reloc@basic-active:
    - shard-dg2:          NOTRUN -> [SKIP][32] ([i915#3281]) +4 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@gem_exec_reloc@basic-active.html

  * igt@gem_exec_reloc@basic-scanout:
    - shard-rkl:          NOTRUN -> [SKIP][33] ([i915#3281]) +12 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@gem_exec_reloc@basic-scanout.html

  * igt@gem_exec_reloc@basic-write-cpu-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][34] ([i915#3281]) +3 other tests skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@gem_exec_reloc@basic-write-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-write-gtt-active:
    - shard-dg1:          NOTRUN -> [SKIP][35] ([i915#3281]) +7 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@gem_exec_reloc@basic-write-gtt-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#4537] / [i915#4812])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-dg2:          NOTRUN -> [ABORT][37] ([i915#7975]) +2 other tests abort
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gem_exec_suspend@basic-s4-devices.html
    - shard-rkl:          NOTRUN -> [ABORT][38] ([i915#7975]) +2 other tests abort
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2:          NOTRUN -> [SKIP][39] ([i915#4860]) +2 other tests skip
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_fence_thrash@bo-write-verify-y:
    - shard-mtlp:         NOTRUN -> [SKIP][40] ([i915#4860])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@gem_fence_thrash@bo-write-verify-y.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][41] ([i915#12193])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg1:          NOTRUN -> [SKIP][42] ([i915#4565])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-tglu-1:       NOTRUN -> [SKIP][43] ([i915#4613]) +2 other tests skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random.html
    - shard-mtlp:         NOTRUN -> [SKIP][44] ([i915#4613])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][45] ([i915#4613]) +5 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random:
    - shard-tglu:         NOTRUN -> [SKIP][46] ([i915#4613]) +1 other test skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-7/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom@lmem0:
    - shard-dg2:          NOTRUN -> [DMESG-WARN][47] ([i915#5493]) +1 other test dmesg-warn
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_lmem_swapping@smem-oom@lmem0.html
    - shard-dg1:          [PASS][48] -> [TIMEOUT][49] ([i915#5493]) +1 other test timeout
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg1-17/igt@gem_lmem_swapping@smem-oom@lmem0.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@gem_lmem_swapping@smem-oom@lmem0.html

  * igt@gem_media_vme:
    - shard-rkl:          NOTRUN -> [SKIP][50] ([i915#284])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@gem_media_vme.html

  * igt@gem_mmap@bad-offset:
    - shard-dg1:          NOTRUN -> [SKIP][51] ([i915#4083]) +3 other tests skip
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@gem_mmap@bad-offset.html

  * igt@gem_mmap@bad-size:
    - shard-mtlp:         NOTRUN -> [SKIP][52] ([i915#4083]) +3 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@gem_mmap@bad-size.html

  * igt@gem_mmap@basic:
    - shard-dg2:          NOTRUN -> [SKIP][53] ([i915#4083])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@gem_mmap@basic.html

  * igt@gem_mmap_gtt@close-race:
    - shard-dg1:          NOTRUN -> [SKIP][54] ([i915#4077]) +11 other tests skip
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@gem_mmap_gtt@close-race.html

  * igt@gem_mmap_gtt@fault-concurrent:
    - shard-mtlp:         NOTRUN -> [SKIP][55] ([i915#4077]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@gem_mmap_gtt@fault-concurrent.html

  * igt@gem_partial_pwrite_pread@writes-after-reads:
    - shard-dg1:          NOTRUN -> [SKIP][56] ([i915#3282]) +4 other tests skip
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@gem_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#3282]) +4 other tests skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_pxp@display-protected-crc:
    - shard-dg2:          NOTRUN -> [SKIP][58] ([i915#4270])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-rkl:          NOTRUN -> [TIMEOUT][59] ([i915#12917] / [i915#12964]) +1 other test timeout
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_pxp@regular-baseline-src-copy-readible:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#4270]) +3 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@gem_pxp@regular-baseline-src-copy-readible.html

  * igt@gem_render_copy@linear-to-vebox-yf-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][61] ([i915#5190] / [i915#8428])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_render_copy@linear-to-vebox-yf-tiled.html

  * igt@gem_render_copy@yf-tiled-ccs-to-x-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][62] ([i915#8428])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@gem_render_copy@yf-tiled-ccs-to-x-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          NOTRUN -> [SKIP][63] ([i915#8411])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#4885])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_partial_pwrite_pread@writes:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#4077]) +5 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_tiled_partial_pwrite_pread@writes.html

  * igt@gem_tiled_pread_pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][66] ([i915#4079])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@gem_tiled_pread_pwrite.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-tglu:         [PASS][67] -> [FAIL][68] ([i915#12941])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-tglu-2/igt@gem_tiled_swapping@non-threaded.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@gem_tiled_swapping@non-threaded.html

  * igt@gem_unfence_active_buffers:
    - shard-dg1:          NOTRUN -> [SKIP][69] ([i915#4879])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@gem_unfence_active_buffers.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#3297]) +1 other test skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][71] ([i915#3297]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@relocations:
    - shard-dg1:          NOTRUN -> [SKIP][72] ([i915#3281] / [i915#3297])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@gem_userptr_blits@relocations.html

  * igt@gem_userptr_blits@unsync-unmap-after-close:
    - shard-tglu-1:       NOTRUN -> [SKIP][73] ([i915#3297]) +2 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@gem_userptr_blits@unsync-unmap-after-close.html
    - shard-mtlp:         NOTRUN -> [SKIP][74] ([i915#3297]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@gem_userptr_blits@unsync-unmap-after-close.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#3297]) +3 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-dg2:          NOTRUN -> [SKIP][76] +10 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-tglu:         NOTRUN -> [SKIP][77] ([i915#2527] / [i915#2856]) +1 other test skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@bb-start-cmd:
    - shard-tglu-1:       NOTRUN -> [SKIP][78] ([i915#2527] / [i915#2856]) +1 other test skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@gen9_exec_parse@bb-start-cmd.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-dg1:          NOTRUN -> [SKIP][79] ([i915#2527])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@gen9_exec_parse@shadow-peek.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-dg2:          NOTRUN -> [SKIP][80] ([i915#2856])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@gen9_exec_parse@valid-registers.html
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#2527]) +4 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_fb_tiling:
    - shard-dg1:          NOTRUN -> [SKIP][82] ([i915#4881])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@i915_fb_tiling.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-rkl:          [PASS][83] -> [ABORT][84] ([i915#9820])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-1/igt@i915_module_load@reload-with-fault-injection.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@i915_module_load@reload-with-fault-injection.html
    - shard-tglu:         [PASS][85] -> [ABORT][86] ([i915#12817] / [i915#9820])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-tglu-3/igt@i915_module_load@reload-with-fault-injection.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-rkl:          NOTRUN -> [SKIP][87] ([i915#8399]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-dg1:          NOTRUN -> [FAIL][88] ([i915#3591])
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
    - shard-dg1:          NOTRUN -> [FAIL][89] ([i915#12739] / [i915#3591])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html

  * igt@i915_pm_rpm@gem-execbuf-stress-pc8:
    - shard-mtlp:         NOTRUN -> [SKIP][90] +2 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@i915_pm_rpm@gem-execbuf-stress-pc8.html

  * igt@i915_pm_rpm@gem-idle:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][91] ([i915#4423])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@i915_pm_rpm@gem-idle.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-dg1:          NOTRUN -> [SKIP][92] ([i915#11681] / [i915#6621])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@i915_query@hwconfig_table:
    - shard-tglu:         NOTRUN -> [SKIP][93] ([i915#6245])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-2/igt@i915_query@hwconfig_table.html

  * igt@i915_query@query-topology-coherent-slice-mask:
    - shard-mtlp:         NOTRUN -> [SKIP][94] ([i915#6188])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@i915_query@query-topology-coherent-slice-mask.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-dg1:          NOTRUN -> [SKIP][95] ([i915#5723])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_selftest@mock@memory_region:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][96] ([i915#9311]) +1 other test dmesg-warn
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@i915_selftest@mock@memory_region.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-d-hdmi-a-1-y-rc-ccs-cc:
    - shard-tglu-1:       NOTRUN -> [SKIP][97] ([i915#8709]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-d-hdmi-a-1-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#8709]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][99] ([i915#8709]) +15 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-tglu-1:       NOTRUN -> [SKIP][100] ([i915#9531])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-mtlp:         [PASS][101] -> [FAIL][102] ([i915#11808] / [i915#5956]) +1 other test fail
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-mtlp-7/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
    - shard-tglu-1:       NOTRUN -> [SKIP][103] ([i915#1769] / [i915#3555])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-tglu:         NOTRUN -> [SKIP][104] ([i915#1769] / [i915#3555])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#5286]) +7 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][106] ([i915#5286]) +3 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-tglu-1:       NOTRUN -> [SKIP][107] ([i915#5286]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-dg1:          NOTRUN -> [SKIP][108] ([i915#4538] / [i915#5286]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-dg1:          NOTRUN -> [SKIP][109] ([i915#3638]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#3638]) +4 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
    - shard-dg2:          NOTRUN -> [SKIP][111] ([i915#4538] / [i915#5190]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-64bpp-rotate-0:
    - shard-dg1:          NOTRUN -> [SKIP][112] ([i915#4538]) +3 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_big_fb@yf-tiled-64bpp-rotate-0.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][113] +51 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][114] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][115] ([i915#6095]) +72 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-y-tiled-gen12-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][116] ([i915#12313])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][117] ([i915#6095]) +39 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-glk:          NOTRUN -> [SKIP][118] +49 other tests skip
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-glk2/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-dg1:          NOTRUN -> [SKIP][119] ([i915#12313]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][120] ([i915#12805])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#12805])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
    - shard-dg1:          NOTRUN -> [SKIP][122] ([i915#12805])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-d-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#6095]) +9 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-mc-ccs@pipe-d-edp-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#6095]) +7 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs-cc@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][125] ([i915#6095]) +39 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][126] ([i915#12313])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][127] ([i915#10307] / [i915#6095]) +119 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][128] ([i915#12313]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_ccs@random-ccs-data-4-tiled-bmg-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][129] ([i915#12313]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][130] ([i915#6095]) +103 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_cdclk@mode-transition:
    - shard-tglu-1:       NOTRUN -> [SKIP][131] ([i915#3742])
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#3742])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][133] ([i915#11616] / [i915#7213]) +4 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_edid@hdmi-edid-change-during-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][134] ([i915#11151] / [i915#7828]) +8 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_chamelium_edid@hdmi-edid-change-during-suspend.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-tglu-1:       NOTRUN -> [SKIP][135] ([i915#11151] / [i915#7828]) +6 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#11151] / [i915#7828]) +3 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-4k.html

  * igt@kms_chamelium_hpd@dp-hpd-after-suspend:
    - shard-dg1:          NOTRUN -> [SKIP][137] ([i915#11151] / [i915#7828]) +7 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@hdmi-hpd:
    - shard-mtlp:         NOTRUN -> [SKIP][138] ([i915#11151] / [i915#7828])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_chamelium_hpd@hdmi-hpd.html

  * igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
    - shard-dg2:          NOTRUN -> [SKIP][139] ([i915#11151] / [i915#7828]) +1 other test skip
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#7118] / [i915#9424])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic-dpms@pipe-a-dp-4:
    - shard-dg2:          NOTRUN -> [TIMEOUT][142] ([i915#7173])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-10/igt@kms_content_protection@atomic-dpms@pipe-a-dp-4.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg1:          NOTRUN -> [SKIP][143] ([i915#3299])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#3116] / [i915#3299])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_content_protection@dp-mst-type-0.html
    - shard-mtlp:         NOTRUN -> [SKIP][145] ([i915#3299])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_content_protection@dp-mst-type-0.html
    - shard-dg2:          NOTRUN -> [SKIP][146] ([i915#3299])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][147] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@lic-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][148] ([i915#9424])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-64x21:
    - shard-mtlp:         NOTRUN -> [SKIP][149] ([i915#8814])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_cursor_crc@cursor-offscreen-64x21.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][150] ([i915#3555])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][151] ([i915#13049])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg1:          NOTRUN -> [SKIP][152] ([i915#13049]) +1 other test skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#3555]) +1 other test skip
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-dg1:          NOTRUN -> [SKIP][154] ([i915#4103] / [i915#4213])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#4103])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#4103])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#9723])
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
    - shard-dg2:          NOTRUN -> [SKIP][158] ([i915#9833])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dp_aux_dev:
    - shard-tglu-1:       NOTRUN -> [SKIP][159] ([i915#1257])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_dp_aux_dev.html

  * igt@kms_dsc@dsc-fractional-bpp:
    - shard-mtlp:         NOTRUN -> [SKIP][160] ([i915#3840] / [i915#9688])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_dsc@dsc-fractional-bpp.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-dg1:          NOTRUN -> [SKIP][161] ([i915#3555] / [i915#3840]) +1 other test skip
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#3840] / [i915#9053])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
    - shard-tglu:         NOTRUN -> [SKIP][163] ([i915#3840] / [i915#9053])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#3955])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
    - shard-tglu:         NOTRUN -> [SKIP][165] ([i915#3469])
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#1839])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#9337])
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][168] ([i915#658])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_feature_discovery@psr1.html
    - shard-rkl:          NOTRUN -> [SKIP][169] ([i915#658])
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-busy-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][170] ([i915#3637])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_flip@2x-busy-flip.html

  * igt@kms_flip@2x-flip-vs-blocking-wf-vblank:
    - shard-tglu-1:       NOTRUN -> [SKIP][171] ([i915#3637]) +5 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_flip@2x-flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][172] ([i915#9934]) +11 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-dg1:          NOTRUN -> [SKIP][173] ([i915#8381]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-flip-vs-panning-vs-hang:
    - shard-tglu:         NOTRUN -> [SKIP][174] ([i915#3637]) +3 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_flip@2x-flip-vs-panning-vs-hang.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][175] ([i915#9934]) +2 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-dg1:          NOTRUN -> [SKIP][176] ([i915#9934]) +5 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@flip-vs-fences:
    - shard-dg2:          NOTRUN -> [SKIP][177] ([i915#8381]) +1 other test skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_flip@flip-vs-fences.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][178] ([i915#12745] / [i915#4839])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-glk2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][179] ([i915#12745])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-glk2/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html

  * igt@kms_flip@plain-flip-ts-check:
    - shard-dg2:          [PASS][180] -> [FAIL][181] ([i915#11989]) +3 other tests fail
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-1/igt@kms_flip@plain-flip-ts-check.html
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-2/igt@kms_flip@plain-flip-ts-check.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][182] ([i915#2672] / [i915#3555]) +2 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][183] ([i915#2672] / [i915#3555] / [i915#8813]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][184] ([i915#2672] / [i915#8813]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#2672] / [i915#3555])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
    - shard-tglu-1:       NOTRUN -> [SKIP][186] ([i915#2672] / [i915#3555]) +2 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][187] ([i915#2587] / [i915#2672]) +3 other tests skip
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling:
    - shard-dg1:          NOTRUN -> [SKIP][188] ([i915#2587] / [i915#2672] / [i915#3555])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][189] ([i915#2587] / [i915#2672]) +1 other test skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-dg2:          NOTRUN -> [SKIP][190] ([i915#2672] / [i915#3555] / [i915#5190])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode:
    - shard-dg2:          NOTRUN -> [SKIP][191] ([i915#2672]) +1 other test skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][192] ([i915#2587] / [i915#2672] / [i915#3555])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][193] ([i915#2672] / [i915#3555])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][194] ([i915#2587] / [i915#2672]) +2 other tests skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][195] ([i915#2672] / [i915#3555]) +3 other tests skip
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][196] ([i915#2672]) +3 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt:
    - shard-dg2:          NOTRUN -> [FAIL][197] ([i915#6880])
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-dg2:          [PASS][198] -> [FAIL][199] ([i915#6880]) +1 other test fail
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][200] ([i915#8708]) +12 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-mtlp:         NOTRUN -> [SKIP][201] ([i915#1825]) +6 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][202] ([i915#8708]) +16 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move:
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#5354]) +7 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][204] ([i915#3458]) +7 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][205] ([i915#8708])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][206] +25 other tests skip
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-indfb-fliptrack-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][207] +33 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][208] ([i915#5439])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-rkl:          NOTRUN -> [SKIP][209] ([i915#9766])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
    - shard-dg2:          NOTRUN -> [SKIP][210] ([i915#9766])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
    - shard-dg1:          NOTRUN -> [SKIP][211] ([i915#3458]) +10 other tests skip
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][212] ([i915#3023]) +26 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][213] ([i915#1825]) +44 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][214] +61 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch:
    - shard-tglu-1:       NOTRUN -> [SKIP][215] ([i915#3555] / [i915#8228])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][216] ([i915#3555] / [i915#8228]) +3 other tests skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-dg2:          NOTRUN -> [SKIP][217] ([i915#12713])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_hdr@brightness-with-hdr.html
    - shard-tglu-1:       NOTRUN -> [SKIP][218] ([i915#12713])
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#3555] / [i915#8228])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-swap:
    - shard-dg1:          NOTRUN -> [SKIP][220] ([i915#3555] / [i915#8228]) +1 other test skip
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle:
    - shard-dg2:          [PASS][221] -> [SKIP][222] ([i915#3555] / [i915#8228])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-10/igt@kms_hdr@static-toggle.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-5/igt@kms_hdr@static-toggle.html
    - shard-tglu:         NOTRUN -> [SKIP][223] ([i915#3555] / [i915#8228])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-mtlp:         NOTRUN -> [SKIP][224] ([i915#3555] / [i915#8228])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][225] ([i915#12394])
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][226] ([i915#6301])
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-2/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#6301])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_panel_fitting@legacy.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#3555]) +6 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][229] ([i915#12247]) +13 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-pixel-format@pipe-c.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers:
    - shard-mtlp:         NOTRUN -> [SKIP][230] ([i915#12247]) +4 other tests skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-modifiers.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25:
    - shard-rkl:          NOTRUN -> [SKIP][231] ([i915#12247] / [i915#6953])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25:
    - shard-tglu:         NOTRUN -> [SKIP][232] ([i915#12247] / [i915#6953])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b:
    - shard-rkl:          NOTRUN -> [SKIP][233] ([i915#12247]) +1 other test skip
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-dg1:          NOTRUN -> [SKIP][234] ([i915#12247] / [i915#6953])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b:
    - shard-dg1:          NOTRUN -> [SKIP][235] ([i915#12247]) +13 other tests skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-b.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][236] ([i915#12343])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][237] ([i915#9812]) +1 other test skip
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([i915#5354])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][239] ([i915#9340])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_pm_lpsp@kms-lpsp.html
    - shard-tglu:         NOTRUN -> [SKIP][240] ([i915#3828])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-rkl:          NOTRUN -> [SKIP][241] ([i915#8430])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-dg1:          NOTRUN -> [SKIP][242] ([i915#9519])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [PASS][243] -> [SKIP][244] ([i915#9519])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-7/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [PASS][245] -> [SKIP][246] ([i915#9519]) +1 other test skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-2/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
    - shard-rkl:          NOTRUN -> [SKIP][247] ([i915#9519]) +2 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@d3hot:
    - shard-dg1:          NOTRUN -> [SKIP][248] ([i915#6524]) +1 other test skip
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][249] ([i915#11520]) +3 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf:
    - shard-rkl:          NOTRUN -> [SKIP][250] ([i915#11520]) +10 other tests skip
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_psr2_sf@fbc-psr2-cursor-plane-update-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-mtlp:         NOTRUN -> [SKIP][251] ([i915#12316]) +2 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][252] ([i915#9808])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][253] ([i915#11520])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-glk2/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area:
    - shard-snb:          NOTRUN -> [SKIP][254] ([i915#11520]) +1 other test skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-snb2/igt@kms_psr2_sf@pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][255] ([i915#11520]) +4 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-dg1:          NOTRUN -> [SKIP][256] ([i915#11520]) +6 other tests skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu-1:       NOTRUN -> [SKIP][257] ([i915#11520]) +6 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-mtlp:         NOTRUN -> [SKIP][258] ([i915#4348])
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-tglu:         NOTRUN -> [SKIP][259] ([i915#9683])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-no-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][260] ([i915#1072] / [i915#9732]) +24 other tests skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_psr@fbc-pr-no-drrs.html

  * igt@kms_psr@fbc-psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][261] ([i915#1072] / [i915#9732]) +7 other tests skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-6/igt@kms_psr@fbc-psr-cursor-mmap-cpu.html

  * igt@kms_psr@fbc-psr2-sprite-plane-move:
    - shard-mtlp:         NOTRUN -> [SKIP][262] ([i915#9688]) +3 other tests skip
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_psr@fbc-psr2-sprite-plane-move.html

  * igt@kms_psr@psr-primary-render:
    - shard-tglu:         NOTRUN -> [SKIP][263] ([i915#9732]) +13 other tests skip
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-6/igt@kms_psr@psr-primary-render.html

  * igt@kms_psr@psr-sprite-blt:
    - shard-snb:          NOTRUN -> [SKIP][264] +63 other tests skip
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-snb2/igt@kms_psr@psr-sprite-blt.html

  * igt@kms_psr@psr-sprite-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][265] ([i915#9732]) +14 other tests skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_psr@psr-sprite-mmap-cpu.html

  * igt@kms_psr@psr2-sprite-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][266] ([i915#1072] / [i915#9732]) +15 other tests skip
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_psr@psr2-sprite-mmap-gtt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-dg1:          NOTRUN -> [SKIP][267] ([i915#9685])
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][268] ([i915#9685])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-mtlp:         NOTRUN -> [SKIP][269] ([i915#5289])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
    - shard-rkl:          NOTRUN -> [SKIP][270] ([i915#5289]) +1 other test skip
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html

  * igt@kms_scaling_modes@scaling-mode-center:
    - shard-dg1:          NOTRUN -> [SKIP][271] ([i915#3555]) +8 other tests skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_scaling_modes@scaling-mode-center.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-mtlp:         NOTRUN -> [ABORT][272] ([i915#13179]) +1 other test abort
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_setmode@basic:
    - shard-tglu-1:       NOTRUN -> [FAIL][273] ([i915#5465]) +2 other tests fail
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_setmode@basic.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg1:          NOTRUN -> [FAIL][274] ([IGT#160] / [i915#6493])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-14/igt@kms_sysfs_edid_timing.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg1:          NOTRUN -> [SKIP][275] ([i915#8623])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-rkl:          NOTRUN -> [SKIP][276] ([i915#8623])
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
    - shard-tglu:         NOTRUN -> [SKIP][277] ([i915#8623])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@wait-forked:
    - shard-rkl:          [PASS][278] -> [DMESG-WARN][279] ([i915#12964]) +8 other tests dmesg-warn
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-5/igt@kms_vblank@wait-forked.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_vblank@wait-forked.html

  * igt@kms_vrr@lobf:
    - shard-mtlp:         NOTRUN -> [SKIP][280] ([i915#11920])
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-5/igt@kms_vrr@lobf.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          NOTRUN -> [SKIP][281] ([i915#9906]) +1 other test skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-dg2:          NOTRUN -> [SKIP][282] ([i915#2437]) +1 other test skip
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@kms_writeback@writeback-fb-id.html
    - shard-tglu-1:       NOTRUN -> [SKIP][283] ([i915#2437])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg1:          NOTRUN -> [SKIP][284] ([i915#2437]) +1 other test skip
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-12/igt@kms_writeback@writeback-invalid-parameters.html
    - shard-rkl:          NOTRUN -> [SKIP][285] ([i915#2437])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-5/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-dg1:          NOTRUN -> [SKIP][286] ([i915#2437] / [i915#9412])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_writeback@writeback-pixel-formats.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][287] ([i915#2436])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          NOTRUN -> [SKIP][288] ([i915#2435])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@perf@per-context-mode-unprivileged.html

  * igt@perf_pmu@rc6@other-idle-gt0:
    - shard-dg2:          NOTRUN -> [SKIP][289] ([i915#8516])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@perf_pmu@rc6@other-idle-gt0.html
    - shard-tglu-1:       NOTRUN -> [SKIP][290] ([i915#8516])
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@perf_pmu@rc6@other-idle-gt0.html

  * igt@prime_vgem@basic-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][291] ([i915#3708] / [i915#4077])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-write:
    - shard-dg1:          NOTRUN -> [SKIP][292] ([i915#3708]) +1 other test skip
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-17/igt@prime_vgem@basic-write.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each:
    - shard-rkl:          NOTRUN -> [SKIP][293] ([i915#9917])
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-1/igt@sriov_basic@enable-vfs-bind-unbind-each.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-tglu-1:       NOTRUN -> [FAIL][294] ([i915#12910])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-1/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random:
    - shard-tglu:         NOTRUN -> [FAIL][295] ([i915#12910]) +8 other tests fail
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-8/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random.html

  * igt@syncobj_eventfd@binary-wait-before-signal:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][296] ([i915#12964]) +10 other tests dmesg-warn
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-3/igt@syncobj_eventfd@binary-wait-before-signal.html

  
#### Possible fixes ####

  * igt@gem_ccs@suspend-resume:
    - shard-dg2:          [INCOMPLETE][297] ([i915#7297]) -> [PASS][298]
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-6/igt@gem_ccs@suspend-resume.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [INCOMPLETE][299] ([i915#12392] / [i915#7297]) -> [PASS][300]
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-6/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-8/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-dg2:          [ABORT][301] ([i915#13427]) -> [PASS][302]
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-4/igt@gem_create@create-ext-cpu-access-big.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-4/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_exec_whisper@basic-queues-priority-all:
    - shard-rkl:          [DMESG-WARN][303] ([i915#12964]) -> [PASS][304]
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-2/igt@gem_exec_whisper@basic-queues-priority-all.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-7/igt@gem_exec_whisper@basic-queues-priority-all.html

  * igt@gem_workarounds@reset:
    - shard-mtlp:         [ABORT][305] ([i915#13193]) -> [PASS][306] +2 other tests pass
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-mtlp-7/igt@gem_workarounds@reset.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@gem_workarounds@reset.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition:
    - shard-rkl:          [FAIL][307] ([i915#11808]) -> [PASS][308]
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-4/igt@kms_atomic_transition@plane-toggle-modeset-transition.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-6/igt@kms_atomic_transition@plane-toggle-modeset-transition.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [FAIL][309] ([i915#5138]) -> [PASS][310]
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-rkl:          [FAIL][311] ([i915#13566]) -> [PASS][312] +3 other tests pass
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-64x21.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-6/igt@kms_cursor_crc@cursor-sliding-64x21.html
    - shard-tglu:         [FAIL][313] ([i915#13566]) -> [PASS][314] +1 other test pass
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-tglu-5/igt@kms_cursor_crc@cursor-sliding-64x21.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-7/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-dg2:          [SKIP][315] ([i915#3555] / [i915#8228]) -> [PASS][316]
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-7/igt@kms_hdr@static-toggle-dpms.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-10/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_pm_rpm@dpms-mode-unset-lpsp:
    - shard-dg2:          [SKIP][317] ([i915#9519]) -> [PASS][318]
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-5/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-4/igt@kms_pm_rpm@dpms-mode-unset-lpsp.html

  * igt@perf@polling@0-rcs0:
    - shard-tglu:         [FAIL][319] ([i915#10538]) -> [PASS][320] +1 other test pass
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-tglu-7/igt@perf@polling@0-rcs0.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-7/igt@perf@polling@0-rcs0.html

  * igt@perf_pmu@module-unload:
    - shard-tglu:         [INCOMPLETE][321] -> [PASS][322]
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-tglu-5/igt@perf_pmu@module-unload.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-tglu-7/igt@perf_pmu@module-unload.html

  
#### Warnings ####

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-mtlp:         [ABORT][323] ([i915#10131]) -> [ABORT][324] ([i915#10131] / [i915#10887] / [i915#9820])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-mtlp-7/igt@i915_module_load@reload-with-fault-injection.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-mtlp-3/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_selftest@mock:
    - shard-glk:          [DMESG-WARN][325] ([i915#9311]) -> [DMESG-WARN][326] ([i915#1982] / [i915#9311])
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-glk9/igt@i915_selftest@mock.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-glk6/igt@i915_selftest@mock.html

  * igt@kms_addfb_basic@addfb25-x-tiled-legacy:
    - shard-dg1:          [SKIP][327] ([i915#4212] / [i915#4423]) -> [SKIP][328] ([i915#4212])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg1-18/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-18/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html

  * igt@kms_content_protection@atomic:
    - shard-dg2:          [TIMEOUT][329] ([i915#7173]) -> [SKIP][330] ([i915#7118] / [i915#9424])
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-10/igt@kms_content_protection@atomic.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-3/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          [SKIP][331] ([i915#7118] / [i915#9424]) -> [TIMEOUT][332] ([i915#7173])
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-7/igt@kms_content_protection@atomic-dpms.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-10/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg1:          [SKIP][333] ([i915#9424]) -> [SKIP][334] ([i915#9433])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg1-14/igt@kms_content_protection@mei-interface.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-13/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][335] ([i915#7118] / [i915#9424]) -> [SKIP][336] ([i915#7118] / [i915#7162] / [i915#9424])
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-7/igt@kms_content_protection@type1.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-10/igt@kms_content_protection@type1.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][337] ([i915#4423]) -> [SKIP][338]
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
    - shard-dg2:          [SKIP][339] ([i915#3458]) -> [SKIP][340] ([i915#10433] / [i915#3458]) +1 other test skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          [SKIP][341] ([i915#10433] / [i915#3458]) -> [SKIP][342] ([i915#3458])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          [SKIP][343] ([i915#4070] / [i915#4816]) -> [SKIP][344] ([i915#4816])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16054/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#160]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/160
  [i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#10887]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10887
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11616]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11616
  [i915#11681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11681
  [i915#11713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11713
  [i915#11808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11808
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#11989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11989
  [i915#12193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12193
  [i915#12247]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12247
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12316]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12316
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12392]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12392
  [i915#12394]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12394
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12739]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12739
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12817
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#12917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12917
  [i915#12941]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12941
  [i915#12964]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12964
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13193]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13193
  [i915#13427]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13427
  [i915#13522]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13522
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
  [i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#3955]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3955
  [i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
  [i915#4213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4213
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4348]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4348
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4565]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4565
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4873]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4873
  [i915#4879]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4879
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
  [i915#4885]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4885
  [i915#4958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4958
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
  [i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
  [i915#5507]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5507
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6118
  [i915#6188]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6188
  [i915#6245]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6245
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6493
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
  [i915#6805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6805
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#6953]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6953
  [i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
  [i915#7297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7297
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8289
  [i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
  [i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
  [i915#8813]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8813
  [i915#8814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8814
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9100]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9100
  [i915#9311]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9311
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
  [i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
  [i915#9808]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9808
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
  [i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_16054 -> Patchwork_144240v1

  CI-20190529: 20190529
  CI_DRM_16054: 907133c4b6b53621c4e90697c1cc85ccef3f5711 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8220: 8220
  Patchwork_144240v1: 907133c4b6b53621c4e90697c1cc85ccef3f5711 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v1/index.html

[-- Attachment #2: Type: text/html, Size: 121587 bytes --]

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Gustavo Sousa]

Quoting Imre Deak (2025-02-03 16:22:44-03:00)
>On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
>> > > > [...]
>> > > >
>> > > > The driver enabling DC6 is not an enough condition for DC6 being allowed
>> > > > from the display side. Some display clock gating etc. configuration by
>> > > > the driver could be blocking it. According to the HW team, DC5 being
>> > > > entered while DC6 is enabled is a guarantee that DC6 is allowed from the
>> > > > display side - i.e. the driver has configured everything correctly for
>> > > > that.
>> > > 
>> > > Fair enough. So IGT test case would check directly if DC5 counter is
>> > > increasing and DC6 is allowed.
>> > > 
>> > > Something as simple as this in the kernel code would tell that
>> > > DC6 is enabled:
>> > > 
>> > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> > > @@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>> > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
>> > >                            intel_de_read(display, dc6_reg));
>> > >  
>> > > +       seq_printf(m, "DC6 allowed: %s\n", str_yes_no((intel_de_read(display,
>> > > +                                                                   DC_STATE_EN)
>> > > +                                                     & 0x3) == 2));
>> > > +
>> > > 
>> > > and
>> > > 
>> > > $ cat i915_dmc_info
>> > > [snip]
>> > > DC3 -> DC5 count: 286
>> > > DC5 -> DC6 count: 0
>> > > DC6 allowed: yes
>> > > [snip]
>> > > 
>> > > $ cat i915_dmc_info
>> > > [snip]
>> > > DC3 -> DC5 count: 292
>> > > DC5 -> DC6 count: 0
>> > > DC6 allowed: yes
>> > > [snip]
>> > > 
>> > > Thoughts?
>> > 
>> > The DC5 increment could've happened while DC6 was disabled by the driver.
>> 
>> Yes, it could... in general the dc6 bit would be zero, but right, there's
>> a possible race.
>> 
>> But should we complicate things when we know that on the test case itself
>> we are in full control of the modeset?! From the test perspective I believe
>> this would be more than enough without complicating things.
>
>Imo having a counter which works based on the condition that guarantees the
>display to allow DC6, would help later in debugging.
>
>> But well, if you really believe that we need to go further in the driver
>> to cover that it is fine by me.
>> 
>> But just to ensure that we are in the same page, could you please open
>> up a bit more of your idea on when to increase the dc5 sw counters
>> in a way that we would ensure that we don't have race and that we
>> get the dc6 allowed counter correctly?
>
>Something like the following:
>
>1. Right after the driver sets DC6_EN, it stores the DC5 HW counter's
>   current value:
>   dc5_start = dc5_current
>2. Right before the driver clears DC6_EN, it updates the DC6 allowed
>   counter:
>   dc6_allowed += dc5_current - dc5_start
>   dc5_start = dc5_current
>3. When userspace reads the counters via debugfs the driver first
>   updates dc6_allowed the same way as 2. did if DC6_EN is set.

This sounds good to me.

I'd like to add that we should ensure that DC6 is really being allowed,
so that might need to be handled inside gen9_set_dc_state(), where
allowed_dc_mask is applied.

--
Gustavo Sousa

>
>> Btw, while doing this experiment I noticed that the debugfs and test
>> also doesn't call that residency anyway and it is just count. So
>> perhaps with your idea we don't need to change the debugfs interface.

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Vivi, Rodrigo]

On Mon, 2025-02-03 at 17:19 -0300, Gustavo Sousa wrote:
> Quoting Imre Deak (2025-02-03 16:22:44-03:00)
> > On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
> > > > > > [...]
> > > > > > 
> > > > > > The driver enabling DC6 is not an enough condition for DC6
> > > > > > being allowed
> > > > > > from the display side. Some display clock gating etc.
> > > > > > configuration by
> > > > > > the driver could be blocking it. According to the HW team,
> > > > > > DC5 being
> > > > > > entered while DC6 is enabled is a guarantee that DC6 is
> > > > > > allowed from the
> > > > > > display side - i.e. the driver has configured everything
> > > > > > correctly for
> > > > > > that.
> > > > > 
> > > > > Fair enough. So IGT test case would check directly if DC5
> > > > > counter is
> > > > > increasing and DC6 is allowed.
> > > > > 
> > > > > Something as simple as this in the kernel code would tell
> > > > > that
> > > > > DC6 is enabled:
> > > > > 
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > @@ -1294,6 +1294,10 @@ static int
> > > > > intel_dmc_debugfs_status_show(struct seq_file *m, void
> > > > > *unused)
> > > > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > > >                            intel_de_read(display, dc6_reg));
> > > > >  
> > > > > +       seq_printf(m, "DC6 allowed: %s\n",
> > > > > str_yes_no((intel_de_read(display,
> > > > > +                                                            
> > > > >        DC_STATE_EN)
> > > > > +                                                     & 0x3)
> > > > > == 2));
> > > > > +
> > > > > 
> > > > > and
> > > > > 
> > > > > $ cat i915_dmc_info
> > > > > [snip]
> > > > > DC3 -> DC5 count: 286
> > > > > DC5 -> DC6 count: 0
> > > > > DC6 allowed: yes
> > > > > [snip]
> > > > > 
> > > > > $ cat i915_dmc_info
> > > > > [snip]
> > > > > DC3 -> DC5 count: 292
> > > > > DC5 -> DC6 count: 0
> > > > > DC6 allowed: yes
> > > > > [snip]
> > > > > 
> > > > > Thoughts?
> > > > 
> > > > The DC5 increment could've happened while DC6 was disabled by
> > > > the driver.
> > > 
> > > Yes, it could... in general the dc6 bit would be zero, but right,
> > > there's
> > > a possible race.
> > > 
> > > But should we complicate things when we know that on the test
> > > case itself
> > > we are in full control of the modeset?! From the test perspective
> > > I believe
> > > this would be more than enough without complicating things.
> > 
> > Imo having a counter which works based on the condition that
> > guarantees the
> > display to allow DC6, would help later in debugging.

yeap, it makes sense

> > 
> > > But well, if you really believe that we need to go further in the
> > > driver
> > > to cover that it is fine by me.
> > > 
> > > But just to ensure that we are in the same page, could you please
> > > open
> > > up a bit more of your idea on when to increase the dc5 sw
> > > counters
> > > in a way that we would ensure that we don't have race and that we
> > > get the dc6 allowed counter correctly?
> > 
> > Something like the following:
> > 
> > 1. Right after the driver sets DC6_EN, it stores the DC5 HW
> > counter's
> >   current value:
> >   dc5_start = dc5_current
> > 2. Right before the driver clears DC6_EN, it updates the DC6
> > allowed
> >   counter:
> >   dc6_allowed += dc5_current - dc5_start
> >   dc5_start = dc5_current
> > 3. When userspace reads the counters via debugfs the driver first
> >   updates dc6_allowed the same way as 2. did if DC6_EN is set.
> 
> This sounds good to me.

I like that as well.

> 
> I'd like to add that we should ensure that DC6 is really being
> allowed,
> so that might need to be handled inside gen9_set_dc_state(), where
> allowed_dc_mask is applied.

well, for that we can also have the 

--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct
seq_file *m, void *unused)
                seq_printf(m, "DC5 -> DC6 count: %d\n",
                           intel_de_read(display, dc6_reg));

+       seq_printf(m, "DC6 allowed: %s\n",
str_yes_no((intel_de_read(display,
+                                                                  
DC_STATE_EN)
+                                                     & 0x3) == 2));

on top of what Imre suggested right?
so the dc6 count is updated and also we have the live view of the
register set

no?

not sure why we need to go to the dc9 func...

> 
> --
> Gustavo Sousa
> 
> > 
> > > Btw, while doing this experiment I noticed that the debugfs and
> > > test
> > > also doesn't call that residency anyway and it is just count. So
> > > perhaps with your idea we don't need to change the debugfs
> > > interface.

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Gustavo Sousa]

Quoting Vivi, Rodrigo (2025-02-03 17:23:53-03:00)
>On Mon, 2025-02-03 at 17:19 -0300, Gustavo Sousa wrote:
>> Quoting Imre Deak (2025-02-03 16:22:44-03:00)
>> > On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
>> > > > > > [...]
>> > > > > > 
>> > > > > > The driver enabling DC6 is not an enough condition for DC6
>> > > > > > being allowed
>> > > > > > from the display side. Some display clock gating etc.
>> > > > > > configuration by
>> > > > > > the driver could be blocking it. According to the HW team,
>> > > > > > DC5 being
>> > > > > > entered while DC6 is enabled is a guarantee that DC6 is
>> > > > > > allowed from the
>> > > > > > display side - i.e. the driver has configured everything
>> > > > > > correctly for
>> > > > > > that.
>> > > > > 
>> > > > > Fair enough. So IGT test case would check directly if DC5
>> > > > > counter is
>> > > > > increasing and DC6 is allowed.
>> > > > > 
>> > > > > Something as simple as this in the kernel code would tell
>> > > > > that
>> > > > > DC6 is enabled:
>> > > > > 
>> > > > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> > > > > @@ -1294,6 +1294,10 @@ static int
>> > > > > intel_dmc_debugfs_status_show(struct seq_file *m, void
>> > > > > *unused)
>> > > > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
>> > > > >                            intel_de_read(display, dc6_reg));
>> > > > >  
>> > > > > +       seq_printf(m, "DC6 allowed: %s\n",
>> > > > > str_yes_no((intel_de_read(display,
>> > > > > +                                                            
>> > > > >        DC_STATE_EN)
>> > > > > +                                                     & 0x3)
>> > > > > == 2));
>> > > > > +
>> > > > > 
>> > > > > and
>> > > > > 
>> > > > > $ cat i915_dmc_info
>> > > > > [snip]
>> > > > > DC3 -> DC5 count: 286
>> > > > > DC5 -> DC6 count: 0
>> > > > > DC6 allowed: yes
>> > > > > [snip]
>> > > > > 
>> > > > > $ cat i915_dmc_info
>> > > > > [snip]
>> > > > > DC3 -> DC5 count: 292
>> > > > > DC5 -> DC6 count: 0
>> > > > > DC6 allowed: yes
>> > > > > [snip]
>> > > > > 
>> > > > > Thoughts?
>> > > > 
>> > > > The DC5 increment could've happened while DC6 was disabled by
>> > > > the driver.
>> > > 
>> > > Yes, it could... in general the dc6 bit would be zero, but right,
>> > > there's
>> > > a possible race.
>> > > 
>> > > But should we complicate things when we know that on the test
>> > > case itself
>> > > we are in full control of the modeset?! From the test perspective
>> > > I believe
>> > > this would be more than enough without complicating things.
>> > 
>> > Imo having a counter which works based on the condition that
>> > guarantees the
>> > display to allow DC6, would help later in debugging.
>
>yeap, it makes sense
>
>> > 
>> > > But well, if you really believe that we need to go further in the
>> > > driver
>> > > to cover that it is fine by me.
>> > > 
>> > > But just to ensure that we are in the same page, could you please
>> > > open
>> > > up a bit more of your idea on when to increase the dc5 sw
>> > > counters
>> > > in a way that we would ensure that we don't have race and that we
>> > > get the dc6 allowed counter correctly?
>> > 
>> > Something like the following:
>> > 
>> > 1. Right after the driver sets DC6_EN, it stores the DC5 HW
>> > counter's
>> >   current value:
>> >   dc5_start = dc5_current
>> > 2. Right before the driver clears DC6_EN, it updates the DC6
>> > allowed
>> >   counter:
>> >   dc6_allowed += dc5_current - dc5_start
>> >   dc5_start = dc5_current
>> > 3. When userspace reads the counters via debugfs the driver first
>> >   updates dc6_allowed the same way as 2. did if DC6_EN is set.
>> 
>> This sounds good to me.
>
>I like that as well.
>
>> 
>> I'd like to add that we should ensure that DC6 is really being
>> allowed,
>> so that might need to be handled inside gen9_set_dc_state(), where
>> allowed_dc_mask is applied.
>
>well, for that we can also have the 
>
>--- a/drivers/gpu/drm/i915/display/intel_dmc.c
>+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>@@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct
>seq_file *m, void *unused)
>                seq_printf(m, "DC5 -> DC6 count: %d\n",
>                           intel_de_read(display, dc6_reg));
>
>+       seq_printf(m, "DC6 allowed: %s\n",
>str_yes_no((intel_de_read(display,
>+                                                                  
>DC_STATE_EN)
>+                                                     & 0x3) == 2));
>
>on top of what Imre suggested right?
>so the dc6 count is updated and also we have the live view of the
>register set

Hm... Not sure if that would be required to validate that the display
engine was ready for DC6. I guess the dc6_allowed counter would be
enough.

>
>no?
>
>not sure why we need to go to the dc9 func...

Hm... dc9? Did you mean gen9_set_dc_state()?

Function sanitizes the target value for DC_STATE_EN so that we do not
use a value that is not allowed (e.g. when the driver was loaded with
enable_dc=0).

--
Gustavo Sousa

>
>> 
>> --
>> Gustavo Sousa
>> 
>> > 
>> > > Btw, while doing this experiment I noticed that the debugfs and
>> > > test
>> > > also doesn't call that residency anyway and it is just count. So
>> > > perhaps with your idea we don't need to change the debugfs
>> > > interface.
>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Vivi, Rodrigo]

On Mon, 2025-02-03 at 17:40 -0300, Gustavo Sousa wrote:
> Quoting Vivi, Rodrigo (2025-02-03 17:23:53-03:00)
> > On Mon, 2025-02-03 at 17:19 -0300, Gustavo Sousa wrote:
> > > Quoting Imre Deak (2025-02-03 16:22:44-03:00)
> > > > On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
> > > > > > > > [...]
> > > > > > > > 
> > > > > > > > The driver enabling DC6 is not an enough condition for
> > > > > > > > DC6
> > > > > > > > being allowed
> > > > > > > > from the display side. Some display clock gating etc.
> > > > > > > > configuration by
> > > > > > > > the driver could be blocking it. According to the HW
> > > > > > > > team,
> > > > > > > > DC5 being
> > > > > > > > entered while DC6 is enabled is a guarantee that DC6 is
> > > > > > > > allowed from the
> > > > > > > > display side - i.e. the driver has configured
> > > > > > > > everything
> > > > > > > > correctly for
> > > > > > > > that.
> > > > > > > 
> > > > > > > Fair enough. So IGT test case would check directly if DC5
> > > > > > > counter is
> > > > > > > increasing and DC6 is allowed.
> > > > > > > 
> > > > > > > Something as simple as this in the kernel code would tell
> > > > > > > that
> > > > > > > DC6 is enabled:
> > > > > > > 
> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > > > > > > @@ -1294,6 +1294,10 @@ static int
> > > > > > > intel_dmc_debugfs_status_show(struct seq_file *m, void
> > > > > > > *unused)
> > > > > > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
> > > > > > >                            intel_de_read(display,
> > > > > > > dc6_reg));
> > > > > > >  
> > > > > > > +       seq_printf(m, "DC6 allowed: %s\n",
> > > > > > > str_yes_no((intel_de_read(display,
> > > > > > > +                                                        
> > > > > > >     
> > > > > > >        DC_STATE_EN)
> > > > > > > +                                                     &
> > > > > > > 0x3)
> > > > > > > == 2));
> > > > > > > +
> > > > > > > 
> > > > > > > and
> > > > > > > 
> > > > > > > $ cat i915_dmc_info
> > > > > > > [snip]
> > > > > > > DC3 -> DC5 count: 286
> > > > > > > DC5 -> DC6 count: 0
> > > > > > > DC6 allowed: yes
> > > > > > > [snip]
> > > > > > > 
> > > > > > > $ cat i915_dmc_info
> > > > > > > [snip]
> > > > > > > DC3 -> DC5 count: 292
> > > > > > > DC5 -> DC6 count: 0
> > > > > > > DC6 allowed: yes
> > > > > > > [snip]
> > > > > > > 
> > > > > > > Thoughts?
> > > > > > 
> > > > > > The DC5 increment could've happened while DC6 was disabled
> > > > > > by
> > > > > > the driver.
> > > > > 
> > > > > Yes, it could... in general the dc6 bit would be zero, but
> > > > > right,
> > > > > there's
> > > > > a possible race.
> > > > > 
> > > > > But should we complicate things when we know that on the test
> > > > > case itself
> > > > > we are in full control of the modeset?! From the test
> > > > > perspective
> > > > > I believe
> > > > > this would be more than enough without complicating things.
> > > > 
> > > > Imo having a counter which works based on the condition that
> > > > guarantees the
> > > > display to allow DC6, would help later in debugging.
> > 
> > yeap, it makes sense
> > 
> > > > 
> > > > > But well, if you really believe that we need to go further in
> > > > > the
> > > > > driver
> > > > > to cover that it is fine by me.
> > > > > 
> > > > > But just to ensure that we are in the same page, could you
> > > > > please
> > > > > open
> > > > > up a bit more of your idea on when to increase the dc5 sw
> > > > > counters
> > > > > in a way that we would ensure that we don't have race and
> > > > > that we
> > > > > get the dc6 allowed counter correctly?
> > > > 
> > > > Something like the following:
> > > > 
> > > > 1. Right after the driver sets DC6_EN, it stores the DC5 HW
> > > > counter's
> > > >   current value:
> > > >   dc5_start = dc5_current
> > > > 2. Right before the driver clears DC6_EN, it updates the DC6
> > > > allowed
> > > >   counter:
> > > >   dc6_allowed += dc5_current - dc5_start
> > > >   dc5_start = dc5_current
> > > > 3. When userspace reads the counters via debugfs the driver
> > > > first
> > > >   updates dc6_allowed the same way as 2. did if DC6_EN is set.
> > > 
> > > This sounds good to me.
> > 
> > I like that as well.
> > 
> > > 
> > > I'd like to add that we should ensure that DC6 is really being
> > > allowed,
> > > so that might need to be handled inside gen9_set_dc_state(),
> > > where
> > > allowed_dc_mask is applied.
> > 
> > well, for that we can also have the 
> > 
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -1294,6 +1294,10 @@ static int
> > intel_dmc_debugfs_status_show(struct
> > seq_file *m, void *unused)
> >                seq_printf(m, "DC5 -> DC6 count: %d\n",
> >                           intel_de_read(display, dc6_reg));
> > 
> > +       seq_printf(m, "DC6 allowed: %s\n",
> > str_yes_no((intel_de_read(display,
> > +                                                                  
> > DC_STATE_EN)
> > +                                                     & 0x3) ==
> > 2));
> > 
> > on top of what Imre suggested right?
> > so the dc6 count is updated and also we have the live view of the
> > register set
> 
> Hm... Not sure if that would be required to validate that the display
> engine was ready for DC6. I guess the dc6_allowed counter would be
> enough.
> 
> > 
> > no?
> > 
> > not sure why we need to go to the dc9 func...
> 
> Hm... dc9? Did you mean gen9_set_dc_state()?

doh! I really need to stop trying work without glasses :)

> 
> Function sanitizes the target value for DC_STATE_EN so that we do not
> use a value that is not allowed (e.g. when the driver was loaded with
> enable_dc=0).

but this function is the only one that really writes the right values
to the registers, so if we need something here, why not just reading
the register directly?

so perhaps I really missed your point on why we would need this...

> 
> --
> Gustavo Sousa
> 
> > 
> > > 
> > > --
> > > Gustavo Sousa
> > > 
> > > > 
> > > > > Btw, while doing this experiment I noticed that the debugfs
> > > > > and
> > > > > test
> > > > > also doesn't call that residency anyway and it is just count.
> > > > > So
> > > > > perhaps with your idea we don't need to change the debugfs
> > > > > interface.
> > 

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Gustavo Sousa]

Quoting Vivi, Rodrigo (2025-02-03 17:59:19-03:00)
>On Mon, 2025-02-03 at 17:40 -0300, Gustavo Sousa wrote:
>> Quoting Vivi, Rodrigo (2025-02-03 17:23:53-03:00)
>> > On Mon, 2025-02-03 at 17:19 -0300, Gustavo Sousa wrote:
>> > > Quoting Imre Deak (2025-02-03 16:22:44-03:00)
>> > > > On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
>> > > > > > > > [...]
>> > > > > > > > 
>> > > > > > > > The driver enabling DC6 is not an enough condition for
>> > > > > > > > DC6
>> > > > > > > > being allowed
>> > > > > > > > from the display side. Some display clock gating etc.
>> > > > > > > > configuration by
>> > > > > > > > the driver could be blocking it. According to the HW
>> > > > > > > > team,
>> > > > > > > > DC5 being
>> > > > > > > > entered while DC6 is enabled is a guarantee that DC6 is
>> > > > > > > > allowed from the
>> > > > > > > > display side - i.e. the driver has configured
>> > > > > > > > everything
>> > > > > > > > correctly for
>> > > > > > > > that.
>> > > > > > > 
>> > > > > > > Fair enough. So IGT test case would check directly if DC5
>> > > > > > > counter is
>> > > > > > > increasing and DC6 is allowed.
>> > > > > > > 
>> > > > > > > Something as simple as this in the kernel code would tell
>> > > > > > > that
>> > > > > > > DC6 is enabled:
>> > > > > > > 
>> > > > > > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> > > > > > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> > > > > > > @@ -1294,6 +1294,10 @@ static int
>> > > > > > > intel_dmc_debugfs_status_show(struct seq_file *m, void
>> > > > > > > *unused)
>> > > > > > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
>> > > > > > >                            intel_de_read(display,
>> > > > > > > dc6_reg));
>> > > > > > >  
>> > > > > > > +       seq_printf(m, "DC6 allowed: %s\n",
>> > > > > > > str_yes_no((intel_de_read(display,
>> > > > > > > +                                                        
>> > > > > > >     
>> > > > > > >        DC_STATE_EN)
>> > > > > > > +                                                     &
>> > > > > > > 0x3)
>> > > > > > > == 2));
>> > > > > > > +
>> > > > > > > 
>> > > > > > > and
>> > > > > > > 
>> > > > > > > $ cat i915_dmc_info
>> > > > > > > [snip]
>> > > > > > > DC3 -> DC5 count: 286
>> > > > > > > DC5 -> DC6 count: 0
>> > > > > > > DC6 allowed: yes
>> > > > > > > [snip]
>> > > > > > > 
>> > > > > > > $ cat i915_dmc_info
>> > > > > > > [snip]
>> > > > > > > DC3 -> DC5 count: 292
>> > > > > > > DC5 -> DC6 count: 0
>> > > > > > > DC6 allowed: yes
>> > > > > > > [snip]
>> > > > > > > 
>> > > > > > > Thoughts?
>> > > > > > 
>> > > > > > The DC5 increment could've happened while DC6 was disabled
>> > > > > > by
>> > > > > > the driver.
>> > > > > 
>> > > > > Yes, it could... in general the dc6 bit would be zero, but
>> > > > > right,
>> > > > > there's
>> > > > > a possible race.
>> > > > > 
>> > > > > But should we complicate things when we know that on the test
>> > > > > case itself
>> > > > > we are in full control of the modeset?! From the test
>> > > > > perspective
>> > > > > I believe
>> > > > > this would be more than enough without complicating things.
>> > > > 
>> > > > Imo having a counter which works based on the condition that
>> > > > guarantees the
>> > > > display to allow DC6, would help later in debugging.
>> > 
>> > yeap, it makes sense
>> > 
>> > > > 
>> > > > > But well, if you really believe that we need to go further in
>> > > > > the
>> > > > > driver
>> > > > > to cover that it is fine by me.
>> > > > > 
>> > > > > But just to ensure that we are in the same page, could you
>> > > > > please
>> > > > > open
>> > > > > up a bit more of your idea on when to increase the dc5 sw
>> > > > > counters
>> > > > > in a way that we would ensure that we don't have race and
>> > > > > that we
>> > > > > get the dc6 allowed counter correctly?
>> > > > 
>> > > > Something like the following:
>> > > > 
>> > > > 1. Right after the driver sets DC6_EN, it stores the DC5 HW
>> > > > counter's
>> > > >   current value:
>> > > >   dc5_start = dc5_current
>> > > > 2. Right before the driver clears DC6_EN, it updates the DC6
>> > > > allowed
>> > > >   counter:
>> > > >   dc6_allowed += dc5_current - dc5_start
>> > > >   dc5_start = dc5_current
>> > > > 3. When userspace reads the counters via debugfs the driver
>> > > > first
>> > > >   updates dc6_allowed the same way as 2. did if DC6_EN is set.
>> > > 
>> > > This sounds good to me.
>> > 
>> > I like that as well.
>> > 
>> > > 
>> > > I'd like to add that we should ensure that DC6 is really being
>> > > allowed,
>> > > so that might need to be handled inside gen9_set_dc_state(),
>> > > where
>> > > allowed_dc_mask is applied.
>> > 
>> > well, for that we can also have the 
>> > 
>> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> > @@ -1294,6 +1294,10 @@ static int
>> > intel_dmc_debugfs_status_show(struct
>> > seq_file *m, void *unused)
>> >                seq_printf(m, "DC5 -> DC6 count: %d\n",
>> >                           intel_de_read(display, dc6_reg));
>> > 
>> > +       seq_printf(m, "DC6 allowed: %s\n",
>> > str_yes_no((intel_de_read(display,
>> > +                                                                  
>> > DC_STATE_EN)
>> > +                                                     & 0x3) ==
>> > 2));
>> > 
>> > on top of what Imre suggested right?
>> > so the dc6 count is updated and also we have the live view of the
>> > register set
>> 
>> Hm... Not sure if that would be required to validate that the display
>> engine was ready for DC6. I guess the dc6_allowed counter would be
>> enough.
>> 
>> > 
>> > no?
>> > 
>> > not sure why we need to go to the dc9 func...
>> 
>> Hm... dc9? Did you mean gen9_set_dc_state()?
>
>doh! I really need to stop trying work without glasses :)
>
>> 
>> Function sanitizes the target value for DC_STATE_EN so that we do not
>> use a value that is not allowed (e.g. when the driver was loaded with
>> enable_dc=0).
>
>but this function is the only one that really writes the right values
>to the registers, so if we need something here, why not just reading
>the register directly?
>
>so perhaps I really missed your point on why we would need this...

Perhaps Imre can explain this better, but I believe the point is that we
want to track increments to DC5 counter when we have DC6 enabled. That
driver-managed counter would be in dc6_allowed.

Repeating Imre's suggestions with a minor tweak:

1. Before we tell the hardware that we are allowing DC6 (disable ->
   DC6), we store the value of the current DC5 counter.
2. After we disable DC states from DC6 (DC6 -> disable), we read the DC5
   counter again and subtract the value from (1). The result would then
   be added to the current value of dc6_allowed.

In (1) I think we should read the DC5 counter before we update
DC_STATE_EN, just to be sure we avoid some sort of race (although that
appears to be unlikely to happen).

During DC6 validation, if the test sees that dc6_allowed was
incremented, that means that the display engine reached a state where
the SOC would be able to put the display in DC6.

--
Gustavo Sousa

>
>> 
>> --
>> Gustavo Sousa
>> 
>> > 
>> > > 
>> > > --
>> > > Gustavo Sousa
>> > > 
>> > > > 
>> > > > > Btw, while doing this experiment I noticed that the debugfs
>> > > > > and
>> > > > > test
>> > > > > also doesn't call that residency anyway and it is just count.
>> > > > > So
>> > > > > perhaps with your idea we don't need to change the debugfs
>> > > > > interface.
>> > 
>

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 05:19:08PM -0300, Gustavo Sousa wrote:
> Quoting Imre Deak (2025-02-03 16:22:44-03:00)
> >On Mon, Feb 03, 2025 at 12:15:26PM -0500, Rodrigo Vivi wrote:
> >> > > > [...]
> >> > > >
> >> > > > The driver enabling DC6 is not an enough condition for DC6 being allowed
> >> > > > from the display side. Some display clock gating etc. configuration by
> >> > > > the driver could be blocking it. According to the HW team, DC5 being
> >> > > > entered while DC6 is enabled is a guarantee that DC6 is allowed from the
> >> > > > display side - i.e. the driver has configured everything correctly for
> >> > > > that.
> >> > > 
> >> > > Fair enough. So IGT test case would check directly if DC5 counter is
> >> > > increasing and DC6 is allowed.
> >> > > 
> >> > > Something as simple as this in the kernel code would tell that
> >> > > DC6 is enabled:
> >> > > 
> >> > > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> >> > > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> >> > > @@ -1294,6 +1294,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >> > >                 seq_printf(m, "DC5 -> DC6 count: %d\n",
> >> > >                            intel_de_read(display, dc6_reg));
> >> > >  
> >> > > +       seq_printf(m, "DC6 allowed: %s\n", str_yes_no((intel_de_read(display,
> >> > > +                                                                   DC_STATE_EN)
> >> > > +                                                     & 0x3) == 2));
> >> > > +
> >> > > 
> >> > > and
> >> > > 
> >> > > $ cat i915_dmc_info
> >> > > [snip]
> >> > > DC3 -> DC5 count: 286
> >> > > DC5 -> DC6 count: 0
> >> > > DC6 allowed: yes
> >> > > [snip]
> >> > > 
> >> > > $ cat i915_dmc_info
> >> > > [snip]
> >> > > DC3 -> DC5 count: 292
> >> > > DC5 -> DC6 count: 0
> >> > > DC6 allowed: yes
> >> > > [snip]
> >> > > 
> >> > > Thoughts?
> >> > 
> >> > The DC5 increment could've happened while DC6 was disabled by the driver.
> >> 
> >> Yes, it could... in general the dc6 bit would be zero, but right, there's
> >> a possible race.
> >> 
> >> But should we complicate things when we know that on the test case itself
> >> we are in full control of the modeset?! From the test perspective I believe
> >> this would be more than enough without complicating things.
> >
> >Imo having a counter which works based on the condition that guarantees the
> >display to allow DC6, would help later in debugging.
> >
> >> But well, if you really believe that we need to go further in the driver
> >> to cover that it is fine by me.
> >> 
> >> But just to ensure that we are in the same page, could you please open
> >> up a bit more of your idea on when to increase the dc5 sw counters
> >> in a way that we would ensure that we don't have race and that we
> >> get the dc6 allowed counter correctly?
> >
> >Something like the following:
> >
> >1. Right after the driver sets DC6_EN, it stores the DC5 HW counter's
> >   current value:
> >   dc5_start = dc5_current
> >2. Right before the driver clears DC6_EN, it updates the DC6 allowed
> >   counter:
> >   dc6_allowed += dc5_current - dc5_start
> >   dc5_start = dc5_current
> >3. When userspace reads the counters via debugfs the driver first
> >   updates dc6_allowed the same way as 2. did if DC6_EN is set.
> 
> This sounds good to me.
> 
> I'd like to add that we should ensure that DC6 is really being allowed,
> so that might need to be handled inside gen9_set_dc_state(), where
> allowed_dc_mask is applied.

Yes, handling 1. and 2. above in gen9_set_dc_state() looks ok to me.

> --
> Gustavo Sousa
> 
> >
> >> Btw, while doing this experiment I noticed that the debugfs and test
> >> also doesn't call that residency anyway and it is just count. So
> >> perhaps with your idea we don't need to change the debugfs interface.

Re: [PATCH] drm/i915/dmc: Add debugfs for dc6 counter

[Imre Deak]

On Mon, Feb 03, 2025 at 06:18:29PM -0300, Gustavo Sousa wrote:
> Quoting Vivi, Rodrigo (2025-02-03 17:59:19-03:00)
> [...]
> Perhaps Imre can explain this better, but I believe the point is that we
> want to track increments to DC5 counter when we have DC6 enabled. That
> driver-managed counter would be in dc6_allowed.
> 
> Repeating Imre's suggestions with a minor tweak:
> 
> 1. Before we tell the hardware that we are allowing DC6 (disable ->
>    DC6), we store the value of the current DC5 counter.
>
> 2. After we disable DC states from DC6 (DC6 -> disable), we read the DC5
>    counter again and subtract the value from (1). The result would then be
>    added to the current value of dc6_allowed.

Yes, with the actual delta being: DC5 counter read here - DC5 counter read
at (1).

> In (1) I think we should read the DC5 counter before we update
> DC_STATE_EN, just to be sure we avoid some sort of race (although that
> appears to be unlikely to happen).

Yes, the orders you described in both (1) and (2) are correct (since a
DC5 -> DC6 or DC6 -> DC5 transition is not possible).

The dc6_allowed counter should be also updated before returning it to
userspace via the debugfs entry, as I mentioned earlier (to account
for the case where DC6 is enabled when the read happens).

> During DC6 validation, if the test sees that dc6_allowed was
> incremented, that means that the display engine reached a state where
> the SOC would be able to put the display in DC6.

Yes, that's my understanding.

--Imre

[PATCH v2] drm/i915/dmc: Create debugfs entry for dc6 counter

[Mohammed Thasleem]

Starting from MTL we don't have a platform agnostic way to validate
DC6 state due to dc6 counter has been removed to validate DC state.

The goal is to validate that the display HW can reach the DC6 power
state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Driver could take a snapshot of the DC5 residency counter right
after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency_counter += dc5_current_count - dc5_start_count

v2: Update the discription. (Imre)
    Read dc5 count during dc6 enable and disable then and update
    dc6 residency counter. (Imre)
    Remove variable from dmc structure. (Jani)
    Updated the subject title.

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  2 ++
 .../i915/display/intel_display_power_well.c   | 20 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 14 ++++++++++---
 3 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 554870d2494b..0a1e3dc2804f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -490,6 +490,8 @@ struct intel_display {
 
 		/* perform PHY state sanity checks? */
 		bool chv_phy_assert[2];
+		unsigned int dc6_residency_counter;
+		unsigned int dc5_start_count;
 	} power;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index f45a4f9ba23c..cfa53ee84323 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -17,6 +17,7 @@
 #include "intel_dkl_phy.h"
 #include "intel_dkl_phy_regs.h"
 #include "intel_dmc.h"
+#include "intel_dmc_regs.h"
 #include "intel_dmc_wl.h"
 #include "intel_dp_aux_regs.h"
 #include "intel_dpio_phy.h"
@@ -755,7 +756,7 @@ void gen9_sanitize_dc_state(struct intel_display *display)
 void gen9_set_dc_state(struct intel_display *display, u32 state)
 {
 	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 val;
+	u32 val, dc5_current_count;
 	u32 mask;
 
 	if (!HAS_DISPLAY(display))
@@ -775,11 +776,28 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
 			power_domains->dc_state, val & mask);
 
+	if (DISPLAY_VER(display) >= 14) {
+		/* If disabling DC6, update dc6_allowed counter */
+		if (!(state & DC_STATE_EN_UPTO_DC6) && (val & DC_STATE_EN_UPTO_DC6)) {
+			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
+			display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;
+			display->power.dc5_start_count = dc5_current_count;
+		}
+	}
+
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(display, val);
 
+	if (DISPLAY_VER(display) >= 14) {
+		/* If enabling DC6, store DC5 count */
+		if ((state & DC_STATE_EN_UPTO_DC6)) {
+			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
+			display->power.dc5_start_count = dc5_current_count;
+		}
+	}
+
 	power_domains->dc_state = val & mask;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 221d3abda791..e4d3ce796c99 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1242,6 +1242,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	struct intel_dmc *dmc = display_to_dmc(display);
 	intel_wakeref_t wakeref;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+	u32 dc5_current_count;
 
 	if (!HAS_DMC(display))
 		return -ENODEV;
@@ -1290,9 +1291,16 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	}
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
-	if (i915_mmio_reg_valid(dc6_reg))
-		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   intel_de_read(display, dc6_reg));
+
+	if (DISPLAY_VER(display) >= 14) {
+		dc5_current_count = intel_de_read(display, dc5_reg);
+		display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;
+		seq_printf(m, "DC6 Residency Counter: %d\n", display->power.dc6_residency_counter);
+	} else {
+		if (i915_mmio_reg_valid(dc6_reg))
+			seq_printf(m, "DC5 -> DC6 count: %d\n",
+				   intel_de_read(display, dc6_reg));
+	}
 
 	seq_printf(m, "program base: 0x%08x\n",
 		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
-- 
2.43.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Add debugfs for dc6 counter (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev2)
URL   : https://patchwork.freedesktop.org/series/144240/
State : warning

== Summary ==

Error: dim checkpatch failed
980328332189 drm/i915/dmc: Create debugfs entry for dc6 counter
-:74: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#74: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:782:
+			display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;

-:117: WARNING:LONG_LINE: line length of 107 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:1294:
+		display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;

total: 0 errors, 2 warnings, 0 checks, 77 lines checked

✗ Fi.CI.SPARSE: warning for drm/i915/dmc: Add debugfs for dc6 counter (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev2)
URL   : https://patchwork.freedesktop.org/series/144240/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✓ i915.CI.BAT: success for drm/i915/dmc: Add debugfs for dc6 counter (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4962 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev2)
URL   : https://patchwork.freedesktop.org/series/144240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16117 -> Patchwork_144240v2
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/index.html

Participating hosts (44 -> 42)
------------------------------

  Missing    (2): fi-snb-2520m fi-pnv-d510 

Known issues
------------

  Here are the changes found in Patchwork_144240v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [PASS][1] -> [DMESG-WARN][2] ([i915#13494])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-mtlp-9/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-mtlp-9/igt@i915_module_load@load.html

  * igt@i915_pm_rpm@module-reload:
    - bat-rpls-4:         [PASS][3] -> [FAIL][4] ([i915#13633])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-rpls-4/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live:
    - bat-twl-1:          [PASS][5] -> [ABORT][6] ([i915#12919] / [i915#13503])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-twl-1/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-twl-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@gt_lrc:
    - bat-twl-1:          [PASS][7] -> [ABORT][8] ([i915#12919])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-twl-1/igt@i915_selftest@live@gt_lrc.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-twl-1/igt@i915_selftest@live@gt_lrc.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][9] -> [SKIP][10] ([i915#9197]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live:
    - bat-mtlp-9:         [ABORT][11] ([i915#13503]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-mtlp-9/igt@i915_selftest@live.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-mtlp-9/igt@i915_selftest@live.html

  * igt@i915_selftest@live@late_gt_pm:
    - bat-mtlp-9:         [ABORT][13] ([i915#13656]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-mtlp-9/igt@i915_selftest@live@late_gt_pm.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-mtlp-9/igt@i915_selftest@live@late_gt_pm.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [DMESG-FAIL][15] ([i915#12061]) -> [PASS][16] +1 other test pass
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-arlh-3/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live@workarounds:
    - bat-adlp-9:         [ABORT][17] ([i915#13399]) -> [INCOMPLETE][18] ([i915#9413]) +1 other test incomplete
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/bat-adlp-9/igt@i915_selftest@live@workarounds.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/bat-adlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
  [i915#13399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13399
  [i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
  [i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
  [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
  [i915#13656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13656
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197
  [i915#9413]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9413


Build changes
-------------

  * Linux: CI_DRM_16117 -> Patchwork_144240v2

  CI-20190529: 20190529
  CI_DRM_16117: 5bf5e8eecd1eaeb1f5c0c36b5047d6884b5b8668 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8228: 8228
  Patchwork_144240v2: 5bf5e8eecd1eaeb1f5c0c36b5047d6884b5b8668 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/index.html

[-- Attachment #2: Type: text/html, Size: 5915 bytes --]

✗ i915.CI.Full: failure for drm/i915/dmc: Add debugfs for dc6 counter (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 100275 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev2)
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16117_full -> Patchwork_144240v2_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v2_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v2_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (11 -> 10)
------------------------------

  Missing    (1): shard-snb-0 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v2_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_tiled_swapping@non-threaded:
    - shard-snb:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-snb5/igt@gem_tiled_swapping@non-threaded.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb5/igt@gem_tiled_swapping@non-threaded.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-dg1:          [PASS][3] -> [SKIP][4] +72 other tests skip
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-dg1:          NOTRUN -> [SKIP][5] +26 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_crc@cursor-random-256x256:
    - shard-dg1:          [PASS][6] -> [DMESG-WARN][7] +1 other test dmesg-warn
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-14/igt@kms_cursor_crc@cursor-random-256x256.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_cursor_crc@cursor-random-256x256.html

  * igt@perf_pmu@module-unload:
    - shard-dg2:          [PASS][8] -> [INCOMPLETE][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg2-10/igt@perf_pmu@module-unload.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@perf_pmu@module-unload.html

  
#### Warnings ####

  * igt@kms_big_fb@4-tiled-8bpp-rotate-0:
    - shard-dg1:          [SKIP][10] ([i915#4538] / [i915#5286]) -> [SKIP][11] +4 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-13/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-dg1:          [SKIP][12] ([i915#3638]) -> [SKIP][13] +2 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg1:          [SKIP][14] ([i915#4538]) -> [SKIP][15] +4 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs:
    - shard-dg1:          [SKIP][16] ([i915#6095]) -> [SKIP][17] +12 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg1:          [SKIP][18] ([i915#12805]) -> [SKIP][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-dg1:          [SKIP][20] ([i915#12313]) -> [SKIP][21] +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg1:          [SKIP][22] ([i915#3299]) -> [SKIP][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-13/igt@kms_content_protection@dp-mst-lic-type-0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@srm:
    - shard-dg1:          [SKIP][24] ([i915#7116]) -> [SKIP][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_content_protection@srm.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-dg1:          [SKIP][26] ([i915#3555]) -> [SKIP][27] +5 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_cursor_crc@cursor-random-32x32.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-sliding-512x512:
    - shard-dg1:          [SKIP][28] ([i915#13049]) -> [SKIP][29] +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_cursor_crc@cursor-sliding-512x512.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_cursor_crc@cursor-sliding-512x512.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-dg1:          [SKIP][30] ([i915#4103] / [i915#4213]) -> [SKIP][31]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-dg1:          [SKIP][32] ([i915#3840]) -> [SKIP][33]
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-bpc:
    - shard-dg1:          [SKIP][34] ([i915#3555] / [i915#3840]) -> [SKIP][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_dsc@dsc-with-bpc.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_dsc@dsc-with-bpc.html

  * igt@kms_hdr@bpc-switch:
    - shard-dg1:          [SKIP][36] ([i915#3555] / [i915#8228]) -> [SKIP][37] +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_hdr@bpc-switch.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_hdr@bpc-switch.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-dg1:          [SKIP][38] ([i915#4884]) -> [SKIP][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_rotation_crc@exhaust-fences.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-dg1:          [SKIP][40] ([i915#5289]) -> [SKIP][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-dg1:          [SKIP][42] ([i915#8623]) -> [SKIP][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@lobf:
    - shard-dg1:          [SKIP][44] ([i915#11920]) -> [SKIP][45]
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_vrr@lobf.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_vrr@lobf.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-dg1:          [SKIP][46] ([i915#9906]) -> [SKIP][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_vrr@seamless-rr-switch-virtual.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_vrr@seamless-rr-switch-virtual.html

  
New tests
---------

  New tests have been introduced between CI_DRM_16117_full and Patchwork_144240v2_full:

### New IGT tests (1) ###

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-dp-3:
    - Statuses : 1 pass(s)
    - Exec time: [4.09] s

  

Known issues
------------

  Here are the changes found in Patchwork_144240v2_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@object-reloc-keep-cache:
    - shard-mtlp:         NOTRUN -> [SKIP][48] ([i915#8411])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@api_intel_bb@object-reloc-keep-cache.html

  * igt@drm_fdinfo@most-busy-idle-check-all@bcs0:
    - shard-dg1:          NOTRUN -> [SKIP][49] ([i915#8414]) +6 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@drm_fdinfo@most-busy-idle-check-all@bcs0.html

  * igt@drm_fdinfo@virtual-busy-hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][50] ([i915#8414])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@drm_fdinfo@virtual-busy-hang.html

  * igt@fbdev@unaligned-write:
    - shard-dg1:          [PASS][51] -> [SKIP][52] ([i915#2582])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@fbdev@unaligned-write.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@fbdev@unaligned-write.html

  * igt@gem_basic@multigpu-create-close:
    - shard-dg2-9:        NOTRUN -> [SKIP][53] ([i915#7697])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          NOTRUN -> [SKIP][54] ([i915#3555] / [i915#9323])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-tglu-1:       NOTRUN -> [SKIP][55] ([i915#3555] / [i915#9323])
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-mtlp:         NOTRUN -> [SKIP][56] ([i915#9323])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
    - shard-tglu:         NOTRUN -> [SKIP][57] ([i915#9323])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-dg1:          NOTRUN -> [SKIP][58] ([i915#7697])
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-mtlp:         NOTRUN -> [SKIP][59] ([i915#7697])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#6335])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_create@create-ext-set-pat:
    - shard-tglu-1:       NOTRUN -> [SKIP][61] ([i915#8562])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_persistence@engines-hostile-preempt:
    - shard-snb:          NOTRUN -> [SKIP][62] ([i915#1099]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb6/igt@gem_ctx_persistence@engines-hostile-preempt.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2-9:        NOTRUN -> [SKIP][63] ([i915#8555])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_ctx_persistence@heartbeat-stop:
    - shard-dg1:          NOTRUN -> [SKIP][64] ([i915#8555])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_ctx_persistence@heartbeat-stop.html

  * igt@gem_ctx_persistence@saturated-hostile-nopreempt:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#5882]) +7 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_ctx_persistence@saturated-hostile-nopreempt.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-tglu:         NOTRUN -> [SKIP][66] ([i915#280])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@gem_ctx_sseu@invalid-args.html
    - shard-mtlp:         NOTRUN -> [SKIP][67] ([i915#280])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-tglu-1:       NOTRUN -> [SKIP][68] ([i915#280])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@hibernate:
    - shard-dg2:          NOTRUN -> [ABORT][69] ([i915#7975])
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@gem_eio@hibernate.html

  * igt@gem_exec_balancer@bonded-dual:
    - shard-mtlp:         NOTRUN -> [SKIP][70] ([i915#4771])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@gem_exec_balancer@bonded-dual.html
    - shard-dg1:          NOTRUN -> [SKIP][71] ([i915#4771])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@gem_exec_balancer@bonded-dual.html

  * igt@gem_exec_balancer@bonded-sync:
    - shard-dg2:          NOTRUN -> [SKIP][72] ([i915#4771])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_exec_balancer@bonded-sync.html

  * igt@gem_exec_balancer@invalid-bonds:
    - shard-mtlp:         NOTRUN -> [SKIP][73] ([i915#4036])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@gem_exec_balancer@invalid-bonds.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#4525]) +1 other test skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#4525])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_fence@submit67:
    - shard-dg2-9:        NOTRUN -> [SKIP][76] ([i915#4812])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_exec_fence@submit67.html

  * igt@gem_exec_flush@basic-uc-prw-default:
    - shard-dg2:          NOTRUN -> [SKIP][77] ([i915#3539])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@gem_exec_flush@basic-uc-prw-default.html

  * igt@gem_exec_flush@basic-uc-ro-default:
    - shard-dg1:          NOTRUN -> [SKIP][78] ([i915#3539] / [i915#4852])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@gem_exec_flush@basic-uc-ro-default.html

  * igt@gem_exec_reloc@basic-cpu-noreloc:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#3281]) +2 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_exec_reloc@basic-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-cpu-read:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#3281]) +6 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@gem_exec_reloc@basic-cpu-read.html

  * igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
    - shard-mtlp:         NOTRUN -> [SKIP][81] ([i915#3281]) +7 other tests skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-read:
    - shard-dg1:          NOTRUN -> [SKIP][82] ([i915#3281]) +2 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_exec_reloc@basic-gtt-read.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-dg2-9:        NOTRUN -> [SKIP][83] ([i915#3281]) +5 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_schedule@preempt-queue-chain:
    - shard-mtlp:         NOTRUN -> [SKIP][84] ([i915#4537] / [i915#4812])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@gem_exec_schedule@preempt-queue-chain.html

  * igt@gem_exec_schedule@reorder-wide:
    - shard-dg2:          NOTRUN -> [SKIP][85] ([i915#4537] / [i915#4812]) +1 other test skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_exec_schedule@reorder-wide.html

  * igt@gem_exec_schedule@wide:
    - shard-tglu:         [PASS][86] -> [INCOMPLETE][87] ([i915#13391]) +1 other test incomplete
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-tglu-9/igt@gem_exec_schedule@wide.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-3/igt@gem_exec_schedule@wide.html

  * igt@gem_exec_suspend@basic-s0@smem:
    - shard-dg2:          [PASS][88] -> [INCOMPLETE][89] ([i915#11441] / [i915#13304]) +1 other test incomplete
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg2-10/igt@gem_exec_suspend@basic-s0@smem.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_exec_suspend@basic-s0@smem.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - shard-rkl:          NOTRUN -> [ABORT][90] ([i915#7975]) +1 other test abort
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2-9:        NOTRUN -> [SKIP][91] ([i915#4860]) +2 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_fence_thrash@bo-write-verify-none:
    - shard-dg2:          NOTRUN -> [SKIP][92] ([i915#4860])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_fence_thrash@bo-write-verify-none.html

  * igt@gem_fenced_exec_thrash@2-spare-fences:
    - shard-dg1:          NOTRUN -> [SKIP][93] ([i915#4860])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_fenced_exec_thrash@2-spare-fences.html

  * igt@gem_huc_copy@huc-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][94] ([i915#2190])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][95] ([i915#4613]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
    - shard-dg1:          NOTRUN -> [SKIP][96] ([i915#12193])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html

  * igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
    - shard-dg1:          NOTRUN -> [SKIP][97] ([i915#4565])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html

  * igt@gem_lmem_swapping@heavy-verify-random-ccs:
    - shard-tglu:         NOTRUN -> [SKIP][98] ([i915#4613]) +2 other tests skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@gem_lmem_swapping@heavy-verify-random-ccs.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-tglu-1:       NOTRUN -> [SKIP][99] ([i915#4613])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#4613])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@gem_lmem_swapping@verify.html

  * igt@gem_madvise@dontneed-before-exec:
    - shard-mtlp:         NOTRUN -> [SKIP][101] ([i915#3282]) +1 other test skip
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@gem_madvise@dontneed-before-exec.html

  * igt@gem_media_vme:
    - shard-dg2-9:        NOTRUN -> [SKIP][102] ([i915#284])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_media_vme.html
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#284])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@gem_media_vme.html

  * igt@gem_mmap@short-mmap:
    - shard-dg2-9:        NOTRUN -> [SKIP][104] ([i915#4083])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_mmap@short-mmap.html

  * igt@gem_mmap_gtt@big-copy:
    - shard-dg2:          NOTRUN -> [SKIP][105] ([i915#4077]) +2 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_mmap_gtt@big-copy.html

  * igt@gem_mmap_wc@coherency:
    - shard-mtlp:         NOTRUN -> [SKIP][106] ([i915#4083]) +5 other tests skip
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@gem_mmap_wc@coherency.html

  * igt@gem_mmap_wc@read:
    - shard-dg1:          NOTRUN -> [SKIP][107] ([i915#4083]) +1 other test skip
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_mmap_wc@read.html

  * igt@gem_partial_pwrite_pread@reads:
    - shard-dg2-9:        NOTRUN -> [SKIP][108] ([i915#3282]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_partial_pwrite_pread@reads.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-display:
    - shard-dg1:          NOTRUN -> [SKIP][109] ([i915#3282]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_partial_pwrite_pread@writes-after-reads-display.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-dg2:          NOTRUN -> [SKIP][110] ([i915#3282])
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_pxp@create-regular-buffer:
    - shard-dg2-9:        NOTRUN -> [SKIP][111] ([i915#4270])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_pxp@create-regular-buffer.html

  * igt@gem_pxp@create-regular-context-1:
    - shard-rkl:          NOTRUN -> [TIMEOUT][112] ([i915#12917] / [i915#12964]) +1 other test timeout
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@gem_pxp@create-regular-context-1.html

  * igt@gem_pxp@create-valid-protected-context:
    - shard-dg2:          NOTRUN -> [SKIP][113] ([i915#4270]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_pxp@create-valid-protected-context.html

  * igt@gem_pxp@display-protected-crc:
    - shard-rkl:          [PASS][114] -> [TIMEOUT][115] ([i915#12917] / [i915#12964])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-rkl-8/igt@gem_pxp@display-protected-crc.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-5/igt@gem_pxp@display-protected-crc.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-rkl:          NOTRUN -> [TIMEOUT][116] ([i915#12964])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-tglu:         NOTRUN -> [SKIP][117] ([i915#13398])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_pxp@protected-raw-src-copy-not-readible:
    - shard-dg1:          NOTRUN -> [SKIP][118] ([i915#4270])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@gem_pxp@protected-raw-src-copy-not-readible.html

  * igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][119] ([i915#5190] / [i915#8428]) +1 other test skip
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@gem_render_copy@mixed-tiled-to-y-tiled-ccs.html

  * igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][120] ([i915#8428]) +3 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@gem_render_copy@y-tiled-ccs-to-yf-tiled-ccs.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][121] ([i915#5190] / [i915#8428]) +3 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-yf-tiled.html

  * igt@gem_render_tiled_blits@basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][122] ([i915#4079])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_render_tiled_blits@basic.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#4079])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_set_tiling_vs_gtt:
    - shard-dg2:          NOTRUN -> [SKIP][124] ([i915#4079])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@gem_set_tiling_vs_gtt.html

  * igt@gem_softpin@evict-snoop-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#4885])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gem_softpin@evict-snoop-interruptible.html

  * igt@gem_tiled_partial_pwrite_pread@reads:
    - shard-rkl:          NOTRUN -> [SKIP][126] ([i915#3282]) +1 other test skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@gem_tiled_partial_pwrite_pread@reads.html

  * igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
    - shard-dg1:          NOTRUN -> [SKIP][127] ([i915#4077]) +6 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html

  * igt@gem_tiling_max_stride:
    - shard-mtlp:         NOTRUN -> [SKIP][128] ([i915#4077]) +7 other tests skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@gem_tiling_max_stride.html

  * igt@gem_userptr_blits@access-control:
    - shard-mtlp:         NOTRUN -> [SKIP][129] ([i915#3297]) +1 other test skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@gem_userptr_blits@access-control.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#3297]) +1 other test skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][131] ([i915#3297]) +2 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@unsync-overlap:
    - shard-tglu-1:       NOTRUN -> [SKIP][132] ([i915#3297])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gem_userptr_blits@unsync-overlap.html

  * igt@gem_userptr_blits@unsync-unmap:
    - shard-dg2-9:        NOTRUN -> [SKIP][133] ([i915#3297]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gem_userptr_blits@unsync-unmap.html

  * igt@gen3_render_mixed_blits:
    - shard-dg2-9:        NOTRUN -> [SKIP][134] +6 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gen3_render_mixed_blits.html

  * igt@gen7_exec_parse@bitmasks:
    - shard-dg2:          NOTRUN -> [SKIP][135] +6 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-5/igt@gen7_exec_parse@bitmasks.html
    - shard-dg1:          NOTRUN -> [SKIP][136] +8 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@gen7_exec_parse@bitmasks.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-dg2-9:        NOTRUN -> [SKIP][137] ([i915#2856]) +1 other test skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@basic-rejected:
    - shard-tglu:         NOTRUN -> [SKIP][138] ([i915#2527] / [i915#2856]) +2 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@gen9_exec_parse@basic-rejected.html

  * igt@gen9_exec_parse@bb-chained:
    - shard-tglu-1:       NOTRUN -> [SKIP][139] ([i915#2527] / [i915#2856])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@gen9_exec_parse@bb-chained.html

  * igt@gen9_exec_parse@bb-oversize:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#2527]) +2 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@gen9_exec_parse@bb-oversize.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-dg2:          NOTRUN -> [SKIP][141] ([i915#2856])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@gen9_exec_parse@bb-start-far.html

  * igt@gen9_exec_parse@cmd-crossing-page:
    - shard-dg1:          NOTRUN -> [SKIP][142] ([i915#2527])
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@gen9_exec_parse@cmd-crossing-page.html

  * igt@gen9_exec_parse@unaligned-jump:
    - shard-mtlp:         NOTRUN -> [SKIP][143] ([i915#2856]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@gen9_exec_parse@unaligned-jump.html

  * igt@i915_module_load@resize-bar:
    - shard-dg1:          NOTRUN -> [SKIP][144] ([i915#7178])
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@i915_module_load@resize-bar.html

  * igt@i915_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][145] ([i915#7091])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@i915_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][146] ([i915#8399])
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-dg2:          [PASS][147] -> [FAIL][148] ([i915#12942]) +1 other test fail
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg2-10/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-7/igt@i915_pm_rc6_residency@rc6-accuracy.html
    - shard-rkl:          NOTRUN -> [FAIL][149] ([i915#12942]) +1 other test fail
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_pm_rps@thresholds-idle-park:
    - shard-mtlp:         NOTRUN -> [SKIP][150] ([i915#11681])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@i915_pm_rps@thresholds-idle-park.html

  * igt@i915_query@hwconfig_table:
    - shard-rkl:          NOTRUN -> [SKIP][151] ([i915#6245])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@i915_query@hwconfig_table.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#5723])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_selftest@mock@memory_region:
    - shard-tglu-1:       NOTRUN -> [DMESG-WARN][153] ([i915#9311]) +1 other test dmesg-warn
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@i915_selftest@mock@memory_region.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-dg2-9:        NOTRUN -> [SKIP][154] ([i915#4077]) +3 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][155] ([i915#5190])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#12454] / [i915#12712])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-3-y-rc-ccs-cc:
    - shard-dg1:          NOTRUN -> [SKIP][157] ([i915#8709]) +3 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events-atomic@pipe-a-hdmi-a-3-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#8709]) +4 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
    - shard-tglu:         NOTRUN -> [SKIP][159] ([i915#8709]) +3 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html

  * igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][160] ([i915#8709]) +7 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-8/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html

  * igt@kms_async_flips@invalid-async-flip-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][161] ([i915#12967])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_async_flips@invalid-async-flip-atomic.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          NOTRUN -> [SKIP][162] ([i915#9531])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_atomic_transition@plane-all-modeset-transition:
    - shard-mtlp:         NOTRUN -> [SKIP][163] ([i915#1769] / [i915#3555])
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_atomic_transition@plane-all-modeset-transition.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-tglu:         [PASS][164] -> [FAIL][165] ([i915#11808]) +1 other test fail
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-tglu-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-9/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-dg1:          NOTRUN -> [SKIP][166] ([i915#4538] / [i915#5286])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-addfb:
    - shard-tglu-1:       NOTRUN -> [SKIP][167] ([i915#5286]) +2 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_big_fb@4-tiled-addfb.html

  * igt@kms_big_fb@4-tiled-addfb-size-overflow:
    - shard-dg1:          NOTRUN -> [SKIP][168] ([i915#5286])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@kms_big_fb@4-tiled-addfb-size-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          NOTRUN -> [SKIP][169] ([i915#5286]) +2 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][170] ([i915#5286]) +4 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [PASS][171] -> [DMESG-FAIL][172] ([i915#11627] / [i915#13314])
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-8bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#3638]) +1 other test skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_big_fb@linear-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-dg2-9:        NOTRUN -> [SKIP][174] ([i915#4538] / [i915#5190]) +5 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
    - shard-mtlp:         NOTRUN -> [SKIP][175] ([i915#6187])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-dg2:          NOTRUN -> [SKIP][176] ([i915#4538] / [i915#5190]) +2 other tests skip
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-mtlp:         NOTRUN -> [SKIP][177] +12 other tests skip
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][178] ([i915#10307] / [i915#10434] / [i915#6095]) +3 other tests skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-8/igt@kms_ccs@bad-pixel-format-y-tiled-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-mtlp:         NOTRUN -> [SKIP][179] ([i915#12313]) +1 other test skip
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#12313])
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][181] ([i915#10307] / [i915#6095]) +159 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-8/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][182] ([i915#6095]) +64 other tests skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_ccs@crc-primary-basic-yf-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][183] ([i915#12805])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#12805])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][185] ([i915#6095]) +15 other tests skip
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-2/igt@kms_ccs@crc-primary-suspend-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][186] ([i915#6095]) +39 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
    - shard-dg2-9:        NOTRUN -> [SKIP][187] ([i915#12313])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][188] ([i915#12313]) +1 other test skip
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#6095]) +74 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-7/igt@kms_ccs@missing-ccs-buffer-y-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][190] ([i915#6095]) +49 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][191] ([i915#6095]) +70 other tests skip
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][192] ([i915#12313])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-9:        NOTRUN -> [SKIP][193] ([i915#10307] / [i915#6095]) +24 other tests skip
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-dg2-9:        NOTRUN -> [SKIP][194] ([i915#11616] / [i915#7213])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_cdclk@mode-transition-all-outputs.html
    - shard-rkl:          NOTRUN -> [SKIP][195] ([i915#3742])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][196] ([i915#11616] / [i915#7213]) +3 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-b-dp-3.html

  * igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][197] ([i915#4087]) +3 other tests skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-8/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_audio@dp-audio:
    - shard-mtlp:         NOTRUN -> [SKIP][198] ([i915#11151] / [i915#7828]) +4 other tests skip
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_chamelium_audio@dp-audio.html

  * igt@kms_chamelium_audio@dp-audio-edid:
    - shard-dg2:          NOTRUN -> [SKIP][199] ([i915#11151] / [i915#7828]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@kms_chamelium_audio@dp-audio-edid.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
    - shard-dg1:          NOTRUN -> [SKIP][200] ([i915#11151] / [i915#7828]) +3 other tests skip
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html

  * igt@kms_chamelium_frames@hdmi-crc-multiple:
    - shard-rkl:          NOTRUN -> [SKIP][201] ([i915#11151] / [i915#7828]) +3 other tests skip
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-multiple.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-tglu-1:       NOTRUN -> [SKIP][202] ([i915#11151] / [i915#7828]) +6 other tests skip
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_chamelium_hpd@vga-hpd-after-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][203] ([i915#11151] / [i915#7828]) +4 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@kms_chamelium_hpd@vga-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@vga-hpd-without-ddc:
    - shard-dg2-9:        NOTRUN -> [SKIP][204] ([i915#11151] / [i915#7828]) +2 other tests skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_chamelium_hpd@vga-hpd-without-ddc.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2-9:        NOTRUN -> [SKIP][205] ([i915#7118] / [i915#9424])
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][206] ([i915#3116] / [i915#3299])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-lic-type-1:
    - shard-rkl:          NOTRUN -> [SKIP][207] ([i915#3116])
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_content_protection@dp-mst-lic-type-1.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][208] ([i915#3116] / [i915#3299])
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@legacy@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][209] ([i915#7173])
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-11/igt@kms_content_protection@legacy@pipe-a-dp-3.html

  * igt@kms_content_protection@mei-interface:
    - shard-dg2-9:        NOTRUN -> [SKIP][210] ([i915#9424])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_content_protection@mei-interface.html
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#9424])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-mtlp:         NOTRUN -> [SKIP][212] ([i915#6944])
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_content_protection@srm.html

  * igt@kms_content_protection@type1:
    - shard-tglu-1:       NOTRUN -> [SKIP][213] ([i915#6944] / [i915#7116] / [i915#7118] / [i915#9424])
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_content_protection@type1.html

  * igt@kms_content_protection@uevent:
    - shard-mtlp:         NOTRUN -> [SKIP][214] ([i915#6944] / [i915#9424]) +1 other test skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_content_protection@uevent.html
    - shard-dg1:          NOTRUN -> [SKIP][215] ([i915#4423] / [i915#7116] / [i915#9424])
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@cursor-onscreen-512x170:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#13049]) +1 other test skip
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_cursor_crc@cursor-onscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-tglu:         NOTRUN -> [SKIP][217] ([i915#3555]) +4 other tests skip
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-random-32x32:
    - shard-tglu-1:       NOTRUN -> [SKIP][218] ([i915#3555]) +6 other tests skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_cursor_crc@cursor-random-32x32.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2-9:        NOTRUN -> [SKIP][219] ([i915#13049])
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_cursor_crc@cursor-random-512x512.html
    - shard-rkl:          NOTRUN -> [SKIP][220] ([i915#13049])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-rapid-movement-max-size:
    - shard-dg2-9:        NOTRUN -> [SKIP][221] ([i915#3555]) +2 other tests skip
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html
    - shard-rkl:          NOTRUN -> [SKIP][222] ([i915#3555]) +5 other tests skip
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_cursor_crc@cursor-rapid-movement-max-size.html

  * igt@kms_cursor_crc@cursor-sliding-256x85:
    - shard-mtlp:         NOTRUN -> [SKIP][223] ([i915#8814])
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_cursor_crc@cursor-sliding-256x85.html

  * igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-4:
    - shard-dg1:          [PASS][224] -> [DMESG-WARN][225] ([i915#4423]) +1 other test dmesg-warn
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-14/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-4.html
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_cursor_crc@cursor-suspend@pipe-d-hdmi-a-4.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][226] ([i915#9809]) +1 other test skip
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-mtlp:         NOTRUN -> [SKIP][227] ([i915#4213])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][228] +14 other tests skip
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
    - shard-dg2-9:        NOTRUN -> [SKIP][229] ([i915#13046] / [i915#5354]) +1 other test skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size:
    - shard-dg2:          NOTRUN -> [SKIP][230] ([i915#13046] / [i915#5354]) +1 other test skip
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-5/igt@kms_cursor_legacy@cursorb-vs-flipa-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-dg1:          NOTRUN -> [DMESG-WARN][231] ([i915#4423])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot:
    - shard-rkl:          NOTRUN -> [SKIP][232] ([i915#9067])
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_cursor_legacy@modeset-atomic-cursor-hotspot.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
    - shard-tglu-1:       NOTRUN -> [SKIP][233] ([i915#4103])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-dg2-9:        NOTRUN -> [SKIP][234] ([i915#4103] / [i915#4213])
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html
    - shard-rkl:          NOTRUN -> [SKIP][235] ([i915#4103])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@psr-dirtyfb-ioctl:
    - shard-dg2-9:        NOTRUN -> [SKIP][236] ([i915#9833])
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-tglu:         NOTRUN -> [SKIP][237] ([i915#1769] / [i915#3555] / [i915#3804])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][238] ([i915#3804])
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
    - shard-tglu:         NOTRUN -> [SKIP][239] ([i915#3804])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_dp_aux_dev:
    - shard-dg2:          [PASS][240] -> [SKIP][241] ([i915#1257])
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg2-10/igt@kms_dp_aux_dev.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@kms_dp_aux_dev.html

  * igt@kms_dsc@dsc-basic:
    - shard-dg2-9:        NOTRUN -> [SKIP][242] ([i915#3555] / [i915#3840])
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_dsc@dsc-basic.html
    - shard-rkl:          NOTRUN -> [SKIP][243] ([i915#3555] / [i915#3840])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-mtlp:         NOTRUN -> [SKIP][244] ([i915#3840])
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-tglu:         NOTRUN -> [SKIP][245] ([i915#3555] / [i915#3840])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][246] ([i915#3555] / [i915#3840])
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][247] ([i915#3840] / [i915#9053])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][248] ([i915#3469])
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@chamelium:
    - shard-tglu-1:       NOTRUN -> [SKIP][249] ([i915#2065] / [i915#4854])
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2-9:        NOTRUN -> [SKIP][250] ([i915#1839])
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_feature_discovery@display-3x.html
    - shard-rkl:          NOTRUN -> [SKIP][251] ([i915#1839]) +1 other test skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-mtlp:         NOTRUN -> [SKIP][252] ([i915#9337])
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-dg2:          NOTRUN -> [SKIP][253] ([i915#658])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-dpms-vs-vblank-race:
    - shard-mtlp:         NOTRUN -> [SKIP][254] ([i915#3637]) +4 other tests skip
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_flip@2x-dpms-vs-vblank-race.html

  * igt@kms_flip@2x-flip-vs-fences:
    - shard-dg2-9:        NOTRUN -> [SKIP][255] ([i915#8381])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_flip@2x-flip-vs-fences.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-dg2-9:        NOTRUN -> [SKIP][256] ([i915#9934]) +1 other test skip
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@2x-plain-flip:
    - shard-dg1:          NOTRUN -> [SKIP][257] ([i915#9934]) +4 other tests skip
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-tglu:         NOTRUN -> [SKIP][258] ([i915#3637]) +2 other tests skip
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@2x-plain-flip-ts-check-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][259] ([i915#3637]) +5 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html

  * igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible:
    - shard-dg2:          NOTRUN -> [SKIP][260] ([i915#9934]) +1 other test skip
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_flip@2x-single-buffer-flip-vs-dpms-off-vs-modeset-interruptible.html

  * igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
    - shard-rkl:          NOTRUN -> [SKIP][261] ([i915#9934]) +3 other tests skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
    - shard-snb:          [PASS][262] -> [FAIL][263] ([i915#11989]) +3 other tests fail
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-snb5/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb2/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-rkl:          [PASS][264] -> [FAIL][265] ([i915#11989])
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-rkl-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1:
    - shard-rkl:          NOTRUN -> [FAIL][266] ([i915#11989])
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible@a-hdmi-a1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a2:
    - shard-rkl:          [PASS][267] -> [DMESG-WARN][268] ([i915#12964]) +3 other tests dmesg-warn
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-rkl-8/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a2.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-5/igt@kms_flip@flip-vs-absolute-wf_vblank@b-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-snb:          [PASS][269] -> [INCOMPLETE][270] ([i915#12745] / [i915#4839])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-snb4/igt@kms_flip@flip-vs-suspend.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-snb:          [PASS][271] -> [INCOMPLETE][272] ([i915#4839])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-snb4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][273] ([i915#2672] / [i915#3555])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
    - shard-tglu:         NOTRUN -> [SKIP][274] ([i915#2587] / [i915#2672]) +2 other tests skip
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][275] ([i915#2672] / [i915#3555]) +2 other tests skip
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
    - shard-tglu-1:       NOTRUN -> [SKIP][276] ([i915#2587] / [i915#2672]) +2 other tests skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg2-9:        NOTRUN -> [SKIP][277] ([i915#2672]) +1 other test skip
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
    - shard-mtlp:         NOTRUN -> [SKIP][278] ([i915#2672] / [i915#8813]) +2 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
    - shard-tglu:         NOTRUN -> [SKIP][279] ([i915#2587] / [i915#2672] / [i915#3555]) +1 other test skip
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][280] ([i915#2672] / [i915#3555]) +3 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode:
    - shard-rkl:          NOTRUN -> [SKIP][281] ([i915#2672]) +3 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling:
    - shard-dg1:          NOTRUN -> [SKIP][282] ([i915#3555]) +1 other test skip
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-linear-to-16bpp-linear-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling:
    - shard-dg1:          [PASS][283] -> [SKIP][284] ([i915#3555]) +4 other tests skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-16bpp-xtile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg2-9:        NOTRUN -> [SKIP][285] ([i915#2672] / [i915#3555]) +1 other test skip
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode:
    - shard-dg1:          NOTRUN -> [SKIP][286] ([i915#2587] / [i915#2672]) +6 other tests skip
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-17/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-upscaling@pipe-a-valid-mode.html

  * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling:
    - shard-mtlp:         NOTRUN -> [SKIP][287] ([i915#2672] / [i915#3555] / [i915#8813]) +4 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-dg2-9:        NOTRUN -> [FAIL][288] ([i915#6880])
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][289] ([i915#8708]) +11 other tests skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-dg1:          [PASS][290] -> [SKIP][291] ([i915#4342]) +4 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt:
    - shard-dg2-9:        NOTRUN -> [SKIP][292] ([i915#8708]) +7 other tests skip
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][293] ([i915#3023]) +14 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          NOTRUN -> [SKIP][294] ([i915#8708]) +2 other tests skip
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
    - shard-dg1:          NOTRUN -> [SKIP][295] ([i915#4342]) +15 other tests skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][296] ([i915#1825]) +23 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen:
    - shard-dg2:          NOTRUN -> [SKIP][297] ([i915#5354]) +9 other tests skip
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-dg2-9:        NOTRUN -> [SKIP][298] ([i915#5354]) +15 other tests skip
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt:
    - shard-dg1:          NOTRUN -> [SKIP][299] ([i915#4423] / [i915#8708])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][300] ([i915#1825]) +24 other tests skip
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite:
    - shard-dg1:          NOTRUN -> [SKIP][301] ([i915#3458])
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-tiling-4:
    - shard-tglu:         NOTRUN -> [SKIP][302] ([i915#5439])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_frontbuffer_tracking@fbcpsr-tiling-4.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu:
    - shard-tglu:         NOTRUN -> [SKIP][303] +57 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
    - shard-dg2-9:        NOTRUN -> [SKIP][304] ([i915#3458]) +8 other tests skip
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][305] ([i915#8708]) +7 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-dg2:          NOTRUN -> [SKIP][306] ([i915#3458]) +3 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
    - shard-tglu-1:       NOTRUN -> [SKIP][307] +61 other tests skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu.html

  * igt@kms_hdr@bpc-switch:
    - shard-dg2:          NOTRUN -> [SKIP][308] ([i915#3555] / [i915#8228])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@invalid-hdr:
    - shard-dg2-9:        NOTRUN -> [SKIP][309] ([i915#3555] / [i915#8228]) +1 other test skip
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_hdr@invalid-hdr.html
    - shard-rkl:          NOTRUN -> [SKIP][310] ([i915#3555] / [i915#8228])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@static-swap:
    - shard-tglu:         NOTRUN -> [SKIP][311] ([i915#3555] / [i915#8228])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][312] ([i915#3555] / [i915#8228]) +1 other test skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][313] ([i915#10656])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-ultra-joiner:
    - shard-dg2:          NOTRUN -> [SKIP][314] ([i915#10656]) +1 other test skip
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_joiner@basic-force-ultra-joiner.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][315] ([i915#12339])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][316] ([i915#13522])
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][317] ([i915#4816])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg2:          NOTRUN -> [SKIP][318] ([i915#6301])
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][319] ([i915#6301])
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1:
    - shard-glk:          [PASS][320] -> [INCOMPLETE][321] ([i915#12756])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-glk9/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-glk4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-1.html

  * igt@kms_plane@plane-position-covered:
    - shard-dg1:          [PASS][322] -> [SKIP][323] ([i915#8825]) +2 other tests skip
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-17/igt@kms_plane@plane-position-covered.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane@plane-position-covered.html

  * igt@kms_plane_alpha_blend@constant-alpha-max:
    - shard-dg1:          [PASS][324] -> [SKIP][325] ([i915#7294]) +1 other test skip
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_plane_alpha_blend@constant-alpha-max.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_alpha_blend@constant-alpha-max.html

  * igt@kms_plane_lowres@tiling-y:
    - shard-mtlp:         NOTRUN -> [SKIP][326] ([i915#3555] / [i915#8821])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_plane_lowres@tiling-y.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-dg2:          NOTRUN -> [SKIP][327] ([i915#8806])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@2x-scaler-multi-pipe:
    - shard-dg2:          NOTRUN -> [SKIP][328] ([i915#13046] / [i915#5354] / [i915#9423])
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_plane_scaling@2x-scaler-multi-pipe.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d:
    - shard-dg1:          NOTRUN -> [SKIP][329] ([i915#12247] / [i915#8152]) +2 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation:
    - shard-dg2-9:        NOTRUN -> [SKIP][330] ([i915#12247] / [i915#9423])
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d:
    - shard-dg2-9:        NOTRUN -> [SKIP][331] ([i915#12247]) +3 other tests skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-rotation@pipe-d.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c:
    - shard-tglu:         NOTRUN -> [SKIP][332] ([i915#12247]) +9 other tests skip
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-c.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25:
    - shard-dg2:          NOTRUN -> [SKIP][333] ([i915#12247] / [i915#6953] / [i915#9423])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][334] ([i915#12247]) +7 other tests skip
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a:
    - shard-mtlp:         NOTRUN -> [SKIP][335] ([i915#12247]) +14 other tests skip
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-a.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d:
    - shard-dg2:          NOTRUN -> [SKIP][336] ([i915#12247]) +3 other tests skip
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling:
    - shard-dg1:          [PASS][337] -> [SKIP][338] ([i915#12247] / [i915#3558] / [i915#8152])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling.html

  * igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-d:
    - shard-dg1:          [PASS][339] -> [SKIP][340] ([i915#12247] / [i915#8152]) +1 other test skip
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-18/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-d.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-d.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5:
    - shard-dg1:          [PASS][341] -> [SKIP][342] ([i915#12247] / [i915#3555] / [i915#6953] / [i915#8152])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b:
    - shard-dg1:          [PASS][343] -> [SKIP][344] ([i915#12247]) +5 other tests skip
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-13/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75:
    - shard-dg1:          NOTRUN -> [SKIP][345] ([i915#12247] / [i915#6953] / [i915#8152])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75.html

  * igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b:
    - shard-dg1:          NOTRUN -> [SKIP][346] ([i915#12247]) +5 other tests skip
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-75@pipe-b.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25:
    - shard-tglu-1:       NOTRUN -> [SKIP][347] ([i915#12247] / [i915#6953])
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c:
    - shard-tglu-1:       NOTRUN -> [SKIP][348] ([i915#12247]) +3 other tests skip
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-c.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][349] ([i915#5354])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][350] ([i915#9812])
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-tglu:         NOTRUN -> [SKIP][351] ([i915#9685])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-4/igt@kms_pm_dc@dc3co-vpb-simulation.html
    - shard-mtlp:         NOTRUN -> [SKIP][352] ([i915#9292])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_dc@dc5-dpms-negative:
    - shard-dg1:          [PASS][353] -> [SKIP][354] ([i915#13441])
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg1-12/igt@kms_pm_dc@dc5-dpms-negative.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_pm_dc@dc5-dpms-negative.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-rkl:          NOTRUN -> [SKIP][355] ([i915#9685])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-dg1:          NOTRUN -> [SKIP][356] ([i915#3828])
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-14/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [PASS][357] -> [FAIL][358] ([i915#9295])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-tglu-10/igt@kms_pm_dc@dc6-dpms.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-7/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-dg1:          NOTRUN -> [FAIL][359] ([i915#12561] / [i915#7330])
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][360] ([i915#3828])
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2-9:        NOTRUN -> [SKIP][361] ([i915#8430])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          [PASS][362] -> [SKIP][363] ([i915#9519])
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-rkl-8/igt@kms_pm_rpm@dpms-non-lpsp.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-dg1:          NOTRUN -> [SKIP][364] ([i915#4423] / [i915#9519])
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][365] ([i915#9519])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [PASS][366] -> [SKIP][367] ([i915#9519]) +1 other test skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg2-7/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-mtlp:         NOTRUN -> [SKIP][368] ([i915#6524])
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-dg2-9:        NOTRUN -> [SKIP][369] ([i915#6524] / [i915#6805])
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area:
    - shard-dg2-9:        NOTRUN -> [SKIP][370] ([i915#11520]) +3 other tests skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_psr2_sf@fbc-pr-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-dg1:          NOTRUN -> [SKIP][371] ([i915#11520]) +1 other test skip
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][372] ([i915#12316]) +5 other tests skip
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area@pipe-b-edp-1.html

  * igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area:
    - shard-snb:          NOTRUN -> [SKIP][373] ([i915#11520]) +2 other tests skip
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb6/igt@kms_psr2_sf@fbc-psr2-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][374] ([i915#9808]) +1 other test skip
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area@pipe-a-edp-1.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          NOTRUN -> [SKIP][375] ([i915#11520]) +5 other tests skip
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
    - shard-tglu:         NOTRUN -> [SKIP][376] ([i915#11520]) +5 other tests skip
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2:          NOTRUN -> [SKIP][377] ([i915#11520]) +1 other test skip
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-6/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu-1:       NOTRUN -> [SKIP][378] ([i915#11520]) +4 other tests skip
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-dg1:          NOTRUN -> [SKIP][379] ([i915#9683])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-dg1:          NOTRUN -> [SKIP][380] ([i915#1072] / [i915#9732]) +6 other tests skip
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg1-15/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@fbc-psr2-cursor-mmap-cpu:
    - shard-mtlp:         NOTRUN -> [SKIP][381] ([i915#9688]) +6 other tests skip
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_psr@fbc-psr2-cursor-mmap-cpu.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-dg2-9:        NOTRUN -> [SKIP][382] ([i915#1072] / [i915#9732]) +9 other tests skip
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@psr-cursor-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][383] ([i915#1072] / [i915#9732]) +8 other tests skip
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_psr@psr-cursor-mmap-cpu.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][384] ([i915#9732]) +16 other tests skip
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr-primary-render:
    - shard-tglu:         NOTRUN -> [SKIP][385] ([i915#9732]) +16 other tests skip
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-5/igt@kms_psr@psr-primary-render.html

  * igt@kms_psr@psr2-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][386] ([i915#1072] / [i915#9732]) +11 other tests skip
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-2/igt@kms_psr@psr2-suspend.html

  * igt@kms_rotation_crc@bad-pixel-format:
    - shard-snb:          NOTRUN -> [SKIP][387] +125 other tests skip
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-snb6/igt@kms_rotation_crc@bad-pixel-format.html

  * igt@kms_rotation_crc@exhaust-fences:
    - shard-mtlp:         NOTRUN -> [SKIP][388] ([i915#4235])
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_rotation_crc@exhaust-fences.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-mtlp:         NOTRUN -> [SKIP][389] ([i915#12755])
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
    - shard-dg2-9:        NOTRUN -> [SKIP][390] ([i915#5190])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][391] ([i915#5289])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-rkl:          NOTRUN -> [SKIP][392] ([i915#5289]) +1 other test skip
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-mtlp:         NOTRUN -> [ABORT][393] ([i915#13179]) +1 other test abort
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-8/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_sequence@get-idle@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [DMESG-WARN][394] ([i915#12964]) +9 other tests dmesg-warn
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_sequence@get-idle@pipe-b-hdmi-a-2.html

  * igt@kms_setmode@invalid-clone-exclusive-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][395] ([i915#3555]) +2 other tests skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_setmode@invalid-clone-exclusive-crtc.html

  * igt@kms_sysfs_edid_timing:
    - shard-dg2:          [PASS][396] -> [FAIL][397] ([IGT#160])
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16117/shard-dg2-10/igt@kms_sysfs_edid_timing.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-3/igt@kms_sysfs_edid_timing.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-dg2-9:        NOTRUN -> [SKIP][398] ([i915#8623])
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_tiled_display@basic-test-pattern.html
    - shard-rkl:          NOTRUN -> [SKIP][399] ([i915#8623])
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-mtlp:         NOTRUN -> [SKIP][400] ([i915#8623])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@flip-basic:
    - shard-mtlp:         NOTRUN -> [SKIP][401] ([i915#3555] / [i915#8808])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-2/igt@kms_vrr@flip-basic.html

  * igt@kms_vrr@lobf:
    - shard-tglu-1:       NOTRUN -> [SKIP][402] ([i915#11920])
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_vrr@lobf.html

  * igt@kms_vrr@max-min:
    - shard-dg2:          NOTRUN -> [SKIP][403] ([i915#9906])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-5/igt@kms_vrr@max-min.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          NOTRUN -> [SKIP][404] ([i915#3555] / [i915#9906])
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-3/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-dg2-9:        NOTRUN -> [SKIP][405] ([i915#9906])
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@kms_vrr@seamless-rr-switch-virtual:
    - shard-mtlp:         NOTRUN -> [SKIP][406] ([i915#8808] / [i915#9906])
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-mtlp-6/igt@kms_vrr@seamless-rr-switch-virtual.html

  * igt@kms_writeback@writeback-check-output:
    - shard-dg2-9:        NOTRUN -> [SKIP][407] ([i915#2437])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-9/igt@kms_writeback@writeback-check-output.html
    - shard-rkl:          NOTRUN -> [SKIP][408] ([i915#2437])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-rkl-1/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-fb-id:
    - shard-tglu-1:       NOTRUN -> [SKIP][409] ([i915#2437])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-tglu-1/igt@kms_writeback@writeback-fb-id.html

  * igt@kms_writeback@writeback-invalid-parameters:
    - shard-dg2:          NOTRUN -> [SKIP][410] ([i915#2437])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/shard-dg2-10/igt@kms_writeback@writeback-invalid-parameters.html

  * igt@perf@global-sseu-config-invalid:
    - shard-mtlp:         NOTRUN -> [SKIP][411] ([i915#7387])
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwor

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v2/index.html

[-- Attachment #2: Type: text/html, Size: 110113 bytes --]

Re: [v2] drm/i915/dmc: Create debugfs entry for dc6 counter

[Almahallawy, Khaled]

On Wed, 2025-02-12 at 17:19 +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
> 
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required.
> According
> to the HW team the display driver has programmed everything correctly
> in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.

Historically speaking, when it comes to debugging DC6 issues and
involve all other teams, the communication between Punit and DE is the
sure way to prove display is innocent especially starting from MTL.
Latest in PTL HSD:14023469804

Trace of PM_REQ_DBG/PM_RSP_DBG registers normally is the first step
needed to shows the comms between Punit/DE and LTR configs. 

So, can we cook something with these register to follow the BKM of
debugging DC issues. 

Thanks
Khaled


> 
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at
> these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
> 
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> 
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>  .../i915/display/intel_display_power_well.c   | 20
> ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 14 ++++++++++---
>  3 files changed, 32 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..0a1e3dc2804f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -490,6 +490,8 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +		unsigned int dc6_residency_counter;
> +		unsigned int dc5_start_count;
>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index f45a4f9ba23c..cfa53ee84323 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -17,6 +17,7 @@
>  #include "intel_dkl_phy.h"
>  #include "intel_dkl_phy_regs.h"
>  #include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dmc_wl.h"
>  #include "intel_dp_aux_regs.h"
>  #include "intel_dpio_phy.h"
> @@ -755,7 +756,7 @@ void gen9_sanitize_dc_state(struct intel_display
> *display)
>  void gen9_set_dc_state(struct intel_display *display, u32 state)
>  {
>  	struct i915_power_domains *power_domains = &display-
> >power.domains;
> -	u32 val;
> +	u32 val, dc5_current_count;
>  	u32 mask;
>  
>  	if (!HAS_DISPLAY(display))
> @@ -775,11 +776,28 @@ void gen9_set_dc_state(struct intel_display
> *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x ->
> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	if (DISPLAY_VER(display) >= 14) {
> +		/* If disabling DC6, update dc6_allowed counter */
> +		if (!(state & DC_STATE_EN_UPTO_DC6) && (val &
> DC_STATE_EN_UPTO_DC6)) {
> +			dc5_current_count = intel_de_read(display,
> DG1_DMC_DEBUG_DC5_COUNT);
> +			display->power.dc6_residency_counter +=
> dc5_current_count - display->power.dc5_start_count;
> +			display->power.dc5_start_count =
> dc5_current_count;
> +		}
> +	}
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (DISPLAY_VER(display) >= 14) {
> +		/* If enabling DC6, store DC5 count */
> +		if ((state & DC_STATE_EN_UPTO_DC6)) {
> +			dc5_current_count = intel_de_read(display,
> DG1_DMC_DEBUG_DC5_COUNT);
> +			display->power.dc5_start_count =
> dc5_current_count;
> +		}
> +	}
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 221d3abda791..e4d3ce796c99 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1242,6 +1242,7 @@ static int intel_dmc_debugfs_status_show(struct
> seq_file *m, void *unused)
>  	struct intel_dmc *dmc = display_to_dmc(display);
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc5_current_count;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1290,9 +1291,16 @@ static int
> intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n",
> intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		dc5_current_count = intel_de_read(display, dc5_reg);
> +		display->power.dc6_residency_counter +=
> dc5_current_count - display->power.dc5_start_count;
> +		seq_printf(m, "DC6 Residency Counter: %d\n",
> display->power.dc6_residency_counter);
> +	} else {
> +		if (i915_mmio_reg_valid(dc6_reg))
> +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> +				   intel_de_read(display, dc6_reg));
> +	}
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc-
> >dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

Re: [PATCH v2] drm/i915/dmc: Create debugfs entry for dc6 counter

[Rodrigo Vivi]

On Wed, Feb 12, 2025 at 05:19:35PM +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
> 
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
> 
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
> 
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> 

Cc: Imre Deak <imre.deak@intel.com>

perhaps a Suggested-by: Imre?

> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>  .../i915/display/intel_display_power_well.c   | 20 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 14 ++++++++++---
>  3 files changed, 32 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..0a1e3dc2804f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -490,6 +490,8 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +		unsigned int dc6_residency_counter;

let's avoid the 'residency' name because it generally means time in that state.

> +		unsigned int dc5_start_count;

Also let's get some consistency counter or count, but not both.

>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index f45a4f9ba23c..cfa53ee84323 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -17,6 +17,7 @@
>  #include "intel_dkl_phy.h"
>  #include "intel_dkl_phy_regs.h"
>  #include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dmc_wl.h"
>  #include "intel_dp_aux_regs.h"
>  #include "intel_dpio_phy.h"
> @@ -755,7 +756,7 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  void gen9_set_dc_state(struct intel_display *display, u32 state)
>  {
>  	struct i915_power_domains *power_domains = &display->power.domains;
> -	u32 val;
> +	u32 val, dc5_current_count;
>  	u32 mask;
>  
>  	if (!HAS_DISPLAY(display))
> @@ -775,11 +776,28 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	if (DISPLAY_VER(display) >= 14) {
> +		/* If disabling DC6, update dc6_allowed counter */
> +		if (!(state & DC_STATE_EN_UPTO_DC6) && (val & DC_STATE_EN_UPTO_DC6)) {
> +			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +			display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;

try to keep this under 80 cols. If needed create a function to handle the
new counters.
But perhaps just reducing the size of the variable name above will help you
here and be enough.

> +			display->power.dc5_start_count = dc5_current_count;
> +		}
> +	}
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (DISPLAY_VER(display) >= 14) {
> +		/* If enabling DC6, store DC5 count */
> +		if ((state & DC_STATE_EN_UPTO_DC6)) {
> +			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +			display->power.dc5_start_count = dc5_current_count;
> +		}
> +	}
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 221d3abda791..e4d3ce796c99 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1242,6 +1242,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_dmc *dmc = display_to_dmc(display);
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc5_current_count;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1290,9 +1291,16 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		dc5_current_count = intel_de_read(display, dc5_reg);
> +		display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;
> +		seq_printf(m, "DC6 Residency Counter: %d\n", display->power.dc6_residency_counter);

 I don't believe we should break the userspace here. Let's keep the old print
for every platform, but have a variable before the print message.

Something like:
if (DISPLAY_VER(display) >= 14)
   dc6_count = //the math here
else
   dc6_count = i915_mmio_reg_valid(dc6_reg) ? intel_de_read(display, dc6_reg) : 0;

seq_printf(m, "DC5 -> DC6 count: %d\n", dc6_count);


> +	} else {
> +		if (i915_mmio_reg_valid(dc6_reg))

I know, the old expectation is that when register is not valid it shouldn't
print. But also this is why I believe that perhaps this should be extended
to every platform, and not only for MTL+...

> +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> +				   intel_de_read(display, dc6_reg));
> +	}
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> -- 
> 2.43.0
> 

Re: [v2] drm/i915/dmc: Create debugfs entry for dc6 counter

[Rodrigo Vivi]

On Wed, Feb 19, 2025 at 01:33:11AM +0000, Almahallawy, Khaled wrote:
> On Wed, 2025-02-12 at 17:19 +0530, Mohammed Thasleem wrote:
> > Starting from MTL we don't have a platform agnostic way to validate
> > DC6 state due to dc6 counter has been removed to validate DC state.
> > 
> > The goal is to validate that the display HW can reach the DC6 power
> > state. There is no HW DC6 residency counter (and there wasn't such
> > a counter earlier either), so an alternative way is required.
> > According
> > to the HW team the display driver has programmed everything correctly
> > in
> > order to allow the DC6 power state if the DC5 power state is reached
> > (indicated by the HW DC5 residency counter incrementing) and DC6 is
> > enabled by the driver.
> 
> Historically speaking, when it comes to debugging DC6 issues and
> involve all other teams, the communication between Punit and DE is the
> sure way to prove display is innocent especially starting from MTL.
> Latest in PTL HSD:14023469804
> 
> Trace of PM_REQ_DBG/PM_RSP_DBG registers normally is the first step
> needed to shows the comms between Punit/DE and LTR configs. 
> 
> So, can we cook something with these register to follow the BKM of
> debugging DC issues. 

I like this. We should probably put more thoughts and effort on
getting this analisis when we find a dc6 bug. But this is orthogonal
to this series. Having the counter is the first line of defense to
tell that we don't actually have a dc6 bug. Then if it is really a
dc6 bug, then we go to these registers.

> 
> Thanks
> Khaled
> 
> 
> > 
> > Driver could take a snapshot of the DC5 residency counter right
> > after it enables DC6 (dc5_residency_start) and increment the SW
> > DC6 residency counter right before it disables DC6 or when user space
> > reads the DC6 counter. So the driver would update the counter at
> > these
> > two points in the following way:
> > dc6_residency_counter += dc5_current_count - dc5_start_count
> > 
> > v2: Update the discription. (Imre)
> >     Read dc5 count during dc6 enable and disable then and update
> >     dc6 residency counter. (Imre)
> >     Remove variable from dmc structure. (Jani)
> >     Updated the subject title.
> > 
> > Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
> >  .../i915/display/intel_display_power_well.c   | 20
> > ++++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_dmc.c      | 14 ++++++++++---
> >  3 files changed, 32 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h
> > b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 554870d2494b..0a1e3dc2804f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -490,6 +490,8 @@ struct intel_display {
> >  
> >  		/* perform PHY state sanity checks? */
> >  		bool chv_phy_assert[2];
> > +		unsigned int dc6_residency_counter;
> > +		unsigned int dc5_start_count;
> >  	} power;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index f45a4f9ba23c..cfa53ee84323 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -17,6 +17,7 @@
> >  #include "intel_dkl_phy.h"
> >  #include "intel_dkl_phy_regs.h"
> >  #include "intel_dmc.h"
> > +#include "intel_dmc_regs.h"
> >  #include "intel_dmc_wl.h"
> >  #include "intel_dp_aux_regs.h"
> >  #include "intel_dpio_phy.h"
> > @@ -755,7 +756,7 @@ void gen9_sanitize_dc_state(struct intel_display
> > *display)
> >  void gen9_set_dc_state(struct intel_display *display, u32 state)
> >  {
> >  	struct i915_power_domains *power_domains = &display-
> > >power.domains;
> > -	u32 val;
> > +	u32 val, dc5_current_count;
> >  	u32 mask;
> >  
> >  	if (!HAS_DISPLAY(display))
> > @@ -775,11 +776,28 @@ void gen9_set_dc_state(struct intel_display
> > *display, u32 state)
> >  		drm_err(display->drm, "DC state mismatch (0x%x ->
> > 0x%x)\n",
> >  			power_domains->dc_state, val & mask);
> >  
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		/* If disabling DC6, update dc6_allowed counter */
> > +		if (!(state & DC_STATE_EN_UPTO_DC6) && (val &
> > DC_STATE_EN_UPTO_DC6)) {
> > +			dc5_current_count = intel_de_read(display,
> > DG1_DMC_DEBUG_DC5_COUNT);
> > +			display->power.dc6_residency_counter +=
> > dc5_current_count - display->power.dc5_start_count;
> > +			display->power.dc5_start_count =
> > dc5_current_count;
> > +		}
> > +	}
> > +
> >  	val &= ~mask;
> >  	val |= state;
> >  
> >  	gen9_write_dc_state(display, val);
> >  
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		/* If enabling DC6, store DC5 count */
> > +		if ((state & DC_STATE_EN_UPTO_DC6)) {
> > +			dc5_current_count = intel_de_read(display,
> > DG1_DMC_DEBUG_DC5_COUNT);
> > +			display->power.dc5_start_count =
> > dc5_current_count;
> > +		}
> > +	}
> > +
> >  	power_domains->dc_state = val & mask;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> > b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 221d3abda791..e4d3ce796c99 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -1242,6 +1242,7 @@ static int intel_dmc_debugfs_status_show(struct
> > seq_file *m, void *unused)
> >  	struct intel_dmc *dmc = display_to_dmc(display);
> >  	intel_wakeref_t wakeref;
> >  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> > +	u32 dc5_current_count;
> >  
> >  	if (!HAS_DMC(display))
> >  		return -ENODEV;
> > @@ -1290,9 +1291,16 @@ static int
> > intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >  	}
> >  
> >  	seq_printf(m, "DC3 -> DC5 count: %d\n",
> > intel_de_read(display, dc5_reg));
> > -	if (i915_mmio_reg_valid(dc6_reg))
> > -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> > -			   intel_de_read(display, dc6_reg));
> > +
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		dc5_current_count = intel_de_read(display, dc5_reg);
> > +		display->power.dc6_residency_counter +=
> > dc5_current_count - display->power.dc5_start_count;
> > +		seq_printf(m, "DC6 Residency Counter: %d\n",
> > display->power.dc6_residency_counter);
> > +	} else {
> > +		if (i915_mmio_reg_valid(dc6_reg))
> > +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> > +				   intel_de_read(display, dc6_reg));
> > +	}
> >  
> >  	seq_printf(m, "program base: 0x%08x\n",
> >  		   intel_de_read(display, DMC_PROGRAM(dmc-
> > >dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> 

Re: [PATCH v2] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Wed, Feb 12, 2025 at 05:19:35PM +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
> 
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
> 
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
> 
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> 
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>  .../i915/display/intel_display_power_well.c   | 20 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 14 ++++++++++---
>  3 files changed, 32 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..0a1e3dc2804f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -490,6 +490,8 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +		unsigned int dc6_residency_counter;
> +		unsigned int dc5_start_count;
>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index f45a4f9ba23c..cfa53ee84323 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -17,6 +17,7 @@
>  #include "intel_dkl_phy.h"
>  #include "intel_dkl_phy_regs.h"
>  #include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dmc_wl.h"
>  #include "intel_dp_aux_regs.h"
>  #include "intel_dpio_phy.h"
> @@ -755,7 +756,7 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  void gen9_set_dc_state(struct intel_display *display, u32 state)
>  {
>  	struct i915_power_domains *power_domains = &display->power.domains;
> -	u32 val;
> +	u32 val, dc5_current_count;
>  	u32 mask;
>  
>  	if (!HAS_DISPLAY(display))
> @@ -775,11 +776,28 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	if (DISPLAY_VER(display) >= 14) {
> +		/* If disabling DC6, update dc6_allowed counter */
> +		if (!(state & DC_STATE_EN_UPTO_DC6) && (val & DC_STATE_EN_UPTO_DC6)) {
> +			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +			display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;
> +			display->power.dc5_start_count = dc5_current_count;

Would be clearer if you used

enable_dc6 = state & DC_STATE_EN_UPTO_DC6
dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6

flags and moved the display version check and counter read/update to a
helper.

> +		}
> +	}
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (DISPLAY_VER(display) >= 14) {
> +		/* If enabling DC6, store DC5 count */
> +		if ((state & DC_STATE_EN_UPTO_DC6)) {
> +			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +			display->power.dc5_start_count = dc5_current_count;
> +		}
> +	}

This could also be in a helper, calling it if !dc6_was_enabled && enable_dc6.

> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 221d3abda791..e4d3ce796c99 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1242,6 +1242,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_dmc *dmc = display_to_dmc(display);
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc5_current_count;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1290,9 +1291,16 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		dc5_current_count = intel_de_read(display, dc5_reg);
> +		display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;


The above needs the i915_power_domains::lock, should be done only if DC6
is enabled, and needs to also update display->power.dc5_start_count.
This is the same update as you do in gen9_set_dc_state(), so could reuse
the helper for that here.

> +		seq_printf(m, "DC6 Residency Counter: %d\n", display->power.dc6_residency_counter);
> +	} else {
> +		if (i915_mmio_reg_valid(dc6_reg))
> +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> +				   intel_de_read(display, dc6_reg));
> +	}
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> -- 
> 2.43.0
> 

Re: [PATCH v2] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Fri, Feb 21, 2025 at 08:35:00PM +0200, Imre Deak wrote:
> On Wed, Feb 12, 2025 at 05:19:35PM +0530, Mohammed Thasleem wrote:
> > Starting from MTL we don't have a platform agnostic way to validate
> > DC6 state due to dc6 counter has been removed to validate DC state.
> > 
> > The goal is to validate that the display HW can reach the DC6 power
> > state. There is no HW DC6 residency counter (and there wasn't such
> > a counter earlier either), so an alternative way is required. According
> > to the HW team the display driver has programmed everything correctly in
> > order to allow the DC6 power state if the DC5 power state is reached
> > (indicated by the HW DC5 residency counter incrementing) and DC6 is
> > enabled by the driver.
> > 
> > Driver could take a snapshot of the DC5 residency counter right
> > after it enables DC6 (dc5_residency_start) and increment the SW
> > DC6 residency counter right before it disables DC6 or when user space
> > reads the DC6 counter. So the driver would update the counter at these
> > two points in the following way:
> > dc6_residency_counter += dc5_current_count - dc5_start_count
> > 
> > v2: Update the discription. (Imre)
> >     Read dc5 count during dc6 enable and disable then and update
> >     dc6 residency counter. (Imre)
> >     Remove variable from dmc structure. (Jani)
> >     Updated the subject title.
> > 
> > Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > ---
> >  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
> >  .../i915/display/intel_display_power_well.c   | 20 ++++++++++++++++++-
> >  drivers/gpu/drm/i915/display/intel_dmc.c      | 14 ++++++++++---
> >  3 files changed, 32 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> > index 554870d2494b..0a1e3dc2804f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> > @@ -490,6 +490,8 @@ struct intel_display {
> >  
> >  		/* perform PHY state sanity checks? */
> >  		bool chv_phy_assert[2];
> > +		unsigned int dc6_residency_counter;
> > +		unsigned int dc5_start_count;
> >  	} power;
> >  
> >  	struct {
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index f45a4f9ba23c..cfa53ee84323 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -17,6 +17,7 @@
> >  #include "intel_dkl_phy.h"
> >  #include "intel_dkl_phy_regs.h"
> >  #include "intel_dmc.h"
> > +#include "intel_dmc_regs.h"
> >  #include "intel_dmc_wl.h"
> >  #include "intel_dp_aux_regs.h"
> >  #include "intel_dpio_phy.h"
> > @@ -755,7 +756,7 @@ void gen9_sanitize_dc_state(struct intel_display *display)
> >  void gen9_set_dc_state(struct intel_display *display, u32 state)
> >  {
> >  	struct i915_power_domains *power_domains = &display->power.domains;
> > -	u32 val;
> > +	u32 val, dc5_current_count;
> >  	u32 mask;
> >  
> >  	if (!HAS_DISPLAY(display))
> > @@ -775,11 +776,28 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
> >  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
> >  			power_domains->dc_state, val & mask);
> >  
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		/* If disabling DC6, update dc6_allowed counter */
> > +		if (!(state & DC_STATE_EN_UPTO_DC6) && (val & DC_STATE_EN_UPTO_DC6)) {
> > +			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> > +			display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;
> > +			display->power.dc5_start_count = dc5_current_count;
> 
> Would be clearer if you used
> 
> enable_dc6 = state & DC_STATE_EN_UPTO_DC6
> dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6
> 
> flags and moved the display version check and counter read/update to a
> helper.

Also, the update above should happen after DC6 is disabled and the
update below should happen before DC6 is enabled.

> > +		}
> > +	}
> > +
> >  	val &= ~mask;
> >  	val |= state;
> >  
> >  	gen9_write_dc_state(display, val);
> >  
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		/* If enabling DC6, store DC5 count */
> > +		if ((state & DC_STATE_EN_UPTO_DC6)) {
> > +			dc5_current_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> > +			display->power.dc5_start_count = dc5_current_count;
> > +		}
> > +	}
> 
> This could also be in a helper, calling it if !dc6_was_enabled && enable_dc6.
> 
> > +
> >  	power_domains->dc_state = val & mask;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index 221d3abda791..e4d3ce796c99 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -1242,6 +1242,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >  	struct intel_dmc *dmc = display_to_dmc(display);
> >  	intel_wakeref_t wakeref;
> >  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> > +	u32 dc5_current_count;
> >  
> >  	if (!HAS_DMC(display))
> >  		return -ENODEV;
> > @@ -1290,9 +1291,16 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >  	}
> >  
> >  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> > -	if (i915_mmio_reg_valid(dc6_reg))
> > -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> > -			   intel_de_read(display, dc6_reg));
> > +
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		dc5_current_count = intel_de_read(display, dc5_reg);
> > +		display->power.dc6_residency_counter += dc5_current_count - display->power.dc5_start_count;
> 
> 
> The above needs the i915_power_domains::lock, should be done only if DC6
> is enabled, and needs to also update display->power.dc5_start_count.
> This is the same update as you do in gen9_set_dc_state(), so could reuse
> the helper for that here.
> 
> > +		seq_printf(m, "DC6 Residency Counter: %d\n", display->power.dc6_residency_counter);
> > +	} else {
> > +		if (i915_mmio_reg_valid(dc6_reg))
> > +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> > +				   intel_de_read(display, dc6_reg));
> > +	}
> >  
> >  	seq_printf(m, "program base: 0x%08x\n",
> >  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > -- 
> > 2.43.0
> > 

[PATCH v3] drm/i915/dmc: Create debugfs entry for dc6 counter

[Mohammed Thasleem]

Starting from MTL we don't have a platform agnostic way to validate
DC6 state due to dc6 counter has been removed to validate DC state.

The goal is to validate that the display HW can reach the DC6 power
state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Driver could take a snapshot of the DC5 residency counter right
after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency_counter += dc5_current_count - dc5_start_count

v2: Update the discription. (Imre)
    Read dc5 count during dc6 enable and disable then and update
    dc6 residency counter. (Imre)
    Remove variable from dmc structure. (Jani)
    Updated the subject title.
v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
    Use flags to check dc6 enable/disable states. (Imre)
    Move the display version check and counter read/update to
    a helper. (Imre)
    Resize the variable length. (Rodrigo)
    Use old dc6 debugfs entry for every platform. (Rodrigo)

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
---
 .../gpu/drm/i915/display/intel_display_core.h |  2 ++
 .../i915/display/intel_display_power_well.c   | 26 +++++++++++++++++++
 .../i915/display/intel_display_power_well.h   |  1 +
 drivers/gpu/drm/i915/display/intel_dmc.c      | 21 ++++++++++++---
 4 files changed, 47 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 554870d2494b..1608268bd9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -490,6 +490,8 @@ struct intel_display {
 
 		/* perform PHY state sanity checks? */
 		bool chv_phy_assert[2];
+		unsigned int dc6_count;
+		unsigned int dc5_start_count;
 	} power;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5b60db597329..8478e687abb7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -17,6 +17,7 @@
 #include "intel_dkl_phy.h"
 #include "intel_dkl_phy_regs.h"
 #include "intel_dmc.h"
+#include "intel_dmc_regs.h"
 #include "intel_dmc_wl.h"
 #include "intel_dp_aux_regs.h"
 #include "intel_dpio_phy.h"
@@ -728,6 +729,22 @@ void gen9_sanitize_dc_state(struct intel_display *display)
 	power_domains->dc_state = val;
 }
 
+void update_dc6_count(struct intel_display *display, bool dc6_en_dis)
+{
+	u32 dc5_cur_count;
+
+	if (DISPLAY_VER(display) < 14)
+		return;
+
+	dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
+
+	if (dc6_en_dis) {
+		display->power.dc6_count += dc5_cur_count - display->power.dc5_start_count;
+		display->power.dc5_start_count = dc5_cur_count;
+	} else
+		display->power.dc5_start_count = dc5_cur_count;
+}
+
 /**
  * gen9_set_dc_state - set target display C power state
  * @display: display instance
@@ -756,6 +773,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	struct i915_power_domains *power_domains = &display->power.domains;
 	u32 val;
 	u32 mask;
+	bool dc6_was_enabled, enable_dc6;
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -774,11 +792,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
 			power_domains->dc_state, val & mask);
 
+	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
+	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
+	if (!dc6_was_enabled && enable_dc6)
+		update_dc6_count(display, false);
+
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(display, val);
 
+	if (!enable_dc6)
+		update_dc6_count(display, true);
+
 	power_domains->dc_state = val & mask;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index ec8e508d0593..54fff1f888b4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -161,6 +161,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
 void gen9_disable_dc_states(struct intel_display *display);
 void bxt_enable_dc9(struct intel_display *display);
 void bxt_disable_dc9(struct intel_display *display);
+void update_dc6_count(struct intel_display *display, bool dc6_en_dis);
 
 extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
 extern const struct i915_power_well_ops chv_pipe_power_well_ops;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa6944e55d95..4cbc54a97655 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,10 +28,12 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_display_power_well.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
 
+
 /**
  * DOC: DMC Firmware Support
  *
@@ -1237,8 +1239,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	struct intel_display *display = m->private;
 	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_dmc *dmc = display_to_dmc(display);
+	struct i915_power_domains *power_domains = &display->power.domains;
 	intel_wakeref_t wakeref;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+	u32 dc6_was_enabled;
 
 	if (!HAS_DMC(display))
 		return -ENODEV;
@@ -1287,9 +1291,20 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	}
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
-	if (i915_mmio_reg_valid(dc6_reg))
-		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   intel_de_read(display, dc6_reg));
+
+	if (DISPLAY_VER(display) >= 14) {
+		dc6_was_enabled = DC_STATE_EN_UPTO_DC6 &
+				  intel_de_read(display, DC_STATE_EN);
+		if (dc6_was_enabled) {
+			mutex_lock(&power_domains->lock);
+			update_dc6_count(display, true);
+			mutex_unlock(&power_domains->lock);
+		}
+	} else
+		display->power.dc6_count = i915_mmio_reg_valid(dc6_reg) ?
+					   intel_de_read(display, dc6_reg) : 0;
+
+	seq_printf(m, "DC5 -> DC6 count: %d\n", display->power.dc6_count);
 
 	seq_printf(m, "program base: 0x%08x\n",
 		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
-- 
2.43.0

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc: Add debugfs for dc6 counter (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev3)
URL   : https://patchwork.freedesktop.org/series/144240/
State : warning

== Summary ==

Error: dim checkpatch failed
6b5ed04d5237 drm/i915/dmc: Create debugfs entry for dc6 counter
-:76: CHECK:BRACES: braces {} should be used on all arms of this statement
#76: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:741:
+	if (dc6_en_dis) {
[...]
+	} else
[...]

-:79: CHECK:BRACES: Unbalanced braces around else statement
#79: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:744:
+	} else

-:139: CHECK:LINE_SPACING: Please don't use multiple blank lines
#139: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:36:
 
+

-:170: CHECK:BRACES: Unbalanced braces around else statement
#170: FILE: drivers/gpu/drm/i915/display/intel_dmc.c:1303:
+	} else

total: 0 errors, 0 warnings, 4 checks, 115 lines checked

✗ Fi.CI.SPARSE: warning for drm/i915/dmc: Add debugfs for dc6 counter (rev3)

[Patchwork]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev3)
URL   : https://patchwork.freedesktop.org/series/144240/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.

✗ i915.CI.BAT: failure for drm/i915/dmc: Add debugfs for dc6 counter (rev3)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7199 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev3)
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16217 -> Patchwork_144240v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v3, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/index.html

Participating hosts (43 -> 42)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v3:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_chamelium_edid@dp-edid-read:
    - bat-dg2-13:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-dg2-13/igt@kms_chamelium_edid@dp-edid-read.html

  
Known issues
------------

  Here are the changes found in Patchwork_144240v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][3] ([i915#1849])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_pm_rpm@module-reload:
    - bat-dg1-7:          [PASS][8] -> [FAIL][9] ([i915#13633])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-dg1-7/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [PASS][10] -> [DMESG-FAIL][11] ([i915#12061]) +1 other test dmesg-fail
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-arls-5/igt@i915_selftest@live@workarounds.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][12] +34 other tests skip
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][13] +9 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][14] -> [SKIP][15] ([i915#9197]) +3 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [DMESG-WARN][16] ([i915#13494]) -> [PASS][17]
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-mtlp-9/igt@i915_module_load@load.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-mtlp-9/igt@i915_module_load@load.html

  * igt@i915_selftest@live:
    - bat-twl-1:          [ABORT][18] ([i915#12919] / [i915#13503]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-twl-1/igt@i915_selftest@live.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-twl-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@perf:
    - bat-twl-1:          [ABORT][20] ([i915#12919]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-twl-1/igt@i915_selftest@live@perf.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-twl-1/igt@i915_selftest@live@perf.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-twl-2:          [ABORT][22] ([i915#12919] / [i915#13503]) -> [INCOMPLETE][23] ([i915#12435] / [i915#12445] / [i915#13776])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-twl-2/igt@i915_selftest@live.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-twl-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@memory_region:
    - bat-twl-2:          [ABORT][24] ([i915#12919]) -> [INCOMPLETE][25] ([i915#12445])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16217/bat-twl-2/igt@i915_selftest@live@memory_region.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/bat-twl-2/igt@i915_selftest@live@memory_region.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
  [i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
  [i915#12919]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12919
  [i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
  [i915#13503]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13503
  [i915#13633]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13633
  [i915#13776]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13776
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16217 -> Patchwork_144240v3

  CI-20190529: 20190529
  CI_DRM_16217: c55ef90b69d314c38a69d1e4b6caf1645ed5d53f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8257: 8257
  Patchwork_144240v3: c55ef90b69d314c38a69d1e4b6caf1645ed5d53f @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v3/index.html

[-- Attachment #2: Type: text/html, Size: 8683 bytes --]

Re: [PATCH v3] drm/i915/dmc: Create debugfs entry for dc6 counter

[Jani Nikula]

On Tue, 04 Mar 2025, Mohammed Thasleem <mohammed.thasleem@intel.com> wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
>
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
>
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
>
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>     Use flags to check dc6 enable/disable states. (Imre)
>     Move the display version check and counter read/update to
>     a helper. (Imre)
>     Resize the variable length. (Rodrigo)
>     Use old dc6 debugfs entry for every platform. (Rodrigo)
>
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>  .../i915/display/intel_display_power_well.c   | 26 +++++++++++++++++++
>  .../i915/display/intel_display_power_well.h   |  1 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 21 ++++++++++++---
>  4 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..1608268bd9e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -490,6 +490,8 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +		unsigned int dc6_count;
> +		unsigned int dc5_start_count;
>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 5b60db597329..8478e687abb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -17,6 +17,7 @@
>  #include "intel_dkl_phy.h"
>  #include "intel_dkl_phy_regs.h"
>  #include "intel_dmc.h"
> +#include "intel_dmc_regs.h"

I would prefer to avoid reading DMC registers in
intel_display_power_well.c. It's intel_dmc.c that's supposed to abstract
all things DMC.

>  #include "intel_dmc_wl.h"
>  #include "intel_dp_aux_regs.h"
>  #include "intel_dpio_phy.h"
> @@ -728,6 +729,22 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  	power_domains->dc_state = val;
>  }
>  
> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis)

As a rule of thumb, functions in file intel_foo.c should be named
intel_foo_something().

What does dc6_en_dis mean? Please name it such that it's understandable.

> +{
> +	u32 dc5_cur_count;
> +
> +	if (DISPLAY_VER(display) < 14)
> +		return;
> +
> +	dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +
> +	if (dc6_en_dis) {
> +		display->power.dc6_count += dc5_cur_count - display->power.dc5_start_count;
> +		display->power.dc5_start_count = dc5_cur_count;
> +	} else
> +		display->power.dc5_start_count = dc5_cur_count;
> +}
> +
>  /**
>   * gen9_set_dc_state - set target display C power state
>   * @display: display instance
> @@ -756,6 +773,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  	struct i915_power_domains *power_domains = &display->power.domains;
>  	u32 val;
>  	u32 mask;
> +	bool dc6_was_enabled, enable_dc6;
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -774,11 +792,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> +	if (!dc6_was_enabled && enable_dc6)
> +		update_dc6_count(display, false);
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (!enable_dc6)
> +		update_dc6_count(display, true);
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index ec8e508d0593..54fff1f888b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -161,6 +161,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
>  void gen9_disable_dc_states(struct intel_display *display);
>  void bxt_enable_dc9(struct intel_display *display);
>  void bxt_disable_dc9(struct intel_display *display);
> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis);
>  
>  extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
>  extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa6944e55d95..4cbc54a97655 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,10 +28,12 @@
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_display_power_well.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
>  #include "intel_step.h"
>  
> +
>  /**
>   * DOC: DMC Firmware Support
>   *
> @@ -1237,8 +1239,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_display *display = m->private;
>  	struct drm_i915_private *i915 = to_i915(display->drm);
>  	struct intel_dmc *dmc = display_to_dmc(display);
> +	struct i915_power_domains *power_domains = &display->power.domains;
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc6_was_enabled;

This is used as a bool, the name sounds like a bool, please make it a
bool. It could also be moved to tighter scope below.

Also, what do you mean "was enabled"? Isn't it "is enabled"? Or just
"dc6_enabled"?

>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1287,9 +1291,20 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		dc6_was_enabled = DC_STATE_EN_UPTO_DC6 &
> +				  intel_de_read(display, DC_STATE_EN);
> +		if (dc6_was_enabled) {
> +			mutex_lock(&power_domains->lock);
> +			update_dc6_count(display, true);
> +			mutex_unlock(&power_domains->lock);
> +		}
> +	} else
> +		display->power.dc6_count = i915_mmio_reg_valid(dc6_reg) ?
> +					   intel_de_read(display, dc6_reg) : 0;

I think the whole division of responsibilities between
intel_display_power.c and intel_dmc.c is messed up here. You add a
function update_dc6_count() that updates the new members you added, but
then you also read DMC registers there *and* update the field here
too. Please consider who does what, and devise the interfaces such that
they respect the boundaries.

If one arm of an if requires braces, then all of them do.

> +
> +	seq_printf(m, "DC5 -> DC6 count: %d\n", display->power.dc6_count);

This now starts always printing zero for !i915_mmio_reg_valid(dc6_reg)
&& display < 14, while previously it was not printed at all.

>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

-- 
Jani Nikula, Intel

Re: [PATCH v3] drm/i915/dmc: Create debugfs entry for dc6 counter

[Jani Nikula]

On Tue, 04 Mar 2025, Mohammed Thasleem <mohammed.thasleem@intel.com> wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
>
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
>
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
>
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>     Use flags to check dc6 enable/disable states. (Imre)
>     Move the display version check and counter read/update to
>     a helper. (Imre)
>     Resize the variable length. (Rodrigo)
>     Use old dc6 debugfs entry for every platform. (Rodrigo)
>
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>  .../i915/display/intel_display_power_well.c   | 26 +++++++++++++++++++
>  .../i915/display/intel_display_power_well.h   |  1 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 21 ++++++++++++---
>  4 files changed, 47 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..1608268bd9e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -490,6 +490,8 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +		unsigned int dc6_count;
> +		unsigned int dc5_start_count;
>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 5b60db597329..8478e687abb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -17,6 +17,7 @@
>  #include "intel_dkl_phy.h"
>  #include "intel_dkl_phy_regs.h"
>  #include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dmc_wl.h"
>  #include "intel_dp_aux_regs.h"
>  #include "intel_dpio_phy.h"
> @@ -728,6 +729,22 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  	power_domains->dc_state = val;
>  }
>  
> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis)
> +{
> +	u32 dc5_cur_count;
> +
> +	if (DISPLAY_VER(display) < 14)
> +		return;
> +
> +	dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +
> +	if (dc6_en_dis) {
> +		display->power.dc6_count += dc5_cur_count - display->power.dc5_start_count;
> +		display->power.dc5_start_count = dc5_cur_count;
> +	} else
> +		display->power.dc5_start_count = dc5_cur_count;
> +}
> +
>  /**
>   * gen9_set_dc_state - set target display C power state
>   * @display: display instance
> @@ -756,6 +773,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  	struct i915_power_domains *power_domains = &display->power.domains;
>  	u32 val;
>  	u32 mask;
> +	bool dc6_was_enabled, enable_dc6;
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -774,11 +792,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> +	if (!dc6_was_enabled && enable_dc6)
> +		update_dc6_count(display, false);
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (!enable_dc6)
> +		update_dc6_count(display, true);
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index ec8e508d0593..54fff1f888b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -161,6 +161,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
>  void gen9_disable_dc_states(struct intel_display *display);
>  void bxt_enable_dc9(struct intel_display *display);
>  void bxt_disable_dc9(struct intel_display *display);
> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis);
>  
>  extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
>  extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa6944e55d95..4cbc54a97655 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,10 +28,12 @@
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_display_power_well.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
>  #include "intel_step.h"
>  
> +

Also, superfluous whitespace.

>  /**
>   * DOC: DMC Firmware Support
>   *
> @@ -1237,8 +1239,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_display *display = m->private;
>  	struct drm_i915_private *i915 = to_i915(display->drm);
>  	struct intel_dmc *dmc = display_to_dmc(display);
> +	struct i915_power_domains *power_domains = &display->power.domains;
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc6_was_enabled;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1287,9 +1291,20 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		dc6_was_enabled = DC_STATE_EN_UPTO_DC6 &
> +				  intel_de_read(display, DC_STATE_EN);
> +		if (dc6_was_enabled) {
> +			mutex_lock(&power_domains->lock);
> +			update_dc6_count(display, true);
> +			mutex_unlock(&power_domains->lock);
> +		}
> +	} else
> +		display->power.dc6_count = i915_mmio_reg_valid(dc6_reg) ?
> +					   intel_de_read(display, dc6_reg) : 0;
> +
> +	seq_printf(m, "DC5 -> DC6 count: %d\n", display->power.dc6_count);
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));

-- 
Jani Nikula, Intel

Re: [PATCH v3] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Tue, Mar 04, 2025 at 12:53:19AM +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
> 
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
> 
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
> 
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>     Use flags to check dc6 enable/disable states. (Imre)
>     Move the display version check and counter read/update to
>     a helper. (Imre)
>     Resize the variable length. (Rodrigo)
>     Use old dc6 debugfs entry for every platform. (Rodrigo)
> 
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>  .../i915/display/intel_display_power_well.c   | 26 +++++++++++++++++++
>  .../i915/display/intel_display_power_well.h   |  1 +
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 21 ++++++++++++---
>  4 files changed, 47 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 554870d2494b..1608268bd9e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -490,6 +490,8 @@ struct intel_display {
>  
>  		/* perform PHY state sanity checks? */
>  		bool chv_phy_assert[2];
> +		unsigned int dc6_count;

I think it's better to use dc6_allowed_count as Rodrigo suggested, not
regarding it as a counter for actual DC6 transitions.

> +		unsigned int dc5_start_count;
>  	} power;
>  
>  	struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 5b60db597329..8478e687abb7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -17,6 +17,7 @@
>  #include "intel_dkl_phy.h"
>  #include "intel_dkl_phy_regs.h"
>  #include "intel_dmc.h"
> +#include "intel_dmc_regs.h"
>  #include "intel_dmc_wl.h"
>  #include "intel_dp_aux_regs.h"
>  #include "intel_dpio_phy.h"
> @@ -728,6 +729,22 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  	power_domains->dc_state = val;
>  }
>  
> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis)

Maybe rename dc6_en_dis to start_tracking?

As Jani suggested the function should be in intel_dmc.c

> +{
> +	u32 dc5_cur_count;
> +
> +	if (DISPLAY_VER(display) < 14)
> +		return;
> +
> +	dc5_cur_count = intel_de_read(display, DG1_DMC_DEBUG_DC5_COUNT);
> +
> +	if (dc6_en_dis) {
> +		display->power.dc6_count += dc5_cur_count - display->power.dc5_start_count;
> +		display->power.dc5_start_count = dc5_cur_count;
> +	} else
> +		display->power.dc5_start_count = dc5_cur_count;

No need to duplicate the above in both branches.

> +}
> +
>  /**
>   * gen9_set_dc_state - set target display C power state
>   * @display: display instance
> @@ -756,6 +773,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  	struct i915_power_domains *power_domains = &display->power.domains;
>  	u32 val;
>  	u32 mask;
> +	bool dc6_was_enabled, enable_dc6;
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -774,11 +792,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> +	if (!dc6_was_enabled && enable_dc6)
> +		update_dc6_count(display, false);
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (!enable_dc6)

This also needs to check dc6_was_enabled, as it could be DC5 not DC6
being disabled for instance.

> +		update_dc6_count(display, true);
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index ec8e508d0593..54fff1f888b4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -161,6 +161,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
>  void gen9_disable_dc_states(struct intel_display *display);
>  void bxt_enable_dc9(struct intel_display *display);
>  void bxt_disable_dc9(struct intel_display *display);
> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis);
>  
>  extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
>  extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa6944e55d95..4cbc54a97655 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,10 +28,12 @@
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_display_power_well.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
>  #include "intel_step.h"
>  
> +
>  /**
>   * DOC: DMC Firmware Support
>   *
> @@ -1237,8 +1239,10 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_display *display = m->private;
>  	struct drm_i915_private *i915 = to_i915(display->drm);
>  	struct intel_dmc *dmc = display_to_dmc(display);
> +	struct i915_power_domains *power_domains = &display->power.domains;
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc6_was_enabled;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1287,9 +1291,20 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		dc6_was_enabled = DC_STATE_EN_UPTO_DC6 &
> +				  intel_de_read(display, DC_STATE_EN);

The above needs to be guarded with power_domains->lock as well,
otherwise its state could change right after you read it.

> +		if (dc6_was_enabled) {
> +			mutex_lock(&power_domains->lock);
> +			update_dc6_count(display, true);
> +			mutex_unlock(&power_domains->lock);
> +		}
> +	} else
> +		display->power.dc6_count = i915_mmio_reg_valid(dc6_reg) ?
> +					   intel_de_read(display, dc6_reg) : 0;

I think it's better to keep the existing way how 'DC5 -> DC6 count' is
printed and add a new field for the DC6 allowed count added in this
patch (keeping the two values separate).

I think it would make sense to also print the DC6 enabled state.

> +
> +	seq_printf(m, "DC5 -> DC6 count: %d\n", display->power.dc6_count);
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> -- 
> 2.43.0
> 

Re: [PATCH v3] drm/i915/dmc: Create debugfs entry for dc6 counter

[Jani Nikula]

On Tue, 04 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Tue, Mar 04, 2025 at 12:53:19AM +0530, Mohammed Thasleem wrote:
>> Starting from MTL we don't have a platform agnostic way to validate
>> DC6 state due to dc6 counter has been removed to validate DC state.
>> 
>> The goal is to validate that the display HW can reach the DC6 power
>> state. There is no HW DC6 residency counter (and there wasn't such
>> a counter earlier either), so an alternative way is required. According
>> to the HW team the display driver has programmed everything correctly in
>> order to allow the DC6 power state if the DC5 power state is reached
>> (indicated by the HW DC5 residency counter incrementing) and DC6 is
>> enabled by the driver.
>> 
>> Driver could take a snapshot of the DC5 residency counter right
>> after it enables DC6 (dc5_residency_start) and increment the SW
>> DC6 residency counter right before it disables DC6 or when user space
>> reads the DC6 counter. So the driver would update the counter at these
>> two points in the following way:
>> dc6_residency_counter += dc5_current_count - dc5_start_count
>> 
>> v2: Update the discription. (Imre)
>>     Read dc5 count during dc6 enable and disable then and update
>>     dc6 residency counter. (Imre)
>>     Remove variable from dmc structure. (Jani)
>>     Updated the subject title.
>> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>>     Use flags to check dc6 enable/disable states. (Imre)
>>     Move the display version check and counter read/update to
>>     a helper. (Imre)
>>     Resize the variable length. (Rodrigo)
>>     Use old dc6 debugfs entry for every platform. (Rodrigo)
>> 
>> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>> ---
>>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
>>  .../i915/display/intel_display_power_well.c   | 26 +++++++++++++++++++
>>  .../i915/display/intel_display_power_well.h   |  1 +
>>  drivers/gpu/drm/i915/display/intel_dmc.c      | 21 ++++++++++++---
>>  4 files changed, 47 insertions(+), 3 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 554870d2494b..1608268bd9e2 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -490,6 +490,8 @@ struct intel_display {
>>  
>>  		/* perform PHY state sanity checks? */
>>  		bool chv_phy_assert[2];
>> +		unsigned int dc6_count;
>
> I think it's better to use dc6_allowed_count as Rodrigo suggested, not
> regarding it as a counter for actual DC6 transitions.
>
>> +		unsigned int dc5_start_count;
>>  	} power;
>>  
>>  	struct {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 5b60db597329..8478e687abb7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -17,6 +17,7 @@
>>  #include "intel_dkl_phy.h"
>>  #include "intel_dkl_phy_regs.h"
>>  #include "intel_dmc.h"
>> +#include "intel_dmc_regs.h"
>>  #include "intel_dmc_wl.h"
>>  #include "intel_dp_aux_regs.h"
>>  #include "intel_dpio_phy.h"
>> @@ -728,6 +729,22 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>>  	power_domains->dc_state = val;
>>  }
>>  
>> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis)
>
> Maybe rename dc6_en_dis to start_tracking?
>
> As Jani suggested the function should be in intel_dmc.c

Well, maybe.

I think the DMC register read should be in intel_dmc.c.

But maybe the display->power.* handling should be in
intel_display_power(_well).c?

IOW, make the functions and interfaces make sense for both. Now there's
no logic in the division.


BR,
Jani.

-- 
Jani Nikula, Intel

Re: [PATCH v3] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Tue, Mar 04, 2025 at 02:16:15PM +0200, Jani Nikula wrote:
> On Tue, 04 Mar 2025, Imre Deak <imre.deak@intel.com> wrote:
> > On Tue, Mar 04, 2025 at 12:53:19AM +0530, Mohammed Thasleem wrote:
> >> Starting from MTL we don't have a platform agnostic way to validate
> >> DC6 state due to dc6 counter has been removed to validate DC state.
> >> 
> >> The goal is to validate that the display HW can reach the DC6 power
> >> state. There is no HW DC6 residency counter (and there wasn't such
> >> a counter earlier either), so an alternative way is required. According
> >> to the HW team the display driver has programmed everything correctly in
> >> order to allow the DC6 power state if the DC5 power state is reached
> >> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> >> enabled by the driver.
> >> 
> >> Driver could take a snapshot of the DC5 residency counter right
> >> after it enables DC6 (dc5_residency_start) and increment the SW
> >> DC6 residency counter right before it disables DC6 or when user space
> >> reads the DC6 counter. So the driver would update the counter at these
> >> two points in the following way:
> >> dc6_residency_counter += dc5_current_count - dc5_start_count
> >> 
> >> v2: Update the discription. (Imre)
> >>     Read dc5 count during dc6 enable and disable then and update
> >>     dc6 residency counter. (Imre)
> >>     Remove variable from dmc structure. (Jani)
> >>     Updated the subject title.
> >> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
> >>     Use flags to check dc6 enable/disable states. (Imre)
> >>     Move the display version check and counter read/update to
> >>     a helper. (Imre)
> >>     Resize the variable length. (Rodrigo)
> >>     Use old dc6 debugfs entry for every platform. (Rodrigo)
> >> 
> >> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> >> ---
> >>  .../gpu/drm/i915/display/intel_display_core.h |  2 ++
> >>  .../i915/display/intel_display_power_well.c   | 26 +++++++++++++++++++
> >>  .../i915/display/intel_display_power_well.h   |  1 +
> >>  drivers/gpu/drm/i915/display/intel_dmc.c      | 21 ++++++++++++---
> >>  4 files changed, 47 insertions(+), 3 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> index 554870d2494b..1608268bd9e2 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> >> @@ -490,6 +490,8 @@ struct intel_display {
> >>  
> >>  		/* perform PHY state sanity checks? */
> >>  		bool chv_phy_assert[2];
> >> +		unsigned int dc6_count;
> >
> > I think it's better to use dc6_allowed_count as Rodrigo suggested, not
> > regarding it as a counter for actual DC6 transitions.
> >
> >> +		unsigned int dc5_start_count;
> >>  	} power;
> >>  
> >>  	struct {
> >> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> index 5b60db597329..8478e687abb7 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> >> @@ -17,6 +17,7 @@
> >>  #include "intel_dkl_phy.h"
> >>  #include "intel_dkl_phy_regs.h"
> >>  #include "intel_dmc.h"
> >> +#include "intel_dmc_regs.h"
> >>  #include "intel_dmc_wl.h"
> >>  #include "intel_dp_aux_regs.h"
> >>  #include "intel_dpio_phy.h"
> >> @@ -728,6 +729,22 @@ void gen9_sanitize_dc_state(struct intel_display *display)
> >>  	power_domains->dc_state = val;
> >>  }
> >>  
> >> +void update_dc6_count(struct intel_display *display, bool dc6_en_dis)
> >
> > Maybe rename dc6_en_dis to start_tracking?
> >
> > As Jani suggested the function should be in intel_dmc.c
> 
> Well, maybe.
> 
> I think the DMC register read should be in intel_dmc.c.
> 
> But maybe the display->power.* handling should be in
> intel_display_power(_well).c?

I think the counters should be stored in the intel_dmc struct and the
dc6_allowed_count should be returned via an interface (for instance just
make the above function return it).

> IOW, make the functions and interfaces make sense for both. Now there's
> no logic in the division.
> 
> 
> BR,
> Jani.
> 
> -- 
> Jani Nikula, Intel

[PATCH v4] drm/i915/dmc: Create debugfs entry for dc6 counter

[Mohammed Thasleem]

Starting from MTL we don't have a platform agnostic way to validate
DC6 state due to dc6 counter has been removed to validate DC state.

The goal is to validate that the display HW can reach the DC6 power
state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Driver could take a snapshot of the DC5 residency counter right
after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency_counter += dc5_current_count - dc5_start_count

v2: Update the discription. (Imre)
    Read dc5 count during dc6 enable and disable then and update
    dc6 residency counter. (Imre)
    Remove variable from dmc structure. (Jani)
    Updated the subject title.
v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
    Use flags to check dc6 enable/disable states. (Imre)
    Move the display version check and counter read/update to
    a helper. (Imre)
    Resize the variable length. (Rodrigo)
    Use old dc6 debugfs entry for every platform. (Rodrigo)
v4: Remove superfluous whitespace. (Jani)
    Read DMC registers in intel_dmc.c (Jani)
    Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
    Rename update_dc6_count and move it to intel_dmc.c (Jani)
    Rename dc6_en_dis to start_tracking. (Imre)
    Have lock for dc6 state read aswelll. (Imre)
    Keep the existing way print 'DC5 -> DC6 count' along with
    new 'DC6 Allowed Count' print. (Imre)
    Add counters in intel_dmc struct. (Imre)
    Have interface to return dc6 allowed count. (Imre)
    Rename dc6_count to dc6_allowed_count. (Rodrigo)

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
---
 .../i915/display/intel_display_power_well.c   |  9 ++++
 drivers/gpu/drm/i915/display/intel_dmc.c      | 46 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
 3 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8ec87ffd87d2..4d97b71cfe11 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -754,6 +754,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	struct i915_power_domains *power_domains = &display->power.domains;
 	u32 val;
 	u32 mask;
+	bool dc6_was_enabled, enable_dc6;
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
 			power_domains->dc_state, val & mask);
 
+	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
+	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
+	if (!dc6_was_enabled && enable_dc6)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(display, val);
 
+	if (!enable_dc6 && dc6_was_enabled)
+		intel_dmc_update_dc6_allowed_count(display, true);
+
 	power_domains->dc_state = val & mask;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa6944e55d95..f560349ddb6b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_display_power_well.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
@@ -57,6 +58,8 @@ struct intel_dmc {
 	const char *fw_path;
 	u32 max_fw_size; /* bytes */
 	u32 version;
+	u32 dc5_start_count;
+	u32 dc6_allowed_count;
 	struct dmc_fw_info {
 		u32 mmio_count;
 		i915_reg_t mmioaddr[20];
@@ -1232,11 +1235,36 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
 			   DMC_VERSION_MINOR(snapshot->version));
 }
 
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
+					bool start_tracking)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+	u32 dc5_cur_count;
+
+	if (DISPLAY_VER(dmc->display) < 14)
+		return;
+
+	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
+
+	if (start_tracking)
+		dmc->dc6_allowed_count += dc5_cur_count - dmc->dc5_start_count;
+
+	dmc->dc5_start_count = dc5_cur_count;
+}
+
+static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+
+	return dmc->dc6_allowed_count;
+}
+
 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 {
 	struct intel_display *display = m->private;
 	struct drm_i915_private *i915 = to_i915(display->drm);
 	struct intel_dmc *dmc = display_to_dmc(display);
+	struct i915_power_domains *power_domains = &display->power.domains;
 	intel_wakeref_t wakeref;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
 
@@ -1287,9 +1315,21 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	}
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
-	if (i915_mmio_reg_valid(dc6_reg))
-		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   intel_de_read(display, dc6_reg));
+
+	if (DISPLAY_VER(display) >= 14) {
+		mutex_lock(&power_domains->lock);
+		bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
+				   intel_de_read(display, DC_STATE_EN);
+		if (dc6_enabled)
+			intel_dmc_update_dc6_allowed_count(display, true);
+
+		mutex_unlock(&power_domains->lock);
+		seq_printf(m, "DC6 Allowed Count : %d\n", intel_dmc_get_dc6_allowed_count(display));
+	} else {
+		if (i915_mmio_reg_valid(dc6_reg)) {
+			seq_printf(m, "DC5 -> DC6 count: %d\n",
+				   intel_de_read(display, dc6_reg)); }
+	}
 
 	seq_printf(m, "program base: 0x%08x\n",
 		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 44cecef98e73..c78426eb4cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
 
 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
 
 void assert_dmc_loaded(struct intel_display *display);
 
-- 
2.43.0

✗ i915.CI.BAT: failure for drm/i915/dmc: Add debugfs for dc6 counter (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 5006 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev4)
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16247 -> Patchwork_144240v4
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v4, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v4:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_flip@basic-plain-flip@c-dp1:
    - bat-apl-1:          [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16247/bat-apl-1/igt@kms_flip@basic-plain-flip@c-dp1.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/bat-apl-1/igt@kms_flip@basic-plain-flip@c-dp1.html

  
Known issues
------------

  Here are the changes found in Patchwork_144240v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][3] ([i915#1849])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [PASS][6] -> [DMESG-WARN][7] ([i915#13494])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16247/bat-mtlp-9/igt@i915_module_load@load.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/bat-mtlp-9/igt@i915_module_load@load.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][8] +34 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][9] -> [SKIP][10] ([i915#9197]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16247/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [INCOMPLETE][11] ([i915#12904]) -> [PASS][12] +1 other test pass
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16247/bat-apl-1/igt@dmabuf@all-tests.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/bat-apl-1/igt@dmabuf@all-tests.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-arlh-3:         [DMESG-FAIL][13] ([i915#12061]) -> [DMESG-FAIL][14] ([i915#12061] / [i915#12435])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16247/bat-arlh-3/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/bat-arlh-3/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13494]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13494
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16247 -> Patchwork_144240v4

  CI-20190529: 20190529
  CI_DRM_16247: 23e0800ae0844e14894062d767edd6d50cab35f7 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8265: bfefe166535d69ca10d32e6ba0093260df21ee3d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_144240v4: 23e0800ae0844e14894062d767edd6d50cab35f7 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v4/index.html

[-- Attachment #2: Type: text/html, Size: 5895 bytes --]

Re: [PATCH v4] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Sun, Mar 09, 2025 at 01:40:02PM +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
> 
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
> 
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
> 
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>     Use flags to check dc6 enable/disable states. (Imre)
>     Move the display version check and counter read/update to
>     a helper. (Imre)
>     Resize the variable length. (Rodrigo)
>     Use old dc6 debugfs entry for every platform. (Rodrigo)
> v4: Remove superfluous whitespace. (Jani)
>     Read DMC registers in intel_dmc.c (Jani)
>     Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
>     Rename update_dc6_count and move it to intel_dmc.c (Jani)
>     Rename dc6_en_dis to start_tracking. (Imre)
>     Have lock for dc6 state read aswelll. (Imre)
>     Keep the existing way print 'DC5 -> DC6 count' along with
>     new 'DC6 Allowed Count' print. (Imre)
>     Add counters in intel_dmc struct. (Imre)
>     Have interface to return dc6 allowed count. (Imre)
>     Rename dc6_count to dc6_allowed_count. (Rodrigo)
> 
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../i915/display/intel_display_power_well.c   |  9 ++++
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 46 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
>  3 files changed, 53 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8ec87ffd87d2..4d97b71cfe11 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -754,6 +754,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  	struct i915_power_domains *power_domains = &display->power.domains;
>  	u32 val;
>  	u32 mask;
> +	bool dc6_was_enabled, enable_dc6;

Try to order these lines in decreasing line length.

>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> +	if (!dc6_was_enabled && enable_dc6)
> +		intel_dmc_update_dc6_allowed_count(display, false);

Tracking starts when enabling DC6, so start_tacking should be true here,

> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (!enable_dc6 && dc6_was_enabled)
> +		intel_dmc_update_dc6_allowed_count(display, true);

and false here.

> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa6944e55d95..f560349ddb6b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,6 +28,7 @@
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_display_power_well.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
>  #include "intel_step.h"
> @@ -57,6 +58,8 @@ struct intel_dmc {
>  	const char *fw_path;
>  	u32 max_fw_size; /* bytes */
>  	u32 version;
> +	u32 dc5_start_count;
> +	u32 dc6_allowed_count;

Maybe

	struct {
		u32 dc5_start;
		u32 count;
	} dc6_allowed;

so it's clearer that the two counters are related.

>  	struct dmc_fw_info {
>  		u32 mmio_count;
>  		i915_reg_t mmioaddr[20];
> @@ -1232,11 +1235,36 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
>  			   DMC_VERSION_MINOR(snapshot->version));
>  }
>  
> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
> +					bool start_tracking)
> +{
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +	u32 dc5_cur_count;
> +
> +	if (DISPLAY_VER(dmc->display) < 14)
> +		return;
> +
> +	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
> +
> +	if (start_tracking)
> +		dmc->dc6_allowed_count += dc5_cur_count - dmc->dc5_start_count;
> +
> +	dmc->dc5_start_count = dc5_cur_count;
> +}
> +
> +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display)
> +{
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +
> +	return dmc->dc6_allowed_count;
> +}
> +
>  static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  {
>  	struct intel_display *display = m->private;
>  	struct drm_i915_private *i915 = to_i915(display->drm);
>  	struct intel_dmc *dmc = display_to_dmc(display);
> +	struct i915_power_domains *power_domains = &display->power.domains;
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>  
> @@ -1287,9 +1315,21 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (DISPLAY_VER(display) >= 14) {
> +		mutex_lock(&power_domains->lock);
> +		bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
> +				   intel_de_read(display, DC_STATE_EN);
> +		if (dc6_enabled)
> +			intel_dmc_update_dc6_allowed_count(display, true);
> +
> +		mutex_unlock(&power_domains->lock);
> +		seq_printf(m, "DC6 Allowed Count : %d\n", intel_dmc_get_dc6_allowed_count(display));

Getting the counter should be also protected with the lock.

Maybe move all the above to helper returning error for DISPLAY_VER < 14
and call that like:

	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
		print dc6_allowed_count
	else if (i915_mmio_reg_valid(dc6_reg))
		print dc6_reg

> +	} else {
> +		if (i915_mmio_reg_valid(dc6_reg)) {
> +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> +				   intel_de_read(display, dc6_reg)); }
> +	}
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 44cecef98e73..c78426eb4cd5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
>  
>  struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
>  void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
>  
>  void assert_dmc_loaded(struct intel_display *display);
>  
> -- 
> 2.43.0
> 

Re: [PATCH v4] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Mon, Mar 10, 2025 at 05:04:49PM +0200, Imre Deak wrote:
> On Sun, Mar 09, 2025 at 01:40:02PM +0530, Mohammed Thasleem wrote:
> > Starting from MTL we don't have a platform agnostic way to validate
> > DC6 state due to dc6 counter has been removed to validate DC state.
> > 
> > The goal is to validate that the display HW can reach the DC6 power
> > state. There is no HW DC6 residency counter (and there wasn't such
> > a counter earlier either), so an alternative way is required. According
> > to the HW team the display driver has programmed everything correctly in
> > order to allow the DC6 power state if the DC5 power state is reached
> > (indicated by the HW DC5 residency counter incrementing) and DC6 is
> > enabled by the driver.
> > 
> > Driver could take a snapshot of the DC5 residency counter right
> > after it enables DC6 (dc5_residency_start) and increment the SW
> > DC6 residency counter right before it disables DC6 or when user space
> > reads the DC6 counter. So the driver would update the counter at these
> > two points in the following way:
> > dc6_residency_counter += dc5_current_count - dc5_start_count
> > 
> > v2: Update the discription. (Imre)
> >     Read dc5 count during dc6 enable and disable then and update
> >     dc6 residency counter. (Imre)
> >     Remove variable from dmc structure. (Jani)
> >     Updated the subject title.
> > v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
> >     Use flags to check dc6 enable/disable states. (Imre)
> >     Move the display version check and counter read/update to
> >     a helper. (Imre)
> >     Resize the variable length. (Rodrigo)
> >     Use old dc6 debugfs entry for every platform. (Rodrigo)
> > v4: Remove superfluous whitespace. (Jani)
> >     Read DMC registers in intel_dmc.c (Jani)
> >     Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
> >     Rename update_dc6_count and move it to intel_dmc.c (Jani)
> >     Rename dc6_en_dis to start_tracking. (Imre)
> >     Have lock for dc6 state read aswelll. (Imre)
> >     Keep the existing way print 'DC5 -> DC6 count' along with
> >     new 'DC6 Allowed Count' print. (Imre)
> >     Add counters in intel_dmc struct. (Imre)
> >     Have interface to return dc6 allowed count. (Imre)
> >     Rename dc6_count to dc6_allowed_count. (Rodrigo)
> > 
> > Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> > ---
> >  .../i915/display/intel_display_power_well.c   |  9 ++++
> >  drivers/gpu/drm/i915/display/intel_dmc.c      | 46 +++++++++++++++++--
> >  drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
> >  3 files changed, 53 insertions(+), 3 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > index 8ec87ffd87d2..4d97b71cfe11 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> > @@ -754,6 +754,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
> >  	struct i915_power_domains *power_domains = &display->power.domains;
> >  	u32 val;
> >  	u32 mask;
> > +	bool dc6_was_enabled, enable_dc6;
> 
> Try to order these lines in decreasing line length.
> 
> >  
> >  	if (!HAS_DISPLAY(display))
> >  		return;
> > @@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
> >  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
> >  			power_domains->dc_state, val & mask);
> >  
> > +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> > +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> > +	if (!dc6_was_enabled && enable_dc6)
> > +		intel_dmc_update_dc6_allowed_count(display, false);
> 
> Tracking starts when enabling DC6, so start_tacking should be true here,
> 
> > +
> >  	val &= ~mask;
> >  	val |= state;
> >  
> >  	gen9_write_dc_state(display, val);
> >  
> > +	if (!enable_dc6 && dc6_was_enabled)
> > +		intel_dmc_update_dc6_allowed_count(display, true);
> 
> and false here.
> 
> > +
> >  	power_domains->dc_state = val & mask;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> > index fa6944e55d95..f560349ddb6b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> > @@ -28,6 +28,7 @@
> >  #include "i915_drv.h"
> >  #include "i915_reg.h"
> >  #include "intel_de.h"
> > +#include "intel_display_power_well.h"
> >  #include "intel_dmc.h"
> >  #include "intel_dmc_regs.h"
> >  #include "intel_step.h"
> > @@ -57,6 +58,8 @@ struct intel_dmc {
> >  	const char *fw_path;
> >  	u32 max_fw_size; /* bytes */
> >  	u32 version;
> > +	u32 dc5_start_count;
> > +	u32 dc6_allowed_count;
> 
> Maybe
> 
> 	struct {
> 		u32 dc5_start;
> 		u32 count;
> 	} dc6_allowed;
> 
> so it's clearer that the two counters are related.
> 
> >  	struct dmc_fw_info {
> >  		u32 mmio_count;
> >  		i915_reg_t mmioaddr[20];
> > @@ -1232,11 +1235,36 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
> >  			   DMC_VERSION_MINOR(snapshot->version));
> >  }
> >  
> > +void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
> > +					bool start_tracking)
> > +{
> > +	struct intel_dmc *dmc = display_to_dmc(display);
> > +	u32 dc5_cur_count;
> > +
> > +	if (DISPLAY_VER(dmc->display) < 14)
> > +		return;
> > +
> > +	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
> > +
> > +	if (start_tracking)

The counter should not be updated when tracking starts (i.e. at the
beginning of the period DC6 is enabled), so the check above should be
negated.

> > +		dmc->dc6_allowed_count += dc5_cur_count - dmc->dc5_start_count;
> > +
> > +	dmc->dc5_start_count = dc5_cur_count;
> > +}
> > +
> > +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display)
> > +{
> > +	struct intel_dmc *dmc = display_to_dmc(display);
> > +
> > +	return dmc->dc6_allowed_count;
> > +}
> > +
> >  static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >  {
> >  	struct intel_display *display = m->private;
> >  	struct drm_i915_private *i915 = to_i915(display->drm);
> >  	struct intel_dmc *dmc = display_to_dmc(display);
> > +	struct i915_power_domains *power_domains = &display->power.domains;
> >  	intel_wakeref_t wakeref;
> >  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> >  
> > @@ -1287,9 +1315,21 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
> >  	}
> >  
> >  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> > -	if (i915_mmio_reg_valid(dc6_reg))
> > -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> > -			   intel_de_read(display, dc6_reg));
> > +
> > +	if (DISPLAY_VER(display) >= 14) {
> > +		mutex_lock(&power_domains->lock);
> > +		bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
> > +				   intel_de_read(display, DC_STATE_EN);
> > +		if (dc6_enabled)
> > +			intel_dmc_update_dc6_allowed_count(display, true);
> > +
> > +		mutex_unlock(&power_domains->lock);
> > +		seq_printf(m, "DC6 Allowed Count : %d\n", intel_dmc_get_dc6_allowed_count(display));
> 
> Getting the counter should be also protected with the lock.
> 
> Maybe move all the above to helper returning error for DISPLAY_VER < 14
> and call that like:
> 
> 	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
> 		print dc6_allowed_count
> 	else if (i915_mmio_reg_valid(dc6_reg))
> 		print dc6_reg
> 
> > +	} else {
> > +		if (i915_mmio_reg_valid(dc6_reg)) {
> > +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> > +				   intel_de_read(display, dc6_reg)); }
> > +	}
> >  
> >  	seq_printf(m, "program base: 0x%08x\n",
> >  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> > index 44cecef98e73..c78426eb4cd5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> > @@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
> >  
> >  struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
> >  void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
> > +void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
> >  
> >  void assert_dmc_loaded(struct intel_display *display);
> >  
> > -- 
> > 2.43.0
> > 

[PATCH v5] drm/i915/dmc: Create debugfs entry for dc6 counter

[Mohammed Thasleem]

Starting from MTL we don't have a platform agnostic way to validate
DC6 state due to dc6 counter has been removed to validate DC state.

The goal is to validate that the display HW can reach the DC6 power
state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Driver could take a snapshot of the DC5 residency counter right
after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency_counter += dc5_current_count - dc5_start_count

v2: Update the discription. (Imre)
    Read dc5 count during dc6 enable and disable then and update
    dc6 residency counter. (Imre)
    Remove variable from dmc structure. (Jani)
    Updated the subject title.
v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
    Use flags to check dc6 enable/disable states. (Imre)
    Move the display version check and counter read/update to
    a helper. (Imre)
    Resize the variable length. (Rodrigo)
    Use old dc6 debugfs entry for every platform. (Rodrigo)
v4: Remove superfluous whitespace. (Jani)
    Read DMC registers in intel_dmc.c (Jani)
    Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
    Rename update_dc6_count and move it to intel_dmc.c (Jani)
    Rename dc6_en_dis to start_tracking. (Imre)
    Have lock for dc6 state read aswelll. (Imre)
    Keep the existing way print 'DC5 -> DC6 count' along with
    new 'DC6 Allowed Count' print. (Imre)
    Add counters in intel_dmc struct. (Imre)
    Have interface to return dc6 allowed count. (Imre)
    Rename dc6_count to dc6_allowed_count. (Rodrigo)
v5: Rename counters and move in to dc6_allowed structure. (Imre)
    Order declaration lines in decreasing line length. (Imre)
    Update start_tacking logic. (Imre)
    Move get couner inside lock and DISPLAY_VER code to helper. (Imre)

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
---
 .../i915/display/intel_display_power_well.c   | 11 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 54 +++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
 3 files changed, 62 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8ec87ffd87d2..574352439573 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -752,8 +752,9 @@ void gen9_sanitize_dc_state(struct intel_display *display)
 void gen9_set_dc_state(struct intel_display *display, u32 state)
 {
 	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 val;
+	bool dc6_was_enabled, enable_dc6;
 	u32 mask;
+	u32 val;
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
 			power_domains->dc_state, val & mask);
 
+	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
+	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
+	if (!dc6_was_enabled && enable_dc6)
+		intel_dmc_update_dc6_allowed_count(display, true);
+
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(display, val);
 
+	if (!enable_dc6 && dc6_was_enabled)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
 	power_domains->dc_state = val & mask;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa6944e55d95..95abeec0586a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_display_power_well.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
@@ -57,6 +58,10 @@ struct intel_dmc {
 	const char *fw_path;
 	u32 max_fw_size; /* bytes */
 	u32 version;
+	struct {
+		u32 dc5_start;
+		u32 count;
+	} dc6_allowed;
 	struct dmc_fw_info {
 		u32 mmio_count;
 		i915_reg_t mmioaddr[20];
@@ -1232,6 +1237,43 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
 			   DMC_VERSION_MINOR(snapshot->version));
 }
 
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
+					bool start_tracking)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+	u32 dc5_cur_count;
+
+	if (DISPLAY_VER(dmc->display) < 14)
+		return;
+
+	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
+
+	if (!start_tracking)
+		dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
+
+	dmc->dc6_allowed.dc5_start = dc5_cur_count;
+}
+
+static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+	struct intel_dmc *dmc = display_to_dmc(display);
+
+	if (DISPLAY_VER(display) < 14)
+		return -ENODEV;
+
+	mutex_lock(&power_domains->lock);
+	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
+			   intel_de_read(display, DC_STATE_EN);
+	if (dc6_enabled)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
+	*count = dmc->dc6_allowed.count;
+	mutex_unlock(&power_domains->lock);
+
+	return 0;
+}
+
 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 {
 	struct intel_display *display = m->private;
@@ -1239,6 +1281,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	struct intel_dmc *dmc = display_to_dmc(display);
 	intel_wakeref_t wakeref;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+	u32 dc6_allowed_count;
 
 	if (!HAS_DMC(display))
 		return -ENODEV;
@@ -1287,9 +1330,14 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	}
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
-	if (i915_mmio_reg_valid(dc6_reg))
-		seq_printf(m, "DC5 -> DC6 count: %d\n",
-			   intel_de_read(display, dc6_reg));
+
+	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count) == 0) {
+		seq_printf(m, "DC6 Allowed Count : %d\n", dc6_allowed_count);
+	} else {
+		if (i915_mmio_reg_valid(dc6_reg)) {
+			seq_printf(m, "DC5 -> DC6 count: %d\n",
+				   intel_de_read(display, dc6_reg)); }
+	}
 
 	seq_printf(m, "program base: 0x%08x\n",
 		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 44cecef98e73..c78426eb4cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
 
 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
 
 void assert_dmc_loaded(struct intel_display *display);
 
-- 
2.43.0

Re: [PATCH v5] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Wed, Mar 12, 2025 at 08:13:10PM +0530, Mohammed Thasleem wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.
> 
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
> 
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
> 
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>     Use flags to check dc6 enable/disable states. (Imre)
>     Move the display version check and counter read/update to
>     a helper. (Imre)
>     Resize the variable length. (Rodrigo)
>     Use old dc6 debugfs entry for every platform. (Rodrigo)
> v4: Remove superfluous whitespace. (Jani)
>     Read DMC registers in intel_dmc.c (Jani)
>     Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
>     Rename update_dc6_count and move it to intel_dmc.c (Jani)
>     Rename dc6_en_dis to start_tracking. (Imre)
>     Have lock for dc6 state read aswelll. (Imre)
>     Keep the existing way print 'DC5 -> DC6 count' along with
>     new 'DC6 Allowed Count' print. (Imre)
>     Add counters in intel_dmc struct. (Imre)
>     Have interface to return dc6 allowed count. (Imre)
>     Rename dc6_count to dc6_allowed_count. (Rodrigo)
> v5: Rename counters and move in to dc6_allowed structure. (Imre)
>     Order declaration lines in decreasing line length. (Imre)
>     Update start_tacking logic. (Imre)
>     Move get couner inside lock and DISPLAY_VER code to helper. (Imre)
> 
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> ---
>  .../i915/display/intel_display_power_well.c   | 11 +++-
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 54 +++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
>  3 files changed, 62 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8ec87ffd87d2..574352439573 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -752,8 +752,9 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  void gen9_set_dc_state(struct intel_display *display, u32 state)
>  {
>  	struct i915_power_domains *power_domains = &display->power.domains;
> -	u32 val;
> +	bool dc6_was_enabled, enable_dc6;
>  	u32 mask;
> +	u32 val;
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> +	if (!dc6_was_enabled && enable_dc6)
> +		intel_dmc_update_dc6_allowed_count(display, true);
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (!enable_dc6 && dc6_was_enabled)
> +		intel_dmc_update_dc6_allowed_count(display, false);
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa6944e55d95..95abeec0586a 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,6 +28,7 @@
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_display_power_well.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
>  #include "intel_step.h"
> @@ -57,6 +58,10 @@ struct intel_dmc {
>  	const char *fw_path;
>  	u32 max_fw_size; /* bytes */
>  	u32 version;
> +	struct {
> +		u32 dc5_start;
> +		u32 count;
> +	} dc6_allowed;
>  	struct dmc_fw_info {
>  		u32 mmio_count;
>  		i915_reg_t mmioaddr[20];
> @@ -1232,6 +1237,43 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
>  			   DMC_VERSION_MINOR(snapshot->version));
>  }
>  
> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
> +					bool start_tracking)
> +{
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +	u32 dc5_cur_count;
> +
> +	if (DISPLAY_VER(dmc->display) < 14)
> +		return;
> +
> +	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
> +
> +	if (!start_tracking)
> +		dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
> +
> +	dmc->dc6_allowed.dc5_start = dc5_cur_count;
> +}
> +
> +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)

The return type isn't compatible with the -ENODEV returned value. I'd
just return a bool, since the reason for an error is always the same.

> +{
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +
> +	if (DISPLAY_VER(display) < 14)
> +		return -ENODEV;
> +
> +	mutex_lock(&power_domains->lock);
> +	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
> +			   intel_de_read(display, DC_STATE_EN);
> +	if (dc6_enabled)
> +		intel_dmc_update_dc6_allowed_count(display, false);
> +
> +	*count = dmc->dc6_allowed.count;
> +	mutex_unlock(&power_domains->lock);
> +
> +	return 0;
> +}
> +
>  static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  {
>  	struct intel_display *display = m->private;
> @@ -1239,6 +1281,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_dmc *dmc = display_to_dmc(display);
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc6_allowed_count;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1287,9 +1330,14 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
> -			   intel_de_read(display, dc6_reg));
> +
> +	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count) == 0) {
> +		seq_printf(m, "DC6 Allowed Count : %d\n", dc6_allowed_count);

"DC5 -> DC6 allowed count: %d\n" would align better with the other
entries printed.

> +	} else {
> +		if (i915_mmio_reg_valid(dc6_reg)) {

The above else/if could be combined to 'else if (i915_mmio_reg_valid(...))'
and the {} could be dropped from around both resultant if branches.

With the above fixed the patch looks ok to me:

Reviewed-by: Imre Deak <imre.deak@intel.com>

> +			seq_printf(m, "DC5 -> DC6 count: %d\n",
> +				   intel_de_read(display, dc6_reg)); }
> +	}
>  
>  	seq_printf(m, "program base: 0x%08x\n",
>  		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 44cecef98e73..c78426eb4cd5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
>  
>  struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
>  void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
>  
>  void assert_dmc_loaded(struct intel_display *display);
>  
> -- 
> 2.43.0
> 

✗ i915.CI.BAT: failure for drm/i915/dmc: Add debugfs for dc6 counter (rev5)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8608 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev5)
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16273 -> Patchwork_144240v5
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v5 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v5, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v5:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@module-reload:
    - bat-dg2-11:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-dg2-11/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-dg2-11/igt@i915_pm_rpm@module-reload.html

  
New tests
---------

  New tests have been introduced between CI_DRM_16273 and Patchwork_144240v5:

### New IGT tests (1) ###

  * igt@i915_selftest@basic-busy:
    - Statuses :
    - Exec time: [None] s

  

Known issues
------------

  Here are the changes found in Patchwork_144240v5 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][3] ([i915#10462]) +1 other test dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@core_auth@basic-auth.html

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][4] ([i915#1849])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([i915#2190])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][6] ([i915#2190])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][7] ([i915#4613]) +3 other tests skip
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][8] ([i915#4613]) +3 other tests skip
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][9] -> [DMESG-FAIL][10] ([i915#12061]) +1 other test dmesg-fail
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-mtlp-8/igt@i915_selftest@live.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-mtlp-8/igt@i915_selftest@live.html
    - bat-arlh-3:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061] / [i915#12435])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-arlh-3/igt@i915_selftest@live.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-arlh-3/igt@i915_selftest@live.html

  * igt@i915_selftest@live@requests:
    - bat-atsm-1:         [PASS][13] -> [INCOMPLETE][14] ([i915#12445])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-atsm-1/igt@i915_selftest@live@requests.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-atsm-1/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@workarounds:
    - bat-arlh-3:         [PASS][15] -> [DMESG-FAIL][16] ([i915#12061])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-arlh-3/igt@i915_selftest@live@workarounds.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-arlh-3/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@too-high:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][17] ([i915#13903]) +2 other tests fail
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][18] +62 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][19] +10 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][20] ([i915#13905])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-FAIL][21] ([i915#13905])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][22] ([i915#13904])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/fi-kbl-8809g/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][23] -> [SKIP][24] ([i915#9197]) +3 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@dmabuf@all-tests:
    - bat-apl-1:          [INCOMPLETE][25] ([i915#12904]) -> [PASS][26] +1 other test pass
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-apl-1/igt@dmabuf@all-tests.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-apl-1/igt@dmabuf@all-tests.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [DMESG-FAIL][27] ([i915#12061]) -> [PASS][28] +1 other test pass
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-arls-5/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [ABORT][29] ([i915#13679]) -> [INCOMPLETE][30] ([i915#12445])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16273/bat-atsm-1/igt@i915_selftest@live.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/bat-atsm-1/igt@i915_selftest@live.html

  
  [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12435
  [i915#12445]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12445
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13679]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13679
  [i915#13903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13903
  [i915#13904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13904
  [i915#13905]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13905
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16273 -> Patchwork_144240v5

  CI-20190529: 20190529
  CI_DRM_16273: ab32fa5b833c1887c0809109b3c8f910031a361d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v5: ab32fa5b833c1887c0809109b3c8f910031a361d @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v5/index.html

[-- Attachment #2: Type: text/html, Size: 10230 bytes --]

Re: [PATCH v5] drm/i915/dmc: Create debugfs entry for dc6 counter

[Naladala, Ramanaidu]

Hi Imre/Thasleem,

On 3/12/2025 8:38 PM, Imre Deak wrote:
> On Wed, Mar 12, 2025 at 08:13:10PM +0530, Mohammed Thasleem wrote:
>> Starting from MTL we don't have a platform agnostic way to validate
>> DC6 state due to dc6 counter has been removed to validate DC state.
>>
>> The goal is to validate that the display HW can reach the DC6 power
>> state. There is no HW DC6 residency counter (and there wasn't such
>> a counter earlier either), so an alternative way is required. According
>> to the HW team the display driver has programmed everything correctly in
>> order to allow the DC6 power state if the DC5 power state is reached
>> (indicated by the HW DC5 residency counter incrementing) and DC6 is
>> enabled by the driver.
>>
>> Driver could take a snapshot of the DC5 residency counter right
>> after it enables DC6 (dc5_residency_start) and increment the SW
>> DC6 residency counter right before it disables DC6 or when user space
>> reads the DC6 counter. So the driver would update the counter at these
>> two points in the following way:
>> dc6_residency_counter += dc5_current_count - dc5_start_count
>>
>> v2: Update the discription. (Imre)
>>      Read dc5 count during dc6 enable and disable then and update
>>      dc6 residency counter. (Imre)
>>      Remove variable from dmc structure. (Jani)
>>      Updated the subject title.
>> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>>      Use flags to check dc6 enable/disable states. (Imre)
>>      Move the display version check and counter read/update to
>>      a helper. (Imre)
>>      Resize the variable length. (Rodrigo)
>>      Use old dc6 debugfs entry for every platform. (Rodrigo)
>> v4: Remove superfluous whitespace. (Jani)
>>      Read DMC registers in intel_dmc.c (Jani)
>>      Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
>>      Rename update_dc6_count and move it to intel_dmc.c (Jani)
>>      Rename dc6_en_dis to start_tracking. (Imre)
>>      Have lock for dc6 state read aswelll. (Imre)
>>      Keep the existing way print 'DC5 -> DC6 count' along with
>>      new 'DC6 Allowed Count' print. (Imre)
>>      Add counters in intel_dmc struct. (Imre)
>>      Have interface to return dc6 allowed count. (Imre)
>>      Rename dc6_count to dc6_allowed_count. (Rodrigo)
>> v5: Rename counters and move in to dc6_allowed structure. (Imre)
>>      Order declaration lines in decreasing line length. (Imre)
>>      Update start_tacking logic. (Imre)
>>      Move get couner inside lock and DISPLAY_VER code to helper. (Imre)
>>
>> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
>> ---
>>   .../i915/display/intel_display_power_well.c   | 11 +++-
>>   drivers/gpu/drm/i915/display/intel_dmc.c      | 54 +++++++++++++++++--
>>   drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
>>   3 files changed, 62 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 8ec87ffd87d2..574352439573 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -752,8 +752,9 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>>   void gen9_set_dc_state(struct intel_display *display, u32 state)
>>   {
>>   	struct i915_power_domains *power_domains = &display->power.domains;
>> -	u32 val;
>> +	bool dc6_was_enabled, enable_dc6;
>>   	u32 mask;
>> +	u32 val;
>>   
>>   	if (!HAS_DISPLAY(display))
>>   		return;
>> @@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>>   		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>>   			power_domains->dc_state, val & mask);
>>   
>> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
>> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
>> +	if (!dc6_was_enabled && enable_dc6)
>> +		intel_dmc_update_dc6_allowed_count(display, true);
>> +
>>   	val &= ~mask;
>>   	val |= state;
>>   
>>   	gen9_write_dc_state(display, val);
>>   
>> +	if (!enable_dc6 && dc6_was_enabled)
>> +		intel_dmc_update_dc6_allowed_count(display, false);
>> +
>>   	power_domains->dc_state = val & mask;
>>   }
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index fa6944e55d95..95abeec0586a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -28,6 +28,7 @@
>>   #include "i915_drv.h"
>>   #include "i915_reg.h"
>>   #include "intel_de.h"
>> +#include "intel_display_power_well.h"
>>   #include "intel_dmc.h"
>>   #include "intel_dmc_regs.h"
>>   #include "intel_step.h"
>> @@ -57,6 +58,10 @@ struct intel_dmc {
>>   	const char *fw_path;
>>   	u32 max_fw_size; /* bytes */
>>   	u32 version;
>> +	struct {
>> +		u32 dc5_start;
>> +		u32 count;
>> +	} dc6_allowed;
>>   	struct dmc_fw_info {
>>   		u32 mmio_count;
>>   		i915_reg_t mmioaddr[20];
>> @@ -1232,6 +1237,43 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
>>   			   DMC_VERSION_MINOR(snapshot->version));
>>   }
>>   
>> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
>> +					bool start_tracking)
>> +{
>> +	struct intel_dmc *dmc = display_to_dmc(display);
>> +	u32 dc5_cur_count;
>> +
>> +	if (DISPLAY_VER(dmc->display) < 14)
>> +		return;
>> +
>> +	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
>> +
>> +	if (!start_tracking)
>> +		dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
>> +
>> +	dmc->dc6_allowed.dc5_start = dc5_cur_count;
>> +}
>> +
>> +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
> The return type isn't compatible with the -ENODEV returned value. I'd
> just return a bool, since the reason for an error is always the same.
>
>> +{
>> +	struct i915_power_domains *power_domains = &display->power.domains;
>> +	struct intel_dmc *dmc = display_to_dmc(display);
>> +
>> +	if (DISPLAY_VER(display) < 14)
>> +		return -ENODEV;
>> +
>> +	mutex_lock(&power_domains->lock);
>> +	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
>> +			   intel_de_read(display, DC_STATE_EN);

The dc6_enabled flag indicates only the DC state limit. If all 
conditions are met, the DMC can entry/exits DC6.

However, if the DC6 conditions are not met, the DMC can perform 
entry/exits up to DC5. Entry/exits from

DC5 to DC3 can also change the DG1_DMC_DEBUG_DC5_COUNT counter values. 
It is better to add a pc10 check

along with the dc6_enabled flag.


Correct me if my understanding is wrong.

>> +	if (dc6_enabled)
>> +		intel_dmc_update_dc6_allowed_count(display, false);
>> +
>> +	*count = dmc->dc6_allowed.count;
>> +	mutex_unlock(&power_domains->lock);
>> +
>> +	return 0;
>> +}
>> +
>>   static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>>   {
>>   	struct intel_display *display = m->private;
>> @@ -1239,6 +1281,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>>   	struct intel_dmc *dmc = display_to_dmc(display);
>>   	intel_wakeref_t wakeref;
>>   	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
>> +	u32 dc6_allowed_count;
>>   
>>   	if (!HAS_DMC(display))
>>   		return -ENODEV;
>> @@ -1287,9 +1330,14 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>>   	}
>>   
>>   	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
>> -	if (i915_mmio_reg_valid(dc6_reg))
>> -		seq_printf(m, "DC5 -> DC6 count: %d\n",
>> -			   intel_de_read(display, dc6_reg));
>> +
>> +	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count) == 0) {
>> +		seq_printf(m, "DC6 Allowed Count : %d\n", dc6_allowed_count);
> "DC5 -> DC6 allowed count: %d\n" would align better with the other
> entries printed.
>
>> +	} else {
>> +		if (i915_mmio_reg_valid(dc6_reg)) {
> The above else/if could be combined to 'else if (i915_mmio_reg_valid(...))'
> and the {} could be dropped from around both resultant if branches.
>
> With the above fixed the patch looks ok to me:
>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
>
>> +			seq_printf(m, "DC5 -> DC6 count: %d\n",
>> +				   intel_de_read(display, dc6_reg)); }
>> +	}
>>   
>>   	seq_printf(m, "program base: 0x%08x\n",
>>   		   intel_de_read(display, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)));
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
>> index 44cecef98e73..c78426eb4cd5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
>> @@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
>>   
>>   struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
>>   void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
>> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
>>   
>>   void assert_dmc_loaded(struct intel_display *display);
>>   
>> -- 
>> 2.43.0
>>

Re: [PATCH v5] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Wed, Mar 12, 2025 at 11:44:20PM +0530, Naladala, Ramanaidu wrote:
> [...]
> > > +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
> > The return type isn't compatible with the -ENODEV returned value. I'd
> > just return a bool, since the reason for an error is always the same.
> > 
> > > +{
> > > +	struct i915_power_domains *power_domains = &display->power.domains;
> > > +	struct intel_dmc *dmc = display_to_dmc(display);
> > > +
> > > +	if (DISPLAY_VER(display) < 14)
> > > +		return -ENODEV;
> > > +
> > > +	mutex_lock(&power_domains->lock);
> > > +	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
> > > +			   intel_de_read(display, DC_STATE_EN);
> 
> The dc6_enabled flag indicates only the DC state limit. If all conditions
> are met, the DMC can entry/exits DC6.
> 
> However, if the DC6 conditions are not met, the DMC can perform entry/exits
> up to DC5. Entry/exits from DC5 to DC3 can also change the DG1_DMC_DEBUG_DC5_COUNT
> counter values. It is better to add a pc10 check along with the dc6_enabled flag.
> 
> Correct me if my understanding is wrong.

According to HW people, the conditions for DC6 are met from the
_display_ side if the conditions for DC5 are met and DC6 is enabled. The
problem of making this dependent on package C states is that those
states also depend on non-display IPs. The purpose of this counter (DC6
allowed) is validating the display driver's DC6 programming, without
depending on the validity of the programming for all other IPs (by
non-display drivers) that could block actual DC6 transitions.

> > > +	if (dc6_enabled)
> > > +		intel_dmc_update_dc6_allowed_count(display, false);
> > > +
> > > +	*count = dmc->dc6_allowed.count;
> > > +	mutex_unlock(&power_domains->lock);
> > > +
> > > +	return 0;
> > > +}
> > > +

Re: [PATCH v5] drm/i915/dmc: Create debugfs entry for dc6 counter

[Naladala, Ramanaidu]

On 3/13/2025 12:19 AM, Imre Deak wrote:
> On Wed, Mar 12, 2025 at 11:44:20PM +0530, Naladala, Ramanaidu wrote:
>> [...]
>>>> +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
>>> The return type isn't compatible with the -ENODEV returned value. I'd
>>> just return a bool, since the reason for an error is always the same.
>>>
>>>> +{
>>>> +	struct i915_power_domains *power_domains = &display->power.domains;
>>>> +	struct intel_dmc *dmc = display_to_dmc(display);
>>>> +
>>>> +	if (DISPLAY_VER(display) < 14)
>>>> +		return -ENODEV;
>>>> +
>>>> +	mutex_lock(&power_domains->lock);
>>>> +	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
>>>> +			   intel_de_read(display, DC_STATE_EN);
>> The dc6_enabled flag indicates only the DC state limit. If all conditions
>> are met, the DMC can entry/exits DC6.
>>
>> However, if the DC6 conditions are not met, the DMC can perform entry/exits
>> up to DC5. Entry/exits from DC5 to DC3 can also change the DG1_DMC_DEBUG_DC5_COUNT
>> counter values. It is better to add a pc10 check along with the dc6_enabled flag.
>>
>> Correct me if my understanding is wrong.
> According to HW people, the conditions for DC6 are met from the
> _display_ side if the conditions for DC5 are met and DC6 is enabled. The
> problem of making this dependent on package C states is that those
> states also depend on non-display IPs. The purpose of this counter (DC6
> allowed) is validating the display driver's DC6 programming, without
> depending on the validity of the programming for all other IPs (by
> non-display drivers) that could block actual DC6 transitions.

In that case, we have the DC3 entry/exit counter 
DG1_DMC_DEBUG_DC1_COUNT. Add a check to ensure it does not change when 
the DC5 counters are changing.

It will confirm the transaction entry/exits are between DC5 and DC6. If 
DC3 counter is changed, don't increment the dc6 counter value.


>
>>>> +	if (dc6_enabled)
>>>> +		intel_dmc_update_dc6_allowed_count(display, false);
>>>> +
>>>> +	*count = dmc->dc6_allowed.count;
>>>> +	mutex_unlock(&power_domains->lock);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +

Re: [PATCH v5] drm/i915/dmc: Create debugfs entry for dc6 counter

[Imre Deak]

On Thu, Mar 13, 2025 at 01:02:09AM +0530, Naladala, Ramanaidu wrote:
> 
> On 3/13/2025 12:19 AM, Imre Deak wrote:
> > On Wed, Mar 12, 2025 at 11:44:20PM +0530, Naladala, Ramanaidu wrote:
> > > [...]
> > > > > +static u32 intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
> > > > The return type isn't compatible with the -ENODEV returned value. I'd
> > > > just return a bool, since the reason for an error is always the same.
> > > > 
> > > > > +{
> > > > > +	struct i915_power_domains *power_domains = &display->power.domains;
> > > > > +	struct intel_dmc *dmc = display_to_dmc(display);
> > > > > +
> > > > > +	if (DISPLAY_VER(display) < 14)
> > > > > +		return -ENODEV;
> > > > > +
> > > > > +	mutex_lock(&power_domains->lock);
> > > > > +	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
> > > > > +			   intel_de_read(display, DC_STATE_EN);
> > > The dc6_enabled flag indicates only the DC state limit. If all conditions
> > > are met, the DMC can entry/exits DC6.
> > > 
> > > However, if the DC6 conditions are not met, the DMC can perform entry/exits
> > > up to DC5. Entry/exits from DC5 to DC3 can also change the DG1_DMC_DEBUG_DC5_COUNT
> > > counter values. It is better to add a pc10 check along with the dc6_enabled flag.
> > > 
> > > Correct me if my understanding is wrong.
> > According to HW people, the conditions for DC6 are met from the
> > _display_ side if the conditions for DC5 are met and DC6 is enabled. The
> > problem of making this dependent on package C states is that those
> > states also depend on non-display IPs. The purpose of this counter (DC6
> > allowed) is validating the display driver's DC6 programming, without
> > depending on the validity of the programming for all other IPs (by
> > non-display drivers) that could block actual DC6 transitions.
> 
> In that case, we have the DC3 entry/exit counter DG1_DMC_DEBUG_DC1_COUNT.
> Add a check to ensure it does not change when the DC5 counters are changing.
> 
> It will confirm the transaction entry/exits are between DC5 and DC6. If DC3
> counter is changed, don't increment the dc6 counter value.

We are using the DG1_DMC_DEBUG_DC5_COUNT (0x134154) register to check
for DC5 _entries_. This matches the bspec (49786) definition of the
register:

"Residency counter for DC5 state. Indicates the number of DC5 entries."

In fact all other DMC_DEBUG_ registers are specified in a similar way,
indicating the residency for a given state, that is entries. Counting
both entries and exits in the same counter would be ultimately broken in
any case.

> > 
> > > > > +	if (dc6_enabled)
> > > > > +		intel_dmc_update_dc6_allowed_count(display, false);
> > > > > +
> > > > > +	*count = dmc->dc6_allowed.count;
> > > > > +	mutex_unlock(&power_domains->lock);
> > > > > +
> > > > > +	return 0;
> > > > > +}
> > > > > +

[PATCH v6] drm/i915/dmc: Create debugfs entry for dc6 counter

[Mohammed Thasleem]

Starting from MTL we don't have a platform agnostic way to validate
DC6 state due to dc6 counter has been removed to validate DC state.

The goal is to validate that the display HW can reach the DC6 power
state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Driver could take a snapshot of the DC5 residency counter right
after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency_counter += dc5_current_count - dc5_start_count

v2: Update the discription. (Imre)
    Read dc5 count during dc6 enable and disable then and update
    dc6 residency counter. (Imre)
    Remove variable from dmc structure. (Jani)
    Updated the subject title.
v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
    Use flags to check dc6 enable/disable states. (Imre)
    Move the display version check and counter read/update to
    a helper. (Imre)
    Resize the variable length. (Rodrigo)
    Use old dc6 debugfs entry for every platform. (Rodrigo)
v4: Remove superfluous whitespace. (Jani)
    Read DMC registers in intel_dmc.c (Jani)
    Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
    Rename update_dc6_count and move it to intel_dmc.c (Jani)
    Rename dc6_en_dis to start_tracking. (Imre)
    Have lock for dc6 state read aswelll. (Imre)
    Keep the existing way print 'DC5 -> DC6 count' along with
    new 'DC6 Allowed Count' print. (Imre)
    Add counters in intel_dmc struct. (Imre)
    Have interface to return dc6 allowed count. (Imre)
    Rename dc6_count to dc6_allowed_count. (Rodrigo)
v5: Rename counters and move in to dc6_allowed structure. (Imre)
    Order declaration lines in decreasing line length. (Imre)
    Update start_tacking logic. (Imre)
    Move get couner inside lock and DISPLAY_VER code to helper. (Imre)
v6: Change intel_dmc_get_dc6_allowed_count return type to bool. (Imre)
    Update debugfs print to better allien with old print. (Imre)
    Remove braces at if/else for signle line statements. (Imre)

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/intel_display_power_well.c   | 11 ++++-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 49 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
 3 files changed, 59 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8ec87ffd87d2..574352439573 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -752,8 +752,9 @@ void gen9_sanitize_dc_state(struct intel_display *display)
 void gen9_set_dc_state(struct intel_display *display, u32 state)
 {
 	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 val;
+	bool dc6_was_enabled, enable_dc6;
 	u32 mask;
+	u32 val;
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
 			power_domains->dc_state, val & mask);
 
+	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
+	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
+	if (!dc6_was_enabled && enable_dc6)
+		intel_dmc_update_dc6_allowed_count(display, true);
+
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(display, val);
 
+	if (!enable_dc6 && dc6_was_enabled)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
 	power_domains->dc_state = val & mask;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa6944e55d95..e2f4d7ac0207 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_display_power_well.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
@@ -57,6 +58,10 @@ struct intel_dmc {
 	const char *fw_path;
 	u32 max_fw_size; /* bytes */
 	u32 version;
+	struct {
+		u32 dc5_start;
+		u32 count;
+	} dc6_allowed;
 	struct dmc_fw_info {
 		u32 mmio_count;
 		i915_reg_t mmioaddr[20];
@@ -1232,6 +1237,43 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
 			   DMC_VERSION_MINOR(snapshot->version));
 }
 
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
+					bool start_tracking)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+	u32 dc5_cur_count;
+
+	if (DISPLAY_VER(dmc->display) < 14)
+		return;
+
+	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
+
+	if (!start_tracking)
+		dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
+
+	dmc->dc6_allowed.dc5_start = dc5_cur_count;
+}
+
+static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+	struct intel_dmc *dmc = display_to_dmc(display);
+
+	if (DISPLAY_VER(display) < 14)
+		return false;
+
+	mutex_lock(&power_domains->lock);
+	bool dc6_enabled = DC_STATE_EN_UPTO_DC6 &
+			   intel_de_read(display, DC_STATE_EN);
+	if (dc6_enabled)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
+	*count = dmc->dc6_allowed.count;
+	mutex_unlock(&power_domains->lock);
+
+	return true;
+}
+
 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 {
 	struct intel_display *display = m->private;
@@ -1239,6 +1281,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	struct intel_dmc *dmc = display_to_dmc(display);
 	intel_wakeref_t wakeref;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+	u32 dc6_allowed_count;
 
 	if (!HAS_DMC(display))
 		return -ENODEV;
@@ -1287,7 +1330,11 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	}
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
-	if (i915_mmio_reg_valid(dc6_reg))
+
+	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
+		seq_printf(m, "DC5 -> DC6 allowed count: %d\n",
+			   dc6_allowed_count);
+	else if (i915_mmio_reg_valid(dc6_reg))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   intel_de_read(display, dc6_reg));
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 44cecef98e73..c78426eb4cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
 
 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
 
 void assert_dmc_loaded(struct intel_display *display);
 
-- 
2.43.0

[PATCH v7] drm/i915/dmc: Create debugfs entry for dc6 counter

[Mohammed Thasleem]

Starting from MTL we don't have a platform agnostic way to validate
DC6 state due to dc6 counter has been removed to validate DC state.

The goal is to validate that the display HW can reach the DC6 power
state. There is no HW DC6 residency counter (and there wasn't such
a counter earlier either), so an alternative way is required. According
to the HW team the display driver has programmed everything correctly in
order to allow the DC6 power state if the DC5 power state is reached
(indicated by the HW DC5 residency counter incrementing) and DC6 is
enabled by the driver.

Driver could take a snapshot of the DC5 residency counter right
after it enables DC6 (dc5_residency_start) and increment the SW
DC6 residency counter right before it disables DC6 or when user space
reads the DC6 counter. So the driver would update the counter at these
two points in the following way:
dc6_residency_counter += dc5_current_count - dc5_start_count

v2: Update the discription. (Imre)
    Read dc5 count during dc6 enable and disable then and update
    dc6 residency counter. (Imre)
    Remove variable from dmc structure. (Jani)
    Updated the subject title.
v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
    Use flags to check dc6 enable/disable states. (Imre)
    Move the display version check and counter read/update to
    a helper. (Imre)
    Resize the variable length. (Rodrigo)
    Use old dc6 debugfs entry for every platform. (Rodrigo)
v4: Remove superfluous whitespace. (Jani)
    Read DMC registers in intel_dmc.c (Jani)
    Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
    Rename update_dc6_count and move it to intel_dmc.c (Jani)
    Rename dc6_en_dis to start_tracking. (Imre)
    Have lock for dc6 state read aswelll. (Imre)
    Keep the existing way print 'DC5 -> DC6 count' along with
    new 'DC6 Allowed Count' print. (Imre)
    Add counters in intel_dmc struct. (Imre)
    Have interface to return dc6 allowed count. (Imre)
    Rename dc6_count to dc6_allowed_count. (Rodrigo)
v5: Rename counters and move in to dc6_allowed structure. (Imre)
    Order declaration lines in decreasing line length. (Imre)
    Update start_tacking logic. (Imre)
    Move get couner inside lock and DISPLAY_VER code to helper. (Imre)
v6: Change intel_dmc_get_dc6_allowed_count return type to bool. (Imre)
    Update debugfs print to better allien with old print. (Imre)
    Remove braces at if/else for signle line statements. (Imre)
v7: Remove in line variable declaration. (Imre)

Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
 .../i915/display/intel_display_power_well.c   | 11 +++-
 drivers/gpu/drm/i915/display/intel_dmc.c      | 50 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
 3 files changed, 60 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8ec87ffd87d2..574352439573 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -752,8 +752,9 @@ void gen9_sanitize_dc_state(struct intel_display *display)
 void gen9_set_dc_state(struct intel_display *display, u32 state)
 {
 	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 val;
+	bool dc6_was_enabled, enable_dc6;
 	u32 mask;
+	u32 val;
 
 	if (!HAS_DISPLAY(display))
 		return;
@@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
 			power_domains->dc_state, val & mask);
 
+	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
+	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
+	if (!dc6_was_enabled && enable_dc6)
+		intel_dmc_update_dc6_allowed_count(display, true);
+
 	val &= ~mask;
 	val |= state;
 
 	gen9_write_dc_state(display, val);
 
+	if (!enable_dc6 && dc6_was_enabled)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
 	power_domains->dc_state = val & mask;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index fa6944e55d95..f9fae88e46d2 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -28,6 +28,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "intel_de.h"
+#include "intel_display_power_well.h"
 #include "intel_dmc.h"
 #include "intel_dmc_regs.h"
 #include "intel_step.h"
@@ -57,6 +58,10 @@ struct intel_dmc {
 	const char *fw_path;
 	u32 max_fw_size; /* bytes */
 	u32 version;
+	struct {
+		u32 dc5_start;
+		u32 count;
+	} dc6_allowed;
 	struct dmc_fw_info {
 		u32 mmio_count;
 		i915_reg_t mmioaddr[20];
@@ -1232,6 +1237,44 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
 			   DMC_VERSION_MINOR(snapshot->version));
 }
 
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
+					bool start_tracking)
+{
+	struct intel_dmc *dmc = display_to_dmc(display);
+	u32 dc5_cur_count;
+
+	if (DISPLAY_VER(dmc->display) < 14)
+		return;
+
+	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
+
+	if (!start_tracking)
+		dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
+
+	dmc->dc6_allowed.dc5_start = dc5_cur_count;
+}
+
+static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+	struct intel_dmc *dmc = display_to_dmc(display);
+	bool dc6_enabled;
+
+	if (DISPLAY_VER(display) < 14)
+		return false;
+
+	mutex_lock(&power_domains->lock);
+	dc6_enabled = intel_de_read(display, DC_STATE_EN) &
+		      DC_STATE_EN_UPTO_DC6;
+	if (dc6_enabled)
+		intel_dmc_update_dc6_allowed_count(display, false);
+
+	*count = dmc->dc6_allowed.count;
+	mutex_unlock(&power_domains->lock);
+
+	return true;
+}
+
 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 {
 	struct intel_display *display = m->private;
@@ -1239,6 +1282,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	struct intel_dmc *dmc = display_to_dmc(display);
 	intel_wakeref_t wakeref;
 	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
+	u32 dc6_allowed_count;
 
 	if (!HAS_DMC(display))
 		return -ENODEV;
@@ -1287,7 +1331,11 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 	}
 
 	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
-	if (i915_mmio_reg_valid(dc6_reg))
+
+	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
+		seq_printf(m, "DC5 -> DC6 allowed count: %d\n",
+			   dc6_allowed_count);
+	else if (i915_mmio_reg_valid(dc6_reg))
 		seq_printf(m, "DC5 -> DC6 count: %d\n",
 			   intel_de_read(display, dc6_reg));
 
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
index 44cecef98e73..c78426eb4cd5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc.h
@@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
 
 struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
 void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
+void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
 
 void assert_dmc_loaded(struct intel_display *display);
 
-- 
2.43.0

✗ i915.CI.BAT: failure for drm/i915/dmc: Add debugfs for dc6 counter (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 8262 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev6)
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16274 -> Patchwork_144240v6
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v6 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v6, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v6:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@module-reload:
    - bat-dg2-11:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-dg2-11/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/bat-dg2-11/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy:
    - bat-apl-1:          [PASS][3] -> [DMESG-WARN][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/bat-apl-1/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-tgl-1115g4:      [PASS][5] -> [SKIP][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/fi-tgl-1115g4/igt@kms_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-tgl-1115g4/igt@kms_pm_rpm@basic-pci-d3-state.html

  * igt@kms_pm_rpm@basic-rte:
    - fi-tgl-1115g4:      [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/fi-tgl-1115g4/igt@kms_pm_rpm@basic-rte.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-tgl-1115g4/igt@kms_pm_rpm@basic-rte.html

  
Known issues
------------

  Here are the changes found in Patchwork_144240v6 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][9] ([i915#10462]) +1 other test dmesg-warn
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@core_auth@basic-auth.html

  * igt@dmabuf@all-tests@dma_fence_chain:
    - fi-bsw-nick:        [PASS][10] -> [INCOMPLETE][11] ([i915#12904]) +1 other test incomplete
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-bsw-nick/igt@dmabuf@all-tests@dma_fence_chain.html

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][12] ([i915#1849])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][13] ([i915#2190])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][14] ([i915#2190])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][16] ([i915#4613]) +3 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_pm_rpm@module-reload:
    - bat-dg1-7:          [PASS][17] -> [FAIL][18] ([i915#13901])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/bat-dg1-7/igt@i915_pm_rpm@module-reload.html
    - bat-rpls-4:         [PASS][19] -> [FAIL][20] ([i915#13901])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-rpls-4/igt@i915_pm_rpm@module-reload.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/bat-rpls-4/igt@i915_pm_rpm@module-reload.html

  * igt@kms_addfb_basic@too-high:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][21] ([i915#13903]) +2 other tests fail
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][22] +62 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][23] +10 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][24] ([i915#13905])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-FAIL][25] ([i915#13905])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][26] ([i915#13904])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/fi-kbl-8809g/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][27] -> [SKIP][28] ([i915#9197]) +3 other tests skip
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-9:         [DMESG-FAIL][29] ([i915#12061]) -> [PASS][30] +1 other test pass
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12904
  [i915#13901]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13901
  [i915#13903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13903
  [i915#13904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13904
  [i915#13905]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13905
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16274 -> Patchwork_144240v6

  CI-20190529: 20190529
  CI_DRM_16274: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v6: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v6/index.html

[-- Attachment #2: Type: text/html, Size: 9643 bytes --]

✗ i915.CI.BAT: failure for drm/i915/dmc: Add debugfs for dc6 counter (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7830 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev7)
URL   : https://patchwork.freedesktop.org/series/144240/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_16274 -> Patchwork_144240v7
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_144240v7 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_144240v7, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_144240v7:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_pm_rpm@module-reload:
    - bat-apl-1:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-apl-1/igt@i915_pm_rpm@module-reload.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-apl-1:          [PASS][3] -> [DMESG-WARN][4] +3 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-apl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  
Known issues
------------

  Here are the changes found in Patchwork_144240v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][5] ([i915#10462]) +1 other test dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@core_auth@basic-auth.html

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][6] ([i915#1849])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][7] ([i915#2190])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][8] ([i915#2190])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][9] ([i915#4613]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][10] ([i915#4613]) +3 other tests skip
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][11] -> [ABORT][12] ([i915#13571])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-6:         [PASS][13] -> [DMESG-FAIL][14] ([i915#12061]) +1 other test dmesg-fail
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-arls-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@too-high:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][15] ([i915#13903]) +2 other tests fail
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][16] +62 other tests skip
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][17] +10 other tests skip
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][18] ([i915#13905])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-FAIL][19] ([i915#13905])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][20] ([i915#13904])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][21] -> [SKIP][22] ([i915#9197]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-9:         [DMESG-FAIL][23] ([i915#12061]) -> [PASS][24] +1 other test pass
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [ABORT][25] ([i915#13679]) -> [ABORT][26] ([i915#13465] / [i915#13679]) +1 other test abort
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-atsm-1/igt@i915_selftest@live@mman.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13465
  [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
  [i915#13679]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13679
  [i915#13903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13903
  [i915#13904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13904
  [i915#13905]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13905
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16274 -> Patchwork_144240v7

  CI-20190529: 20190529
  CI_DRM_16274: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v7: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

[-- Attachment #2: Type: text/html, Size: 9246 bytes --]

Re: [PATCH v7] drm/i915/dmc: Create debugfs entry for dc6 counter

[Jani Nikula]

On Thu, 13 Mar 2025, Mohammed Thasleem <mohammed.thasleem@intel.com> wrote:
> Starting from MTL we don't have a platform agnostic way to validate
> DC6 state due to dc6 counter has been removed to validate DC state.

Can you please stop posting all patch revisions in-reply to the same
thread please. It's starting to get pretty confusing with seven versions
and all the patchwork replies.

BR,
Jani.

>
> The goal is to validate that the display HW can reach the DC6 power
> state. There is no HW DC6 residency counter (and there wasn't such
> a counter earlier either), so an alternative way is required. According
> to the HW team the display driver has programmed everything correctly in
> order to allow the DC6 power state if the DC5 power state is reached
> (indicated by the HW DC5 residency counter incrementing) and DC6 is
> enabled by the driver.
>
> Driver could take a snapshot of the DC5 residency counter right
> after it enables DC6 (dc5_residency_start) and increment the SW
> DC6 residency counter right before it disables DC6 or when user space
> reads the DC6 counter. So the driver would update the counter at these
> two points in the following way:
> dc6_residency_counter += dc5_current_count - dc5_start_count
>
> v2: Update the discription. (Imre)
>     Read dc5 count during dc6 enable and disable then and update
>     dc6 residency counter. (Imre)
>     Remove variable from dmc structure. (Jani)
>     Updated the subject title.
> v3: Add i915_power_domains lock to updated dc6 count in debugfs. (Imre)
>     Use flags to check dc6 enable/disable states. (Imre)
>     Move the display version check and counter read/update to
>     a helper. (Imre)
>     Resize the variable length. (Rodrigo)
>     Use old dc6 debugfs entry for every platform. (Rodrigo)
> v4: Remove superfluous whitespace. (Jani)
>     Read DMC registers in intel_dmc.c (Jani)
>     Rename dc6_en_dis to dc6_enabled and change its type to bool. (Jani)
>     Rename update_dc6_count and move it to intel_dmc.c (Jani)
>     Rename dc6_en_dis to start_tracking. (Imre)
>     Have lock for dc6 state read aswelll. (Imre)
>     Keep the existing way print 'DC5 -> DC6 count' along with
>     new 'DC6 Allowed Count' print. (Imre)
>     Add counters in intel_dmc struct. (Imre)
>     Have interface to return dc6 allowed count. (Imre)
>     Rename dc6_count to dc6_allowed_count. (Rodrigo)
> v5: Rename counters and move in to dc6_allowed structure. (Imre)
>     Order declaration lines in decreasing line length. (Imre)
>     Update start_tacking logic. (Imre)
>     Move get couner inside lock and DISPLAY_VER code to helper. (Imre)
> v6: Change intel_dmc_get_dc6_allowed_count return type to bool. (Imre)
>     Update debugfs print to better allien with old print. (Imre)
>     Remove braces at if/else for signle line statements. (Imre)
> v7: Remove in line variable declaration. (Imre)
>
> Signed-off-by: Mohammed Thasleem <mohammed.thasleem@intel.com>
> Reviewed-by: Imre Deak <imre.deak@intel.com>
> ---
>  .../i915/display/intel_display_power_well.c   | 11 +++-
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 50 ++++++++++++++++++-
>  drivers/gpu/drm/i915/display/intel_dmc.h      |  1 +
>  3 files changed, 60 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 8ec87ffd87d2..574352439573 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -752,8 +752,9 @@ void gen9_sanitize_dc_state(struct intel_display *display)
>  void gen9_set_dc_state(struct intel_display *display, u32 state)
>  {
>  	struct i915_power_domains *power_domains = &display->power.domains;
> -	u32 val;
> +	bool dc6_was_enabled, enable_dc6;
>  	u32 mask;
> +	u32 val;
>  
>  	if (!HAS_DISPLAY(display))
>  		return;
> @@ -772,11 +773,19 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
>  		drm_err(display->drm, "DC state mismatch (0x%x -> 0x%x)\n",
>  			power_domains->dc_state, val & mask);
>  
> +	enable_dc6 = state & DC_STATE_EN_UPTO_DC6;
> +	dc6_was_enabled = val & DC_STATE_EN_UPTO_DC6;
> +	if (!dc6_was_enabled && enable_dc6)
> +		intel_dmc_update_dc6_allowed_count(display, true);
> +
>  	val &= ~mask;
>  	val |= state;
>  
>  	gen9_write_dc_state(display, val);
>  
> +	if (!enable_dc6 && dc6_was_enabled)
> +		intel_dmc_update_dc6_allowed_count(display, false);
> +
>  	power_domains->dc_state = val & mask;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
> index fa6944e55d95..f9fae88e46d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -28,6 +28,7 @@
>  #include "i915_drv.h"
>  #include "i915_reg.h"
>  #include "intel_de.h"
> +#include "intel_display_power_well.h"
>  #include "intel_dmc.h"
>  #include "intel_dmc_regs.h"
>  #include "intel_step.h"
> @@ -57,6 +58,10 @@ struct intel_dmc {
>  	const char *fw_path;
>  	u32 max_fw_size; /* bytes */
>  	u32 version;
> +	struct {
> +		u32 dc5_start;
> +		u32 count;
> +	} dc6_allowed;
>  	struct dmc_fw_info {
>  		u32 mmio_count;
>  		i915_reg_t mmioaddr[20];
> @@ -1232,6 +1237,44 @@ void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct
>  			   DMC_VERSION_MINOR(snapshot->version));
>  }
>  
> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display,
> +					bool start_tracking)
> +{
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +	u32 dc5_cur_count;
> +
> +	if (DISPLAY_VER(dmc->display) < 14)
> +		return;
> +
> +	dc5_cur_count = intel_de_read(dmc->display, DG1_DMC_DEBUG_DC5_COUNT);
> +
> +	if (!start_tracking)
> +		dmc->dc6_allowed.count += dc5_cur_count - dmc->dc6_allowed.dc5_start;
> +
> +	dmc->dc6_allowed.dc5_start = dc5_cur_count;
> +}
> +
> +static bool intel_dmc_get_dc6_allowed_count(struct intel_display *display, u32 *count)
> +{
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +	struct intel_dmc *dmc = display_to_dmc(display);
> +	bool dc6_enabled;
> +
> +	if (DISPLAY_VER(display) < 14)
> +		return false;
> +
> +	mutex_lock(&power_domains->lock);
> +	dc6_enabled = intel_de_read(display, DC_STATE_EN) &
> +		      DC_STATE_EN_UPTO_DC6;
> +	if (dc6_enabled)
> +		intel_dmc_update_dc6_allowed_count(display, false);
> +
> +	*count = dmc->dc6_allowed.count;
> +	mutex_unlock(&power_domains->lock);
> +
> +	return true;
> +}
> +
>  static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  {
>  	struct intel_display *display = m->private;
> @@ -1239,6 +1282,7 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	struct intel_dmc *dmc = display_to_dmc(display);
>  	intel_wakeref_t wakeref;
>  	i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG;
> +	u32 dc6_allowed_count;
>  
>  	if (!HAS_DMC(display))
>  		return -ENODEV;
> @@ -1287,7 +1331,11 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
>  	}
>  
>  	seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(display, dc5_reg));
> -	if (i915_mmio_reg_valid(dc6_reg))
> +
> +	if (intel_dmc_get_dc6_allowed_count(display, &dc6_allowed_count))
> +		seq_printf(m, "DC5 -> DC6 allowed count: %d\n",
> +			   dc6_allowed_count);
> +	else if (i915_mmio_reg_valid(dc6_reg))
>  		seq_printf(m, "DC5 -> DC6 count: %d\n",
>  			   intel_de_read(display, dc6_reg));
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h
> index 44cecef98e73..c78426eb4cd5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.h
> @@ -26,6 +26,7 @@ void intel_dmc_debugfs_register(struct intel_display *display);
>  
>  struct intel_dmc_snapshot *intel_dmc_snapshot_capture(struct intel_display *display);
>  void intel_dmc_snapshot_print(const struct intel_dmc_snapshot *snapshot, struct drm_printer *p);
> +void intel_dmc_update_dc6_allowed_count(struct intel_display *display, bool start_tracking);
>  
>  void assert_dmc_loaded(struct intel_display *display);

-- 
Jani Nikula, Intel

✓ i915.CI.BAT: success for drm/i915/dmc: Add debugfs for dc6 counter (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 7453 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev7)
URL   : https://patchwork.freedesktop.org/series/144240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16274 -> Patchwork_144240v7
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_144240v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][1] ([i915#10462]) +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@core_auth@basic-auth.html

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][2] ([i915#1849])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][7] -> [ABORT][8] ([i915#13571])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
    - bat-apl-1:          [PASS][9] -> [FAIL][10] ([i915#13901])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-apl-1/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-6:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-arls-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@too-high:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][13] ([i915#13903]) +2 other tests fail
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][14] +62 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][15] +10 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][16] ([i915#13905])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-FAIL][17] ([i915#13905])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][18] ([i915#13904])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-apl-1:          [PASS][19] -> [DMESG-WARN][20] ([i915#13770]) +3 other tests dmesg-warn
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-apl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][21] -> [SKIP][22] ([i915#9197]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-9:         [DMESG-FAIL][23] ([i915#12061]) -> [PASS][24] +1 other test pass
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [ABORT][25] ([i915#13679]) -> [ABORT][26] ([i915#13465] / [i915#13679]) +1 other test abort
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-atsm-1/igt@i915_selftest@live@mman.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13465
  [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
  [i915#13679]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13679
  [i915#13770]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13770
  [i915#13901]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13901
  [i915#13903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13903
  [i915#13904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13904
  [i915#13905]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13905
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16274 -> Patchwork_144240v7

  CI-20190529: 20190529
  CI_DRM_16274: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v7: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

[-- Attachment #2: Type: text/html, Size: 8819 bytes --]

✓ i915.CI.BAT: success for drm/i915/dmc: Add debugfs for dc6 counter (rev7)

[Patchwork]

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== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev7)
URL   : https://patchwork.freedesktop.org/series/144240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16274 -> Patchwork_144240v7
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

Participating hosts (44 -> 43)
------------------------------

  Missing    (1): fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_144240v7 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][1] ([i915#10462]) +1 other test dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@core_auth@basic-auth.html

  * igt@fbdev@info:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][2] ([i915#1849])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@fbdev@info.html

  * igt@gem_huc_copy@huc-copy:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][3] ([i915#2190])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@gem_huc_copy@huc-copy.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][4] ([i915#2190])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@parallel-random-engines:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][5] ([i915#4613]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@gem_lmem_swapping@parallel-random-engines.html

  * igt@gem_lmem_swapping@random-engines:
    - fi-skl-6600u:       NOTRUN -> [SKIP][6] ([i915#4613]) +3 other tests skip
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@gem_lmem_swapping@random-engines.html

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-guc:         [PASS][7] -> [ABORT][8] ([i915#13571])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
    - bat-apl-1:          [PASS][9] -> [FAIL][10] ([i915#13901])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-apl-1/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-6:         [PASS][11] -> [DMESG-FAIL][12] ([i915#12061]) +1 other test dmesg-fail
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-arls-6/igt@i915_selftest@live@workarounds.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-arls-6/igt@i915_selftest@live@workarounds.html

  * igt@kms_addfb_basic@too-high:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][13] ([i915#13903]) +2 other tests fail
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_addfb_basic@too-high.html

  * igt@kms_dsc@dsc-basic:
    - fi-kbl-8809g:       NOTRUN -> [SKIP][14] +62 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_dsc@dsc-basic.html
    - fi-skl-6600u:       NOTRUN -> [SKIP][15] +10 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-skl-6600u/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-connector-state:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-WARN][16] ([i915#13905])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_force_connector_basic@force-connector-state.html

  * igt@kms_force_connector_basic@force-edid:
    - fi-kbl-8809g:       NOTRUN -> [DMESG-FAIL][17] ([i915#13905])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_force_connector_basic@force-edid.html

  * igt@kms_hdmi_inject@inject-audio:
    - fi-kbl-8809g:       NOTRUN -> [FAIL][18] ([i915#13904])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/fi-kbl-8809g/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24:
    - bat-apl-1:          [PASS][19] -> [DMESG-WARN][20] ([i915#13770]) +3 other tests dmesg-warn
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-apl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-apl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-xr24.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence:
    - bat-dg2-11:         [PASS][21] -> [SKIP][22] ([i915#9197]) +2 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-dg2-11/igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-mtlp-9:         [DMESG-FAIL][23] ([i915#12061]) -> [PASS][24] +1 other test pass
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [ABORT][25] ([i915#13679]) -> [ABORT][26] ([i915#13465] / [i915#13679]) +1 other test abort
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_16274/bat-atsm-1/igt@i915_selftest@live@mman.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#10462]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10462
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13465
  [i915#13571]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13571
  [i915#13679]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13679
  [i915#13770]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13770
  [i915#13901]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13901
  [i915#13903]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13903
  [i915#13904]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13904
  [i915#13905]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13905
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#9197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9197


Build changes
-------------

  * Linux: CI_DRM_16274 -> Patchwork_144240v7

  CI-20190529: 20190529
  CI_DRM_16274: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v7: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

[-- Attachment #2: Type: text/html, Size: 8819 bytes --]

✓ i915.CI.Full: success for drm/i915/dmc: Add debugfs for dc6 counter (rev7)

[Patchwork]

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== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev7)
URL   : https://patchwork.freedesktop.org/series/144240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16274_full -> Patchwork_144240v7_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_16274 -> Patchwork_144240v7

  CI_DRM_16274: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v7: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

[-- Attachment #2: Type: text/html, Size: 1554 bytes --]

✓ i915.CI.Full: success for drm/i915/dmc: Add debugfs for dc6 counter (rev7)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 997 bytes --]

== Series Details ==

Series: drm/i915/dmc: Add debugfs for dc6 counter (rev7)
URL   : https://patchwork.freedesktop.org/series/144240/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_16274_full -> Patchwork_144240v7_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (12 -> 12)
------------------------------

  No changes in participating hosts


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_16274 -> Patchwork_144240v7

  CI_DRM_16274: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8271: 8271
  Patchwork_144240v7: e2e6ad67ea058d5b08490a2b3dab2152fcfcc24e @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_144240v7/index.html

[-- Attachment #2: Type: text/html, Size: 1554 bytes --]