* [PATCH 00/13] drm/i915: Plane register cleanups
@ 2024-05-16 13:56 Ville Syrjala
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
` (23 more replies)
0 siblings, 24 replies; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Bunch of cleanup mostly around plane registers.
Ville Syrjälä (13):
drm/i915: Add skl+ plane name aliases to enum plane_id
drm/i915: Clean up the cursor register defines
drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
drm/i915: Simplify PIPESRC_ERLY_TPT definition
drm/i915: Rename selective fetch plane registers
drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
drm/i915: Add separate defines for cursor WM/DDB register bits
drm/i915: Move PIPEGCMAX to intel_color_regs.h
drm/i915: Extract i9xx_plane_regs.h
drm/i915: Polish pre-skl primary plane registers
drm/i915: Document a few pre-skl primary plane platform dependencies
drm/i915: Polish sprite plane register definitions
drm/i915: Document which platforms use which sprite registers
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 +
.../gpu/drm/i915/display/i9xx_plane_regs.h | 110 ++++++++
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
.../gpu/drm/i915/display/intel_color_regs.h | 5 +
drivers/gpu/drm/i915/display/intel_crtc.c | 6 +-
drivers/gpu/drm/i915/display/intel_cursor.c | 42 ++-
.../gpu/drm/i915/display/intel_cursor_regs.h | 66 +++--
drivers/gpu/drm/i915/display/intel_display.c | 9 +-
.../drm/i915/display/intel_display_limits.h | 21 +-
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 49 +---
.../gpu/drm/i915/display/intel_sprite_regs.h | 242 ++++++++++--------
.../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +-
.../drm/i915/display/skl_universal_plane.c | 35 ++-
.../drm/i915/display/skl_universal_plane.h | 3 -
.../i915/display/skl_universal_plane_regs.h | 68 +++++
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 91 +------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
25 files changed, 449 insertions(+), 313 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h
--
2.44.1
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-17 15:33 ` Jani Nikula
2024-05-17 17:12 ` [PATCH v2 " Ville Syrjala
2024-05-16 13:56 ` [PATCH 02/13] drm/i915: Clean up the cursor register defines Ville Syrjala
` (22 subsequent siblings)
23 siblings, 2 replies; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++----
drivers/gpu/drm/i915/display/intel_display.c | 8 +++----
.../drm/i915/display/intel_display_limits.h | 21 ++++++++++++-------
.../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +-
.../drm/i915/display/skl_universal_plane.c | 19 ++++++++---------
5 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 339010384b86..ca6dc1dc56c8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
if (DISPLAY_VER(dev_priv) >= 9)
- primary = skl_universal_plane_create(dev_priv, pipe,
- PLANE_PRIMARY);
+ primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
else
primary = intel_primary_plane_create(dev_priv, pipe);
if (IS_ERR(primary)) {
@@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
struct intel_plane *plane;
if (DISPLAY_VER(dev_priv) >= 9)
- plane = skl_universal_plane_create(dev_priv, pipe,
- PLANE_SPRITE0 + sprite);
+ plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite);
else
plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
if (IS_ERR(plane)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cce1420fb541..ee2df655b0ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
linked_state->uapi.dst = plane_state->uapi.dst;
if (icl_is_hdr_plane(dev_priv, plane->id)) {
- if (linked->id == PLANE_SPRITE5)
+ if (linked->id == PLANE_7)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
- else if (linked->id == PLANE_SPRITE4)
+ else if (linked->id == PLANE_6)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
- else if (linked->id == PLANE_SPRITE3)
+ else if (linked->id == PLANE_5)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
- else if (linked->id == PLANE_SPRITE2)
+ else if (linked->id == PLANE_4)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 5126d0b5ae5d..c4775c99dc83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -60,16 +60,23 @@ enum transcoder {
* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
*/
enum plane_id {
- PLANE_PRIMARY,
- PLANE_SPRITE0,
- PLANE_SPRITE1,
- PLANE_SPRITE2,
- PLANE_SPRITE3,
- PLANE_SPRITE4,
- PLANE_SPRITE5,
+ /* skl+ universal plane names */
+ PLANE_1,
+ PLANE_2,
+ PLANE_3,
+ PLANE_4,
+ PLANE_5,
+ PLANE_6,
+ PLANE_7,
+
PLANE_CURSOR,
I915_MAX_PLANES,
+
+ /* pre-skl plane names */
+ PLANE_PRIMARY = PLANE_1,
+ PLANE_SPRITE0,
+ PLANE_SPRITE1,
};
enum port {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
index a76b48ebc2d3..4853c4806004 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
@@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
* pipe simultaneously.
*/
if (DISPLAY_VER(dev_priv) >= 9 &&
- to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
+ to_intel_plane(plane)->id >= PLANE_3 &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 32d10e62b2b9..d0bfee2ca643 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
- return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
+ return BIT(PLANE_6) | BIT(PLANE_7);
else
- return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+ return BIT(PLANE_4) | BIT(PLANE_5);
}
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
@@ -252,7 +252,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
u8 icl_hdr_plane_mask(void)
{
- return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
+ return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3);
}
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
@@ -2099,7 +2099,7 @@ static bool skl_plane_has_fbc(struct drm_i915_private *i915,
if (DISPLAY_VER(i915) >= 20)
return icl_is_hdr_plane(i915, plane_id);
else
- return plane_id == PLANE_PRIMARY;
+ return plane_id == PLANE_1;
}
static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
@@ -2123,7 +2123,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
return false;
- if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
+ if (plane_id != PLANE_1 && plane_id != PLANE_2)
return false;
return true;
@@ -2331,8 +2331,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
return pipe != PIPE_C;
return pipe != PIPE_C &&
- (plane_id == PLANE_PRIMARY ||
- plane_id == PLANE_SPRITE0);
+ (plane_id == PLANE_1 || plane_id == PLANE_2);
}
static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
@@ -2350,7 +2349,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
- return plane_id < PLANE_SPRITE4;
+ return plane_id < PLANE_6;
}
static u8 skl_get_plane_caps(struct drm_i915_private *i915,
@@ -2439,7 +2438,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
- if (plane_id == PLANE_PRIMARY) {
+ if (plane_id == PLANE_1) {
plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10);
plane->async_flip = skl_plane_async_flip;
plane->enable_flip_done = skl_plane_enable_flip_done;
@@ -2461,7 +2460,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
else
plane_funcs = &skl_plane_funcs;
- if (plane_id == PLANE_PRIMARY)
+ if (plane_id == PLANE_1)
plane_type = DRM_PLANE_TYPE_PRIMARY;
else
plane_type = DRM_PLANE_TYPE_OVERLAY;
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 02/13] drm/i915: Clean up the cursor register defines
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 9:10 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Ville Syrjala
` (21 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Group the cursor register defines such that everything to
do with one register is in one place.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_cursor_regs.h | 52 +++++++++----------
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index c2190af1e9f5..270c26c2e6df 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -9,6 +9,7 @@
#include "intel_display_reg_defs.h"
#define _CURACNTR 0x70080
+#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR)
/* Old style CUR*CNTR flags (desktop 8xx) */
#define CURSOR_ENABLE REG_BIT(31)
#define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
@@ -38,61 +39,60 @@
#define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
#define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
#define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
+
#define _CURABASE 0x70084
+#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE)
+
#define _CURAPOS 0x70088
-#define _CURAPOS_ERLY_TPT 0x7008c
+#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS)
#define CURSOR_POS_Y_SIGN REG_BIT(31)
#define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
#define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
#define CURSOR_POS_X_SIGN REG_BIT(15)
#define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
#define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
+
+#define _CURAPOS_ERLY_TPT 0x7008c
+#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT)
+
#define _CURASIZE 0x700a0 /* 845/865 */
+#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE)
#define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
#define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
#define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
#define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
+
#define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
+#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A)
#define CUR_FBC_EN REG_BIT(31)
#define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
#define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
+
#define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
+#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A)
+
#define _CURASURFLIVE 0x700ac /* g4x+ */
-#define _CURBCNTR 0x700c0
-#define _CURBBASE 0x700c4
-#define _CURBPOS 0x700c8
-
-#define _CURBCNTR_IVB 0x71080
-#define _CURBBASE_IVB 0x71084
-#define _CURBPOS_IVB 0x71088
-
-#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
-#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
-#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
-#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
-#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
-#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
-#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
-#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
+#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE)
/* skl+ */
#define _CUR_WM_A_0 0x70140
#define _CUR_WM_B_0 0x71140
+#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
+
#define _CUR_WM_SAGV_A 0x70158
#define _CUR_WM_SAGV_B 0x71158
+#define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
+
#define _CUR_WM_SAGV_TRANS_A 0x7015C
#define _CUR_WM_SAGV_TRANS_B 0x7115C
+#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
+
#define _CUR_WM_TRANS_A 0x70168
#define _CUR_WM_TRANS_B 0x71168
-#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
-#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
-#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
-#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
-#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
+#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
-/* skl+ */
-#define _CUR_BUF_CFG_A 0x7017c
-#define _CUR_BUF_CFG_B 0x7117c
-#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+#define _CUR_BUF_CFG_A 0x7017c
+#define _CUR_BUF_CFG_B 0x7117c
+#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
#endif /* __INTEL_CURSOR_REGS_H__ */
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
2024-05-16 13:56 ` [PATCH 02/13] drm/i915: Clean up the cursor register defines Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 9:27 ` Jani Nikula
2024-05-20 17:14 ` [PATCH v2 " Ville Syrjala
2024-05-16 13:56 ` [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition Ville Syrjala
` (20 subsequent siblings)
23 siblings, 2 replies; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +++++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index c780ce146131..b44809899502 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
}
static void wa_16021440873(struct intel_plane *plane,
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
PIPESRC_HEIGHT(et_y_position));
@@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
val);
}
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
plane_state->ctl);
} else {
/* Wa_16021440873 */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 270c26c2e6df..ab02d497fba6 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -95,4 +95,9 @@
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
+#define _SEL_FETCH_CUR_CTL_B 0x71880
+#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
+#define SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
+
#endif /* __INTEL_CURSOR_REGS_H__ */
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (2 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 9:35 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 05/13] drm/i915: Rename selective fetch plane registers Ville Syrjala
` (19 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
so using _MMIO_TRANS2() for it is not really correct. Also since this
is a pipe register, and not present on CHV, the registers will be
equally spaced out, so we can use the simpler _MMIO_PIPE() instead
of _MMIO_PIPE2().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index b44809899502..7983cbaf83f7 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane,
intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
- intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
+ intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
PIPESRC_HEIGHT(et_y_position));
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index df0d14a5023f..d49e869f6be2 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2381,7 +2381,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
if (!crtc_state->enable_psr2_su_region_et)
return;
- intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
+ intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
crtc_state->pipe_srcsz_early_tpt);
}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index e14cb48f2614..47e3a2e2977c 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -248,8 +248,8 @@
/* PSR2 Early transport */
#define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
-
-#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
+#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
+#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 05/13] drm/i915: Rename selective fetch plane registers
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (3 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 9:39 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() Ville Syrjala
` (18 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename the selective fetch plane registers to match the spec.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +++++-----
drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++++++------
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 47e3a2e2977c..f0bd0a726d7a 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -276,23 +276,23 @@
_SEL_FETCH_PLANE_BASE_A(plane))
#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
-#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
+#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_CTL_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
-#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
+#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
#define _SEL_FETCH_PLANE_POS_1_A 0x70894
-#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
+#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_POS_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
-#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
+#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_SIZE_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
-#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
+#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
_SEL_FETCH_PLANE_OFFSET_1_A - \
_SEL_FETCH_PLANE_BASE_1_A)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index d0bfee2ca643..6601baf18ae4 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+ intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
}
static void
@@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
val |= plane_state->uapi.dst.x1;
- intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
+ intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
x = plane_state->view.color_plane[color_plane].x;
@@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
val = y << 16 | x;
- intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
+ intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id),
val);
/* Sizes are 0 based */
val = (drm_rect_height(clip) - 1) << 16;
val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
- intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
+ intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
}
static void
@@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane,
return;
if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
- intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
- PLANE_SEL_FETCH_CTL_ENABLE);
+ intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id),
+ SEL_FETCH_PLANE_CTL_ENABLE);
else
icl_plane_disable_sel_fetch_arm(plane, crtc_state);
}
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (4 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 05/13] drm/i915: Rename selective fetch plane registers Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-23 9:15 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits Ville Syrjala
` (17 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
for the SEL_FETCH_PLANE registers. A bit more tedious to have
to define 8 raw register offsets for everything, but perhaps
a bit easier to understand since we use a standard mechanism
now instead of hand rolling the arithmetic.
Also bloat-o-meter says:
add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326)
Function old new delta
icl_plane_update_arm 510 446 -64
icl_plane_disable_sel_fetch_arm.isra 158 54 -104
icl_plane_update_noarm 1898 1740 -158
Total: Before=2574502, After=2574176, chg -0.01%
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 ------------
.../i915/display/skl_universal_plane_regs.h | 68 +++++++++++++++++++
2 files changed, 68 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index f0bd0a726d7a..289c371c98d1 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -251,51 +251,6 @@
#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
-#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
-#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
-#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
-#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
-#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
-#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
-#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
-#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
-#define _SEL_FETCH_PLANE_BASE_1_B 0x71890
-
-#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
- _SEL_FETCH_PLANE_BASE_1_A, \
- _SEL_FETCH_PLANE_BASE_2_A, \
- _SEL_FETCH_PLANE_BASE_3_A, \
- _SEL_FETCH_PLANE_BASE_4_A, \
- _SEL_FETCH_PLANE_BASE_5_A, \
- _SEL_FETCH_PLANE_BASE_6_A, \
- _SEL_FETCH_PLANE_BASE_7_A, \
- _SEL_FETCH_PLANE_BASE_CUR_A)
-#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
-#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
- _SEL_FETCH_PLANE_BASE_1_A + \
- _SEL_FETCH_PLANE_BASE_A(plane))
-
-#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
-#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_CTL_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
-
-#define _SEL_FETCH_PLANE_POS_1_A 0x70894
-#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_POS_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-
-#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
-#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_SIZE_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-
-#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
-#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
- _SEL_FETCH_PLANE_OFFSET_1_A - \
- _SEL_FETCH_PLANE_BASE_1_A)
-
#define _ALPM_CTL_A 0x60950
#define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
#define ALPM_CTL_ALPM_ENABLE REG_BIT(31)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
index cb3bdd71b6b2..a6528e0d719e 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
@@ -17,6 +17,17 @@
#define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
_MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
+ _PICK_EVEN_2RANGES((plane), PLANE_5, \
+ _PIPE((pipe), (reg_1_a), (reg_1_b)), \
+ _PIPE((pipe), (reg_2_a), (reg_2_b)), \
+ _PIPE((pipe), (reg_5_a), (reg_5_b)), \
+ _PIPE((pipe), (reg_6_a), (reg_6_b)))
+#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
+ _MMIO(_SEL_FETCH((pipe), (plane), \
+ (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b), \
+ (reg_5_a), (reg_5_b), (reg_6_a), (reg_6_b)))
+
#define _PLANE_CTL_1_A 0x70180
#define _PLANE_CTL_2_A 0x70280
#define _PLANE_CTL_1_B 0x71180
@@ -367,4 +378,61 @@
#define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
#define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
+#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 /* mtl+ */
+#define _SEL_FETCH_PLANE_CTL_2_A 0x708b0
+#define _SEL_FETCH_PLANE_CTL_5_A 0x70920
+#define _SEL_FETCH_PLANE_CTL_6_A 0x70940
+#define _SEL_FETCH_PLANE_CTL_1_B 0x71890
+#define _SEL_FETCH_PLANE_CTL_2_B 0x718b0
+#define _SEL_FETCH_PLANE_CTL_5_B 0x71920
+#define _SEL_FETCH_PLANE_CTL_6_B 0x71940
+#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
+ _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \
+ _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \
+ _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \
+ _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B)
+#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
+
+#define _SEL_FETCH_PLANE_POS_1_A 0x70894 /* mtl+ */
+#define _SEL_FETCH_PLANE_POS_2_A 0x708b4
+#define _SEL_FETCH_PLANE_POS_5_A 0x70924
+#define _SEL_FETCH_PLANE_POS_6_A 0x70944
+#define _SEL_FETCH_PLANE_POS_1_B 0x71894
+#define _SEL_FETCH_PLANE_POS_2_B 0x718b4
+#define _SEL_FETCH_PLANE_POS_5_B 0x71924
+#define _SEL_FETCH_PLANE_POS_6_B 0x71944
+#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
+
+#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 /* mtl+ */
+#define _SEL_FETCH_PLANE_SIZE_2_A 0x708b8
+#define _SEL_FETCH_PLANE_SIZE_5_A 0x70928
+#define _SEL_FETCH_PLANE_SIZE_6_A 0x70948
+#define _SEL_FETCH_PLANE_SIZE_1_B 0x71898
+#define _SEL_FETCH_PLANE_SIZE_2_B 0x718b8
+#define _SEL_FETCH_PLANE_SIZE_5_B 0x71928
+#define _SEL_FETCH_PLANE_SIZE_6_B 0x71948
+#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
+
+#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c /* mtl+ */
+#define _SEL_FETCH_PLANE_OFFSET_2_A 0x708bc
+#define _SEL_FETCH_PLANE_OFFSET_5_A 0x7092c
+#define _SEL_FETCH_PLANE_OFFSET_6_A 0x7094c
+#define _SEL_FETCH_PLANE_OFFSET_1_B 0x7189c
+#define _SEL_FETCH_PLANE_OFFSET_2_B 0x718bc
+#define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c
+#define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c
+#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
+
#endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (5 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:24 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h Ville Syrjala
` (16 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make a more thorough split between universal planes vs. cursors
by defining the contents of the cursor WM/DDB registers separately.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++++++++++++++----
.../gpu/drm/i915/display/intel_cursor_regs.h | 9 +++++
.../drm/i915/display/skl_universal_plane.c | 4 +--
.../drm/i915/display/skl_universal_plane.h | 3 --
4 files changed, 39 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 7983cbaf83f7..cea0cfed569d 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -24,7 +24,6 @@
#include "intel_psr.h"
#include "intel_psr_regs.h"
#include "intel_vblank.h"
-#include "skl_universal_plane.h"
#include "skl_watermark.h"
#include "gem/i915_gem_object.h"
@@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
}
}
+static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
+{
+ if (!entry->end)
+ return 0;
+
+ return CUR_BUF_END(entry->end - 1) |
+ CUR_BUF_START(entry->start);
+}
+
+static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
+{
+ u32 val = 0;
+
+ if (level->enable)
+ val |= CUR_WM_EN;
+ if (level->ignore_lines)
+ val |= CUR_WM_IGNORE_LINES;
+ val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
+ val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
+
+ return val;
+}
+
static void skl_write_cursor_wm(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state)
{
@@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane,
for (level = 0; level < i915->display.wm.num_levels; level++)
intel_de_write_fw(i915, CUR_WM(pipe, level),
- skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
+ skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
- skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
+ skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
if (HAS_HW_SAGV_WM(i915)) {
const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
- skl_plane_wm_reg_val(&wm->sagv.wm0));
+ skl_cursor_wm_reg_val(&wm->sagv.wm0));
intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
- skl_plane_wm_reg_val(&wm->sagv.trans_wm));
+ skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
}
intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
- skl_plane_ddb_reg_val(ddb));
+ skl_cursor_ddb_reg_val(ddb));
}
/* TODO: split into noarm+arm pair */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index ab02d497fba6..307a850d54b6 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -78,6 +78,10 @@
#define _CUR_WM_A_0 0x70140
#define _CUR_WM_B_0 0x71140
#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
+#define CUR_WM_EN REG_BIT(31)
+#define CUR_WM_IGNORE_LINES REG_BIT(30)
+#define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
+#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
#define _CUR_WM_SAGV_A 0x70158
#define _CUR_WM_SAGV_B 0x71158
@@ -94,6 +98,11 @@
#define _CUR_BUF_CFG_A 0x7017c
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
+#define CUR_BUF_END_MASK REG_GENMASK(27, 16)
+#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))
+#define CUR_BUF_START_MASK REG_GENMASK(11, 0)
+#define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, (start))
#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
#define _SEL_FETCH_CUR_CTL_B 0x71880
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 6601baf18ae4..de51652358c9 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -622,7 +622,7 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
return stride / skl_plane_stride_mult(fb, color_plane, rotation);
}
-u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
+static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
{
if (!entry->end)
return 0;
@@ -631,7 +631,7 @@ u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
PLANE_BUF_START(entry->start);
}
-u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
+static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
{
u32 val = 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
index 8eb4521ee851..541489479135 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
@@ -37,7 +37,4 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
u8 icl_hdr_plane_mask(void);
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
-u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
-u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
-
#endif
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (6 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:07 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h Ville Syrjala
` (15 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
PIPEGCMAX was left behind when all other gamma registers moved
into intel_color_regs.h.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_color_regs.h | 5 +++++
drivers/gpu/drm/i915/i915_reg.h | 4 ----
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index bb99ea533842..61c18b4a7fa5 100644
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -36,6 +36,11 @@
_CHV_PALETTE_C, _CHV_PALETTE_C) + \
(i) * 4)
+/* i965/g4x/vlv/chv */
+#define _PIPEAGCMAX 0x70010
+#define _PIPEBGCMAX 0x71010
+#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */
+
/* ilk+ palette */
#define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 52b029cd3981..f5e8833cc37e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1882,10 +1882,6 @@
#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
#define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
-#define _PIPEAGCMAX 0x70010
-#define _PIPEBGCMAX 0x71010
-#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */
-
#define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
#define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (7 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:09 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers Ville Syrjala
` (14 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Relocate all pre-skl primary plane register definitions
into their own declutter i915_reg.h.
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Cc: Zhi Wang <zhi.wang.linux@gmail.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/i9xx_plane.c | 1 +
.../gpu/drm/i915/display/i9xx_plane_regs.h | 98 +++++++++++++++++++
.../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
drivers/gpu/drm/i915/display/intel_color.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 1 +
drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
drivers/gpu/drm/i915/gvt/display.c | 1 +
drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
drivers/gpu/drm/i915/gvt/handlers.c | 1 +
drivers/gpu/drm/i915/i915_reg.h | 87 +---------------
drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
13 files changed, 110 insertions(+), 87 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
index ea4d8ba55ad8..1f05f9184cb2 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane.c
+++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
@@ -10,6 +10,7 @@
#include "i915_reg.h"
#include "i9xx_plane.h"
+#include "i9xx_plane_regs.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
new file mode 100644
index 000000000000..0bf2cd42bce7
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2024 Intel Corporation
+ */
+
+#ifndef __I9XX_PLANE_REGS_H__
+#define __I9XX_PLANE_REGS_H__
+
+#include "intel_display_reg_defs.h"
+
+#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
+#define _DSPACNTR 0x70180
+#define DISP_ENABLE REG_BIT(31)
+#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
+#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
+#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
+#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
+#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
+#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
+#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
+#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
+#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
+#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
+#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
+#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
+#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
+#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
+#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
+#define DISP_STEREO_ENABLE REG_BIT(25)
+#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
+#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
+#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
+#define DISP_SRC_KEY_ENABLE REG_BIT(22)
+#define DISP_LINE_DOUBLE REG_BIT(20)
+#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
+#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
+#define DISP_ROTATE_180 REG_BIT(15)
+#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
+#define DISP_TILED REG_BIT(10)
+#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
+#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
+#define _DSPAADDR 0x70184
+#define _DSPASTRIDE 0x70188
+#define _DSPAPOS 0x7018C /* reserved */
+#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
+#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
+#define DISP_POS_X_MASK REG_GENMASK(15, 0)
+#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
+#define _DSPASIZE 0x70190
+#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
+#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
+#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
+#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
+#define _DSPASURF 0x7019C /* 965+ only */
+#define DISP_ADDR_MASK REG_GENMASK(31, 12)
+#define _DSPATILEOFF 0x701A4 /* 965+ only */
+#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
+#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
+#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
+#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
+#define _DSPAOFFSET 0x701A4 /* HSW */
+#define _DSPASURFLIVE 0x701AC
+#define _DSPAGAMC 0x701E0
+
+#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
+#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
+#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
+#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
+#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
+#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
+#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
+#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
+#define DSPLINOFF(plane) DSPADDR(plane)
+#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
+#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
+
+/* CHV pipe B primary plane */
+#define _PRIMPOS_A 0x60a08
+#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
+#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
+#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
+#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
+#define _PRIMSIZE_A 0x60a0c
+#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
+#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
+#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
+#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
+#define _PRIMCNSTALPHA_A 0x60a10
+#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
+#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
+#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
+
+#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
+#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
+#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
+
+#endif /* __I9XX_PLANE_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 27224ecdc94c..a2a827070c33 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -40,6 +40,7 @@
#include "i915_config.h"
#include "i915_reg.h"
+#include "i9xx_plane_regs.h"
#include "intel_atomic_plane.h"
#include "intel_cdclk.h"
#include "intel_display_rps.h"
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index d23163dc64d4..82b155708422 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -22,7 +22,7 @@
*
*/
-#include "i915_reg.h"
+#include "i9xx_plane_regs.h"
#include "intel_color.h"
#include "intel_color_regs.h"
#include "intel_de.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ee2df655b0ab..1e8e2fd52cf6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -54,6 +54,7 @@
#include "i915_reg.h"
#include "i915_utils.h"
#include "i9xx_plane.h"
+#include "i9xx_plane_regs.h"
#include "i9xx_wm.h"
#include "intel_atomic.h"
#include "intel_atomic_plane.h"
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index 50dd8eb9012e..680d7fc39503 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -48,6 +48,7 @@
#include "i915_utils.h"
#include "i915_vgpu.h"
#include "i915_vma.h"
+#include "i9xx_plane_regs.h"
#include "intel_cdclk.h"
#include "intel_de.h"
#include "intel_display_device.h"
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index 4be8cb65fb7e..2c315caf2414 100644
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -49,6 +49,7 @@
#include "i915_pvinfo.h"
#include "trace.h"
+#include "display/i9xx_plane_regs.h"
#include "display/intel_display.h"
#include "display/intel_sprite_regs.h"
#include "gem/i915_gem_context.h"
diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 73ea8be0f80b..dafa13ac826b 100644
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -37,6 +37,7 @@
#include "gvt.h"
#include "display/bxt_dpio_phy_regs.h"
+#include "display/i9xx_plane_regs.h"
#include "display/intel_cursor_regs.h"
#include "display/intel_display.h"
#include "display/intel_dpio_phy.h"
diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
index e78de423a6c7..521dee39e5fb 100644
--- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
+++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
@@ -40,6 +40,7 @@
#include "i915_pvinfo.h"
#include "i915_reg.h"
+#include "display/i9xx_plane_regs.h"
#include "display/intel_cursor_regs.h"
#include "display/intel_sprite_regs.h"
#include "display/skl_universal_plane_regs.h"
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 6f633035618e..27ef6dfee641 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -42,6 +42,7 @@
#include "i915_pvinfo.h"
#include "intel_mchbar_regs.h"
#include "display/bxt_dpio_phy_regs.h"
+#include "display/i9xx_plane_regs.h"
#include "display/intel_cursor_regs.h"
#include "display/intel_display_types.h"
#include "display/intel_dmc_regs.h"
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f5e8833cc37e..29f69ad8f704 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2260,75 +2260,7 @@
#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
-/* Display A control */
-#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
-#define _DSPACNTR 0x70180
-#define DISP_ENABLE REG_BIT(31)
-#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
-#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
-#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
-#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
-#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
-#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
-#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
-#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
-#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
-#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
-#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
-#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
-#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
-#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
-#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
-#define DISP_STEREO_ENABLE REG_BIT(25)
-#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
-#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
-#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
-#define DISP_SRC_KEY_ENABLE REG_BIT(22)
-#define DISP_LINE_DOUBLE REG_BIT(20)
-#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
-#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
-#define DISP_ROTATE_180 REG_BIT(15)
-#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
-#define DISP_TILED REG_BIT(10)
-#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
-#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
-#define _DSPAADDR 0x70184
-#define _DSPASTRIDE 0x70188
-#define _DSPAPOS 0x7018C /* reserved */
-#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
-#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
-#define DISP_POS_X_MASK REG_GENMASK(15, 0)
-#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
-#define _DSPASIZE 0x70190
-#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
-#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
-#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
-#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
-#define _DSPASURF 0x7019C /* 965+ only */
-#define DISP_ADDR_MASK REG_GENMASK(31, 12)
-#define _DSPATILEOFF 0x701A4 /* 965+ only */
-#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
-#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
-#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
-#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
-#define _DSPAOFFSET 0x701A4 /* HSW */
-#define _DSPASURFLIVE 0x701AC
-#define _DSPAGAMC 0x701E0
-
-#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
-#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
-#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
-#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
-#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
-#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
-#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
-#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
-#define DSPLINOFF(plane) DSPADDR(plane)
-#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
-#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
-#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
-
-/* CHV pipe B blender and primary plane */
+/* CHV pipe B blender */
#define _CHV_BLEND_A 0x60a00
#define CHV_BLEND_MASK REG_GENMASK(31, 30)
#define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
@@ -2338,26 +2270,9 @@
#define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
#define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
#define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
-#define _PRIMPOS_A 0x60a08
-#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
-#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
-#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
-#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
-#define _PRIMSIZE_A 0x60a0c
-#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
-#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
-#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
-#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
-#define _PRIMCNSTALPHA_A 0x60a10
-#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
-#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
-#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
#define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
#define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
-#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
-#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
-#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
/* Display/Sprite base address macros */
#define DISP_BASEADDR_MASK (0xfffff000)
diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index 1dc5281b2ade..5c5685ebd49e 100644
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -25,6 +25,7 @@
*
*/
+#include "display/i9xx_plane_regs.h"
#include "display/intel_de.h"
#include "display/intel_display.h"
#include "display/intel_display_trace.h"
diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
index b485976976db..2375292292b6 100644
--- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
+++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
@@ -4,6 +4,7 @@
*/
#include "display/bxt_dpio_phy_regs.h"
+#include "display/i9xx_plane_regs.h"
#include "display/intel_audio_regs.h"
#include "display/intel_backlight_regs.h"
#include "display/intel_color_regs.h"
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (8 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:12 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies Ville Syrjala
` (13 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Group the pre-skl primary plane register definitions
sensible, and toss in a few comments to indicate which
platforms have what.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/i9xx_plane_regs.h | 46 ++++++++++++-------
1 file changed, 29 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 0bf2cd42bce7..929b26faf31e 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -9,7 +9,10 @@
#include "intel_display_reg_defs.h"
#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
+#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
+
#define _DSPACNTR 0x70180
+#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
#define DISP_ENABLE REG_BIT(31)
#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
@@ -39,60 +42,69 @@
#define DISP_TILED REG_BIT(10)
#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
+
#define _DSPAADDR 0x70184
+#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
+
+#define _DSPALINOFF 0x70184
+#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
+
#define _DSPASTRIDE 0x70188
+#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
+
#define _DSPAPOS 0x7018C /* reserved */
+#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
#define DISP_POS_X_MASK REG_GENMASK(15, 0)
#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
+
#define _DSPASIZE 0x70190
+#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
+
#define _DSPASURF 0x7019C /* 965+ only */
+#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
+
#define _DSPATILEOFF 0x701A4 /* 965+ only */
+#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
+
#define _DSPAOFFSET 0x701A4 /* HSW */
+#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
+
#define _DSPASURFLIVE 0x701AC
+#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
+
#define _DSPAGAMC 0x701E0
-
-#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
-#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
-#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
-#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
-#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
-#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
-#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
-#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
-#define DSPLINOFF(plane) DSPADDR(plane)
-#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
-#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
-#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
/* CHV pipe B primary plane */
#define _PRIMPOS_A 0x60a08
+#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
+
#define _PRIMSIZE_A 0x60a0c
+#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
+
#define _PRIMCNSTALPHA_A 0x60a10
+#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
-#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
-#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
-#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
-
#endif /* __I9XX_PLANE_REGS_H__ */
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (9 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:16 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 12/13] drm/i915: Polish sprite plane register definitions Ville Syrjala
` (12 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add some notes indicatign which plane registers/bits are
valid for which platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/i9xx_plane_regs.h | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
index 929b26faf31e..d74a74d1f29a 100644
--- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
+++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
@@ -37,53 +37,53 @@
#define DISP_LINE_DOUBLE REG_BIT(20)
#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
-#define DISP_ROTATE_180 REG_BIT(15)
+#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
-#define DISP_TILED REG_BIT(10)
+#define DISP_TILED REG_BIT(10) /* i965+ */
#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
-#define _DSPAADDR 0x70184
+#define _DSPAADDR 0x70184 /* pre-i965 */
#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
-#define _DSPALINOFF 0x70184
+#define _DSPALINOFF 0x70184 /* i965+ */
#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
#define _DSPASTRIDE 0x70188
#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
-#define _DSPAPOS 0x7018C /* reserved */
+#define _DSPAPOS 0x7018C /* pre-g4x */
#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
#define DISP_POS_X_MASK REG_GENMASK(15, 0)
#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
-#define _DSPASIZE 0x70190
+#define _DSPASIZE 0x70190 /* pre-g4x */
#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
-#define _DSPASURF 0x7019C /* 965+ only */
+#define _DSPASURF 0x7019C /* i965+ */
#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
#define DISP_ADDR_MASK REG_GENMASK(31, 12)
-#define _DSPATILEOFF 0x701A4 /* 965+ only */
+#define _DSPATILEOFF 0x701A4 /* i965+ */
#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
-#define _DSPAOFFSET 0x701A4 /* HSW */
+#define _DSPAOFFSET 0x701A4 /* hsw+ */
#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
-#define _DSPASURFLIVE 0x701AC
+#define _DSPASURFLIVE 0x701AC /* g4x+ */
#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
-#define _DSPAGAMC 0x701E0
+#define _DSPAGAMC 0x701E0 /* pre-g4x */
#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
/* CHV pipe B primary plane */
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 12/13] drm/i915: Polish sprite plane register definitions
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (10 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:17 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 13/13] drm/i915: Document which platforms use which sprite registers Ville Syrjala
` (11 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Group the sprite plane register definitions such that everything
to do wiht the same register is in one place.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++++++++++--------
1 file changed, 134 insertions(+), 97 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
index bb67705652b2..c27adbaf0f00 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -7,6 +7,8 @@
#include "intel_display_reg_defs.h"
#define _DVSACNTR 0x72180
+#define _DVSBCNTR 0x73180
+#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
#define DVS_ENABLE REG_BIT(31)
#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
@@ -28,31 +30,67 @@
#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
#define DVS_TILED REG_BIT(10)
#define DVS_DEST_KEY REG_BIT(2)
+
#define _DVSALINOFF 0x72184
+#define _DVSBLINOFF 0x73184
+#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
+
#define _DVSASTRIDE 0x72188
+#define _DVSBSTRIDE 0x73188
+#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
+
#define _DVSAPOS 0x7218c
+#define _DVSBPOS 0x7318c
+#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
#define DVS_POS_Y_MASK REG_GENMASK(31, 16)
#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
#define DVS_POS_X_MASK REG_GENMASK(15, 0)
#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
+
#define _DVSASIZE 0x72190
+#define _DVSBSIZE 0x73190
+#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
#define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
#define DVS_WIDTH_MASK REG_GENMASK(15, 0)
#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
+
#define _DVSAKEYVAL 0x72194
+#define _DVSBKEYVAL 0x73194
+#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
+
#define _DVSAKEYMSK 0x72198
+#define _DVSBKEYMSK 0x73198
+#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
+
#define _DVSASURF 0x7219c
+#define _DVSBSURF 0x7319c
+#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
#define DVS_ADDR_MASK REG_GENMASK(31, 12)
+
#define _DVSAKEYMAXVAL 0x721a0
+#define _DVSBKEYMAXVAL 0x731a0
+#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
+
#define _DVSATILEOFF 0x721a4
+#define _DVSBTILEOFF 0x731a4
+#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
+
#define _DVSASURFLIVE 0x721ac
+#define _DVSBSURFLIVE 0x731ac
+#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
+
#define _DVSAGAMC_G4X 0x721e0 /* g4x */
+#define _DVSBGAMC_G4X 0x731e0 /* g4x */
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
+
#define _DVSASCALE 0x72204
+#define _DVSBSCALE 0x73204
+#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
#define DVS_SCALE_ENABLE REG_BIT(31)
#define DVS_FILTER_MASK REG_GENMASK(30, 29)
#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
@@ -64,42 +102,18 @@
#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
+
#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
-#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
-
-#define _DVSBCNTR 0x73180
-#define _DVSBLINOFF 0x73184
-#define _DVSBSTRIDE 0x73188
-#define _DVSBPOS 0x7318c
-#define _DVSBSIZE 0x73190
-#define _DVSBKEYVAL 0x73194
-#define _DVSBKEYMSK 0x73198
-#define _DVSBSURF 0x7319c
-#define _DVSBKEYMAXVAL 0x731a0
-#define _DVSBTILEOFF 0x731a4
-#define _DVSBSURFLIVE 0x731ac
-#define _DVSBGAMC_G4X 0x731e0 /* g4x */
-#define _DVSBSCALE 0x73204
#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
-#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
-
-#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
-#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
-#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
-#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
-#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
-#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
-#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
-#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
-#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
-#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
-#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
-#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
-#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
+
+#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
+#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
#define _SPRA_CTL 0x70280
+#define _SPRB_CTL 0x71280
+#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
#define SPRITE_ENABLE REG_BIT(31)
#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
@@ -125,31 +139,67 @@
#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
#define SPRITE_TILED REG_BIT(10)
#define SPRITE_DEST_KEY REG_BIT(2)
+
#define _SPRA_LINOFF 0x70284
+#define _SPRB_LINOFF 0x71284
+#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
+
#define _SPRA_STRIDE 0x70288
+#define _SPRB_STRIDE 0x71288
+#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
+
#define _SPRA_POS 0x7028c
+#define _SPRB_POS 0x7128c
+#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
#define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
+
#define _SPRA_SIZE 0x70290
+#define _SPRB_SIZE 0x71290
+#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
+
#define _SPRA_KEYVAL 0x70294
+#define _SPRB_KEYVAL 0x71294
+#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
+
#define _SPRA_KEYMSK 0x70298
+#define _SPRB_KEYMSK 0x71298
+#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
+
#define _SPRA_SURF 0x7029c
+#define _SPRB_SURF 0x7129c
+#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
#define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
+
#define _SPRA_KEYMAX 0x702a0
+#define _SPRB_KEYMAX 0x712a0
+#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
+
#define _SPRA_TILEOFF 0x702a4
+#define _SPRB_TILEOFF 0x712a4
+#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
+
#define _SPRA_OFFSET 0x702a4
+#define _SPRB_OFFSET 0x712a4
+#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
+
#define _SPRA_SURFLIVE 0x702ac
+#define _SPRB_SURFLIVE 0x712ac
+#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+
#define _SPRA_SCALE 0x70304
+#define _SPRB_SCALE 0x71304
+#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
#define SPRITE_SCALE_ENABLE REG_BIT(31)
#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
@@ -161,45 +211,27 @@
#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
+
#define _SPRA_GAMC 0x70400
-#define _SPRA_GAMC16 0x70440
-#define _SPRA_GAMC17 0x7044c
-
-#define _SPRB_CTL 0x71280
-#define _SPRB_LINOFF 0x71284
-#define _SPRB_STRIDE 0x71288
-#define _SPRB_POS 0x7128c
-#define _SPRB_SIZE 0x71290
-#define _SPRB_KEYVAL 0x71294
-#define _SPRB_KEYMSK 0x71298
-#define _SPRB_SURF 0x7129c
-#define _SPRB_KEYMAX 0x712a0
-#define _SPRB_TILEOFF 0x712a4
-#define _SPRB_OFFSET 0x712a4
-#define _SPRB_SURFLIVE 0x712ac
-#define _SPRB_SCALE 0x71304
#define _SPRB_GAMC 0x71400
-#define _SPRB_GAMC16 0x71440
-#define _SPRB_GAMC17 0x7144c
-
-#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
-#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
-#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
-#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
-#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
-#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
-#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
-#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
-#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
-#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
-#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
-#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
+
+#define _SPRA_GAMC16 0x70440
+#define _SPRB_GAMC16 0x71440
#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
+
+#define _SPRA_GAMC17 0x7044c
+#define _SPRB_GAMC17 0x7144c
#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
-#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
+
+#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+ _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
+#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
+ _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
+#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
+#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
#define SP_ENABLE REG_BIT(31)
#define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
#define SP_FORMAT_MASK REG_GENMASK(29, 26)
@@ -225,80 +257,85 @@
#define SP_ROTATE_180 REG_BIT(15)
#define SP_TILED REG_BIT(10)
#define SP_MIRROR REG_BIT(8) /* CHV pipe B */
+
#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
+#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
+#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
+
#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
+#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
+#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
+
#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
+#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
+#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
#define SP_POS_Y_MASK REG_GENMASK(31, 16)
#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
#define SP_POS_X_MASK REG_GENMASK(15, 0)
#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
+
#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
+#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
+#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
#define SP_HEIGHT_MASK REG_GENMASK(31, 16)
#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
#define SP_WIDTH_MASK REG_GENMASK(15, 0)
#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
+
#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
+#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
+
#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
+#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
+#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
+
#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
+#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
+#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
#define SP_ADDR_MASK REG_GENMASK(31, 12)
+
#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
+#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
+
#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
+#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
+#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
#define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
+
#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
+#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
#define SP_CONST_ALPHA_ENABLE REG_BIT(31)
#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
+
#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
+#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
+
#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
+#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
+#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
#define SP_CONTRAST_MASK REG_GENMASK(26, 18)
#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
+
#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
+#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
+#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
#define SP_SH_SIN_MASK REG_GENMASK(26, 16)
#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
#define SP_SH_COS_MASK REG_GENMASK(9, 0)
#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
+
#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
-
-#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
-#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
-#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
-#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
-#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
-#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
-#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
-#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
-#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
-#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
-#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
-#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
-#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
-#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
-
-#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
- _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
-#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
- _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
-
-#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
-#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
-#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
-#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
-#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
-#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
-#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
-#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
-#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
-#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
-#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
/*
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* [PATCH 13/13] drm/i915: Document which platforms use which sprite registers
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (11 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 12/13] drm/i915: Polish sprite plane register definitions Ville Syrjala
@ 2024-05-16 13:56 ` Ville Syrjala
2024-05-20 13:18 ` Jani Nikula
2024-05-16 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups Patchwork
` (10 subsequent siblings)
23 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-16 13:56 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Note which sprite registers are valid for which platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
.../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++++++++++--------
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
index c27adbaf0f00..73021e3ced6d 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
@@ -6,6 +6,7 @@
#include "intel_display_reg_defs.h"
+/* g4x/ilk/snb video sprite */
#define _DVSACNTR 0x72180
#define _DVSBCNTR 0x73180
#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
@@ -111,6 +112,7 @@
#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
+/* ivb/hsw/bdw sprite */
#define _SPRA_CTL 0x70280
#define _SPRB_CTL 0x71280
#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
@@ -140,8 +142,8 @@
#define SPRITE_TILED REG_BIT(10)
#define SPRITE_DEST_KEY REG_BIT(2)
-#define _SPRA_LINOFF 0x70284
-#define _SPRB_LINOFF 0x71284
+#define _SPRA_LINOFF 0x70284 /* ivb */
+#define _SPRB_LINOFF 0x71284 /* ivb */
#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
#define _SPRA_STRIDE 0x70288
@@ -181,24 +183,24 @@
#define _SPRB_KEYMAX 0x712a0
#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
-#define _SPRA_TILEOFF 0x702a4
-#define _SPRB_TILEOFF 0x712a4
+#define _SPRA_TILEOFF 0x702a4 /* ivb */
+#define _SPRB_TILEOFF 0x712a4 /* ivb */
#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
-#define _SPRA_OFFSET 0x702a4
-#define _SPRB_OFFSET 0x712a4
+#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */
+#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */
#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
#define _SPRA_SURFLIVE 0x702ac
#define _SPRB_SURFLIVE 0x712ac
#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
-#define _SPRA_SCALE 0x70304
-#define _SPRB_SCALE 0x71304
+#define _SPRA_SCALE 0x70304 /* ivb */
+#define _SPRB_SCALE 0x71304 /* ivb */
#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
#define SPRITE_SCALE_ENABLE REG_BIT(31)
#define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
@@ -224,6 +226,7 @@
#define _SPRB_GAMC17 0x7144c
#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
+/* vlv/chv sprite */
#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
_PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (12 preceding siblings ...)
2024-05-16 13:56 ` [PATCH 13/13] drm/i915: Document which platforms use which sprite registers Ville Syrjala
@ 2024-05-16 14:36 ` Patchwork
2024-05-16 14:36 ` ✗ Fi.CI.SPARSE: " Patchwork
` (9 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-16 14:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanups
URL : https://patchwork.freedesktop.org/series/133701/
State : warning
== Summary ==
Error: dim checkpatch failed
2cd1d3b16e64 drm/i915: Add skl+ plane name aliases to enum plane_id
ad5e92ec05c2 drm/i915: Clean up the cursor register defines
7220bc7c82e0 drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
9477d75d613a drm/i915: Simplify PIPESRC_ERLY_TPT definition
-:54: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:252:
+#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
bb31d70432ff drm/i915: Rename selective fetch plane registers
d6e1c598110f drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
-:90: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20:
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20:
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
+ _PICK_EVEN_2RANGES((plane), PLANE_5, \
+ _PIPE((pipe), (reg_1_a), (reg_1_b)), \
+ _PIPE((pipe), (reg_2_a), (reg_2_b)), \
+ _PIPE((pipe), (reg_5_a), (reg_5_b)), \
+ _PIPE((pipe), (reg_6_a), (reg_6_b)))
-:96: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#96: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:26:
+#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
-:117: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:390:
+ _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \
-:118: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:391:
+ _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \
-:119: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#119: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:392:
+ _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \
-:120: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#120: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:393:
+ _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B)
-:132: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#132: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:405:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:133: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#133: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:406:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:134: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#134: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:407:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:135: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#135: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:408:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
-:146: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:419:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:147: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#147: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:420:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:148: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#148: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:421:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:149: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:422:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
-:160: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:433:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:161: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#161: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:434:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:162: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#162: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:435:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:163: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#163: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:436:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
total: 0 errors, 18 warnings, 1 checks, 129 lines checked
b2c21e2c199b drm/i915: Add separate defines for cursor WM/DDB register bits
-:62: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:597:
+ skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
total: 0 errors, 1 warnings, 0 checks, 107 lines checked
4f55aa37ef0c drm/i915: Move PIPEGCMAX to intel_color_regs.h
72bbeba17259 drm/i915: Extract i9xx_plane_regs.h
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#29:
new file mode 100644
-:109: WARNING:LONG_LINE_COMMENT: line length of 116 exceeds 100 columns
#109: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:76:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 2 warnings, 0 checks, 278 lines checked
15ddd4a2177e drm/i915: Polish pre-skl primary plane registers
-:89: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#89: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:87:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 1 warnings, 0 checks, 96 lines checked
554bc0f1d34b drm/i915: Document a few pre-skl primary plane platform dependencies
466e7977948e drm/i915: Polish sprite plane register definitions
-:87: WARNING:LONG_LINE_COMMENT: line length of 108 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:89:
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
-:303: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#303: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:287:
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-:316: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#316: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:300:
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-:328: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#328: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:312:
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-:335: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:319:
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
total: 0 errors, 5 warnings, 0 checks, 369 lines checked
e4fee9e8867a drm/i915: Document which platforms use which sprite registers
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanups
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (13 preceding siblings ...)
2024-05-16 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups Patchwork
@ 2024-05-16 14:36 ` Patchwork
2024-05-16 18:21 ` ✗ Fi.CI.BAT: failure " Patchwork
` (8 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-16 14:36 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanups
URL : https://patchwork.freedesktop.org/series/133701/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Plane register cleanups
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (14 preceding siblings ...)
2024-05-16 14:36 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-05-16 18:21 ` Patchwork
2024-05-17 18:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev2) Patchwork
` (7 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-16 18:21 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 17736 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanups
URL : https://patchwork.freedesktop.org/series/133701/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14775 -> Patchwork_133701v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133701v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133701v1, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (2): fi-elk-e7500 bat-arls-3
Missing (2): bat-dg2-11 fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133701v1:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-1:
- bat-adlp-9: [PASS][1] -> [FAIL][2] +3 other tests fail
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-3:
- bat-arls-3: NOTRUN -> [FAIL][3] +3 other tests fail
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-dp-3.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1:
- fi-tgl-1115g4: [PASS][4] -> [DMESG-FAIL][5] +3 other tests dmesg-fail
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/fi-tgl-1115g4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-hdmi-a-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-1:
- bat-adls-6: [PASS][6] -> [FAIL][7] +3 other tests fail
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adls-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adls-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1:
- fi-rkl-11600: [PASS][8] -> [FAIL][9] +2 other tests fail
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3:
- bat-adlp-6: [PASS][10] -> [FAIL][11] +3 other tests fail
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adlp-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1:
- bat-adln-1: [PASS][12] -> [FAIL][13] +2 other tests fail
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-adln-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-adln-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-hdmi-a-2:
- bat-arls-1: [PASS][14] -> [FAIL][15] +3 other tests fail
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-hdmi-a-2.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-hdmi-a-2.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1:
- bat-arls-2: [PASS][16] -> [FAIL][17] +3 other tests fail
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html
- bat-mtlp-8: [PASS][18] -> [FAIL][19] +3 other tests fail
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html
- bat-rplp-1: [PASS][20] -> [FAIL][21] +3 other tests fail
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-rplp-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-rplp-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-edp-1.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-hdmi-a-2:
- bat-dg2-14: [PASS][22] -> [FAIL][23] +3 other tests fail
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-dg2-14/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-hdmi-a-2.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-dg2-14/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-d-hdmi-a-2.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_flip@basic-flip-vs-dpms@a-dp6:
- {bat-mtlp-9}: [PASS][24] -> [DMESG-WARN][25]
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms@a-dp6.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-mtlp-9/igt@kms_flip@basic-flip-vs-dpms@a-dp6.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-9:
- {bat-mtlp-9}: NOTRUN -> [FAIL][26] +2 other tests fail
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-mtlp-9/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-dp-9.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-2:
- {bat-rpls-4}: [PASS][27] -> [FAIL][28] +3 other tests fail
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-rpls-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-2.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-rpls-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-2.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3:
- {bat-arls-4}: [PASS][29] -> [FAIL][30] +3 other tests fail
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-4/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-dp-3.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1:
- {bat-twl-1}: [PASS][31] -> [FAIL][32] +2 other tests fail
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-c-edp-1.html
* igt@kms_pipe_crc_basic@read-crc@pipe-d-dp-8:
- {bat-mtlp-9}: NOTRUN -> [DMESG-WARN][33]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-mtlp-9/igt@kms_pipe_crc_basic@read-crc@pipe-d-dp-8.html
Known issues
------------
Here are the changes found in Patchwork_133701v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-arls-3: NOTRUN -> [SKIP][34] ([i915#9318])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@debugfs_test@basic-hwmon.html
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-8: [PASS][35] -> [FAIL][36] ([i915#10378])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-dg2-8/igt@gem_lmem_swapping@basic@lmem0.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-dg2-8/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-arls-3: NOTRUN -> [SKIP][37] ([i915#10213]) +3 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-arls-3: NOTRUN -> [SKIP][38] ([i915#4083])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][39] ([i915#10197] / [i915#10211] / [i915#4079])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_blits@basic:
- bat-arls-3: NOTRUN -> [SKIP][40] ([i915#10196] / [i915#4077]) +2 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-arls-3: NOTRUN -> [SKIP][41] ([i915#10206] / [i915#4079])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-arls-3: NOTRUN -> [SKIP][42] ([i915#10209])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@i915_pm_rps@basic-api.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-arls-3: NOTRUN -> [SKIP][43] ([i915#10200]) +9 other tests skip
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-arls-3: NOTRUN -> [SKIP][44] ([i915#10202]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_dsc@dsc-basic:
- bat-arls-3: NOTRUN -> [SKIP][45] ([i915#9886])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_dsc@dsc-basic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-arls-3: NOTRUN -> [SKIP][46] ([i915#10207])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-2:
- bat-dg1-7: [PASS][47] -> [DMESG-FAIL][48] ([i915#6020]) +3 other tests dmesg-fail
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-dg1-7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-2.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-dg1-7/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-hdmi-a-2.html
* igt@kms_pm_backlight@basic-brightness:
- bat-arls-3: NOTRUN -> [SKIP][49] ([i915#9812])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_pm_backlight@basic-brightness.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- fi-elk-e7500: NOTRUN -> [SKIP][50] +24 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/fi-elk-e7500/igt@kms_pm_rpm@basic-pci-d3-state.html
* igt@kms_psr@psr-primary-mmap-gtt:
- bat-arls-3: NOTRUN -> [SKIP][51] ([i915#9732]) +3 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_psr@psr-primary-mmap-gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-arls-3: NOTRUN -> [SKIP][52] ([i915#10208] / [i915#8809])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-mmap:
- bat-arls-3: NOTRUN -> [SKIP][53] ([i915#10196] / [i915#3708] / [i915#4077]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-fence-read:
- bat-arls-3: NOTRUN -> [SKIP][54] ([i915#10212] / [i915#3708])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-read:
- bat-arls-3: NOTRUN -> [SKIP][55] ([i915#10214] / [i915#3708])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@prime_vgem@basic-read.html
* igt@prime_vgem@basic-write:
- bat-arls-3: NOTRUN -> [SKIP][56] ([i915#10216] / [i915#3708])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-3/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@core_auth@basic-auth:
- {bat-apl-1}: [DMESG-WARN][57] ([i915#1982]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-apl-1/igt@core_auth@basic-auth.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-apl-1/igt@core_auth@basic-auth.html
* igt@i915_selftest@live@active:
- bat-arls-1: [DMESG-WARN][59] ([i915#10999]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-1/igt@i915_selftest@live@active.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-1/igt@i915_selftest@live@active.html
* igt@i915_selftest@live@objects:
- bat-arls-1: [DMESG-FAIL][61] ([i915#10262]) -> [PASS][62] +22 other tests pass
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14775/bat-arls-1/igt@i915_selftest@live@objects.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/bat-arls-1/igt@i915_selftest@live@objects.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10196
[i915#10197]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10197
[i915#10200]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10200
[i915#10202]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10202
[i915#10206]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10206
[i915#10207]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10207
[i915#10208]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10208
[i915#10209]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10209
[i915#10211]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10211
[i915#10212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10212
[i915#10213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10213
[i915#10214]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10214
[i915#10216]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10216
[i915#10262]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10262
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10979]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10979
[i915#10999]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10999
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#6020]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6020
[i915#6121]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6121
[i915#8809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8809
[i915#9318]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9318
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
[i915#9886]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9886
Build changes
-------------
* Linux: CI_DRM_14775 -> Patchwork_133701v1
CI-20190529: 20190529
CI_DRM_14775: 3b6a503228b84c010794599203ac3e1e3d349bab @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7858: 133c90d6aabcd90871e36946317c90ee83c2f847 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133701v1: 3b6a503228b84c010794599203ac3e1e3d349bab @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v1/index.html
[-- Attachment #2: Type: text/html, Size: 19714 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
@ 2024-05-17 15:33 ` Jani Nikula
2024-05-17 15:55 ` Ville Syrjälä
2024-05-17 17:12 ` [PATCH v2 " Ville Syrjala
1 sibling, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-17 15:33 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
> of unnecessary head scratching. Add aliases using the skl+ plane
> names.
> And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
> as we only ever have 0-2 sprites per pipe on those platforms.
Should these be changed too?
- intel_plane_set_ckey()
- for_each_plane_id_on_crtc()
I'm not sure. But there's one real issue:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 32d10e62b2b9..d0bfee2ca643 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
> {
> if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
> - return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> + return BIT(PLANE_6) | BIT(PLANE_7);
> else
> - return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
> + return BIT(PLANE_4) | BIT(PLANE_5);
The if branches got swapped?
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
2024-05-17 15:33 ` Jani Nikula
@ 2024-05-17 15:55 ` Ville Syrjälä
0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2024-05-17 15:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, May 17, 2024 at 06:33:46PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
> > of unnecessary head scratching. Add aliases using the skl+ plane
> > names.
> > And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
> > as we only ever have 0-2 sprites per pipe on those platforms.
>
> Should these be changed too?
>
> - intel_plane_set_ckey()
I suppose one could consider splitting this to pre-skl
vs. skl+ variants and using the appropriate names
in each. But the whole ckey uapi is really designed
around the pre-skl single primary + single sprite world
view, so using the PLANE_PRIMARY name there seems OK.
> - for_each_plane_id_on_crtc()
There's not really a right answer here I guess. As
long as it's 0 where we start this will work.
> I'm not sure. But there's one real issue:
>
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index 32d10e62b2b9..d0bfee2ca643 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> > static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
> > {
> > if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
> > - return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> > + return BIT(PLANE_6) | BIT(PLANE_7);
> > else
> > - return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
> > + return BIT(PLANE_4) | BIT(PLANE_5);
>
> The if branches got swapped?
Yeah. Good catch. I suspect my brain was in the
"newer platforms surely have more things" mindset.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
2024-05-17 15:33 ` Jani Nikula
@ 2024-05-17 17:12 ` Ville Syrjala
2024-05-20 8:56 ` Jani Nikula
1 sibling, 1 reply; 49+ messages in thread
From: Ville Syrjala @ 2024-05-17 17:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
of unnecessary head scratching. Add aliases using the skl+ plane
names.
And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
as we only ever have 0-2 sprites per pipe on those platforms.
v2: Don't break icl_nv12_y_plane_mask() (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++----
drivers/gpu/drm/i915/display/intel_display.c | 8 +++----
.../drm/i915/display/intel_display_limits.h | 21 ++++++++++++-------
.../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +-
.../drm/i915/display/skl_universal_plane.c | 19 ++++++++---------
5 files changed, 30 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 339010384b86..ca6dc1dc56c8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
if (DISPLAY_VER(dev_priv) >= 9)
- primary = skl_universal_plane_create(dev_priv, pipe,
- PLANE_PRIMARY);
+ primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
else
primary = intel_primary_plane_create(dev_priv, pipe);
if (IS_ERR(primary)) {
@@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
struct intel_plane *plane;
if (DISPLAY_VER(dev_priv) >= 9)
- plane = skl_universal_plane_create(dev_priv, pipe,
- PLANE_SPRITE0 + sprite);
+ plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite);
else
plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
if (IS_ERR(plane)) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index cce1420fb541..ee2df655b0ab 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
linked_state->uapi.dst = plane_state->uapi.dst;
if (icl_is_hdr_plane(dev_priv, plane->id)) {
- if (linked->id == PLANE_SPRITE5)
+ if (linked->id == PLANE_7)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
- else if (linked->id == PLANE_SPRITE4)
+ else if (linked->id == PLANE_6)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
- else if (linked->id == PLANE_SPRITE3)
+ else if (linked->id == PLANE_5)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
- else if (linked->id == PLANE_SPRITE2)
+ else if (linked->id == PLANE_4)
plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
else
MISSING_CASE(linked->id);
diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
index 5126d0b5ae5d..c4775c99dc83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_limits.h
+++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
@@ -60,16 +60,23 @@ enum transcoder {
* (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
*/
enum plane_id {
- PLANE_PRIMARY,
- PLANE_SPRITE0,
- PLANE_SPRITE1,
- PLANE_SPRITE2,
- PLANE_SPRITE3,
- PLANE_SPRITE4,
- PLANE_SPRITE5,
+ /* skl+ universal plane names */
+ PLANE_1,
+ PLANE_2,
+ PLANE_3,
+ PLANE_4,
+ PLANE_5,
+ PLANE_6,
+ PLANE_7,
+
PLANE_CURSOR,
I915_MAX_PLANES,
+
+ /* pre-skl plane names */
+ PLANE_PRIMARY = PLANE_1,
+ PLANE_SPRITE0,
+ PLANE_SPRITE1,
};
enum port {
diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
index a76b48ebc2d3..4853c4806004 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
@@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
* pipe simultaneously.
*/
if (DISPLAY_VER(dev_priv) >= 9 &&
- to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
+ to_intel_plane(plane)->id >= PLANE_3 &&
set->flags & I915_SET_COLORKEY_DESTINATION)
return -EINVAL;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 32d10e62b2b9..d99fec8e5233 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
{
if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
- return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
+ return BIT(PLANE_4) | BIT(PLANE_5);
else
- return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
+ return BIT(PLANE_6) | BIT(PLANE_7);
}
bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
@@ -252,7 +252,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
u8 icl_hdr_plane_mask(void)
{
- return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
+ return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3);
}
bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
@@ -2099,7 +2099,7 @@ static bool skl_plane_has_fbc(struct drm_i915_private *i915,
if (DISPLAY_VER(i915) >= 20)
return icl_is_hdr_plane(i915, plane_id);
else
- return plane_id == PLANE_PRIMARY;
+ return plane_id == PLANE_1;
}
static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
@@ -2123,7 +2123,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
return false;
- if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
+ if (plane_id != PLANE_1 && plane_id != PLANE_2)
return false;
return true;
@@ -2331,8 +2331,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
return pipe != PIPE_C;
return pipe != PIPE_C &&
- (plane_id == PLANE_PRIMARY ||
- plane_id == PLANE_SPRITE0);
+ (plane_id == PLANE_1 || plane_id == PLANE_2);
}
static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
@@ -2350,7 +2349,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
return false;
- return plane_id < PLANE_SPRITE4;
+ return plane_id < PLANE_6;
}
static u8 skl_get_plane_caps(struct drm_i915_private *i915,
@@ -2439,7 +2438,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
plane->get_hw_state = skl_plane_get_hw_state;
plane->check_plane = skl_plane_check;
- if (plane_id == PLANE_PRIMARY) {
+ if (plane_id == PLANE_1) {
plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10);
plane->async_flip = skl_plane_async_flip;
plane->enable_flip_done = skl_plane_enable_flip_done;
@@ -2461,7 +2460,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
else
plane_funcs = &skl_plane_funcs;
- if (plane_id == PLANE_PRIMARY)
+ if (plane_id == PLANE_1)
plane_type = DRM_PLANE_TYPE_PRIMARY;
else
plane_type = DRM_PLANE_TYPE_OVERLAY;
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev2)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (15 preceding siblings ...)
2024-05-16 18:21 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2024-05-17 18:07 ` Patchwork
2024-05-17 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-17 18:07 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/133701/
State : warning
== Summary ==
Error: dim checkpatch failed
6b9d030f5372 drm/i915: Add skl+ plane name aliases to enum plane_id
e764cc62d70e drm/i915: Clean up the cursor register defines
29a094b876cf drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
d32d8a4a18e8 drm/i915: Simplify PIPESRC_ERLY_TPT definition
-:54: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#54: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:252:
+#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
0e608f6cec24 drm/i915: Rename selective fetch plane registers
6b95624ddd17 drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
-:90: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20:
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20:
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
+ _PICK_EVEN_2RANGES((plane), PLANE_5, \
+ _PIPE((pipe), (reg_1_a), (reg_1_b)), \
+ _PIPE((pipe), (reg_2_a), (reg_2_b)), \
+ _PIPE((pipe), (reg_5_a), (reg_5_b)), \
+ _PIPE((pipe), (reg_6_a), (reg_6_b)))
-:96: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#96: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:26:
+#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
-:117: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:390:
+ _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \
-:118: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:391:
+ _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \
-:119: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#119: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:392:
+ _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \
-:120: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#120: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:393:
+ _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B)
-:132: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#132: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:405:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:133: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#133: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:406:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:134: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#134: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:407:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:135: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#135: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:408:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
-:146: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:419:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:147: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#147: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:420:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:148: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#148: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:421:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:149: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:422:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
-:160: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:433:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:161: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#161: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:434:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:162: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#162: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:435:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:163: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#163: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:436:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
total: 0 errors, 18 warnings, 1 checks, 129 lines checked
fb5ecc54b897 drm/i915: Add separate defines for cursor WM/DDB register bits
-:62: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#62: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:597:
+ skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
total: 0 errors, 1 warnings, 0 checks, 107 lines checked
ac02c9644921 drm/i915: Move PIPEGCMAX to intel_color_regs.h
c9cd098e1814 drm/i915: Extract i9xx_plane_regs.h
-:29: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#29:
new file mode 100644
-:109: WARNING:LONG_LINE_COMMENT: line length of 116 exceeds 100 columns
#109: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:76:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 2 warnings, 0 checks, 278 lines checked
96b6d4a46db9 drm/i915: Polish pre-skl primary plane registers
-:89: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#89: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:87:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 1 warnings, 0 checks, 96 lines checked
4aa992b81797 drm/i915: Document a few pre-skl primary plane platform dependencies
06e94408419e drm/i915: Polish sprite plane register definitions
-:87: WARNING:LONG_LINE_COMMENT: line length of 108 exceeds 100 columns
#87: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:89:
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
-:303: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#303: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:287:
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-:316: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#316: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:300:
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-:328: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#328: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:312:
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-:335: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#335: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:319:
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
total: 0 errors, 5 warnings, 0 checks, 369 lines checked
a76d7f9381e9 drm/i915: Document which platforms use which sprite registers
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanups (rev2)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (16 preceding siblings ...)
2024-05-17 18:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev2) Patchwork
@ 2024-05-17 18:08 ` Patchwork
2024-05-17 18:26 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-17 18:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/133701/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Plane register cleanups (rev2)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (17 preceding siblings ...)
2024-05-17 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-05-17 18:26 ` Patchwork
2024-05-18 5:46 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-17 18:26 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4612 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/133701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14783 -> Patchwork_133701v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/index.html
Participating hosts (42 -> 37)
------------------------------
Missing (5): fi-kbl-7567u fi-snb-2520m fi-cfl-8109u fi-kbl-8809g bat-dg2-11
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133701v2:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-edp-1:
- {bat-twl-1}: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-edp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-a-edp-1.html
Known issues
------------
Here are the changes found in Patchwork_133701v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][3] ([i915#4613]) +2 other tests skip
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/bat-adlm-1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_module_load@load:
- bat-arls-3: [PASS][4] -> [ABORT][5] ([i915#11041])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/bat-arls-3/igt@i915_module_load@load.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/bat-arls-3/igt@i915_module_load@load.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [PASS][6] -> [ABORT][7] ([i915#10594])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- bat-mtlp-8: [PASS][8] -> [DMESG-WARN][9] ([i915#9157]) +1 other test dmesg-warn
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- {bat-mtlp-9}: [WARN][10] ([i915#10436]) -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/bat-mtlp-9/igt@i915_pm_rpm@module-reload.html
* igt@kms_pm_rpm@basic-pci-d3-state:
- {bat-mtlp-9}: [DMESG-WARN][12] ([i915#10435]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/bat-mtlp-9/igt@kms_pm_rpm@basic-pci-d3-state.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/bat-mtlp-9/igt@kms_pm_rpm@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10435
[i915#10436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10436
[i915#10594]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10594
[i915#11041]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11041
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
Build changes
-------------
* Linux: CI_DRM_14783 -> Patchwork_133701v2
CI-20190529: 20190529
CI_DRM_14783: bb0d6cdd4afb60a01432f817c52f198f64620728 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7861: 7861
Patchwork_133701v2: bb0d6cdd4afb60a01432f817c52f198f64620728 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/index.html
[-- Attachment #2: Type: text/html, Size: 5310 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Plane register cleanups (rev2)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (18 preceding siblings ...)
2024-05-17 18:26 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-05-18 5:46 ` Patchwork
2024-05-20 18:08 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3) Patchwork
` (3 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-18 5:46 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 80774 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanups (rev2)
URL : https://patchwork.freedesktop.org/series/133701/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14783_full -> Patchwork_133701v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133701v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133701v2_full, please notify your bug team ('I915-ci-infra@lists.freedesktop.org') to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133701v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-1:
- shard-dg2: NOTRUN -> [INCOMPLETE][1] +1 other test incomplete
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-c-hdmi-a-1.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf@psr2-pipe-b-edp-1:
- shard-mtlp: [PASS][2] -> [ABORT][3] +1 other test abort
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-mtlp-2/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf@psr2-pipe-b-edp-1.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-8/igt@kms_psr2_sf@cursor-plane-move-continuous-exceed-fully-sf@psr2-pipe-b-edp-1.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0:
- shard-tglu: [WARN][4] ([i915#2681]) -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@i915_pm_rc6_residency@rc6-idle@gt0-rcs0.html
New tests
---------
New tests have been introduced between CI_DRM_14783_full and Patchwork_133701v2_full:
### New IGT tests (2) ###
* igt@kms_flip@flip-vs-suspend@d-hdmi-a3:
- Statuses : 1 pass(s)
- Exec time: [6.74] s
* igt@perf@buffer-fill@1-vcs0:
- Statuses : 1 pass(s)
- Exec time: [4.22] s
Known issues
------------
Here are the changes found in Patchwork_133701v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@object-reloc-keep-cache:
- shard-rkl: NOTRUN -> [SKIP][6] ([i915#8411])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@api_intel_bb@object-reloc-keep-cache.html
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#8411])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@api_intel_bb@object-reloc-keep-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg1: NOTRUN -> [SKIP][8] ([i915#11078])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@device_reset@cold-reset-bound.html
* igt@device_reset@unbind-cold-reset-rebind:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#11078])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@device_reset@unbind-cold-reset-rebind.html
* igt@drm_fdinfo@busy-idle@bcs0:
- shard-dg2: NOTRUN -> [SKIP][10] ([i915#8414]) +7 other tests skip
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@drm_fdinfo@busy-idle@bcs0.html
* igt@drm_fdinfo@busy@vcs1:
- shard-dg1: NOTRUN -> [SKIP][11] ([i915#8414]) +12 other tests skip
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@drm_fdinfo@busy@vcs1.html
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [PASS][12] -> [FAIL][13] ([i915#7742])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-rkl-6/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_bad_reloc@negative-reloc-lut:
- shard-rkl: NOTRUN -> [SKIP][14] ([i915#3281]) +8 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@gem_bad_reloc@negative-reloc-lut.html
* igt@gem_basic@multigpu-create-close:
- shard-dg2: NOTRUN -> [SKIP][15] ([i915#7697])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@gem_basic@multigpu-create-close.html
* igt@gem_busy@semaphore:
- shard-dg1: NOTRUN -> [SKIP][16] ([i915#3936])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_busy@semaphore.html
* igt@gem_ccs@block-multicopy-inplace:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#3555] / [i915#9323])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gem_ccs@block-multicopy-inplace.html
* igt@gem_ccs@ctrl-surf-copy-new-ctx:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#9323])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@gem_ccs@ctrl-surf-copy-new-ctx.html
* igt@gem_close_race@multigpu-basic-process:
- shard-tglu: NOTRUN -> [SKIP][19] ([i915#7697])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@gem_close_race@multigpu-basic-process.html
* igt@gem_create@create-ext-cpu-access-sanity-check:
- shard-rkl: NOTRUN -> [SKIP][20] ([i915#6335])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@gem_create@create-ext-cpu-access-sanity-check.html
* igt@gem_create@create-ext-set-pat:
- shard-rkl: NOTRUN -> [SKIP][21] ([i915#8562])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_persistence@hostile:
- shard-snb: NOTRUN -> [SKIP][22] ([i915#1099]) +1 other test skip
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-snb4/igt@gem_ctx_persistence@hostile.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg1: NOTRUN -> [SKIP][23] ([i915#280])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@gem_ctx_sseu@invalid-args.html
- shard-tglu: NOTRUN -> [SKIP][24] ([i915#280])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][25] ([i915#7975] / [i915#8213])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg2: [PASS][26] -> [FAIL][27] ([i915#5784])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-6/igt@gem_eio@kms.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-6/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-dg1: [PASS][28] -> [FAIL][29] ([i915#5784])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg1-13/igt@gem_eio@reset-stress.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-18/igt@gem_eio@reset-stress.html
* igt@gem_exec_balancer@bonded-false-hang:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#4812])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@gem_exec_balancer@bonded-false-hang.html
* igt@gem_exec_balancer@bonded-pair:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#4771])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4771]) +2 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@parallel-bb-first:
- shard-rkl: NOTRUN -> [SKIP][33] ([i915#4525])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@sliced:
- shard-dg1: NOTRUN -> [SKIP][34] ([i915#4812])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_exec_balancer@sliced.html
* igt@gem_exec_capture@capture-invisible@smem0:
- shard-tglu: NOTRUN -> [SKIP][35] ([i915#6334])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@gem_exec_capture@capture-invisible@smem0.html
* igt@gem_exec_capture@many-4k-zero:
- shard-glk: NOTRUN -> [FAIL][36] ([i915#9606])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk1/igt@gem_exec_capture@many-4k-zero.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][37] ([i915#2842]) +3 other tests fail
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk7/igt@gem_exec_fair@basic-none-rrul@rcs0.html
- shard-rkl: NOTRUN -> [FAIL][38] ([i915#2842])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-pace-solo:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#3539]) +2 other tests skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@gem_exec_fair@basic-pace-solo.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-tglu: [PASS][40] -> [FAIL][41] ([i915#2842])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-tglu-2/igt@gem_exec_fair@basic-pace@rcs0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-rkl: [PASS][42] -> [FAIL][43] ([i915#2842]) +4 other tests fail
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-rkl-4/igt@gem_exec_fair@basic-pace@vecs0.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_fair@basic-throttle:
- shard-dg1: NOTRUN -> [SKIP][44] ([i915#3539]) +1 other test skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_exec_fair@basic-throttle.html
* igt@gem_exec_flush@basic-wb-rw-before-default:
- shard-dg1: NOTRUN -> [SKIP][45] ([i915#3539] / [i915#4852]) +2 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@gem_exec_flush@basic-wb-rw-before-default.html
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#3539] / [i915#4852])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@gem_exec_flush@basic-wb-rw-before-default.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#3281]) +4 other tests skip
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_exec_reloc@basic-wc-gtt-active:
- shard-mtlp: NOTRUN -> [SKIP][48] ([i915#3281])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@gem_exec_reloc@basic-wc-gtt-active.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-dg1: NOTRUN -> [SKIP][49] ([i915#3281]) +4 other tests skip
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@preempt-queue-contexts:
- shard-dg2: NOTRUN -> [SKIP][50] ([i915#4537] / [i915#4812])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_exec_schedule@preempt-queue-contexts.html
* igt@gem_fence_thrash@bo-write-verify-threaded-none:
- shard-dg2: NOTRUN -> [SKIP][51] ([i915#4860])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@gem_fence_thrash@bo-write-verify-threaded-none.html
* igt@gem_lmem_swapping@basic:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#4613]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg2: NOTRUN -> [FAIL][53] ([i915#10378])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
- shard-dg2: [PASS][54] -> [FAIL][55] ([i915#10378])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
* igt@gem_lmem_swapping@parallel-multi:
- shard-tglu: NOTRUN -> [SKIP][56] ([i915#4613])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@gem_lmem_swapping@parallel-multi.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-glk: NOTRUN -> [SKIP][57] ([i915#4613]) +2 other tests skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk6/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_media_vme:
- shard-dg2: NOTRUN -> [SKIP][58] ([i915#284])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_media_vme.html
* igt@gem_mmap@basic:
- shard-dg1: NOTRUN -> [SKIP][59] ([i915#4083]) +1 other test skip
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@big-copy:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#4077]) +12 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_gtt@cpuset-basic-small-copy-odd:
- shard-mtlp: NOTRUN -> [SKIP][61] ([i915#4077]) +1 other test skip
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@gem_mmap_gtt@cpuset-basic-small-copy-odd.html
* igt@gem_mmap_gtt@flink-race:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#4077]) +7 other tests skip
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_mmap_gtt@flink-race.html
* igt@gem_mmap_wc@fault-concurrent:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#4083]) +4 other tests skip
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@gem_mmap_wc@fault-concurrent.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][64] ([i915#3282]) +2 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pread@display:
- shard-dg2: NOTRUN -> [SKIP][65] ([i915#3282]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_pread@display.html
* igt@gem_pxp@create-regular-buffer:
- shard-rkl: NOTRUN -> [SKIP][66] ([i915#4270])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-dg1: NOTRUN -> [SKIP][67] ([i915#4270]) +3 other tests skip
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
- shard-tglu: NOTRUN -> [SKIP][68] ([i915#4270]) +2 other tests skip
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@reject-modify-context-protection-off-1:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#4270])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@gem_pxp@reject-modify-context-protection-off-1.html
* igt@gem_pxp@verify-pxp-execution-after-suspend-resume:
- shard-dg2: NOTRUN -> [SKIP][70] ([i915#4270]) +4 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@gem_pxp@verify-pxp-execution-after-suspend-resume.html
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#5190] / [i915#8428]) +2 other tests skip
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
* igt@gem_render_tiled_blits@basic:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#4079])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_render_tiled_blits@basic.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-dg2: NOTRUN -> [SKIP][73] ([i915#4079]) +2 other tests skip
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_spin_batch@spin-all-new:
- shard-dg2: NOTRUN -> [FAIL][74] ([i915#5889])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@gem_spin_batch@spin-all-new.html
* igt@gem_tiled_partial_pwrite_pread@reads:
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#3282])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gem_tiled_partial_pwrite_pread@reads.html
* igt@gem_userptr_blits@invalid-mmap-offset-unsync:
- shard-rkl: NOTRUN -> [SKIP][76] ([i915#3297])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg2: NOTRUN -> [SKIP][77] ([i915#3297] / [i915#4880])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-dg1: NOTRUN -> [SKIP][78] ([i915#3297] / [i915#4880])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg1: NOTRUN -> [SKIP][79] ([i915#3297])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@gem_userptr_blits@unsync-unmap-cycles.html
- shard-tglu: NOTRUN -> [SKIP][80] ([i915#3297])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#2527])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@batch-invalid-length:
- shard-dg1: NOTRUN -> [SKIP][82] ([i915#2527]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@gen9_exec_parse@batch-invalid-length.html
* igt@gen9_exec_parse@bb-start-cmd:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#2856]) +1 other test skip
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@gen9_exec_parse@bb-start-cmd.html
* igt@gen9_exec_parse@unaligned-access:
- shard-tglu: NOTRUN -> [SKIP][84] ([i915#2527] / [i915#2856])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@gen9_exec_parse@unaligned-access.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][85] ([i915#4881])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@i915_fb_tiling.html
* igt@i915_module_load@load:
- shard-mtlp: NOTRUN -> [SKIP][86] ([i915#6227])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@i915_module_load@load.html
* igt@i915_pm_freq_mult@media-freq@gt0:
- shard-dg1: NOTRUN -> [SKIP][87] ([i915#6590])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@i915_pm_freq_mult@media-freq@gt0.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0:
- shard-dg1: [PASS][88] -> [FAIL][89] ([i915#3591])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vecs0.html
* igt@i915_pm_rps@basic-api:
- shard-dg2: NOTRUN -> [SKIP][90] ([i915#6621])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@min-max-config-loaded:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#6621])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@i915_pm_rps@min-max-config-loaded.html
* igt@i915_pm_sseu@full-enable:
- shard-dg2: NOTRUN -> [SKIP][92] ([i915#4387])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@test-query-geometry-subslices:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#5723])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@i915_query@test-query-geometry-subslices.html
- shard-tglu: NOTRUN -> [SKIP][94] ([i915#5723])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@i915_query@test-query-geometry-subslices.html
* igt@intel_hwmon@hwmon-write:
- shard-rkl: NOTRUN -> [SKIP][95] ([i915#7707])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@intel_hwmon@hwmon-write.html
* igt@kms_addfb_basic@basic-x-tiled-legacy:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#4212]) +1 other test skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_addfb_basic@basic-x-tiled-legacy.html
* igt@kms_addfb_basic@framebuffer-vs-set-tiling:
- shard-dg1: NOTRUN -> [SKIP][97] ([i915#4212])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg1: NOTRUN -> [SKIP][98] ([i915#1769] / [i915#3555])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-16bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][99] ([i915#5286]) +2 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-dg1: NOTRUN -> [SKIP][100] ([i915#4538] / [i915#5286]) +3 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
- shard-tglu: NOTRUN -> [SKIP][101] ([i915#5286]) +3 other tests skip
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][102] +20 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-270:
- shard-mtlp: NOTRUN -> [SKIP][103]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_big_fb@x-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][104] ([i915#3638]) +2 other tests skip
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_big_fb@x-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-dg1: NOTRUN -> [SKIP][105] ([i915#3638]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#4538] / [i915#5190]) +10 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
- shard-dg1: NOTRUN -> [SKIP][107] ([i915#4538]) +3 other tests skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html
* igt@kms_big_joiner@basic-force-joiner:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#10656])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@kms_big_joiner@basic-force-joiner.html
* igt@kms_big_joiner@invalid-modeset:
- shard-dg1: NOTRUN -> [SKIP][109] ([i915#10656])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_big_joiner@invalid-modeset.html
* igt@kms_big_joiner@invalid-modeset-force-joiner:
- shard-tglu: NOTRUN -> [SKIP][110] ([i915#10656])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@kms_big_joiner@invalid-modeset-force-joiner.html
* igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#6095]) +61 other tests skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
* igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
- shard-dg2: NOTRUN -> [SKIP][112] ([i915#10278])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#10307] / [i915#10434] / [i915#6095]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-rc-ccs-cc@pipe-d-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][114] ([i915#6095]) +19 other tests skip
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][115] ([i915#6095]) +3 other tests skip
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs-cc@pipe-b-edp-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#6095]) +75 other tests skip
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-13/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-d-hdmi-a-3.html
* igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][117] ([i915#10278])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_ccs@random-ccs-data-4-tiled-xe2-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-dp-4:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#10307] / [i915#6095]) +149 other tests skip
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_ccs@random-ccs-data-y-tiled-gen12-mc-ccs@pipe-c-dp-4.html
* igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#4087]) +3 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-2/igt@kms_cdclk@plane-scaling@pipe-d-hdmi-a-2.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#7828]) +9 other tests skip
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
- shard-mtlp: NOTRUN -> [SKIP][121] ([i915#7828])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html
* igt@kms_chamelium_frames@hdmi-crc-single:
- shard-rkl: NOTRUN -> [SKIP][122] ([i915#7828]) +3 other tests skip
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_chamelium_frames@hdmi-crc-single.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-tglu: NOTRUN -> [SKIP][123] ([i915#7828]) +2 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#7828]) +6 other tests skip
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
* igt@kms_content_protection@atomic-dpms:
- shard-dg1: NOTRUN -> [SKIP][125] ([i915#7116] / [i915#9424])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_content_protection@atomic-dpms.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-rkl: NOTRUN -> [SKIP][126] ([i915#3116]) +2 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
- shard-dg2: NOTRUN -> [SKIP][127] ([i915#3299])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@mei-interface:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#9424])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_content_protection@mei-interface.html
- shard-dg1: NOTRUN -> [SKIP][129] ([i915#9433])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_content_protection@mei-interface.html
* igt@kms_content_protection@srm:
- shard-mtlp: NOTRUN -> [SKIP][130] ([i915#6944])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_content_protection@srm.html
* igt@kms_content_protection@uevent:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#7118] / [i915#9424]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-32x10:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#3555]) +4 other tests skip
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-32x10:
- shard-dg1: NOTRUN -> [SKIP][133] ([i915#3555]) +7 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x170:
- shard-tglu: NOTRUN -> [SKIP][134] ([i915#3359])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@kms_cursor_crc@cursor-rapid-movement-512x170.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-dg1: NOTRUN -> [SKIP][135] ([i915#3359])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x170:
- shard-rkl: NOTRUN -> [SKIP][136] ([i915#3359])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_cursor_crc@cursor-sliding-512x170.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: NOTRUN -> [FAIL][137] ([i915#2346])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#9723])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@psr-dirtyfb-ioctl:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#9833])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@kms_dirtyfb@psr-dirtyfb-ioctl.html
* igt@kms_display_modes@mst-extended-mode-negative:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#8588])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_display_modes@mst-extended-mode-negative.html
- shard-dg1: NOTRUN -> [SKIP][141] ([i915#8588])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_display_modes@mst-extended-mode-negative.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][142] ([i915#3804])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
* igt@kms_draw_crc@draw-method-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#8812])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_draw_crc@draw-method-mmap-gtt.html
* igt@kms_dsc@dsc-with-bpc-formats:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#3555] / [i915#3840])
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_dsc@dsc-with-bpc-formats.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg1: NOTRUN -> [SKIP][145] ([i915#3840] / [i915#9053])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglu: NOTRUN -> [SKIP][146] ([i915#3469])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_feature_discovery@chamelium:
- shard-dg2: NOTRUN -> [SKIP][147] ([i915#4854])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_feature_discovery@chamelium.html
* igt@kms_feature_discovery@display-2x:
- shard-dg1: NOTRUN -> [SKIP][148] ([i915#1839])
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_feature_discovery@display-2x.html
- shard-tglu: NOTRUN -> [SKIP][149] ([i915#1839])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_feature_discovery@display-2x.html
* igt@kms_feature_discovery@display-3x:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#1839])
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_feature_discovery@display-3x.html
* igt@kms_feature_discovery@dp-mst:
- shard-mtlp: NOTRUN -> [SKIP][151] ([i915#9337])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_feature_discovery@dp-mst.html
* igt@kms_feature_discovery@psr1:
- shard-dg2: NOTRUN -> [SKIP][152] ([i915#658]) +1 other test skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_feature_discovery@psr1.html
* igt@kms_fence_pin_leak:
- shard-dg1: NOTRUN -> [SKIP][153] ([i915#4881])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-fences:
- shard-dg2: NOTRUN -> [SKIP][154] ([i915#8381])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@kms_flip@2x-flip-vs-fences.html
* igt@kms_flip@2x-nonexisting-fb-interruptible:
- shard-tglu: NOTRUN -> [SKIP][155] ([i915#3637]) +2 other tests skip
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_flip@2x-nonexisting-fb-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][156] +25 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-wf_vblank-ts-check-interruptible:
- shard-dg1: NOTRUN -> [SKIP][157] ([i915#9934]) +7 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_flip@2x-wf_vblank-ts-check-interruptible.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@a-vga1:
- shard-snb: [PASS][158] -> [ABORT][159] ([i915#8852])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-snb5/igt@kms_flip@flip-vs-blocking-wf-vblank@a-vga1.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-snb7/igt@kms_flip@flip-vs-blocking-wf-vblank@a-vga1.html
* igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1:
- shard-snb: [PASS][160] -> [FAIL][161] ([i915#2122]) +1 other test fail
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-snb5/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-snb7/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg1: NOTRUN -> [SKIP][162] ([i915#8381])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][163] ([i915#2672]) +1 other test skip
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][164] ([i915#2587] / [i915#2672]) +2 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
- shard-tglu: NOTRUN -> [SKIP][165] ([i915#2587] / [i915#2672]) +1 other test skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][166] ([i915#2672]) +3 other tests skip
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [PASS][167] -> [FAIL][168] ([i915#6880])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-mtlp: NOTRUN -> [SKIP][169] ([i915#1825]) +2 other tests skip
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][170] ([i915#8708]) +15 other tests skip
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][171] ([i915#1825]) +20 other tests skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-cur-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-dg1: NOTRUN -> [SKIP][172] +33 other tests skip
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt:
- shard-snb: NOTRUN -> [SKIP][173] +52 other tests skip
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-snb4/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc:
- shard-rkl: NOTRUN -> [SKIP][174] ([i915#3023]) +15 other tests skip
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb101010-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-dg2: NOTRUN -> [SKIP][175] ([i915#9766])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-dg2: NOTRUN -> [SKIP][176] ([i915#3458]) +17 other tests skip
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][177] ([i915#5354]) +25 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-tglu: NOTRUN -> [SKIP][178] +33 other tests skip
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][179] ([i915#8708]) +16 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite:
- shard-dg1: NOTRUN -> [SKIP][180] ([i915#3458]) +14 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_frontbuffer_tracking@psr-rgb565-draw-pwrite.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-dg2: NOTRUN -> [SKIP][181] ([i915#3555] / [i915#8228]) +1 other test skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_hdr@bpc-switch-suspend.html
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#3555] / [i915#8228]) +1 other test skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_hdr@invalid-hdr:
- shard-tglu: NOTRUN -> [SKIP][183] ([i915#3555] / [i915#8228])
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_hdr@invalid-hdr.html
* igt@kms_panel_fitting@atomic-fastset:
- shard-rkl: NOTRUN -> [SKIP][184] ([i915#6301])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_panel_fitting@atomic-fastset.html
* igt@kms_panel_fitting@legacy:
- shard-dg1: NOTRUN -> [SKIP][185] ([i915#6301])
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_panel_fitting@legacy.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- shard-mtlp: [PASS][186] -> [DMESG-WARN][187] ([i915#9157]) +1 other test dmesg-warn
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-mtlp-3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][188] ([i915#3555]) +3 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][189] ([i915#3555] / [i915#8806])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@2x-scaler-multi-pipe:
- shard-dg2: NOTRUN -> [SKIP][190] ([i915#5354] / [i915#9423])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_plane_scaling@2x-scaler-multi-pipe.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][191] ([i915#9423]) +7 other tests skip
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][192] ([i915#9423]) +11 other tests skip
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_plane_scaling@plane-downscale-factor-0-5-with-rotation@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][193] ([i915#9423]) +5 other tests skip
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][194] ([i915#5235]) +11 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-c-hdmi-a-4.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][195] ([i915#5235] / [i915#9423]) +7 other tests skip
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#5235]) +7 other tests skip
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][197] ([i915#5235]) +3 other tests skip
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][198] +287 other tests skip
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk7/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-dg1: NOTRUN -> [SKIP][199] ([i915#5354]) +1 other test skip
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-tglu: NOTRUN -> [SKIP][200] ([i915#9685]) +1 other test skip
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc5-psr:
- shard-rkl: NOTRUN -> [SKIP][201] ([i915#9685])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#3361])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg1: NOTRUN -> [SKIP][203] ([i915#9685])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-dg2: NOTRUN -> [SKIP][204] ([i915#8430])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@dpms-lpsp:
- shard-dg2: [PASS][205] -> [SKIP][206] ([i915#9519]) +2 other tests skip
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-5/igt@kms_pm_rpm@dpms-lpsp.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-dg2: NOTRUN -> [SKIP][207] ([i915#9519]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg1: NOTRUN -> [SKIP][208] ([i915#9519])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
- shard-rkl: NOTRUN -> [SKIP][209] ([i915#9519])
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
* igt@kms_prime@d3hot:
- shard-dg1: NOTRUN -> [SKIP][210] ([i915#6524])
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@kms_prime@d3hot.html
* igt@kms_psr2_su@page_flip-p010:
- shard-dg2: NOTRUN -> [SKIP][211] ([i915#9683])
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_psr2_su@page_flip-p010.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#9683])
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_psr2_su@page_flip-xrgb8888.html
- shard-tglu: NOTRUN -> [SKIP][213] ([i915#9683])
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-primary-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][214] ([i915#1072] / [i915#9673] / [i915#9732]) +3 other tests skip
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_psr@fbc-pr-primary-mmap-gtt.html
* igt@kms_psr@fbc-psr-cursor-mmap-gtt:
- shard-tglu: NOTRUN -> [SKIP][215] ([i915#9732]) +6 other tests skip
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_psr@fbc-psr-cursor-mmap-gtt.html
* igt@kms_psr@fbc-psr-primary-blt:
- shard-dg2: NOTRUN -> [SKIP][216] ([i915#1072] / [i915#9732]) +13 other tests skip
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_psr@fbc-psr-primary-blt.html
* igt@kms_psr@fbc-psr2-sprite-plane-move@edp-1:
- shard-mtlp: NOTRUN -> [SKIP][217] ([i915#9688])
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_psr@fbc-psr2-sprite-plane-move@edp-1.html
* igt@kms_psr@fbc-psr2-suspend:
- shard-rkl: NOTRUN -> [SKIP][218] ([i915#1072] / [i915#9732]) +11 other tests skip
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_psr@fbc-psr2-suspend.html
* igt@kms_psr@psr2-primary-mmap-cpu:
- shard-dg1: NOTRUN -> [SKIP][219] ([i915#1072] / [i915#9732]) +19 other tests skip
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@kms_psr@psr2-primary-mmap-cpu.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2: NOTRUN -> [SKIP][220] ([i915#4235])
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
- shard-dg2: NOTRUN -> [SKIP][221] ([i915#5190])
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270:
- shard-dg2: NOTRUN -> [SKIP][222] ([i915#4235] / [i915#5190])
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-270.html
* igt@kms_setmode@clone-exclusive-crtc:
- shard-tglu: NOTRUN -> [SKIP][223] ([i915#3555]) +2 other tests skip
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-9/igt@kms_setmode@clone-exclusive-crtc.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-glk: NOTRUN -> [FAIL][224] ([i915#10959])
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk7/igt@kms_tiled_display@basic-test-pattern.html
- shard-rkl: NOTRUN -> [SKIP][225] ([i915#8623])
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-1/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_vrr@seamless-rr-switch-vrr:
- shard-dg2: NOTRUN -> [SKIP][226] ([i915#9906]) +1 other test skip
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@kms_vrr@seamless-rr-switch-vrr.html
* igt@kms_writeback@writeback-check-output:
- shard-dg1: NOTRUN -> [SKIP][227] ([i915#2437])
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@kms_writeback@writeback-check-output.html
- shard-tglu: NOTRUN -> [SKIP][228] ([i915#2437])
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-check-output-xrgb2101010:
- shard-dg2: NOTRUN -> [SKIP][229] ([i915#2437] / [i915#9412])
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@kms_writeback@writeback-check-output-xrgb2101010.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-glk: NOTRUN -> [SKIP][230] ([i915#2437]) +1 other test skip
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-glk1/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: NOTRUN -> [FAIL][231] ([i915#7484])
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@cpu-hotplug:
- shard-dg1: NOTRUN -> [SKIP][232] ([i915#8850])
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6@other-idle-gt0:
- shard-dg2: NOTRUN -> [SKIP][233] ([i915#8516])
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@perf_pmu@rc6@other-idle-gt0.html
* igt@prime_vgem@basic-gtt:
- shard-dg2: NOTRUN -> [SKIP][234] ([i915#3708] / [i915#4077])
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-write:
- shard-dg1: NOTRUN -> [SKIP][235] ([i915#3708])
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@prime_vgem@basic-write.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-dg1: NOTRUN -> [SKIP][236] ([i915#9917])
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-16/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-dg2: NOTRUN -> [FAIL][237] ([i915#9779])
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@syncobj_wait@invalid-wait-zero-handles.html
- shard-rkl: NOTRUN -> [FAIL][238] ([i915#9779])
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@v3d/v3d_create_bo@create-bo-zeroed:
- shard-mtlp: NOTRUN -> [SKIP][239] ([i915#2575])
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@v3d/v3d_create_bo@create-bo-zeroed.html
* igt@v3d/v3d_submit_cl@bad-extension:
- shard-dg1: NOTRUN -> [SKIP][240] ([i915#2575]) +10 other tests skip
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@v3d/v3d_submit_cl@bad-extension.html
* igt@v3d/v3d_submit_csd@bad-flag:
- shard-dg2: NOTRUN -> [SKIP][241] ([i915#2575]) +10 other tests skip
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-7/igt@v3d/v3d_submit_csd@bad-flag.html
* igt@v3d/v3d_submit_csd@bad-multisync-in-sync:
- shard-tglu: NOTRUN -> [SKIP][242] ([i915#2575]) +8 other tests skip
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-10/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html
* igt@vc4/vc4_mmap@mmap-bo:
- shard-dg2: NOTRUN -> [SKIP][243] ([i915#7711]) +6 other tests skip
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@vc4/vc4_mmap@mmap-bo.html
* igt@vc4/vc4_tiling@set-bad-handle:
- shard-rkl: NOTRUN -> [SKIP][244] ([i915#7711]) +4 other tests skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@vc4/vc4_tiling@set-bad-handle.html
* igt@vc4/vc4_tiling@set-bad-modifier:
- shard-mtlp: NOTRUN -> [SKIP][245] ([i915#7711])
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@vc4/vc4_tiling@set-bad-modifier.html
* igt@vc4/vc4_wait_bo@unused-bo-0ns:
- shard-dg1: NOTRUN -> [SKIP][246] ([i915#7711]) +8 other tests skip
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-14/igt@vc4/vc4_wait_bo@unused-bo-0ns.html
#### Possible fixes ####
* igt@gem_ctx_freq@sysfs@gt0:
- shard-dg2: [FAIL][247] ([i915#9561]) -> [PASS][248]
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-11/igt@gem_ctx_freq@sysfs@gt0.html
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-3/igt@gem_ctx_freq@sysfs@gt0.html
* igt@gem_exec_parallel@userptr@vecs0:
- shard-dg1: [INCOMPLETE][249] -> [PASS][250]
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg1-15/igt@gem_exec_parallel@userptr@vecs0.html
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-18/igt@gem_exec_parallel@userptr@vecs0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg2: [FAIL][251] ([i915#10378]) -> [PASS][252]
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-8/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [TIMEOUT][253] ([i915#5493]) -> [PASS][254]
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-1/igt@gem_lmem_swapping@smem-oom@lmem0.html
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-3/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [INCOMPLETE][255] ([i915#9820] / [i915#9849]) -> [PASS][256]
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg1-18/igt@i915_module_load@reload-with-fault-injection.html
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-15/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0:
- shard-dg1: [FAIL][257] ([i915#3591]) -> [PASS][258] +1 other test pass
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@gt0-vcs0.html
* igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@a-hdmi-a1:
- shard-snb: [ABORT][259] -> [PASS][260]
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-snb6/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@a-hdmi-a1.html
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-snb4/igt@kms_flip@single-buffer-flip-vs-dpms-off-vs-modeset@a-hdmi-a1.html
* igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a4:
- shard-dg1: [FAIL][261] ([i915#2122]) -> [PASS][262]
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg1-16/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a4.html
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg1-17/igt@kms_flip@wf_vblank-ts-check-interruptible@a-hdmi-a4.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-dg2: [FAIL][263] ([i915#6880]) -> [PASS][264] +1 other test pass
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [FAIL][265] ([i915#9295]) -> [PASS][266]
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-tglu-7/igt@kms_pm_dc@dc6-dpms.html
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-4/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_rpm@dpms-mode-unset-non-lpsp:
- shard-rkl: [SKIP][267] ([i915#9519]) -> [PASS][268] +2 other tests pass
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-rkl-4/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-3/igt@kms_pm_rpm@dpms-mode-unset-non-lpsp.html
* igt@kms_pm_rpm@i2c:
- shard-dg2: [FAIL][269] ([i915#8717]) -> [PASS][270]
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-2/igt@kms_pm_rpm@i2c.html
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-3/igt@kms_pm_rpm@i2c.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-snb: [FAIL][271] ([i915#9196]) -> [PASS][272]
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-snb2/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-snb4/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1:
- shard-tglu: [FAIL][273] ([i915#9196]) -> [PASS][274] +1 other test pass
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-tglu-6/igt@kms_universal_plane@cursor-fb-leak@pipe-b-hdmi-a-1.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1:
- shard-mtlp: [FAIL][275] ([i915#9196]) -> [PASS][276]
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-mtlp-6/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-d-edp-1.html
* igt@perf_pmu@busy-double-start@vecs1:
- shard-dg2: [FAIL][277] ([i915#4349]) -> [PASS][278] +3 other tests pass
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-2/igt@perf_pmu@busy-double-start@vecs1.html
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html
#### Warnings ####
* igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0:
- shard-dg2: [FAIL][279] ([i915#10378]) -> [FAIL][280] ([i915#10446])
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-1/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-5/igt@gem_lmem_swapping@heavy-verify-multi-ccs@lmem0.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-mtlp: [ABORT][281] -> [SKIP][282]
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-mtlp-1/igt@kms_big_fb@linear-8bpp-rotate-270.html
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-mtlp-6/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [SKIP][283] ([i915#10433] / [i915#3458]) -> [SKIP][284] ([i915#3458]) +3 other tests skip
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][285] ([i915#4816]) -> [SKIP][286] ([i915#4070] / [i915#4816])
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_psr@psr-cursor-mmap-cpu:
- shard-dg2: [SKIP][287] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][288] ([i915#1072] / [i915#9732]) +9 other tests skip
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-11/igt@kms_psr@psr-cursor-mmap-cpu.html
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-10/igt@kms_psr@psr-cursor-mmap-cpu.html
* igt@kms_psr@psr-cursor-render:
- shard-dg2: [SKIP][289] ([i915#1072] / [i915#9732]) -> [SKIP][290] ([i915#1072] / [i915#9673] / [i915#9732]) +10 other tests skip
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-10/igt@kms_psr@psr-cursor-render.html
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-11/igt@kms_psr@psr-cursor-render.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][291] ([i915#5493]) -> [CRASH][292] ([i915#9351])
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14783/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10446]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10446
[i915#10656]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10656
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#10959]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10959
[i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
[i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3936]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3936
[i915#4070]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
[i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4881
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
[i915#5784]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5784
[i915#5889]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5889
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6227
[i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
[i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
[i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
[i915#7116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7116
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7484]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7484
[i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7975
[i915#8213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8588]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8588
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8717
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
[i915#8852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8852
[i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9412
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
[i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9779]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9779
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9833]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9833
[i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
Build changes
-------------
* Linux: CI_DRM_14783 -> Patchwork_133701v2
CI-20190529: 20190529
CI_DRM_14783: bb0d6cdd4afb60a01432f817c52f198f64620728 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7861: 7861
Patchwork_133701v2: bb0d6cdd4afb60a01432f817c52f198f64620728 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v2/index.html
[-- Attachment #2: Type: text/html, Size: 98718 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH v2 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id
2024-05-17 17:12 ` [PATCH v2 " Ville Syrjala
@ 2024-05-20 8:56 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 8:56 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Fri, 17 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Using PLANE_PRIMARY + PLANE_SPRITE? on skl+ results in a bunch
> of unnecessary head scratching. Add aliases using the skl+ plane
> names.
> And for pre-skl we only need to keep PRIMARY,SPRITE0,SPRITE1
> as we only ever have 0-2 sprites per pipe on those platforms.
>
> v2: Don't break icl_nv12_y_plane_mask() (Jani)
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crtc.c | 6 ++----
> drivers/gpu/drm/i915/display/intel_display.c | 8 +++----
> .../drm/i915/display/intel_display_limits.h | 21 ++++++++++++-------
> .../gpu/drm/i915/display/intel_sprite_uapi.c | 2 +-
> .../drm/i915/display/skl_universal_plane.c | 19 ++++++++---------
> 5 files changed, 30 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 339010384b86..ca6dc1dc56c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -310,8 +310,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> crtc->num_scalers = DISPLAY_RUNTIME_INFO(dev_priv)->num_scalers[pipe];
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - primary = skl_universal_plane_create(dev_priv, pipe,
> - PLANE_PRIMARY);
> + primary = skl_universal_plane_create(dev_priv, pipe, PLANE_1);
> else
> primary = intel_primary_plane_create(dev_priv, pipe);
> if (IS_ERR(primary)) {
> @@ -326,8 +325,7 @@ int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
> struct intel_plane *plane;
>
> if (DISPLAY_VER(dev_priv) >= 9)
> - plane = skl_universal_plane_create(dev_priv, pipe,
> - PLANE_SPRITE0 + sprite);
> + plane = skl_universal_plane_create(dev_priv, pipe, PLANE_2 + sprite);
> else
> plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
> if (IS_ERR(plane)) {
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index cce1420fb541..ee2df655b0ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4121,13 +4121,13 @@ static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
> linked_state->uapi.dst = plane_state->uapi.dst;
>
> if (icl_is_hdr_plane(dev_priv, plane->id)) {
> - if (linked->id == PLANE_SPRITE5)
> + if (linked->id == PLANE_7)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
> - else if (linked->id == PLANE_SPRITE4)
> + else if (linked->id == PLANE_6)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
> - else if (linked->id == PLANE_SPRITE3)
> + else if (linked->id == PLANE_5)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
> - else if (linked->id == PLANE_SPRITE2)
> + else if (linked->id == PLANE_4)
> plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
> else
> MISSING_CASE(linked->id);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_limits.h b/drivers/gpu/drm/i915/display/intel_display_limits.h
> index 5126d0b5ae5d..c4775c99dc83 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_limits.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_limits.h
> @@ -60,16 +60,23 @@ enum transcoder {
> * (eg. PLANE_CTL(), PS_PLANE_SEL(), etc.) so adjust with care.
> */
> enum plane_id {
> - PLANE_PRIMARY,
> - PLANE_SPRITE0,
> - PLANE_SPRITE1,
> - PLANE_SPRITE2,
> - PLANE_SPRITE3,
> - PLANE_SPRITE4,
> - PLANE_SPRITE5,
> + /* skl+ universal plane names */
> + PLANE_1,
> + PLANE_2,
> + PLANE_3,
> + PLANE_4,
> + PLANE_5,
> + PLANE_6,
> + PLANE_7,
> +
> PLANE_CURSOR,
>
> I915_MAX_PLANES,
> +
> + /* pre-skl plane names */
> + PLANE_PRIMARY = PLANE_1,
> + PLANE_SPRITE0,
> + PLANE_SPRITE1,
> };
>
> enum port {
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
> index a76b48ebc2d3..4853c4806004 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
> +++ b/drivers/gpu/drm/i915/display/intel_sprite_uapi.c
> @@ -74,7 +74,7 @@ int intel_sprite_set_colorkey_ioctl(struct drm_device *dev, void *data,
> * pipe simultaneously.
> */
> if (DISPLAY_VER(dev_priv) >= 9 &&
> - to_intel_plane(plane)->id >= PLANE_SPRITE1 &&
> + to_intel_plane(plane)->id >= PLANE_3 &&
> set->flags & I915_SET_COLORKEY_DESTINATION)
> return -EINVAL;
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 32d10e62b2b9..d99fec8e5233 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -238,9 +238,9 @@ int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
> static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
> {
> if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
> - return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
> + return BIT(PLANE_4) | BIT(PLANE_5);
> else
> - return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
> + return BIT(PLANE_6) | BIT(PLANE_7);
> }
>
> bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> @@ -252,7 +252,7 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
>
> u8 icl_hdr_plane_mask(void)
> {
> - return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
> + return BIT(PLANE_1) | BIT(PLANE_2) | BIT(PLANE_3);
> }
>
> bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
> @@ -2099,7 +2099,7 @@ static bool skl_plane_has_fbc(struct drm_i915_private *i915,
> if (DISPLAY_VER(i915) >= 20)
> return icl_is_hdr_plane(i915, plane_id);
> else
> - return plane_id == PLANE_PRIMARY;
> + return plane_id == PLANE_1;
> }
>
> static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
> @@ -2123,7 +2123,7 @@ static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
> return false;
>
> - if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
> + if (plane_id != PLANE_1 && plane_id != PLANE_2)
> return false;
>
> return true;
> @@ -2331,8 +2331,7 @@ static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
> return pipe != PIPE_C;
>
> return pipe != PIPE_C &&
> - (plane_id == PLANE_PRIMARY ||
> - plane_id == PLANE_SPRITE0);
> + (plane_id == PLANE_1 || plane_id == PLANE_2);
> }
>
> static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> @@ -2350,7 +2349,7 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
> if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
> return false;
>
> - return plane_id < PLANE_SPRITE4;
> + return plane_id < PLANE_6;
> }
>
> static u8 skl_get_plane_caps(struct drm_i915_private *i915,
> @@ -2439,7 +2438,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> plane->get_hw_state = skl_plane_get_hw_state;
> plane->check_plane = skl_plane_check;
>
> - if (plane_id == PLANE_PRIMARY) {
> + if (plane_id == PLANE_1) {
> plane->need_async_flip_toggle_wa = IS_DISPLAY_VER(dev_priv, 9, 10);
> plane->async_flip = skl_plane_async_flip;
> plane->enable_flip_done = skl_plane_enable_flip_done;
> @@ -2461,7 +2460,7 @@ skl_universal_plane_create(struct drm_i915_private *dev_priv,
> else
> plane_funcs = &skl_plane_funcs;
>
> - if (plane_id == PLANE_PRIMARY)
> + if (plane_id == PLANE_1)
> plane_type = DRM_PLANE_TYPE_PRIMARY;
> else
> plane_type = DRM_PLANE_TYPE_OVERLAY;
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
2024-05-16 13:56 ` [PATCH 02/13] drm/i915: Clean up the cursor register defines Ville Syrjala
@ 2024-05-20 9:10 ` Jani Nikula
2024-05-20 16:23 ` Ville Syrjälä
0 siblings, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 9:10 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Group the cursor register defines such that everything to
> do with one register is in one place.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
but a couple of nitpicks inline...
> ---
> .../gpu/drm/i915/display/intel_cursor_regs.h | 52 +++++++++----------
> 1 file changed, 26 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index c2190af1e9f5..270c26c2e6df 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -9,6 +9,7 @@
> #include "intel_display_reg_defs.h"
>
> #define _CURACNTR 0x70080
> +#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR)
In addition to code movement, these add braces around (dev_priv) and
(pipe). While it makes review harder by breaking 'git show
--color-moved', I also think it's kind of unnecessary when they're only
passed on as parameters. Or is there some corner case where it matters?
Comma has the lowest precedence, and I don't think you could easily pass
in a value with a comma operator.
No need to change for this, it's not wrong either.
> /* Old style CUR*CNTR flags (desktop 8xx) */
> #define CURSOR_ENABLE REG_BIT(31)
> #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
> @@ -38,61 +39,60 @@
> #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
> #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
> #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
> +
> #define _CURABASE 0x70084
> +#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE)
> +
> #define _CURAPOS 0x70088
> -#define _CURAPOS_ERLY_TPT 0x7008c
> +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS)
> #define CURSOR_POS_Y_SIGN REG_BIT(31)
> #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
> #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
> #define CURSOR_POS_X_SIGN REG_BIT(15)
> #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
> #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
> +
> +#define _CURAPOS_ERLY_TPT 0x7008c
> +#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT)
> +
> #define _CURASIZE 0x700a0 /* 845/865 */
> +#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE)
> #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
> #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
> #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
> #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
> +
> #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
> +#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A)
> #define CUR_FBC_EN REG_BIT(31)
> #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
> #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
> +
> #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
> +#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A)
> +
> #define _CURASURFLIVE 0x700ac /* g4x+ */
> -#define _CURBCNTR 0x700c0
> -#define _CURBBASE 0x700c4
> -#define _CURBPOS 0x700c8
> -
> -#define _CURBCNTR_IVB 0x71080
> -#define _CURBBASE_IVB 0x71084
> -#define _CURBPOS_IVB 0x71088
> -
> -#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
> -#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
> -#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
> -#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
> -#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
> -#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
> -#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
> -#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
> +#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE)
>
> /* skl+ */
> #define _CUR_WM_A_0 0x70140
> #define _CUR_WM_B_0 0x71140
> +#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
> +
> #define _CUR_WM_SAGV_A 0x70158
> #define _CUR_WM_SAGV_B 0x71158
> +#define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> +
> #define _CUR_WM_SAGV_TRANS_A 0x7015C
> #define _CUR_WM_SAGV_TRANS_B 0x7115C
> +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> +
> #define _CUR_WM_TRANS_A 0x70168
> #define _CUR_WM_TRANS_B 0x71168
> -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
There's some unmentioned drive-by cleanup here too. No biggie, but I've
found 'git show --color-moved' to be such a powerful aid in reviewing
code movement patches that I'd prefer these to be separate. No need to
change now, because I already reviewed it. :)
BR,
Jani.
> -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> +#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
>
> -/* skl+ */
> -#define _CUR_BUF_CFG_A 0x7017c
> -#define _CUR_BUF_CFG_B 0x7117c
> -#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> +#define _CUR_BUF_CFG_A 0x7017c
> +#define _CUR_BUF_CFG_B 0x7117c
> +#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
>
> #endif /* __INTEL_CURSOR_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
2024-05-16 13:56 ` [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Ville Syrjala
@ 2024-05-20 9:27 ` Jani Nikula
2024-05-20 17:08 ` Ville Syrjälä
2024-05-20 17:14 ` [PATCH v2 " Ville Syrjala
1 sibling, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 9:27 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split the cursor stuff from the rest of the selective fetch
> plane registers so that we can collect all cursor registers
> in intel_cursor_regs.h. Also take the opportunity to rename
> the registers to match the spec.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
> drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +++++
> 2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index c780ce146131..b44809899502 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
> if (!crtc_state->enable_psr2_sel_fetch)
> return;
>
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
> }
>
> static void wa_16021440873(struct intel_plane *plane,
> @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
> ctl &= ~MCURSOR_MODE_MASK;
> ctl |= MCURSOR_MODE_64_2B;
>
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
> + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
>
> intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
> PIPESRC_HEIGHT(et_y_position));
> @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
> val);
> }
>
> - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
> plane_state->ctl);
> } else {
> /* Wa_16021440873 */
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index 270c26c2e6df..ab02d497fba6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -95,4 +95,9 @@
> #define _CUR_BUF_CFG_B 0x7117c
> #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
>
> +#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
> +#define _SEL_FETCH_CUR_CTL_B 0x71880
> +#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
_SEL_FETCH_CUR_CTL_A is doubled, the latter should be _B.
With that,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
I must admit I was trying to follow how PLANE_SEL_FETCH_CTL(pipe,
CURSOR_A) ends up being identical to this new SEL_FETCH_CUR_CTL(pipe),
but holy crap it trips my brain completely. How did we come up with so
many levels of abstractions for this stuff, in such complicated ways?!
:o
> +#define SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
> +
> #endif /* __INTEL_CURSOR_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
2024-05-16 13:56 ` [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition Ville Syrjala
@ 2024-05-20 9:35 ` Jani Nikula
2024-05-20 9:37 ` Jani Nikula
0 siblings, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 9:35 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
> so using _MMIO_TRANS2() for it is not really correct. Also since this
> is a pipe register, and not present on CHV, the registers will be
> equally spaced out, so we can use the simpler _MMIO_PIPE() instead
> of _MMIO_PIPE2().
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index b44809899502..7983cbaf83f7 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -525,7 +525,7 @@ static void wa_16021440873(struct intel_plane *plane,
>
> intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
>
> - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
> + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
> PIPESRC_HEIGHT(et_y_position));
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index df0d14a5023f..d49e869f6be2 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2381,7 +2381,7 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
> if (!crtc_state->enable_psr2_su_region_et)
> return;
>
> - intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, crtc->pipe),
> + intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
> crtc_state->pipe_srcsz_early_tpt);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index e14cb48f2614..47e3a2e2977c 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -248,8 +248,8 @@
>
> /* PSR2 Early transport */
> #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074
> -
> -#define PIPE_SRCSZ_ERLY_TPT(dev_priv, trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A)
> +#define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
> +#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
>
> #define _SEL_FETCH_PLANE_BASE_1_A 0x70890
> #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
2024-05-20 9:35 ` Jani Nikula
@ 2024-05-20 9:37 ` Jani Nikula
2024-05-20 9:56 ` Hogander, Jouni
0 siblings, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 9:37 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Jouni Högander
On Mon, 20 May 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000 range.
>> so using _MMIO_TRANS2() for it is not really correct. Also since this
>> is a pipe register, and not present on CHV, the registers will be
>> equally spaced out, so we can use the simpler _MMIO_PIPE() instead
>> of _MMIO_PIPE2().
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Side note, while reviewing this I found this monstrosity:
static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
if (!dev_priv->display.params.enable_psr2_sel_fetch &&
intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 sel fetch not enabled, disabled by parameter\n");
return false;
}
if (crtc_state->uapi.async_flip) {
drm_dbg_kms(&dev_priv->drm,
"PSR2 sel fetch not enabled, async flip enabled\n");
return false;
}
return crtc_state->enable_psr2_sel_fetch = true;
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
}
Judging by name, a predicate function to check if config is valid,
actually modifies the config in what looks like a typoed return
statement. Ugh.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 05/13] drm/i915: Rename selective fetch plane registers
2024-05-16 13:56 ` [PATCH 05/13] drm/i915: Rename selective fetch plane registers Ville Syrjala
@ 2024-05-20 9:39 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 9:39 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename the selective fetch plane registers to match the spec.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr_regs.h | 10 +++++-----
> drivers/gpu/drm/i915/display/skl_universal_plane.c | 12 ++++++------
> 2 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 47e3a2e2977c..f0bd0a726d7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -276,23 +276,23 @@
> _SEL_FETCH_PLANE_BASE_A(plane))
>
> #define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> -#define PLANE_SEL_FETCH_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> _SEL_FETCH_PLANE_CTL_1_A - \
> _SEL_FETCH_PLANE_BASE_1_A)
> -#define PLANE_SEL_FETCH_CTL_ENABLE REG_BIT(31)
> +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
>
> #define _SEL_FETCH_PLANE_POS_1_A 0x70894
> -#define PLANE_SEL_FETCH_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> _SEL_FETCH_PLANE_POS_1_A - \
> _SEL_FETCH_PLANE_BASE_1_A)
>
> #define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
> -#define PLANE_SEL_FETCH_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> _SEL_FETCH_PLANE_SIZE_1_A - \
> _SEL_FETCH_PLANE_BASE_1_A)
>
> #define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
> -#define PLANE_SEL_FETCH_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> _SEL_FETCH_PLANE_OFFSET_1_A - \
> _SEL_FETCH_PLANE_BASE_1_A)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index d0bfee2ca643..6601baf18ae4 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -705,7 +705,7 @@ static void icl_plane_disable_sel_fetch_arm(struct intel_plane *plane,
> if (!crtc_state->enable_psr2_sel_fetch)
> return;
>
> - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id), 0);
> }
>
> static void
> @@ -1304,7 +1304,7 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
>
> val = (clip->y1 + plane_state->uapi.dst.y1) << 16;
> val |= plane_state->uapi.dst.x1;
> - intel_de_write_fw(i915, PLANE_SEL_FETCH_POS(pipe, plane->id), val);
> + intel_de_write_fw(i915, SEL_FETCH_PLANE_POS(pipe, plane->id), val);
>
> x = plane_state->view.color_plane[color_plane].x;
>
> @@ -1319,13 +1319,13 @@ static void icl_plane_update_sel_fetch_noarm(struct intel_plane *plane,
>
> val = y << 16 | x;
>
> - intel_de_write_fw(i915, PLANE_SEL_FETCH_OFFSET(pipe, plane->id),
> + intel_de_write_fw(i915, SEL_FETCH_PLANE_OFFSET(pipe, plane->id),
> val);
>
> /* Sizes are 0 based */
> val = (drm_rect_height(clip) - 1) << 16;
> val |= (drm_rect_width(&plane_state->uapi.src) >> 16) - 1;
> - intel_de_write_fw(i915, PLANE_SEL_FETCH_SIZE(pipe, plane->id), val);
> + intel_de_write_fw(i915, SEL_FETCH_PLANE_SIZE(pipe, plane->id), val);
> }
>
> static void
> @@ -1414,8 +1414,8 @@ static void icl_plane_update_sel_fetch_arm(struct intel_plane *plane,
> return;
>
> if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0)
> - intel_de_write_fw(i915, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> - PLANE_SEL_FETCH_CTL_ENABLE);
> + intel_de_write_fw(i915, SEL_FETCH_PLANE_CTL(pipe, plane->id),
> + SEL_FETCH_PLANE_CTL_ENABLE);
> else
> icl_plane_disable_sel_fetch_arm(plane, crtc_state);
> }
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition
2024-05-20 9:37 ` Jani Nikula
@ 2024-05-20 9:56 ` Hogander, Jouni
0 siblings, 0 replies; 49+ messages in thread
From: Hogander, Jouni @ 2024-05-20 9:56 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, intel-gfx@lists.freedesktop.org,
jani.nikula@linux.intel.com
On Mon, 2024-05-20 at 12:37 +0300, Jani Nikula wrote:
> On Mon, 20 May 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> > On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com>
> > wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > PIPESRC_ERLY_TPT is a pipe register, and it lives in the 0x70000
> > > range.
> > > so using _MMIO_TRANS2() for it is not really correct. Also since
> > > this
> > > is a pipe register, and not present on CHV, the registers will be
> > > equally spaced out, so we can use the simpler _MMIO_PIPE()
> > > instead
> > > of _MMIO_PIPE2().
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> Side note, while reviewing this I found this monstrosity:
>
> static bool intel_psr2_sel_fetch_config_valid(struct intel_dp
> *intel_dp,
> struct intel_crtc_state
> *crtc_state)
> {
> struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>
> if (!dev_priv->display.params.enable_psr2_sel_fetch &&
> intel_dp->psr.debug != I915_PSR_DEBUG_ENABLE_SEL_FETCH) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 sel fetch not enabled, disabled by
> parameter\n");
> return false;
> }
>
> if (crtc_state->uapi.async_flip) {
> drm_dbg_kms(&dev_priv->drm,
> "PSR2 sel fetch not enabled, async flip
> enabled\n");
> return false;
> }
>
> return crtc_state->enable_psr2_sel_fetch = true;
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> }
>
> Judging by name, a predicate function to check if config is valid,
> actually modifies the config in what looks like a typoed return
> statement. Ugh.
Yes, I have inhaled this already enough that it begun to look like
normal.
BR,
Jouni Högander
>
> BR,
> Jani.
>
>
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h
2024-05-16 13:56 ` [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h Ville Syrjala
@ 2024-05-20 13:07 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:07 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> PIPEGCMAX was left behind when all other gamma registers moved
> into intel_color_regs.h.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color_regs.h | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 4 ----
> 2 files changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
> index bb99ea533842..61c18b4a7fa5 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
> @@ -36,6 +36,11 @@
> _CHV_PALETTE_C, _CHV_PALETTE_C) + \
> (i) * 4)
>
> +/* i965/g4x/vlv/chv */
> +#define _PIPEAGCMAX 0x70010
> +#define _PIPEBGCMAX 0x71010
> +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */
> +
> /* ilk+ palette */
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 52b029cd3981..f5e8833cc37e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1882,10 +1882,6 @@
> #define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL)
> #define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT)
>
> -#define _PIPEAGCMAX 0x70010
> -#define _PIPEBGCMAX 0x71010
> -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */
> -
> #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */
> #define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A)
> #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13)
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h
2024-05-16 13:56 ` [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h Ville Syrjala
@ 2024-05-20 13:09 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:09 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx; +Cc: Zhenyu Wang, Zhi Wang
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Relocate all pre-skl primary plane register definitions
> into their own declutter i915_reg.h.
>
> Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
> Cc: Zhi Wang <zhi.wang.linux@gmail.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/i9xx_plane.c | 1 +
> .../gpu/drm/i915/display/i9xx_plane_regs.h | 98 +++++++++++++++++++
> .../gpu/drm/i915/display/intel_atomic_plane.c | 1 +
> drivers/gpu/drm/i915/display/intel_color.c | 2 +-
> drivers/gpu/drm/i915/display/intel_display.c | 1 +
> drivers/gpu/drm/i915/display/intel_fbc.c | 1 +
> drivers/gpu/drm/i915/gvt/cmd_parser.c | 1 +
> drivers/gpu/drm/i915/gvt/display.c | 1 +
> drivers/gpu/drm/i915/gvt/fb_decoder.c | 1 +
> drivers/gpu/drm/i915/gvt/handlers.c | 1 +
> drivers/gpu/drm/i915/i915_reg.h | 87 +---------------
> drivers/gpu/drm/i915/intel_clock_gating.c | 1 +
> drivers/gpu/drm/i915/intel_gvt_mmio_table.c | 1 +
> 13 files changed, 110 insertions(+), 87 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/display/i9xx_plane_regs.h
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane.c b/drivers/gpu/drm/i915/display/i9xx_plane.c
> index ea4d8ba55ad8..1f05f9184cb2 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane.c
> @@ -10,6 +10,7 @@
>
> #include "i915_reg.h"
> #include "i9xx_plane.h"
> +#include "i9xx_plane_regs.h"
> #include "intel_atomic.h"
> #include "intel_atomic_plane.h"
> #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> new file mode 100644
> index 000000000000..0bf2cd42bce7
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> @@ -0,0 +1,98 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2024 Intel Corporation
> + */
> +
> +#ifndef __I9XX_PLANE_REGS_H__
> +#define __I9XX_PLANE_REGS_H__
> +
> +#include "intel_display_reg_defs.h"
> +
> +#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> +#define _DSPACNTR 0x70180
> +#define DISP_ENABLE REG_BIT(31)
> +#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
> +#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
> +#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
> +#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
> +#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
> +#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
> +#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
> +#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
> +#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
> +#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
> +#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
> +#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
> +#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
> +#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
> +#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
> +#define DISP_STEREO_ENABLE REG_BIT(25)
> +#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> +#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
> +#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
> +#define DISP_SRC_KEY_ENABLE REG_BIT(22)
> +#define DISP_LINE_DOUBLE REG_BIT(20)
> +#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
> +#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
> +#define DISP_ROTATE_180 REG_BIT(15)
> +#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
> +#define DISP_TILED REG_BIT(10)
> +#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
> +#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
> +#define _DSPAADDR 0x70184
> +#define _DSPASTRIDE 0x70188
> +#define _DSPAPOS 0x7018C /* reserved */
> +#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
> +#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
> +#define DISP_POS_X_MASK REG_GENMASK(15, 0)
> +#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
> +#define _DSPASIZE 0x70190
> +#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
> +#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
> +#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
> +#define _DSPASURF 0x7019C /* 965+ only */
> +#define DISP_ADDR_MASK REG_GENMASK(31, 12)
> +#define _DSPATILEOFF 0x701A4 /* 965+ only */
> +#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> +#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
> +#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
> +#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
> +#define _DSPAOFFSET 0x701A4 /* HSW */
> +#define _DSPASURFLIVE 0x701AC
> +#define _DSPAGAMC 0x701E0
> +
> +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
> +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
> +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
> +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
> +#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
> +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
> +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
> +#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
> +#define DSPLINOFF(plane) DSPADDR(plane)
> +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
> +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
> +#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
> +
> +/* CHV pipe B primary plane */
> +#define _PRIMPOS_A 0x60a08
> +#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
> +#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
> +#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
> +#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
> +#define _PRIMSIZE_A 0x60a0c
> +#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
> +#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
> +#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
> +#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
> +#define _PRIMCNSTALPHA_A 0x60a10
> +#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
> +#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> +#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
> +
> +#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
> +#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
> +#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
> +
> +#endif /* __I9XX_PLANE_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> index 27224ecdc94c..a2a827070c33 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
> @@ -40,6 +40,7 @@
>
> #include "i915_config.h"
> #include "i915_reg.h"
> +#include "i9xx_plane_regs.h"
> #include "intel_atomic_plane.h"
> #include "intel_cdclk.h"
> #include "intel_display_rps.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index d23163dc64d4..82b155708422 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -22,7 +22,7 @@
> *
> */
>
> -#include "i915_reg.h"
> +#include "i9xx_plane_regs.h"
> #include "intel_color.h"
> #include "intel_color_regs.h"
> #include "intel_de.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ee2df655b0ab..1e8e2fd52cf6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -54,6 +54,7 @@
> #include "i915_reg.h"
> #include "i915_utils.h"
> #include "i9xx_plane.h"
> +#include "i9xx_plane_regs.h"
> #include "i9xx_wm.h"
> #include "intel_atomic.h"
> #include "intel_atomic_plane.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
> index 50dd8eb9012e..680d7fc39503 100644
> --- a/drivers/gpu/drm/i915/display/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/display/intel_fbc.c
> @@ -48,6 +48,7 @@
> #include "i915_utils.h"
> #include "i915_vgpu.h"
> #include "i915_vma.h"
> +#include "i9xx_plane_regs.h"
> #include "intel_cdclk.h"
> #include "intel_de.h"
> #include "intel_display_device.h"
> diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> index 4be8cb65fb7e..2c315caf2414 100644
> --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
> +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
> @@ -49,6 +49,7 @@
> #include "i915_pvinfo.h"
> #include "trace.h"
>
> +#include "display/i9xx_plane_regs.h"
> #include "display/intel_display.h"
> #include "display/intel_sprite_regs.h"
> #include "gem/i915_gem_context.h"
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 73ea8be0f80b..dafa13ac826b 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -37,6 +37,7 @@
> #include "gvt.h"
>
> #include "display/bxt_dpio_phy_regs.h"
> +#include "display/i9xx_plane_regs.h"
> #include "display/intel_cursor_regs.h"
> #include "display/intel_display.h"
> #include "display/intel_dpio_phy.h"
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> index e78de423a6c7..521dee39e5fb 100644
> --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -40,6 +40,7 @@
> #include "i915_pvinfo.h"
> #include "i915_reg.h"
>
> +#include "display/i9xx_plane_regs.h"
> #include "display/intel_cursor_regs.h"
> #include "display/intel_sprite_regs.h"
> #include "display/skl_universal_plane_regs.h"
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 6f633035618e..27ef6dfee641 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -42,6 +42,7 @@
> #include "i915_pvinfo.h"
> #include "intel_mchbar_regs.h"
> #include "display/bxt_dpio_phy_regs.h"
> +#include "display/i9xx_plane_regs.h"
> #include "display/intel_cursor_regs.h"
> #include "display/intel_display_types.h"
> #include "display/intel_dmc_regs.h"
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index f5e8833cc37e..29f69ad8f704 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2260,75 +2260,7 @@
> #define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X)
> #define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X)
>
> -/* Display A control */
> -#define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> -#define _DSPACNTR 0x70180
> -#define DISP_ENABLE REG_BIT(31)
> -#define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
> -#define DISP_FORMAT_MASK REG_GENMASK(29, 26)
> -#define DISP_FORMAT_8BPP REG_FIELD_PREP(DISP_FORMAT_MASK, 2)
> -#define DISP_FORMAT_BGRA555 REG_FIELD_PREP(DISP_FORMAT_MASK, 3)
> -#define DISP_FORMAT_BGRX555 REG_FIELD_PREP(DISP_FORMAT_MASK, 4)
> -#define DISP_FORMAT_BGRX565 REG_FIELD_PREP(DISP_FORMAT_MASK, 5)
> -#define DISP_FORMAT_BGRX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 6)
> -#define DISP_FORMAT_BGRA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 7)
> -#define DISP_FORMAT_RGBX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 8)
> -#define DISP_FORMAT_RGBA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 9)
> -#define DISP_FORMAT_BGRX101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 10)
> -#define DISP_FORMAT_BGRA101010 REG_FIELD_PREP(DISP_FORMAT_MASK, 11)
> -#define DISP_FORMAT_RGBX161616 REG_FIELD_PREP(DISP_FORMAT_MASK, 12)
> -#define DISP_FORMAT_RGBX888 REG_FIELD_PREP(DISP_FORMAT_MASK, 14)
> -#define DISP_FORMAT_RGBA888 REG_FIELD_PREP(DISP_FORMAT_MASK, 15)
> -#define DISP_STEREO_ENABLE REG_BIT(25)
> -#define DISP_PIPE_CSC_ENABLE REG_BIT(24) /* ilk+ */
> -#define DISP_PIPE_SEL_MASK REG_GENMASK(25, 24)
> -#define DISP_PIPE_SEL(pipe) REG_FIELD_PREP(DISP_PIPE_SEL_MASK, (pipe))
> -#define DISP_SRC_KEY_ENABLE REG_BIT(22)
> -#define DISP_LINE_DOUBLE REG_BIT(20)
> -#define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
> -#define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
> -#define DISP_ROTATE_180 REG_BIT(15)
> -#define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
> -#define DISP_TILED REG_BIT(10)
> -#define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
> -#define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
> -#define _DSPAADDR 0x70184
> -#define _DSPASTRIDE 0x70188
> -#define _DSPAPOS 0x7018C /* reserved */
> -#define DISP_POS_Y_MASK REG_GENMASK(31, 16)
> -#define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
> -#define DISP_POS_X_MASK REG_GENMASK(15, 0)
> -#define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
> -#define _DSPASIZE 0x70190
> -#define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
> -#define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
> -#define DISP_WIDTH_MASK REG_GENMASK(15, 0)
> -#define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
> -#define _DSPASURF 0x7019C /* 965+ only */
> -#define DISP_ADDR_MASK REG_GENMASK(31, 12)
> -#define _DSPATILEOFF 0x701A4 /* 965+ only */
> -#define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> -#define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
> -#define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
> -#define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
> -#define _DSPAOFFSET 0x701A4 /* HSW */
> -#define _DSPASURFLIVE 0x701AC
> -#define _DSPAGAMC 0x701E0
> -
> -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
> -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
> -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
> -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
> -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
> -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
> -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
> -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
> -#define DSPLINOFF(plane) DSPADDR(plane)
> -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
> -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
> -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
> -
> -/* CHV pipe B blender and primary plane */
> +/* CHV pipe B blender */
> #define _CHV_BLEND_A 0x60a00
> #define CHV_BLEND_MASK REG_GENMASK(31, 30)
> #define CHV_BLEND_LEGACY REG_FIELD_PREP(CHV_BLEND_MASK, 0)
> @@ -2338,26 +2270,9 @@
> #define CHV_CANVAS_RED_MASK REG_GENMASK(29, 20)
> #define CHV_CANVAS_GREEN_MASK REG_GENMASK(19, 10)
> #define CHV_CANVAS_BLUE_MASK REG_GENMASK(9, 0)
> -#define _PRIMPOS_A 0x60a08
> -#define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
> -#define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
> -#define PRIM_POS_X_MASK REG_GENMASK(15, 0)
> -#define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
> -#define _PRIMSIZE_A 0x60a0c
> -#define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
> -#define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
> -#define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
> -#define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
> -#define _PRIMCNSTALPHA_A 0x60a10
> -#define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
> -#define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> -#define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
>
> #define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A)
> #define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A)
> -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
> -#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
> -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
>
> /* Display/Sprite base address macros */
> #define DISP_BASEADDR_MASK (0xfffff000)
> diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
> index 1dc5281b2ade..5c5685ebd49e 100644
> --- a/drivers/gpu/drm/i915/intel_clock_gating.c
> +++ b/drivers/gpu/drm/i915/intel_clock_gating.c
> @@ -25,6 +25,7 @@
> *
> */
>
> +#include "display/i9xx_plane_regs.h"
> #include "display/intel_de.h"
> #include "display/intel_display.h"
> #include "display/intel_display_trace.h"
> diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> index b485976976db..2375292292b6 100644
> --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c
> @@ -4,6 +4,7 @@
> */
>
> #include "display/bxt_dpio_phy_regs.h"
> +#include "display/i9xx_plane_regs.h"
> #include "display/intel_audio_regs.h"
> #include "display/intel_backlight_regs.h"
> #include "display/intel_color_regs.h"
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers
2024-05-16 13:56 ` [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers Ville Syrjala
@ 2024-05-20 13:12 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:12 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Group the pre-skl primary plane register definitions
> sensible, and toss in a few comments to indicate which
> platforms have what.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/i9xx_plane_regs.h | 46 ++++++++++++-------
> 1 file changed, 29 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> index 0bf2cd42bce7..929b26faf31e 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> @@ -9,7 +9,10 @@
> #include "intel_display_reg_defs.h"
>
> #define _DSPAADDR_VLV 0x7017C /* vlv/chv */
> +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
> +
> #define _DSPACNTR 0x70180
> +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
> #define DISP_ENABLE REG_BIT(31)
> #define DISP_PIPE_GAMMA_ENABLE REG_BIT(30)
> #define DISP_FORMAT_MASK REG_GENMASK(29, 26)
> @@ -39,60 +42,69 @@
> #define DISP_TILED REG_BIT(10)
> #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
> #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
> +
> #define _DSPAADDR 0x70184
> +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
> +
> +#define _DSPALINOFF 0x70184
> +#define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
> +
> #define _DSPASTRIDE 0x70188
> +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
> +
> #define _DSPAPOS 0x7018C /* reserved */
> +#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
> #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
> #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
> #define DISP_POS_X_MASK REG_GENMASK(15, 0)
> #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
> +
> #define _DSPASIZE 0x70190
> +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
> #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
> #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
> #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
> #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
> +
> #define _DSPASURF 0x7019C /* 965+ only */
> +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
> #define DISP_ADDR_MASK REG_GENMASK(31, 12)
> +
> #define _DSPATILEOFF 0x701A4 /* 965+ only */
> +#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
> #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
> #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
> +
> #define _DSPAOFFSET 0x701A4 /* HSW */
> +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
> +
> #define _DSPASURFLIVE 0x701AC
> +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
> +
> #define _DSPAGAMC 0x701E0
> -
> -#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV)
> -#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR)
> -#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
> -#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
> -#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
> -#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
> -#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
> -#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
> -#define DSPLINOFF(plane) DSPADDR(plane)
> -#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
> -#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
> -#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
> +#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
>
> /* CHV pipe B primary plane */
> #define _PRIMPOS_A 0x60a08
> +#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
> #define PRIM_POS_Y_MASK REG_GENMASK(31, 16)
> #define PRIM_POS_Y(y) REG_FIELD_PREP(PRIM_POS_Y_MASK, (y))
> #define PRIM_POS_X_MASK REG_GENMASK(15, 0)
> #define PRIM_POS_X(x) REG_FIELD_PREP(PRIM_POS_X_MASK, (x))
> +
> #define _PRIMSIZE_A 0x60a0c
> +#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
> #define PRIM_HEIGHT_MASK REG_GENMASK(31, 16)
> #define PRIM_HEIGHT(h) REG_FIELD_PREP(PRIM_HEIGHT_MASK, (h))
> #define PRIM_WIDTH_MASK REG_GENMASK(15, 0)
> #define PRIM_WIDTH(w) REG_FIELD_PREP(PRIM_WIDTH_MASK, (w))
> +
> #define _PRIMCNSTALPHA_A 0x60a10
> +#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
> #define PRIM_CONST_ALPHA_ENABLE REG_BIT(31)
> #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha))
>
> -#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A)
> -#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A)
> -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A)
> -
> #endif /* __I9XX_PLANE_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies
2024-05-16 13:56 ` [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies Ville Syrjala
@ 2024-05-20 13:16 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:16 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add some notes indicatign which plane registers/bits are
*indicating
> valid for which platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
because I'm not going to chase through all the specs for these. ;)
> ---
> .../gpu/drm/i915/display/i9xx_plane_regs.h | 22 +++++++++----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> index 929b26faf31e..d74a74d1f29a 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/i9xx_plane_regs.h
> @@ -37,53 +37,53 @@
> #define DISP_LINE_DOUBLE REG_BIT(20)
> #define DISP_STEREO_POLARITY_SECOND REG_BIT(18)
> #define DISP_ALPHA_PREMULTIPLY REG_BIT(16) /* CHV pipe B */
> -#define DISP_ROTATE_180 REG_BIT(15)
> +#define DISP_ROTATE_180 REG_BIT(15) /* i965+ */
> #define DISP_TRICKLE_FEED_DISABLE REG_BIT(14) /* g4x+ */
> -#define DISP_TILED REG_BIT(10)
> +#define DISP_TILED REG_BIT(10) /* i965+ */
> #define DISP_ASYNC_FLIP REG_BIT(9) /* g4x+ */
> #define DISP_MIRROR REG_BIT(8) /* CHV pipe B */
>
> -#define _DSPAADDR 0x70184
> +#define _DSPAADDR 0x70184 /* pre-i965 */
> #define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR)
>
> -#define _DSPALINOFF 0x70184
> +#define _DSPALINOFF 0x70184 /* i965+ */
> #define DSPLINOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPALINOFF)
>
> #define _DSPASTRIDE 0x70188
> #define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE)
>
> -#define _DSPAPOS 0x7018C /* reserved */
> +#define _DSPAPOS 0x7018C /* pre-g4x */
> #define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS)
> #define DISP_POS_Y_MASK REG_GENMASK(31, 16)
> #define DISP_POS_Y(y) REG_FIELD_PREP(DISP_POS_Y_MASK, (y))
> #define DISP_POS_X_MASK REG_GENMASK(15, 0)
> #define DISP_POS_X(x) REG_FIELD_PREP(DISP_POS_X_MASK, (x))
>
> -#define _DSPASIZE 0x70190
> +#define _DSPASIZE 0x70190 /* pre-g4x */
> #define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE)
> #define DISP_HEIGHT_MASK REG_GENMASK(31, 16)
> #define DISP_HEIGHT(h) REG_FIELD_PREP(DISP_HEIGHT_MASK, (h))
> #define DISP_WIDTH_MASK REG_GENMASK(15, 0)
> #define DISP_WIDTH(w) REG_FIELD_PREP(DISP_WIDTH_MASK, (w))
>
> -#define _DSPASURF 0x7019C /* 965+ only */
> +#define _DSPASURF 0x7019C /* i965+ */
> #define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF)
> #define DISP_ADDR_MASK REG_GENMASK(31, 12)
>
> -#define _DSPATILEOFF 0x701A4 /* 965+ only */
> +#define _DSPATILEOFF 0x701A4 /* i965+ */
> #define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF)
> #define DISP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define DISP_OFFSET_Y(y) REG_FIELD_PREP(DISP_OFFSET_Y_MASK, (y))
> #define DISP_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define DISP_OFFSET_X(x) REG_FIELD_PREP(DISP_OFFSET_X_MASK, (x))
>
> -#define _DSPAOFFSET 0x701A4 /* HSW */
> +#define _DSPAOFFSET 0x701A4 /* hsw+ */
> #define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET)
>
> -#define _DSPASURFLIVE 0x701AC
> +#define _DSPASURFLIVE 0x701AC /* g4x+ */
> #define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE)
>
> -#define _DSPAGAMC 0x701E0
> +#define _DSPAGAMC 0x701E0 /* pre-g4x */
> #define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
>
> /* CHV pipe B primary plane */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions
2024-05-16 13:56 ` [PATCH 12/13] drm/i915: Polish sprite plane register definitions Ville Syrjala
@ 2024-05-20 13:17 ` Jani Nikula
2024-05-20 13:18 ` Jani Nikula
0 siblings, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:17 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Group the sprite plane register definitions such that everything
> to do wiht the same register is in one place.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++++++++++--------
> 1 file changed, 134 insertions(+), 97 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> index bb67705652b2..c27adbaf0f00 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> @@ -7,6 +7,8 @@
> #include "intel_display_reg_defs.h"
>
> #define _DVSACNTR 0x72180
> +#define _DVSBCNTR 0x73180
> +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> #define DVS_ENABLE REG_BIT(31)
> #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
> #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
> @@ -28,31 +30,67 @@
> #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
> #define DVS_TILED REG_BIT(10)
> #define DVS_DEST_KEY REG_BIT(2)
> +
> #define _DVSALINOFF 0x72184
> +#define _DVSBLINOFF 0x73184
> +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
> +
> #define _DVSASTRIDE 0x72188
> +#define _DVSBSTRIDE 0x73188
> +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
> +
> #define _DVSAPOS 0x7218c
> +#define _DVSBPOS 0x7318c
> +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
> #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
> #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
> #define DVS_POS_X_MASK REG_GENMASK(15, 0)
> #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
> +
> #define _DVSASIZE 0x72190
> +#define _DVSBSIZE 0x73190
> +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
> #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
> #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
> #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
> #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
> +
> #define _DVSAKEYVAL 0x72194
> +#define _DVSBKEYVAL 0x73194
> +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> +
> #define _DVSAKEYMSK 0x72198
> +#define _DVSBKEYMSK 0x73198
> +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> +
> #define _DVSASURF 0x7219c
> +#define _DVSBSURF 0x7319c
> +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
> #define DVS_ADDR_MASK REG_GENMASK(31, 12)
> +
> #define _DVSAKEYMAXVAL 0x721a0
> +#define _DVSBKEYMAXVAL 0x731a0
> +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
> +
> #define _DVSATILEOFF 0x721a4
> +#define _DVSBTILEOFF 0x731a4
> +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
> #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
> #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
> +
> #define _DVSASURFLIVE 0x721ac
> +#define _DVSBSURFLIVE 0x731ac
> +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
> +
> #define _DVSAGAMC_G4X 0x721e0 /* g4x */
> +#define _DVSBGAMC_G4X 0x731e0 /* g4x */
> +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
> +
> #define _DVSASCALE 0x72204
> +#define _DVSBSCALE 0x73204
> +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
> #define DVS_SCALE_ENABLE REG_BIT(31)
> #define DVS_FILTER_MASK REG_GENMASK(30, 29)
> #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
> @@ -64,42 +102,18 @@
> #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
> #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
> +
> #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
> -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
> -
> -#define _DVSBCNTR 0x73180
> -#define _DVSBLINOFF 0x73184
> -#define _DVSBSTRIDE 0x73188
> -#define _DVSBPOS 0x7318c
> -#define _DVSBSIZE 0x73190
> -#define _DVSBKEYVAL 0x73194
> -#define _DVSBKEYMSK 0x73198
> -#define _DVSBSURF 0x7319c
> -#define _DVSBKEYMAXVAL 0x731a0
> -#define _DVSBTILEOFF 0x731a4
> -#define _DVSBSURFLIVE 0x731ac
> -#define _DVSBGAMC_G4X 0x731e0 /* g4x */
> -#define _DVSBSCALE 0x73204
> #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
> -#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
> -
> -#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> -#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
> -#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
> -#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
> -#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
> -#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
> -#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
> -#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
> -#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
> -#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
> -#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
> -#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
> -#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
> #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
> +
> +#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
> +#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
> #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
>
> #define _SPRA_CTL 0x70280
> +#define _SPRB_CTL 0x71280
> +#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> #define SPRITE_ENABLE REG_BIT(31)
> #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
> #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
> @@ -125,31 +139,67 @@
> #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
> #define SPRITE_TILED REG_BIT(10)
> #define SPRITE_DEST_KEY REG_BIT(2)
> +
> #define _SPRA_LINOFF 0x70284
> +#define _SPRB_LINOFF 0x71284
> +#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
> +
> #define _SPRA_STRIDE 0x70288
> +#define _SPRB_STRIDE 0x71288
> +#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
> +
> #define _SPRA_POS 0x7028c
> +#define _SPRB_POS 0x7128c
> +#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
> #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
> #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
> #define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
> #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
> +
> #define _SPRA_SIZE 0x70290
> +#define _SPRB_SIZE 0x71290
> +#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
> #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
> #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
> #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
> #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
> +
> #define _SPRA_KEYVAL 0x70294
> +#define _SPRB_KEYVAL 0x71294
> +#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
> +
> #define _SPRA_KEYMSK 0x70298
> +#define _SPRB_KEYMSK 0x71298
> +#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
> +
> #define _SPRA_SURF 0x7029c
> +#define _SPRB_SURF 0x7129c
> +#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> #define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
> +
> #define _SPRA_KEYMAX 0x702a0
> +#define _SPRB_KEYMAX 0x712a0
> +#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> +
> #define _SPRA_TILEOFF 0x702a4
> +#define _SPRB_TILEOFF 0x712a4
> +#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
> #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
> +
> #define _SPRA_OFFSET 0x702a4
> +#define _SPRB_OFFSET 0x712a4
> +#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> +
> #define _SPRA_SURFLIVE 0x702ac
> +#define _SPRB_SURFLIVE 0x712ac
> +#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> +
> #define _SPRA_SCALE 0x70304
> +#define _SPRB_SCALE 0x71304
> +#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> #define SPRITE_SCALE_ENABLE REG_BIT(31)
> #define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
> #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
> @@ -161,45 +211,27 @@
> #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
> #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
> #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
> +
> #define _SPRA_GAMC 0x70400
> -#define _SPRA_GAMC16 0x70440
> -#define _SPRA_GAMC17 0x7044c
> -
> -#define _SPRB_CTL 0x71280
> -#define _SPRB_LINOFF 0x71284
> -#define _SPRB_STRIDE 0x71288
> -#define _SPRB_POS 0x7128c
> -#define _SPRB_SIZE 0x71290
> -#define _SPRB_KEYVAL 0x71294
> -#define _SPRB_KEYMSK 0x71298
> -#define _SPRB_SURF 0x7129c
> -#define _SPRB_KEYMAX 0x712a0
> -#define _SPRB_TILEOFF 0x712a4
> -#define _SPRB_OFFSET 0x712a4
> -#define _SPRB_SURFLIVE 0x712ac
> -#define _SPRB_SCALE 0x71304
> #define _SPRB_GAMC 0x71400
> -#define _SPRB_GAMC16 0x71440
> -#define _SPRB_GAMC17 0x7144c
> -
> -#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> -#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
> -#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
> -#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
> -#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
> -#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
> -#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
> -#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
> -#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
> -#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> -#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
> -#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
> +
> +#define _SPRA_GAMC16 0x70440
> +#define _SPRB_GAMC16 0x71440
> #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
> +
> +#define _SPRA_GAMC17 0x7044c
> +#define _SPRB_GAMC17 0x7144c
> #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
> -#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
> +
> +#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> + _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
> +#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> + _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
>
> #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
> +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
> +#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
> #define SP_ENABLE REG_BIT(31)
> #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
> #define SP_FORMAT_MASK REG_GENMASK(29, 26)
> @@ -225,80 +257,85 @@
> #define SP_ROTATE_180 REG_BIT(15)
> #define SP_TILED REG_BIT(10)
> #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
> +
> #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
> +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
> +#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
> +
> #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
> +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
> +#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
> +
> #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
> +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
> +#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
> #define SP_POS_Y_MASK REG_GENMASK(31, 16)
> #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
> #define SP_POS_X_MASK REG_GENMASK(15, 0)
> #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
> +
> #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
> +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
> +#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
> #define SP_HEIGHT_MASK REG_GENMASK(31, 16)
> #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
> #define SP_WIDTH_MASK REG_GENMASK(15, 0)
> #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
> +
> #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
> +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
> +#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
> +
> #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
> +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
> +#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
> +
> #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
> +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
> +#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
> #define SP_ADDR_MASK REG_GENMASK(31, 12)
> +
> #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
> +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
> +#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> +
> #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
> +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
> +#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
> #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
> #define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
> +
> #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
> +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> +#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
> #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
> #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
> +
> #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
> +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
> +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
> +
> #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
> +#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
> +#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
> #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
> #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
> #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
> #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
> +
> #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
> +#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
> +#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
> #define SP_SH_SIN_MASK REG_GENMASK(26, 16)
> #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
> #define SP_SH_COS_MASK REG_GENMASK(9, 0)
> #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
> +
> #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
> -
> -#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
> -#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
> -#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
> -#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
> -#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
> -#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
> -#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
> -#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
> -#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
> -#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
> -#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
> -#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
> -#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
> -#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
> #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
> -
> -#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> - _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
> -#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> - _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
> -
> -#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
> -#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
> -#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
> -#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
> -#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
> -#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
> -#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
> -#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
> -#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
> -#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
> -#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
> -#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
> -#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
> -#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
> #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
>
> /*
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 12/13] drm/i915: Polish sprite plane register definitions
2024-05-20 13:17 ` Jani Nikula
@ 2024-05-20 13:18 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:18 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Mon, 20 May 2024, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>>
>> Group the sprite plane register definitions such that everything
>> to do wiht the same register is in one place.
*with
>>
>> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>> ---
>> .../gpu/drm/i915/display/intel_sprite_regs.h | 231 ++++++++++--------
>> 1 file changed, 134 insertions(+), 97 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
>> index bb67705652b2..c27adbaf0f00 100644
>> --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
>> @@ -7,6 +7,8 @@
>> #include "intel_display_reg_defs.h"
>>
>> #define _DVSACNTR 0x72180
>> +#define _DVSBCNTR 0x73180
>> +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
>> #define DVS_ENABLE REG_BIT(31)
>> #define DVS_PIPE_GAMMA_ENABLE REG_BIT(30)
>> #define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27)
>> @@ -28,31 +30,67 @@
>> #define DVS_TRICKLE_FEED_DISABLE REG_BIT(14)
>> #define DVS_TILED REG_BIT(10)
>> #define DVS_DEST_KEY REG_BIT(2)
>> +
>> #define _DVSALINOFF 0x72184
>> +#define _DVSBLINOFF 0x73184
>> +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
>> +
>> #define _DVSASTRIDE 0x72188
>> +#define _DVSBSTRIDE 0x73188
>> +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
>> +
>> #define _DVSAPOS 0x7218c
>> +#define _DVSBPOS 0x7318c
>> +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
>> #define DVS_POS_Y_MASK REG_GENMASK(31, 16)
>> #define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y))
>> #define DVS_POS_X_MASK REG_GENMASK(15, 0)
>> #define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x))
>> +
>> #define _DVSASIZE 0x72190
>> +#define _DVSBSIZE 0x73190
>> +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
>> #define DVS_HEIGHT_MASK REG_GENMASK(31, 16)
>> #define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h))
>> #define DVS_WIDTH_MASK REG_GENMASK(15, 0)
>> #define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w))
>> +
>> #define _DVSAKEYVAL 0x72194
>> +#define _DVSBKEYVAL 0x73194
>> +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
>> +
>> #define _DVSAKEYMSK 0x72198
>> +#define _DVSBKEYMSK 0x73198
>> +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
>> +
>> #define _DVSASURF 0x7219c
>> +#define _DVSBSURF 0x7319c
>> +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
>> #define DVS_ADDR_MASK REG_GENMASK(31, 12)
>> +
>> #define _DVSAKEYMAXVAL 0x721a0
>> +#define _DVSBKEYMAXVAL 0x731a0
>> +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
>> +
>> #define _DVSATILEOFF 0x721a4
>> +#define _DVSBTILEOFF 0x731a4
>> +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
>> #define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16)
>> #define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y))
>> #define DVS_OFFSET_X_MASK REG_GENMASK(15, 0)
>> #define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x))
>> +
>> #define _DVSASURFLIVE 0x721ac
>> +#define _DVSBSURFLIVE 0x731ac
>> +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
>> +
>> #define _DVSAGAMC_G4X 0x721e0 /* g4x */
>> +#define _DVSBGAMC_G4X 0x731e0 /* g4x */
>> +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
>> +
>> #define _DVSASCALE 0x72204
>> +#define _DVSBSCALE 0x73204
>> +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
>> #define DVS_SCALE_ENABLE REG_BIT(31)
>> #define DVS_FILTER_MASK REG_GENMASK(30, 29)
>> #define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0)
>> @@ -64,42 +102,18 @@
>> #define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w))
>> #define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
>> #define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h))
>> +
>> #define _DVSAGAMC_ILK 0x72300 /* ilk/snb */
>> -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
>> -
>> -#define _DVSBCNTR 0x73180
>> -#define _DVSBLINOFF 0x73184
>> -#define _DVSBSTRIDE 0x73188
>> -#define _DVSBPOS 0x7318c
>> -#define _DVSBSIZE 0x73190
>> -#define _DVSBKEYVAL 0x73194
>> -#define _DVSBKEYMSK 0x73198
>> -#define _DVSBSURF 0x7319c
>> -#define _DVSBKEYMAXVAL 0x731a0
>> -#define _DVSBTILEOFF 0x731a4
>> -#define _DVSBSURFLIVE 0x731ac
>> -#define _DVSBGAMC_G4X 0x731e0 /* g4x */
>> -#define _DVSBSCALE 0x73204
>> #define _DVSBGAMC_ILK 0x73300 /* ilk/snb */
>> -#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
>> -
>> -#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
>> -#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
>> -#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
>> -#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS)
>> -#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF)
>> -#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
>> -#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE)
>> -#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE)
>> -#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
>> -#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
>> -#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
>> -#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
>> -#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
>> #define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */
>> +
>> +#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */
>> +#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
>> #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
>>
>> #define _SPRA_CTL 0x70280
>> +#define _SPRB_CTL 0x71280
>> +#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
>> #define SPRITE_ENABLE REG_BIT(31)
>> #define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30)
>> #define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28)
>> @@ -125,31 +139,67 @@
>> #define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13)
>> #define SPRITE_TILED REG_BIT(10)
>> #define SPRITE_DEST_KEY REG_BIT(2)
>> +
>> #define _SPRA_LINOFF 0x70284
>> +#define _SPRB_LINOFF 0x71284
>> +#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
>> +
>> #define _SPRA_STRIDE 0x70288
>> +#define _SPRB_STRIDE 0x71288
>> +#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
>> +
>> #define _SPRA_POS 0x7028c
>> +#define _SPRB_POS 0x7128c
>> +#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
>> #define SPRITE_POS_Y_MASK REG_GENMASK(31, 16)
>> #define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y))
>> #define SPRITE_POS_X_MASK REG_GENMASK(15, 0)
>> #define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x))
>> +
>> #define _SPRA_SIZE 0x70290
>> +#define _SPRB_SIZE 0x71290
>> +#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
>> #define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16)
>> #define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h))
>> #define SPRITE_WIDTH_MASK REG_GENMASK(15, 0)
>> #define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w))
>> +
>> #define _SPRA_KEYVAL 0x70294
>> +#define _SPRB_KEYVAL 0x71294
>> +#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
>> +
>> #define _SPRA_KEYMSK 0x70298
>> +#define _SPRB_KEYMSK 0x71298
>> +#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
>> +
>> #define _SPRA_SURF 0x7029c
>> +#define _SPRB_SURF 0x7129c
>> +#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
>> #define SPRITE_ADDR_MASK REG_GENMASK(31, 12)
>> +
>> #define _SPRA_KEYMAX 0x702a0
>> +#define _SPRB_KEYMAX 0x712a0
>> +#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
>> +
>> #define _SPRA_TILEOFF 0x702a4
>> +#define _SPRB_TILEOFF 0x712a4
>> +#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
>> #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
>> #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
>> #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
>> #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
>> +
>> #define _SPRA_OFFSET 0x702a4
>> +#define _SPRB_OFFSET 0x712a4
>> +#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
>> +
>> #define _SPRA_SURFLIVE 0x702ac
>> +#define _SPRB_SURFLIVE 0x712ac
>> +#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>> +
>> #define _SPRA_SCALE 0x70304
>> +#define _SPRB_SCALE 0x71304
>> +#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
>> #define SPRITE_SCALE_ENABLE REG_BIT(31)
>> #define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
>> #define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0)
>> @@ -161,45 +211,27 @@
>> #define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w))
>> #define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0)
>> #define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h))
>> +
>> #define _SPRA_GAMC 0x70400
>> -#define _SPRA_GAMC16 0x70440
>> -#define _SPRA_GAMC17 0x7044c
>> -
>> -#define _SPRB_CTL 0x71280
>> -#define _SPRB_LINOFF 0x71284
>> -#define _SPRB_STRIDE 0x71288
>> -#define _SPRB_POS 0x7128c
>> -#define _SPRB_SIZE 0x71290
>> -#define _SPRB_KEYVAL 0x71294
>> -#define _SPRB_KEYMSK 0x71298
>> -#define _SPRB_SURF 0x7129c
>> -#define _SPRB_KEYMAX 0x712a0
>> -#define _SPRB_TILEOFF 0x712a4
>> -#define _SPRB_OFFSET 0x712a4
>> -#define _SPRB_SURFLIVE 0x712ac
>> -#define _SPRB_SCALE 0x71304
>> #define _SPRB_GAMC 0x71400
>> -#define _SPRB_GAMC16 0x71440
>> -#define _SPRB_GAMC17 0x7144c
>> -
>> -#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
>> -#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
>> -#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
>> -#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS)
>> -#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
>> -#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
>> -#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
>> -#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
>> -#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
>> -#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
>> -#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
>> -#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
>> #define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */
>> +
>> +#define _SPRA_GAMC16 0x70440
>> +#define _SPRB_GAMC16 0x71440
>> #define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */
>> +
>> +#define _SPRA_GAMC17 0x7044c
>> +#define _SPRB_GAMC17 0x7144c
>> #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
>> -#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>> +
>> +#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
>> + _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
>> +#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
>> + _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
>>
>> #define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
>> +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
>> +#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
>> #define SP_ENABLE REG_BIT(31)
>> #define SP_PIPE_GAMMA_ENABLE REG_BIT(30)
>> #define SP_FORMAT_MASK REG_GENMASK(29, 26)
>> @@ -225,80 +257,85 @@
>> #define SP_ROTATE_180 REG_BIT(15)
>> #define SP_TILED REG_BIT(10)
>> #define SP_MIRROR REG_BIT(8) /* CHV pipe B */
>> +
>> #define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
>> +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
>> +#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
>> +
>> #define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
>> +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
>> +#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
>> +
>> #define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
>> +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
>> +#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
>> #define SP_POS_Y_MASK REG_GENMASK(31, 16)
>> #define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y))
>> #define SP_POS_X_MASK REG_GENMASK(15, 0)
>> #define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x))
>> +
>> #define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
>> +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
>> +#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
>> #define SP_HEIGHT_MASK REG_GENMASK(31, 16)
>> #define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h))
>> #define SP_WIDTH_MASK REG_GENMASK(15, 0)
>> #define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w))
>> +
>> #define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
>> +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
>> +#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
>> +
>> #define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
>> +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
>> +#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
>> +
>> #define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
>> +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
>> +#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
>> #define SP_ADDR_MASK REG_GENMASK(31, 12)
>> +
>> #define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
>> +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
>> +#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
>> +
>> #define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
>> +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
>> +#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
>> #define SP_OFFSET_Y_MASK REG_GENMASK(31, 16)
>> #define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y))
>> #define SP_OFFSET_X_MASK REG_GENMASK(15, 0)
>> #define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x))
>> +
>> #define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
>> +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
>> +#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
>> #define SP_CONST_ALPHA_ENABLE REG_BIT(31)
>> #define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0)
>> #define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha))
>> +
>> #define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac)
>> +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
>> +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
>> +
>> #define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0)
>> +#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
>> +#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
>> #define SP_CONTRAST_MASK REG_GENMASK(26, 18)
>> #define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */
>> #define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0)
>> #define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */
>> +
>> #define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4)
>> +#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
>> +#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
>> #define SP_SH_SIN_MASK REG_GENMASK(26, 16)
>> #define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */
>> #define SP_SH_COS_MASK REG_GENMASK(9, 0)
>> #define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */
>> +
>> #define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0)
>> -
>> -#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
>> -#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
>> -#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
>> -#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
>> -#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
>> -#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
>> -#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
>> -#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
>> -#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
>> -#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
>> -#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
>> -#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac)
>> -#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0)
>> -#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4)
>> #define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0)
>> -
>> -#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
>> - _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
>> -#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
>> - _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b)))
>> -
>> -#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR)
>> -#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF)
>> -#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE)
>> -#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS)
>> -#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE)
>> -#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
>> -#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK)
>> -#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF)
>> -#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
>> -#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF)
>> -#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
>> -#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
>> -#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0)
>> -#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1)
>> #define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */
>>
>> /*
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 13/13] drm/i915: Document which platforms use which sprite registers
2024-05-16 13:56 ` [PATCH 13/13] drm/i915: Document which platforms use which sprite registers Ville Syrjala
@ 2024-05-20 13:18 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:18 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Note which sprite registers are valid for which platforms.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_sprite_regs.h | 19 +++++++++++--------
> 1 file changed, 11 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> index c27adbaf0f00..73021e3ced6d 100644
> --- a/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h
> @@ -6,6 +6,7 @@
>
> #include "intel_display_reg_defs.h"
>
> +/* g4x/ilk/snb video sprite */
> #define _DVSACNTR 0x72180
> #define _DVSBCNTR 0x73180
> #define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR)
> @@ -111,6 +112,7 @@
> #define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */
> #define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */
>
> +/* ivb/hsw/bdw sprite */
> #define _SPRA_CTL 0x70280
> #define _SPRB_CTL 0x71280
> #define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
> @@ -140,8 +142,8 @@
> #define SPRITE_TILED REG_BIT(10)
> #define SPRITE_DEST_KEY REG_BIT(2)
>
> -#define _SPRA_LINOFF 0x70284
> -#define _SPRB_LINOFF 0x71284
> +#define _SPRA_LINOFF 0x70284 /* ivb */
> +#define _SPRB_LINOFF 0x71284 /* ivb */
> #define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
>
> #define _SPRA_STRIDE 0x70288
> @@ -181,24 +183,24 @@
> #define _SPRB_KEYMAX 0x712a0
> #define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
>
> -#define _SPRA_TILEOFF 0x702a4
> -#define _SPRB_TILEOFF 0x712a4
> +#define _SPRA_TILEOFF 0x702a4 /* ivb */
> +#define _SPRB_TILEOFF 0x712a4 /* ivb */
> #define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
> #define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16)
> #define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y))
> #define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0)
> #define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x))
>
> -#define _SPRA_OFFSET 0x702a4
> -#define _SPRB_OFFSET 0x712a4
> +#define _SPRA_OFFSET 0x702a4 /* hsw/bdw */
> +#define _SPRB_OFFSET 0x712a4 /* hsw/bdw */
> #define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
>
> #define _SPRA_SURFLIVE 0x702ac
> #define _SPRB_SURFLIVE 0x712ac
> #define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
>
> -#define _SPRA_SCALE 0x70304
> -#define _SPRB_SCALE 0x71304
> +#define _SPRA_SCALE 0x70304 /* ivb */
> +#define _SPRB_SCALE 0x71304 /* ivb */
> #define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
> #define SPRITE_SCALE_ENABLE REG_BIT(31)
> #define SPRITE_FILTER_MASK REG_GENMASK(30, 29)
> @@ -224,6 +226,7 @@
> #define _SPRB_GAMC17 0x7144c
> #define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */
>
> +/* vlv/chv sprite */
> #define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \
> _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b))
> #define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits
2024-05-16 13:56 ` [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits Ville Syrjala
@ 2024-05-20 13:24 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 13:24 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make a more thorough split between universal planes vs. cursors
> by defining the contents of the cursor WM/DDB registers separately.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I like this better than exposing the reg val functions.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cursor.c | 34 +++++++++++++++----
> .../gpu/drm/i915/display/intel_cursor_regs.h | 9 +++++
> .../drm/i915/display/skl_universal_plane.c | 4 +--
> .../drm/i915/display/skl_universal_plane.h | 3 --
> 4 files changed, 39 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> index 7983cbaf83f7..cea0cfed569d 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> @@ -24,7 +24,6 @@
> #include "intel_psr.h"
> #include "intel_psr_regs.h"
> #include "intel_vblank.h"
> -#include "skl_universal_plane.h"
> #include "skl_watermark.h"
>
> #include "gem/i915_gem_object.h"
> @@ -559,6 +558,29 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
> }
> }
>
> +static u32 skl_cursor_ddb_reg_val(const struct skl_ddb_entry *entry)
> +{
> + if (!entry->end)
> + return 0;
> +
> + return CUR_BUF_END(entry->end - 1) |
> + CUR_BUF_START(entry->start);
> +}
> +
> +static u32 skl_cursor_wm_reg_val(const struct skl_wm_level *level)
> +{
> + u32 val = 0;
> +
> + if (level->enable)
> + val |= CUR_WM_EN;
> + if (level->ignore_lines)
> + val |= CUR_WM_IGNORE_LINES;
> + val |= REG_FIELD_PREP(CUR_WM_BLOCKS_MASK, level->blocks);
> + val |= REG_FIELD_PREP(CUR_WM_LINES_MASK, level->lines);
> +
> + return val;
> +}
> +
> static void skl_write_cursor_wm(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state)
> {
> @@ -572,22 +594,22 @@ static void skl_write_cursor_wm(struct intel_plane *plane,
>
> for (level = 0; level < i915->display.wm.num_levels; level++)
> intel_de_write_fw(i915, CUR_WM(pipe, level),
> - skl_plane_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
> + skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
>
> intel_de_write_fw(i915, CUR_WM_TRANS(pipe),
> - skl_plane_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
> + skl_cursor_wm_reg_val(skl_plane_trans_wm(pipe_wm, plane_id)));
>
> if (HAS_HW_SAGV_WM(i915)) {
> const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
>
> intel_de_write_fw(i915, CUR_WM_SAGV(pipe),
> - skl_plane_wm_reg_val(&wm->sagv.wm0));
> + skl_cursor_wm_reg_val(&wm->sagv.wm0));
> intel_de_write_fw(i915, CUR_WM_SAGV_TRANS(pipe),
> - skl_plane_wm_reg_val(&wm->sagv.trans_wm));
> + skl_cursor_wm_reg_val(&wm->sagv.trans_wm));
> }
>
> intel_de_write_fw(i915, CUR_BUF_CFG(pipe),
> - skl_plane_ddb_reg_val(ddb));
> + skl_cursor_ddb_reg_val(ddb));
> }
>
> /* TODO: split into noarm+arm pair */
> diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> index ab02d497fba6..307a850d54b6 100644
> --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> @@ -78,6 +78,10 @@
> #define _CUR_WM_A_0 0x70140
> #define _CUR_WM_B_0 0x71140
> #define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
> +#define CUR_WM_EN REG_BIT(31)
> +#define CUR_WM_IGNORE_LINES REG_BIT(30)
> +#define CUR_WM_LINES_MASK REG_GENMASK(26, 14)
> +#define CUR_WM_BLOCKS_MASK REG_GENMASK(11, 0)
>
> #define _CUR_WM_SAGV_A 0x70158
> #define _CUR_WM_SAGV_B 0x71158
> @@ -94,6 +98,11 @@
> #define _CUR_BUF_CFG_A 0x7017c
> #define _CUR_BUF_CFG_B 0x7117c
> #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> +/* skl+: 10 bits, icl+ 11 bits, adlp+ 12 bits */
> +#define CUR_BUF_END_MASK REG_GENMASK(27, 16)
> +#define CUR_BUF_END(end) REG_FIELD_PREP(CUR_BUF_END_MASK, (end))
> +#define CUR_BUF_START_MASK REG_GENMASK(11, 0)
> +#define CUR_BUF_START(start) REG_FIELD_PREP(CUR_BUF_START_MASK, (start))
>
> #define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
> #define _SEL_FETCH_CUR_CTL_B 0x71880
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 6601baf18ae4..de51652358c9 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -622,7 +622,7 @@ static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> return stride / skl_plane_stride_mult(fb, color_plane, rotation);
> }
>
> -u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> +static u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> {
> if (!entry->end)
> return 0;
> @@ -631,7 +631,7 @@ u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry)
> PLANE_BUF_START(entry->start);
> }
>
> -u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> +static u32 skl_plane_wm_reg_val(const struct skl_wm_level *level)
> {
> u32 val = 0;
>
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.h b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> index 8eb4521ee851..541489479135 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.h
> @@ -37,7 +37,4 @@ bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
> u8 icl_hdr_plane_mask(void);
> bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id);
>
> -u32 skl_plane_ddb_reg_val(const struct skl_ddb_entry *entry);
> -u32 skl_plane_wm_reg_val(const struct skl_wm_level *level);
> -
> #endif
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
2024-05-20 9:10 ` Jani Nikula
@ 2024-05-20 16:23 ` Ville Syrjälä
2024-05-20 16:34 ` Jani Nikula
0 siblings, 1 reply; 49+ messages in thread
From: Ville Syrjälä @ 2024-05-20 16:23 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Group the cursor register defines such that everything to
> > do with one register is in one place.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> but a couple of nitpicks inline...
>
> > ---
> > .../gpu/drm/i915/display/intel_cursor_regs.h | 52 +++++++++----------
> > 1 file changed, 26 insertions(+), 26 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > index c2190af1e9f5..270c26c2e6df 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > @@ -9,6 +9,7 @@
> > #include "intel_display_reg_defs.h"
> >
> > #define _CURACNTR 0x70080
> > +#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURACNTR)
>
> In addition to code movement, these add braces around (dev_priv) and
> (pipe). While it makes review harder by breaking 'git show
> --color-moved',
Sorry. Forgot I snuck it in there.
> I also think it's kind of unnecessary when they're only
> passed on as parameters. Or is there some corner case where it matters?
I think cargo-culting is probably the best argument for protecting
each and every macro argument. If used universally then I think
it'll be a bit more likely that newly added macros, where it
might matter more, will inherit it as well.
And we've certainly had incidents with misplaced commas (the
i915_reg_t addition was a reaction to one such event), so I
wouldn't dare claim that there is zero chance of screwups
with these.
> Comma has the lowest precedence, and I don't think you could easily pass
> in a value with a comma operator.
>
> No need to change for this, it's not wrong either.
>
> > /* Old style CUR*CNTR flags (desktop 8xx) */
> > #define CURSOR_ENABLE REG_BIT(31)
> > #define CURSOR_PIPE_GAMMA_ENABLE REG_BIT(30)
> > @@ -38,61 +39,60 @@
> > #define MCURSOR_MODE_128_ARGB_AX (0x20 | MCURSOR_MODE_128_32B_AX)
> > #define MCURSOR_MODE_256_ARGB_AX (0x20 | MCURSOR_MODE_256_32B_AX)
> > #define MCURSOR_MODE_64_ARGB_AX (0x20 | MCURSOR_MODE_64_32B_AX)
> > +
> > #define _CURABASE 0x70084
> > +#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURABASE)
> > +
> > #define _CURAPOS 0x70088
> > -#define _CURAPOS_ERLY_TPT 0x7008c
> > +#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS)
> > #define CURSOR_POS_Y_SIGN REG_BIT(31)
> > #define CURSOR_POS_Y_MASK REG_GENMASK(30, 16)
> > #define CURSOR_POS_Y(y) REG_FIELD_PREP(CURSOR_POS_Y_MASK, (y))
> > #define CURSOR_POS_X_SIGN REG_BIT(15)
> > #define CURSOR_POS_X_MASK REG_GENMASK(14, 0)
> > #define CURSOR_POS_X(x) REG_FIELD_PREP(CURSOR_POS_X_MASK, (x))
> > +
> > +#define _CURAPOS_ERLY_TPT 0x7008c
> > +#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURAPOS_ERLY_TPT)
> > +
> > #define _CURASIZE 0x700a0 /* 845/865 */
> > +#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASIZE)
> > #define CURSOR_HEIGHT_MASK REG_GENMASK(21, 12)
> > #define CURSOR_HEIGHT(h) REG_FIELD_PREP(CURSOR_HEIGHT_MASK, (h))
> > #define CURSOR_WIDTH_MASK REG_GENMASK(9, 0)
> > #define CURSOR_WIDTH(w) REG_FIELD_PREP(CURSOR_WIDTH_MASK, (w))
> > +
> > #define _CUR_FBC_CTL_A 0x700a0 /* ivb+ */
> > +#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_FBC_CTL_A)
> > #define CUR_FBC_EN REG_BIT(31)
> > #define CUR_FBC_HEIGHT_MASK REG_GENMASK(7, 0)
> > #define CUR_FBC_HEIGHT(h) REG_FIELD_PREP(CUR_FBC_HEIGHT_MASK, (h))
> > +
> > #define _CUR_CHICKEN_A 0x700a4 /* mtl+ */
> > +#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CUR_CHICKEN_A)
> > +
> > #define _CURASURFLIVE 0x700ac /* g4x+ */
> > -#define _CURBCNTR 0x700c0
> > -#define _CURBBASE 0x700c4
> > -#define _CURBPOS 0x700c8
> > -
> > -#define _CURBCNTR_IVB 0x71080
> > -#define _CURBBASE_IVB 0x71084
> > -#define _CURBPOS_IVB 0x71088
> > -
> > -#define CURCNTR(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR)
> > -#define CURBASE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE)
> > -#define CURPOS(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS)
> > -#define CURPOS_ERLY_TPT(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT)
> > -#define CURSIZE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE)
> > -#define CUR_FBC_CTL(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A)
> > -#define CUR_CHICKEN(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A)
> > -#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE)
> > +#define CURSURFLIVE(dev_priv, pipe) _MMIO_CURSOR2((dev_priv), (pipe), _CURASURFLIVE)
> >
> > /* skl+ */
> > #define _CUR_WM_A_0 0x70140
> > #define _CUR_WM_B_0 0x71140
> > +#define CUR_WM(pipe, level) _MMIO(_PIPE((pipe), _CUR_WM_A_0, _CUR_WM_B_0) + (level) * 4)
> > +
> > #define _CUR_WM_SAGV_A 0x70158
> > #define _CUR_WM_SAGV_B 0x71158
> > +#define CUR_WM_SAGV(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> > +
> > #define _CUR_WM_SAGV_TRANS_A 0x7015C
> > #define _CUR_WM_SAGV_TRANS_B 0x7115C
> > +#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> > +
> > #define _CUR_WM_TRANS_A 0x70168
> > #define _CUR_WM_TRANS_B 0x71168
> > -#define _CUR_WM_0(pipe) _PIPE(pipe, _CUR_WM_A_0, _CUR_WM_B_0)
> > -#define CUR_WM(pipe, level) _MMIO(_CUR_WM_0(pipe) + ((4) * (level)))
>
> There's some unmentioned drive-by cleanup here too. No biggie, but I've
> found 'git show --color-moved' to be such a powerful aid in reviewing
> code movement patches that I'd prefer these to be separate. No need to
> change now, because I already reviewed it. :)
Agreed. I suppose I got a bit of tunnel vision here and didn't do
a proper job of reviewing my own stuff before sending it out.
I'll need to add --color-moved to my "this should be pure
code movement" checklist...
>
> BR,
> Jani.
>
> > -#define CUR_WM_SAGV(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_A, _CUR_WM_SAGV_B)
> > -#define CUR_WM_SAGV_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_SAGV_TRANS_A, _CUR_WM_SAGV_TRANS_B)
> > -#define CUR_WM_TRANS(pipe) _MMIO_PIPE(pipe, _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> > +#define CUR_WM_TRANS(pipe) _MMIO_PIPE((pipe), _CUR_WM_TRANS_A, _CUR_WM_TRANS_B)
> >
> > -/* skl+ */
> > -#define _CUR_BUF_CFG_A 0x7017c
> > -#define _CUR_BUF_CFG_B 0x7117c
> > -#define CUR_BUF_CFG(pipe) _MMIO_PIPE(pipe, _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> > +#define _CUR_BUF_CFG_A 0x7017c
> > +#define _CUR_BUF_CFG_B 0x7117c
> > +#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> >
> > #endif /* __INTEL_CURSOR_REGS_H__ */
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 02/13] drm/i915: Clean up the cursor register defines
2024-05-20 16:23 ` Ville Syrjälä
@ 2024-05-20 16:34 ` Jani Nikula
0 siblings, 0 replies; 49+ messages in thread
From: Jani Nikula @ 2024-05-20 16:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, 20 May 2024, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Mon, May 20, 2024 at 12:10:30PM +0300, Jani Nikula wrote:
>> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
>> I also think it's kind of unnecessary when they're only
>> passed on as parameters. Or is there some corner case where it matters?
>
> I think cargo-culting is probably the best argument for protecting
> each and every macro argument. If used universally then I think
> it'll be a bit more likely that newly added macros, where it
> might matter more, will inherit it as well.
That's a good point.
BR,
Jani.
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
2024-05-20 9:27 ` Jani Nikula
@ 2024-05-20 17:08 ` Ville Syrjälä
0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2024-05-20 17:08 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Mon, May 20, 2024 at 12:27:20PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Split the cursor stuff from the rest of the selective fetch
> > plane registers so that we can collect all cursor registers
> > in intel_cursor_regs.h. Also take the opportunity to rename
> > the registers to match the spec.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
> > drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +++++
> > 2 files changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
> > index c780ce146131..b44809899502 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor.c
> > @@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
> > if (!crtc_state->enable_psr2_sel_fetch)
> > return;
> >
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
> > + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
> > }
> >
> > static void wa_16021440873(struct intel_plane *plane,
> > @@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
> > ctl &= ~MCURSOR_MODE_MASK;
> > ctl |= MCURSOR_MODE_64_2B;
> >
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
> > + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
> >
> > intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
> > PIPESRC_HEIGHT(et_y_position));
> > @@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
> > val);
> > }
> >
> > - intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
> > + intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
> > plane_state->ctl);
> > } else {
> > /* Wa_16021440873 */
> > diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > index 270c26c2e6df..ab02d497fba6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
> > @@ -95,4 +95,9 @@
> > #define _CUR_BUF_CFG_B 0x7117c
> > #define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
> >
> > +#define _SEL_FETCH_CUR_CTL_A 0x70880 /* mtl+ */
> > +#define _SEL_FETCH_CUR_CTL_B 0x71880
> > +#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_A)
>
> _SEL_FETCH_CUR_CTL_A is doubled, the latter should be _B.
Derp. I also don't know where I got that mtl+ note. I must have been
thinking about early transport or something, but selective fetch
in general should be a thing for tgl+.
>
> With that,
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
> I must admit I was trying to follow how PLANE_SEL_FETCH_CTL(pipe,
> CURSOR_A) ends up being identical to this new SEL_FETCH_CUR_CTL(pipe),
> but holy crap it trips my brain completely. How did we come up with so
> many levels of abstractions for this stuff, in such complicated ways?!
> :o
>
>
> > +#define SEL_FETCH_CUR_CTL_ENABLE REG_BIT(31)
> > +
> > #endif /* __INTEL_CURSOR_REGS_H__ */
>
> --
> Jani Nikula, Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* [PATCH v2 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
2024-05-16 13:56 ` [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Ville Syrjala
2024-05-20 9:27 ` Jani Nikula
@ 2024-05-20 17:14 ` Ville Syrjala
1 sibling, 0 replies; 49+ messages in thread
From: Ville Syrjala @ 2024-05-20 17:14 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split the cursor stuff from the rest of the selective fetch
plane registers so that we can collect all cursor registers
in intel_cursor_regs.h. Also take the opportunity to rename
the registers to match the spec.
v2: Pass the correct register offset fpr pipe B (Jani)
s/mtl+/tgl+/ as that's where this was introduced
Drop the bogus SEL_FETCH_CUR_CTL_ENABLE bit, the contents
actually match the normal CUR_CTL register
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_cursor.c | 6 +++---
drivers/gpu/drm/i915/display/intel_cursor_regs.h | 5 +++++
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index c780ce146131..b44809899502 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -508,7 +508,7 @@ static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
if (!crtc_state->enable_psr2_sel_fetch)
return;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), 0);
}
static void wa_16021440873(struct intel_plane *plane,
@@ -523,7 +523,7 @@ static void wa_16021440873(struct intel_plane *plane,
ctl &= ~MCURSOR_MODE_MASK;
ctl |= MCURSOR_MODE_64_2B;
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe), ctl);
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(dev_priv, pipe),
PIPESRC_HEIGHT(et_y_position));
@@ -548,7 +548,7 @@ static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
val);
}
- intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
+ intel_de_write_fw(dev_priv, SEL_FETCH_CUR_CTL(pipe),
plane_state->ctl);
} else {
/* Wa_16021440873 */
diff --git a/drivers/gpu/drm/i915/display/intel_cursor_regs.h b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
index 270c26c2e6df..e58930ff32ea 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cursor_regs.h
@@ -95,4 +95,9 @@
#define _CUR_BUF_CFG_B 0x7117c
#define CUR_BUF_CFG(pipe) _MMIO_PIPE((pipe), _CUR_BUF_CFG_A, _CUR_BUF_CFG_B)
+/* tgl+ */
+#define _SEL_FETCH_CUR_CTL_A 0x70880
+#define _SEL_FETCH_CUR_CTL_B 0x71880
+#define SEL_FETCH_CUR_CTL(pipe) _MMIO_PIPE((pipe), _SEL_FETCH_CUR_CTL_A, _SEL_FETCH_CUR_CTL_B)
+
#endif /* __INTEL_CURSOR_REGS_H__ */
--
2.44.1
^ permalink raw reply related [flat|nested] 49+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (19 preceding siblings ...)
2024-05-18 5:46 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2024-05-20 18:08 ` Patchwork
2024-05-20 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-20 18:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/133701/
State : warning
== Summary ==
Error: dim checkpatch failed
9638afbf50ae drm/i915: Add skl+ plane name aliases to enum plane_id
4d3ce0118a4b drm/i915: Clean up the cursor register defines
49ffeb900e72 drm/i915: Add separate define for SEL_FETCH_CUR_CTL()
e5eefbbe6b08 drm/i915: Simplify PIPESRC_ERLY_TPT definition
-:55: WARNING:LONG_LINE: line length of 106 exceeds 100 columns
#55: FILE: drivers/gpu/drm/i915/display/intel_psr_regs.h:256:
+#define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
total: 0 errors, 1 warnings, 0 checks, 26 lines checked
49bf1f81d37a drm/i915: Rename selective fetch plane registers
26034ecefc36 drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
-:90: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20:
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
-:90: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#90: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:20:
+#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
+ _PICK_EVEN_2RANGES((plane), PLANE_5, \
+ _PIPE((pipe), (reg_1_a), (reg_1_b)), \
+ _PIPE((pipe), (reg_2_a), (reg_2_b)), \
+ _PIPE((pipe), (reg_5_a), (reg_5_b)), \
+ _PIPE((pipe), (reg_6_a), (reg_6_b)))
-:96: WARNING:LONG_LINE: line length of 110 exceeds 100 columns
#96: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:26:
+#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
-:117: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#117: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:390:
+ _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \
-:118: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#118: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:391:
+ _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \
-:119: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#119: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:392:
+ _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \
-:120: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#120: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:393:
+ _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B)
-:132: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#132: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:405:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:133: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#133: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:406:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:134: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#134: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:407:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:135: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#135: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:408:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
-:146: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#146: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:419:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:147: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#147: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:420:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:148: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#148: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:421:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:149: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#149: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:422:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
-:160: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#160: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:433:
+ _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
-:161: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#161: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:434:
+ _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
-:162: WARNING:LONG_LINE: line length of 117 exceeds 100 columns
#162: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:435:
+ _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
-:163: WARNING:LONG_LINE: line length of 115 exceeds 100 columns
#163: FILE: drivers/gpu/drm/i915/display/skl_universal_plane_regs.h:436:
+ _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
total: 0 errors, 18 warnings, 1 checks, 129 lines checked
17d28d1fa42d drm/i915: Add separate defines for cursor WM/DDB register bits
-:63: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#63: FILE: drivers/gpu/drm/i915/display/intel_cursor.c:597:
+ skl_cursor_wm_reg_val(skl_plane_wm_level(pipe_wm, plane_id, level)));
total: 0 errors, 1 warnings, 0 checks, 107 lines checked
2b8ba2490bb1 drm/i915: Move PIPEGCMAX to intel_color_regs.h
c2318fee4bb2 drm/i915: Extract i9xx_plane_regs.h
-:30: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#30:
new file mode 100644
-:110: WARNING:LONG_LINE_COMMENT: line length of 116 exceeds 100 columns
#110: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:76:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 2 warnings, 0 checks, 278 lines checked
b2963797f811 drm/i915: Polish pre-skl primary plane registers
-:90: WARNING:LONG_LINE: line length of 132 exceeds 100 columns
#90: FILE: drivers/gpu/drm/i915/display/i9xx_plane_regs.h:87:
+#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */
total: 0 errors, 1 warnings, 0 checks, 96 lines checked
033d0ca297b6 drm/i915: Document a few pre-skl primary plane platform dependencies
f62f6b19525f drm/i915: Polish sprite plane register definitions
-:88: WARNING:LONG_LINE_COMMENT: line length of 108 exceeds 100 columns
#88: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:89:
+#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */
-:304: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#304: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:287:
+#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL)
-:317: WARNING:LONG_LINE: line length of 103 exceeds 100 columns
#317: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:300:
+#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL)
-:329: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#329: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:312:
+#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA)
-:336: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#336: FILE: drivers/gpu/drm/i915/display/intel_sprite_regs.h:319:
+#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE)
total: 0 errors, 5 warnings, 0 checks, 369 lines checked
5471bc08a773 drm/i915: Document which platforms use which sprite registers
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: Plane register cleanups (rev3)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (20 preceding siblings ...)
2024-05-20 18:08 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3) Patchwork
@ 2024-05-20 18:08 ` Patchwork
2024-05-20 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-21 5:29 ` ✗ Fi.CI.IGT: failure " Patchwork
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-20 18:08 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Plane register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/133701/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Plane register cleanups (rev3)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (21 preceding siblings ...)
2024-05-20 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2024-05-20 18:20 ` Patchwork
2024-05-21 5:29 ` ✗ Fi.CI.IGT: failure " Patchwork
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-20 18:20 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4037 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/133701/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_14785 -> Patchwork_133701v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (1): fi-bsw-n3050
Missing (1): bat-arls-1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133701v3:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- {bat-twl-1}: [PASS][1] -> [DMESG-WARN][2] +1 other test dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-twl-1/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
Known issues
------------
Here are the changes found in Patchwork_133701v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_lmem_swapping@basic@lmem0:
- bat-dg2-9: [PASS][3] -> [FAIL][4] ([i915#10378])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-dg2-9/igt@gem_lmem_swapping@basic@lmem0.html
* igt@gem_lmem_swapping@random-engines:
- fi-bsw-n3050: NOTRUN -> [SKIP][5] +19 other tests skip
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/fi-bsw-n3050/igt@gem_lmem_swapping@random-engines.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- bat-mtlp-8: [PASS][6] -> [DMESG-WARN][7] ([i915#9157]) +1 other test dmesg-warn
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
#### Possible fixes ####
* igt@i915_module_load@load:
- bat-dg2-8: [DMESG-WARN][8] ([i915#10014]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-dg2-8/igt@i915_module_load@load.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-dg2-8/igt@i915_module_load@load.html
* igt@i915_selftest@live@gt_timelines:
- bat-arls-2: [INCOMPLETE][10] -> [PASS][11]
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/bat-arls-2/igt@i915_selftest@live@gt_timelines.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/bat-arls-2/igt@i915_selftest@live@gt_timelines.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#10014]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10014
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
Build changes
-------------
* Linux: CI_DRM_14785 -> Patchwork_133701v3
CI-20190529: 20190529
CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133701v3: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/index.html
[-- Attachment #2: Type: text/html, Size: 4800 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: Plane register cleanups (rev3)
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
` (22 preceding siblings ...)
2024-05-20 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2024-05-21 5:29 ` Patchwork
23 siblings, 0 replies; 49+ messages in thread
From: Patchwork @ 2024-05-21 5:29 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 84420 bytes --]
== Series Details ==
Series: drm/i915: Plane register cleanups (rev3)
URL : https://patchwork.freedesktop.org/series/133701/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_14785_full -> Patchwork_133701v3_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_133701v3_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_133701v3_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 10)
------------------------------
Additional (1): shard-snb-0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_133701v3_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_suspend@basic-s3-without-i915:
- shard-dg2: [PASS][1] -> [WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@i915_suspend@basic-s3-without-i915.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
- shard-snb: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-snb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-snb4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_vrr@seamless-rr-switch-virtual:
- shard-tglu: NOTRUN -> [SKIP][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_vrr@seamless-rr-switch-virtual.html
New tests
---------
New tests have been introduced between CI_DRM_14785_full and Patchwork_133701v3_full:
### New IGT tests (5) ###
* igt@kms_plane_lowres@tiling-4@pipe-a-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [7.74] s
* igt@kms_plane_lowres@tiling-4@pipe-b-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [7.37] s
* igt@kms_plane_lowres@tiling-4@pipe-c-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [7.38] s
* igt@kms_plane_lowres@tiling-4@pipe-d-hdmi-a-1:
- Statuses : 1 pass(s)
- Exec time: [7.60] s
* igt@perf@blocking@1-vcs1:
- Statuses : 1 pass(s)
- Exec time: [10.02] s
Known issues
------------
Here are the changes found in Patchwork_133701v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@device_reset@unbind-reset-rebind:
- shard-dg1: NOTRUN -> [INCOMPLETE][6] ([i915#9408])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@device_reset@unbind-reset-rebind.html
* igt@drm_fdinfo@busy-check-all:
- shard-dg2: NOTRUN -> [SKIP][7] ([i915#5608]) +3 other tests skip
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@drm_fdinfo@busy-check-all.html
* igt@drm_fdinfo@busy-hang@bcs0:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#8414]) +6 other tests skip
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@drm_fdinfo@busy-hang@bcs0.html
* igt@drm_fdinfo@virtual-busy-idle-all:
- shard-dg1: NOTRUN -> [SKIP][9] ([i915#8414]) +1 other test skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@drm_fdinfo@virtual-busy-idle-all.html
* igt@drm_fdinfo@virtual-idle:
- shard-rkl: NOTRUN -> [FAIL][10] ([i915#7742])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@drm_fdinfo@virtual-idle.html
* igt@gem_create@create-ext-set-pat:
- shard-dg2: NOTRUN -> [SKIP][11] ([i915#8562])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][12] -> [FAIL][13] ([i915#6268])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-3/igt@gem_ctx_exec@basic-nohangcheck.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-5/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-dg2: NOTRUN -> [SKIP][14] ([i915#280])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@kms:
- shard-tglu: [PASS][15] -> [INCOMPLETE][16] ([i915#10513])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-tglu-6/igt@gem_eio@kms.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-4/igt@gem_eio@kms.html
* igt@gem_exec_balancer@bonded-sync:
- shard-dg1: NOTRUN -> [SKIP][17] ([i915#4771])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_exec_balancer@bonded-sync.html
* igt@gem_exec_balancer@hog:
- shard-dg2: NOTRUN -> [SKIP][18] ([i915#4812])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_exec_balancer@hog.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-rkl: NOTRUN -> [SKIP][19] ([i915#4525])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_capture@many-4k-incremental:
- shard-dg1: NOTRUN -> [FAIL][20] ([i915#9606])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_exec_capture@many-4k-incremental.html
* igt@gem_exec_fair@basic-deadline:
- shard-dg1: NOTRUN -> [SKIP][21] ([i915#3539] / [i915#4852]) +2 other tests skip
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-pace@bcs0:
- shard-tglu: NOTRUN -> [FAIL][22] ([i915#2842]) +4 other tests fail
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@gem_exec_fair@basic-pace@bcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [PASS][23] -> [FAIL][24] ([i915#2842]) +3 other tests fail
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-5/igt@gem_exec_fair@basic-pace@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-3/igt@gem_exec_fair@basic-pace@rcs0.html
- shard-tglu: NOTRUN -> [FAIL][25] ([i915#2876])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-uc-prw-default:
- shard-dg2: NOTRUN -> [SKIP][26] ([i915#3539])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_exec_flush@basic-uc-prw-default.html
* igt@gem_exec_reloc@basic-scanout:
- shard-rkl: NOTRUN -> [SKIP][27] ([i915#3281]) +4 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@gem_exec_reloc@basic-scanout.html
* igt@gem_exec_reloc@basic-write-gtt-active:
- shard-dg1: NOTRUN -> [SKIP][28] ([i915#3281]) +1 other test skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_exec_reloc@basic-write-gtt-active.html
* igt@gem_exec_reloc@basic-write-read-active:
- shard-dg2: NOTRUN -> [SKIP][29] ([i915#3281]) +5 other tests skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@gem_exec_reloc@basic-write-read-active.html
* igt@gem_exec_schedule@pi-distinct-iova:
- shard-snb: NOTRUN -> [SKIP][30] +25 other tests skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-snb5/igt@gem_exec_schedule@pi-distinct-iova.html
* igt@gem_exec_schedule@reorder-wide:
- shard-dg1: NOTRUN -> [SKIP][31] ([i915#4812])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_exec_schedule@reorder-wide.html
* igt@gem_fenced_exec_thrash@2-spare-fences:
- shard-dg2: NOTRUN -> [SKIP][32] ([i915#4860])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_fenced_exec_thrash@2-spare-fences.html
* igt@gem_lmem_swapping@heavy-multi@lmem0:
- shard-dg1: [PASS][33] -> [FAIL][34] ([i915#10378])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg1-16/igt@gem_lmem_swapping@heavy-multi@lmem0.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_lmem_swapping@heavy-multi@lmem0.html
* igt@gem_lmem_swapping@heavy-random@lmem0:
- shard-dg1: NOTRUN -> [FAIL][35] ([i915#10378])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_lmem_swapping@heavy-random@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random@lmem0:
- shard-dg2: [PASS][36] -> [FAIL][37] ([i915#10378])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-11/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-3/igt@gem_lmem_swapping@heavy-verify-random@lmem0.html
* igt@gem_lmem_swapping@massive-random:
- shard-tglu: NOTRUN -> [SKIP][38] ([i915#4613])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@gem_lmem_swapping@massive-random.html
* igt@gem_lmem_swapping@parallel-random-verify-ccs:
- shard-rkl: NOTRUN -> [SKIP][39] ([i915#4613]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [PASS][40] -> [TIMEOUT][41] ([i915#5493])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-11/igt@gem_lmem_swapping@smem-oom@lmem0.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
- shard-dg1: NOTRUN -> [TIMEOUT][42] ([i915#5493])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_lmem_swapping@verify-ccs:
- shard-dg2: NOTRUN -> [SKIP][43] ([i915#9643])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_lmem_swapping@verify-ccs.html
* igt@gem_lmem_swapping@verify-random-ccs:
- shard-glk: NOTRUN -> [SKIP][44] ([i915#4613]) +2 other tests skip
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-glk3/igt@gem_lmem_swapping@verify-random-ccs.html
* igt@gem_mmap_gtt@zero-extend:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#4077]) +3 other tests skip
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_mmap_gtt@zero-extend.html
* igt@gem_mmap_wc@bad-size:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#4083]) +1 other test skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@gem_mmap_wc@bad-size.html
- shard-dg1: NOTRUN -> [SKIP][47] ([i915#4083])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_mmap_wc@bad-size.html
* igt@gem_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][48] ([i915#3282]) +2 other tests skip
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@gem_partial_pwrite_pread@writes-after-reads.html
- shard-dg2: NOTRUN -> [SKIP][49] ([i915#3282])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@gem_partial_pwrite_pread@writes-after-reads.html
* igt@gem_pxp@create-regular-buffer:
- shard-rkl: NOTRUN -> [SKIP][50] ([i915#4270]) +3 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@gem_pxp@create-regular-buffer.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-dg1: NOTRUN -> [SKIP][51] ([i915#4270]) +2 other tests skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gem_pxp@protected-raw-src-copy-not-readible:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#4270])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_pxp@protected-raw-src-copy-not-readible.html
* igt@gem_pxp@verify-pxp-key-change-after-suspend-resume:
- shard-tglu: NOTRUN -> [SKIP][53] ([i915#4270]) +1 other test skip
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@gem_pxp@verify-pxp-key-change-after-suspend-resume.html
* igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#5190] / [i915#8428]) +1 other test skip
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html
* igt@gem_set_tiling_vs_blt@tiled-to-tiled:
- shard-dg1: NOTRUN -> [SKIP][55] ([i915#4079])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
* igt@gem_tiled_partial_pwrite_pread@writes-after-reads:
- shard-dg1: NOTRUN -> [SKIP][56] ([i915#4077]) +4 other tests skip
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_tiled_partial_pwrite_pread@writes-after-reads.html
* igt@gem_userptr_blits@create-destroy-unsync:
- shard-rkl: NOTRUN -> [SKIP][57] ([i915#3297]) +1 other test skip
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@gem_userptr_blits@create-destroy-unsync.html
* igt@gem_userptr_blits@forbidden-operations:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#3282]) +4 other tests skip
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@gem_userptr_blits@forbidden-operations.html
* igt@gem_userptr_blits@map-fixed-invalidate:
- shard-dg1: NOTRUN -> [SKIP][59] ([i915#3297] / [i915#4880])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_userptr_blits@map-fixed-invalidate.html
* igt@gem_userptr_blits@sync-unmap:
- shard-dg2: [PASS][60] -> [SKIP][61] ([i915#2575]) +24 other tests skip
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_userptr_blits@sync-unmap.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_userptr_blits@sync-unmap.html
* igt@gem_userptr_blits@unsync-unmap:
- shard-dg1: NOTRUN -> [SKIP][62] ([i915#3297])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@gem_userptr_blits@unsync-unmap.html
* igt@gem_userptr_blits@unsync-unmap-cycles:
- shard-dg2: NOTRUN -> [SKIP][63] ([i915#3297])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@gem_userptr_blits@unsync-unmap-cycles.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-tglu: NOTRUN -> [SKIP][64] ([i915#2527] / [i915#2856])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@bb-start-param:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#2527]) +1 other test skip
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-glk: [PASS][66] -> [INCOMPLETE][67] ([i915#9849])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-glk8/igt@i915_module_load@reload-with-fault-injection.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-glk8/igt@i915_module_load@reload-with-fault-injection.html
- shard-mtlp: [PASS][68] -> [ABORT][69] ([i915#10131] / [i915#9820])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-mtlp-1/igt@i915_module_load@reload-with-fault-injection.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-mtlp-6/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_module_load@resize-bar:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#6412])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@i915_module_load@resize-bar.html
* igt@i915_pm_rps@basic-api:
- shard-dg1: NOTRUN -> [SKIP][71] ([i915#6621])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-dg1: NOTRUN -> [SKIP][72] ([i915#8925])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@i915_pm_sseu@full-enable:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#4387])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@i915_pm_sseu@full-enable.html
- shard-tglu: NOTRUN -> [SKIP][74] ([i915#4387])
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@i915_pm_sseu@full-enable.html
* igt@i915_query@test-query-geometry-subslices:
- shard-rkl: NOTRUN -> [SKIP][75] ([i915#5723])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@i915_query@test-query-geometry-subslices.html
* igt@i915_suspend@basic-s3-without-i915:
- shard-rkl: [PASS][76] -> [INCOMPLETE][77] ([i915#4817])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-5/igt@i915_suspend@basic-s3-without-i915.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-3/igt@i915_suspend@basic-s3-without-i915.html
* igt@intel_hwmon@hwmon-read:
- shard-tglu: NOTRUN -> [SKIP][78] ([i915#7707])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@intel_hwmon@hwmon-read.html
* igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling:
- shard-dg1: NOTRUN -> [SKIP][79] ([i915#4212])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_addfb_basic@addfb25-framebuffer-vs-set-tiling.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#8709]) +3 other tests skip
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-5/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-1-y-rc-ccs-cc.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs:
- shard-dg1: NOTRUN -> [SKIP][81] ([i915#8709]) +7 other tests skip
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc-ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#8709]) +11 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-c-hdmi-a-1-4-mc-ccs.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg1: NOTRUN -> [SKIP][83] ([i915#9531])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#1769] / [i915#3555])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#5286]) +3 other tests skip
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_big_fb@4-tiled-8bpp-rotate-0.html
* igt@kms_big_fb@4-tiled-addfb:
- shard-tglu: NOTRUN -> [SKIP][86] ([i915#5286]) +2 other tests skip
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_big_fb@4-tiled-addfb.html
* igt@kms_big_fb@linear-64bpp-rotate-90:
- shard-rkl: NOTRUN -> [SKIP][87] ([i915#3638]) +1 other test skip
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_big_fb@linear-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][88] ([i915#3638]) +1 other test skip
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#4538] / [i915#5190]) +2 other tests skip
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-270:
- shard-dg1: NOTRUN -> [SKIP][90] ([i915#4538])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@kms_big_fb@yf-tiled-32bpp-rotate-270.html
* igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs:
- shard-dg1: NOTRUN -> [SKIP][91] ([i915#10278])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_ccs@bad-rotation-90-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs:
- shard-rkl: NOTRUN -> [SKIP][92] ([i915#10278]) +1 other test skip
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-xe2-ccs.html
* igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][93] ([i915#6095]) +79 other tests skip
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_ccs@crc-primary-rotation-180-y-tiled-ccs@pipe-a-hdmi-a-3.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc:
- shard-dg2: NOTRUN -> [SKIP][94] +13 other tests skip
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc.html
* igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#10307] / [i915#6095]) +179 other tests skip
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-gen12-mc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][96] ([i915#6095]) +43 other tests skip
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][97] ([i915#6095]) +11 other tests skip
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_ccs@random-ccs-data-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][98] ([i915#10307] / [i915#10434] / [i915#6095]) +7 other tests skip
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#7213]) +3 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html
* igt@kms_cdclk@plane-scaling:
- shard-rkl: NOTRUN -> [SKIP][100] ([i915#3742]) +1 other test skip
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_cdclk@plane-scaling.html
- shard-tglu: NOTRUN -> [SKIP][101] ([i915#3742])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_cdclk@plane-scaling.html
* igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][102] ([i915#4087]) +3 other tests skip
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-5/igt@kms_cdclk@plane-scaling@pipe-b-hdmi-a-3.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-dg1: NOTRUN -> [SKIP][103] ([i915#7828]) +4 other tests skip
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_frames@dp-crc-fast:
- shard-dg2: NOTRUN -> [SKIP][104] ([i915#7828])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_chamelium_frames@dp-crc-fast.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- shard-tglu: NOTRUN -> [SKIP][105] ([i915#7828]) +3 other tests skip
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd-fast:
- shard-rkl: NOTRUN -> [SKIP][106] ([i915#7828]) +5 other tests skip
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_chamelium_hpd@vga-hpd-fast.html
* igt@kms_content_protection@dp-mst-type-1:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#3299]) +1 other test skip
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_content_protection@dp-mst-type-1.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][108] ([i915#7118] / [i915#9424])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_content_protection@type1.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-dg2: NOTRUN -> [SKIP][109] ([i915#3555]) +1 other test skip
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x512:
- shard-dg1: NOTRUN -> [SKIP][110] ([i915#3359]) +2 other tests skip
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_cursor_crc@cursor-random-512x512.html
* igt@kms_cursor_crc@cursor-sliding-512x512:
- shard-rkl: NOTRUN -> [SKIP][111] ([i915#3359]) +1 other test skip
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-512x512.html
* igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
- shard-rkl: NOTRUN -> [SKIP][112] ([i915#9723])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][113] ([i915#9227])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-1.html
* igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][114] ([i915#9723])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_dirtyfb@fbc-dirtyfb-ioctl@a-hdmi-a-3.html
* igt@kms_draw_crc@draw-method-mmap-wc:
- shard-dg1: NOTRUN -> [SKIP][115] ([i915#8812])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@kms_draw_crc@draw-method-mmap-wc.html
* igt@kms_dsc@dsc-with-formats:
- shard-tglu: NOTRUN -> [SKIP][116] ([i915#3555] / [i915#3840])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_dsc@dsc-with-formats.html
* igt@kms_dsc@dsc-with-output-formats:
- shard-dg2: NOTRUN -> [SKIP][117] ([i915#3555] / [i915#3840])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_dsc@dsc-with-output-formats.html
* igt@kms_feature_discovery@display-4x:
- shard-dg1: NOTRUN -> [SKIP][118] ([i915#1839])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_feature_discovery@display-4x.html
* igt@kms_feature_discovery@dp-mst:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#9337])
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_feature_discovery@dp-mst.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1:
- shard-snb: [PASS][120] -> [FAIL][121] ([i915#2122]) +1 other test fail
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-snb5/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-snb7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-flip-vs-panning-interruptible:
- shard-tglu: NOTRUN -> [SKIP][122] ([i915#3637])
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_flip@2x-flip-vs-panning-interruptible.html
* igt@kms_flip@2x-plain-flip:
- shard-rkl: NOTRUN -> [SKIP][123] +32 other tests skip
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_flip@2x-plain-flip.html
* igt@kms_flip@2x-plain-flip-interruptible:
- shard-dg1: NOTRUN -> [SKIP][124] ([i915#9934])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@kms_flip@2x-plain-flip-interruptible.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-tglu: NOTRUN -> [SKIP][125] ([i915#3637] / [i915#3966])
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode:
- shard-dg1: NOTRUN -> [SKIP][126] ([i915#2587] / [i915#2672])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][127] ([i915#2672]) +2 other tests skip
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][128] ([i915#2672])
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode:
- shard-tglu: NOTRUN -> [SKIP][129] ([i915#2587] / [i915#2672]) +1 other test skip
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling:
- shard-dg2: NOTRUN -> [SKIP][130] ([i915#5190])
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
- shard-dg2: [PASS][131] -> [FAIL][132] ([i915#6880]) +1 other test fail
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbc-2p-rte:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#5354]) +15 other tests skip
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg1: NOTRUN -> [SKIP][134] ([i915#8708]) +8 other tests skip
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbc-stridechange:
- shard-dg2: [PASS][135] -> [SKIP][136] +4 other tests skip
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-stridechange.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-stridechange.html
* igt@kms_frontbuffer_tracking@fbc-tiling-y:
- shard-dg2: NOTRUN -> [SKIP][137] ([i915#10055])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-tiling-y.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt:
- shard-rkl: NOTRUN -> [SKIP][138] ([i915#3023]) +18 other tests skip
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
- shard-dg2: NOTRUN -> [SKIP][139] ([i915#3458]) +4 other tests skip
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][140] ([i915#8708]) +9 other tests skip
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@pipe-fbc-rte:
- shard-rkl: NOTRUN -> [SKIP][141] ([i915#9766])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
- shard-tglu: NOTRUN -> [SKIP][142] ([i915#9766])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html
* igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt:
- shard-dg1: NOTRUN -> [SKIP][143] ([i915#3458]) +3 other tests skip
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][144] ([i915#1825]) +20 other tests skip
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt:
- shard-tglu: NOTRUN -> [SKIP][145] +26 other tests skip
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-blt.html
* igt@kms_hdr@static-toggle:
- shard-rkl: NOTRUN -> [SKIP][146] ([i915#3555] / [i915#8228])
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_hdr@static-toggle.html
- shard-tglu: NOTRUN -> [SKIP][147] ([i915#3555] / [i915#8228])
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_hdr@static-toggle.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1:
- shard-mtlp: [PASS][148] -> [DMESG-WARN][149] ([i915#9157]) +1 other test dmesg-warn
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-mtlp-8/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-mtlp-3/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-nv12@pipe-b-edp-1.html
* igt@kms_plane_lowres@tiling-yf:
- shard-rkl: NOTRUN -> [SKIP][150] ([i915#3555]) +6 other tests skip
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-y:
- shard-dg2: NOTRUN -> [SKIP][151] ([i915#8806])
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_plane_multiple@tiling-y.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg1: NOTRUN -> [SKIP][152] ([i915#3555]) +3 other tests skip
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-tglu: NOTRUN -> [FAIL][153] ([i915#8292])
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][154] ([i915#8292])
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][155] ([i915#8292])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-17/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-4.html
* igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3:
- shard-dg2: NOTRUN -> [SKIP][156] ([i915#9423]) +11 other tests skip
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-5/igt@kms_plane_scaling@plane-downscale-factor-0-25-with-modifiers@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][157] ([i915#9423]) +3 other tests skip
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][158] ([i915#9423]) +11 other tests skip
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-d-hdmi-a-3.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][159] ([i915#5176] / [i915#9423]) +1 other test skip
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-2/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][160] ([i915#5176] / [i915#9423]) +3 other tests skip
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-a-hdmi-a-3.html
* igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-1:
- shard-tglu: NOTRUN -> [SKIP][161] ([i915#9423]) +3 other tests skip
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-3:
- shard-dg1: NOTRUN -> [SKIP][162] ([i915#5235]) +7 other tests skip
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-factor-0-25@pipe-b-hdmi-a-3.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling:
- shard-dg2: NOTRUN -> [SKIP][163] ([i915#2575] / [i915#9423])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][164] ([i915#5235]) +3 other tests skip
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-1:
- shard-dg2: NOTRUN -> [SKIP][165] ([i915#5235] / [i915#9423]) +15 other tests skip
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-4/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-d-hdmi-a-1.html
* igt@kms_pm_backlight@fade-with-dpms:
- shard-rkl: NOTRUN -> [SKIP][166] ([i915#5354])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_pm_backlight@fade-with-dpms.html
* igt@kms_pm_dc@dc3co-vpb-simulation:
- shard-rkl: NOTRUN -> [SKIP][167] ([i915#9685])
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_pm_dc@dc3co-vpb-simulation.html
* igt@kms_pm_dc@dc6-dpms:
- shard-tglu: [PASS][168] -> [FAIL][169] ([i915#9295])
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-tglu-10/igt@kms_pm_dc@dc6-dpms.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-8/igt@kms_pm_dc@dc6-dpms.html
* igt@kms_pm_lpsp@screens-disabled:
- shard-tglu: NOTRUN -> [SKIP][170] ([i915#8430])
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_pm_lpsp@screens-disabled.html
* igt@kms_pm_rpm@drm-resources-equal:
- shard-dg2: [PASS][171] -> [SKIP][172] ([i915#9980]) +1 other test skip
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_pm_rpm@drm-resources-equal.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_pm_rpm@drm-resources-equal.html
* igt@kms_pm_rpm@modeset-non-lpsp:
- shard-dg2: NOTRUN -> [SKIP][173] ([i915#9519])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_pm_rpm@modeset-non-lpsp.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [PASS][174] -> [SKIP][175] ([i915#9519])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
* igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-rkl: NOTRUN -> [SKIP][176] ([i915#9519])
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area:
- shard-dg1: NOTRUN -> [SKIP][177] +18 other tests skip
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_psr2_sf@fbc-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-xrgb8888:
- shard-dg1: NOTRUN -> [SKIP][178] ([i915#9683])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_psr2_su@page_flip-xrgb8888.html
* igt@kms_psr@fbc-pr-no-drrs:
- shard-tglu: NOTRUN -> [SKIP][179] ([i915#9732]) +7 other tests skip
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_psr@fbc-pr-no-drrs.html
* igt@kms_psr@fbc-psr2-sprite-mmap-cpu:
- shard-dg2: NOTRUN -> [SKIP][180] ([i915#1072] / [i915#9732]) +9 other tests skip
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@kms_psr@fbc-psr2-sprite-mmap-cpu.html
* igt@kms_psr@fbc-psr2-sprite-render:
- shard-rkl: NOTRUN -> [SKIP][181] ([i915#1072] / [i915#9732]) +15 other tests skip
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@kms_psr@fbc-psr2-sprite-render.html
* igt@kms_psr@psr2-sprite-blt:
- shard-dg1: NOTRUN -> [SKIP][182] ([i915#1072] / [i915#9732]) +4 other tests skip
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_psr@psr2-sprite-blt.html
* igt@kms_psr@psr2-sprite-plane-onoff:
- shard-glk: NOTRUN -> [SKIP][183] +122 other tests skip
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-glk1/igt@kms_psr@psr2-sprite-plane-onoff.html
* igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
- shard-dg2: NOTRUN -> [SKIP][184] ([i915#9685])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
* igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
- shard-rkl: NOTRUN -> [SKIP][185] ([i915#5289]) +2 other tests skip
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
- shard-tglu: NOTRUN -> [SKIP][186] ([i915#5289]) +1 other test skip
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html
* igt@kms_rotation_crc@sprite-rotation-270:
- shard-dg2: NOTRUN -> [SKIP][187] ([i915#4235])
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_rotation_crc@sprite-rotation-270.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-tglu: NOTRUN -> [SKIP][188] ([i915#3555]) +3 other tests skip
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][189] ([i915#5465]) +3 other tests fail
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-snb7/igt@kms_setmode@basic@pipe-a-vga-1-pipe-b-hdmi-a-1.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-rkl: NOTRUN -> [SKIP][190] ([i915#8623])
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
- shard-tglu: NOTRUN -> [SKIP][191] ([i915#8623])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1:
- shard-mtlp: [PASS][192] -> [FAIL][193] ([i915#9196])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-mtlp-7/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-mtlp-4/igt@kms_universal_plane@cursor-fb-leak@pipe-b-edp-1.html
* igt@kms_vblank@query-forked-hang:
- shard-dg2: NOTRUN -> [SKIP][194] ([i915#2575]) +29 other tests skip
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_vblank@query-forked-hang.html
* igt@kms_vrr@flip-basic-fastset:
- shard-dg1: NOTRUN -> [SKIP][195] ([i915#9906])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@kms_vrr@flip-basic-fastset.html
* igt@kms_vrr@seamless-rr-switch-drrs:
- shard-rkl: NOTRUN -> [SKIP][196] ([i915#9906])
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-drrs.html
- shard-tglu: NOTRUN -> [SKIP][197] ([i915#9906])
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@kms_vrr@seamless-rr-switch-drrs.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-dg1: NOTRUN -> [SKIP][198] ([i915#2437])
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@kms_writeback@writeback-invalid-parameters.html
- shard-dg2: NOTRUN -> [SKIP][199] ([i915#2437])
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_writeback@writeback-invalid-parameters.html
* igt@perf@gen12-group-concurrent-oa-buffer-read:
- shard-dg2: [PASS][200] -> [SKIP][201] ([i915#5608])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@perf@gen12-group-concurrent-oa-buffer-read.html
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@perf@gen12-group-concurrent-oa-buffer-read.html
* igt@perf_pmu@cpu-hotplug:
- shard-rkl: NOTRUN -> [SKIP][202] ([i915#8850])
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@perf_pmu@cpu-hotplug.html
* igt@perf_pmu@rc6-all-gts:
- shard-dg1: NOTRUN -> [SKIP][203] ([i915#8516])
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@perf_pmu@rc6-all-gts.html
* igt@runner@aborted:
- shard-glk: NOTRUN -> [FAIL][204] ([i915#10291])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-glk1/igt@runner@aborted.html
* igt@sriov_basic@bind-unbind-vf:
- shard-dg2: NOTRUN -> [SKIP][205] ([i915#9917])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@sriov_basic@bind-unbind-vf.html
* igt@sriov_basic@enable-vfs-autoprobe-on:
- shard-tglu: NOTRUN -> [SKIP][206] ([i915#9917])
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@sriov_basic@enable-vfs-autoprobe-on.html
- shard-rkl: NOTRUN -> [SKIP][207] ([i915#9917]) +1 other test skip
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-6/igt@sriov_basic@enable-vfs-autoprobe-on.html
* igt@syncobj_wait@invalid-wait-zero-handles:
- shard-rkl: NOTRUN -> [FAIL][208] ([i915#9779])
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@syncobj_wait@invalid-wait-zero-handles.html
* igt@v3d/v3d_submit_cl@single-in-sync:
- shard-tglu: NOTRUN -> [SKIP][209] ([i915#2575]) +5 other tests skip
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@v3d/v3d_submit_cl@single-in-sync.html
* igt@v3d/v3d_submit_csd@single-in-sync:
- shard-dg1: NOTRUN -> [SKIP][210] ([i915#2575]) +3 other tests skip
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@v3d/v3d_submit_csd@single-in-sync.html
* igt@vc4/vc4_label_bo@set-label:
- shard-rkl: NOTRUN -> [SKIP][211] ([i915#7711]) +4 other tests skip
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-4/igt@vc4/vc4_label_bo@set-label.html
* igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem:
- shard-dg1: NOTRUN -> [SKIP][212] ([i915#7711]) +2 other tests skip
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-13/igt@vc4/vc4_purgeable_bo@access-purgeable-bo-mem.html
* igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice:
- shard-dg2: NOTRUN -> [SKIP][213] ([i915#7711]) +1 other test skip
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@vc4/vc4_purgeable_bo@mark-unpurgeable-twice.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [FAIL][214] ([i915#7742]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-4/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-tglu: [FAIL][216] ([i915#6268]) -> [PASS][217]
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-tglu-5/igt@gem_ctx_exec@basic-nohangcheck.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-6/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: [FAIL][218] ([i915#2842]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-5/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_lmem_swapping@heavy-verify-multi@lmem0:
- shard-dg2: [FAIL][220] ([i915#10378]) -> [PASS][221] +1 other test pass
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-6/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-4/igt@gem_lmem_swapping@heavy-verify-multi@lmem0.html
* igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0:
- shard-dg2: [FAIL][222] ([i915#10446]) -> [PASS][223]
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-8/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-2/igt@gem_lmem_swapping@heavy-verify-random-ccs@lmem0.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-tglu: [INCOMPLETE][224] ([i915#10047] / [i915#9820]) -> [PASS][225]
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-tglu-5/igt@i915_module_load@reload-with-fault-injection.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-7/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_freq_api@freq-suspend@gt0:
- shard-dg2: [INCOMPLETE][226] ([i915#9407]) -> [PASS][227]
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-10/igt@i915_pm_freq_api@freq-suspend@gt0.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@i915_pm_freq_api@freq-suspend@gt0.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-snb: [SKIP][228] -> [PASS][229]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-snb5/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-snb7/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1:
- shard-snb: [INCOMPLETE][230] ([i915#4839]) -> [PASS][231]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-snb6/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-snb5/igt@kms_flip@flip-vs-suspend-interruptible@b-hdmi-a1.html
* igt@kms_pm_rpm@i2c:
- shard-dg2: [FAIL][232] ([i915#8717]) -> [PASS][233]
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-2/igt@kms_pm_rpm@i2c.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-5/igt@kms_pm_rpm@i2c.html
* igt@kms_pm_rpm@modeset-lpsp-stress:
- shard-dg2: [SKIP][234] ([i915#9519]) -> [PASS][235] +3 other tests pass
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-1/igt@kms_pm_rpm@modeset-lpsp-stress.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-10/igt@kms_pm_rpm@modeset-lpsp-stress.html
- shard-rkl: [SKIP][236] ([i915#9519]) -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress.html
* igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1:
- shard-tglu: [FAIL][238] ([i915#9196]) -> [PASS][239]
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-tglu-8/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-tglu-9/igt@kms_universal_plane@cursor-fb-leak@pipe-a-hdmi-a-1.html
#### Warnings ####
* igt@gem_exec_balancer@bonded-pair:
- shard-dg2: [SKIP][240] ([i915#4771]) -> [SKIP][241] ([i915#2575])
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_exec_balancer@bonded-pair.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_exec_balancer@bonded-pair.html
* igt@gem_exec_flush@basic-batch-kernel-default-cmd:
- shard-dg2: [SKIP][242] ([i915#3539] / [i915#4852]) -> [SKIP][243] ([i915#2575])
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_exec_flush@basic-batch-kernel-default-cmd.html
* igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
- shard-dg2: [SKIP][244] ([i915#3281]) -> [SKIP][245] ([i915#2575]) +1 other test skip
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html
* igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible:
- shard-dg2: [SKIP][246] ([i915#4860]) -> [SKIP][247] ([i915#2575])
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_fenced_exec_thrash@no-spare-fences-busy-interruptible.html
* igt@gem_mmap_gtt@big-copy:
- shard-dg2: [SKIP][248] ([i915#4077]) -> [SKIP][249] ([i915#2575]) +1 other test skip
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_mmap_gtt@big-copy.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_mmap_gtt@big-copy.html
* igt@gem_mmap_wc@read:
- shard-dg2: [SKIP][250] ([i915#4083]) -> [SKIP][251] ([i915#2575])
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_mmap_wc@read.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_mmap_wc@read.html
* igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
- shard-dg2: [SKIP][252] ([i915#3282]) -> [SKIP][253] ([i915#2575])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
* igt@gem_pxp@create-regular-context-2:
- shard-dg2: [SKIP][254] ([i915#4270]) -> [SKIP][255] ([i915#2575]) +1 other test skip
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_pxp@create-regular-context-2.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_pxp@create-regular-context-2.html
* igt@gem_render_copy@y-tiled-to-vebox-yf-tiled:
- shard-dg2: [SKIP][256] ([i915#5190] / [i915#8428]) -> [SKIP][257] ([i915#2575] / [i915#5190])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gem_render_copy@y-tiled-to-vebox-yf-tiled.html
* igt@gen9_exec_parse@basic-rejected:
- shard-dg2: [SKIP][258] ([i915#2856]) -> [SKIP][259] ([i915#2575])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@gen9_exec_parse@basic-rejected.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@gen9_exec_parse@basic-rejected.html
* igt@i915_module_load@reload-with-fault-injection:
- shard-dg1: [ABORT][260] ([i915#9820]) -> [INCOMPLETE][261] ([i915#1982] / [i915#9849])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg1-13/igt@i915_module_load@reload-with-fault-injection.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-17/igt@i915_module_load@reload-with-fault-injection.html
- shard-dg2: [ABORT][262] ([i915#9820]) -> [INCOMPLETE][263] ([i915#1982] / [i915#9849])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-8/igt@i915_module_load@reload-with-fault-injection.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-2/igt@i915_module_load@reload-with-fault-injection.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-90:
- shard-dg2: [SKIP][264] ([i915#4538] / [i915#5190]) -> [SKIP][265] ([i915#5190]) +2 other tests skip
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_big_fb@yf-tiled-8bpp-rotate-90.html
* igt@kms_chamelium_audio@dp-audio-edid:
- shard-dg2: [SKIP][266] ([i915#7828]) -> [SKIP][267] ([i915#2575]) +1 other test skip
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_chamelium_audio@dp-audio-edid.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_chamelium_audio@dp-audio-edid.html
* igt@kms_content_protection@content-type-change:
- shard-dg2: [SKIP][268] ([i915#9424]) -> [SKIP][269] ([i915#2575])
[268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_content_protection@content-type-change.html
[269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_content_protection@content-type-change.html
* igt@kms_content_protection@mei-interface:
- shard-dg1: [SKIP][270] ([i915#9433]) -> [SKIP][271] ([i915#9424])
[270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg1-13/igt@kms_content_protection@mei-interface.html
[271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-15/igt@kms_content_protection@mei-interface.html
* igt@kms_cursor_crc@cursor-onscreen-512x512:
- shard-dg2: [SKIP][272] ([i915#3359]) -> [SKIP][273] ([i915#2575])
[272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_cursor_crc@cursor-onscreen-512x512.html
[273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-512x512.html
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-dg2: [SKIP][274] ([i915#5354]) -> [SKIP][275] ([i915#2575])
[274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
[275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic.html
* igt@kms_feature_discovery@psr2:
- shard-dg2: [SKIP][276] ([i915#658]) -> [SKIP][277] ([i915#2575])
[276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_feature_discovery@psr2.html
[277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-modeset:
- shard-dg2: [SKIP][278] -> [SKIP][279] ([i915#2575]) +1 other test skip
[278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_flip@2x-flip-vs-modeset.html
[279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_flip@2x-flip-vs-modeset.html
* igt@kms_flip@flip-vs-fences-interruptible:
- shard-dg2: [SKIP][280] ([i915#8381]) -> [SKIP][281] ([i915#2575])
[280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_flip@flip-vs-fences-interruptible.html
[281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_flip@flip-vs-fences-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [FAIL][282] ([i915#6880]) -> [SKIP][283]
[282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
[283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-dg2: [SKIP][284] ([i915#10433] / [i915#3458]) -> [SKIP][285] ([i915#3458]) +1 other test skip
[284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
[285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt:
- shard-dg2: [SKIP][286] ([i915#8708]) -> [SKIP][287] +5 other tests skip
[286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
[287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
- shard-dg2: [SKIP][288] ([i915#3458]) -> [SKIP][289] ([i915#10433] / [i915#3458]) +6 other tests skip
[288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
[289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt:
- shard-dg2: [SKIP][290] ([i915#3458]) -> [SKIP][291] +5 other tests skip
[290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
[291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render:
- shard-dg2: [SKIP][292] ([i915#5354]) -> [SKIP][293] +3 other tests skip
[292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html
[293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_pm_dc@dc6-psr:
- shard-dg2: [SKIP][294] ([i915#9685]) -> [SKIP][295]
[294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_pm_dc@dc6-psr.html
[295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_pm_dc@dc6-psr.html
* igt@kms_pm_dc@dc9-dpms:
- shard-rkl: [SKIP][296] ([i915#3361]) -> [SKIP][297] ([i915#4281])
[296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-rkl-2/igt@kms_pm_dc@dc9-dpms.html
[297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-rkl-5/igt@kms_pm_dc@dc9-dpms.html
* igt@kms_psr@pr-cursor-mmap-cpu:
- shard-dg1: [SKIP][298] ([i915#1072] / [i915#9732]) -> [SKIP][299] ([i915#1072] / [i915#4423] / [i915#9732])
[298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg1-13/igt@kms_psr@pr-cursor-mmap-cpu.html
[299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg1-17/igt@kms_psr@pr-cursor-mmap-cpu.html
* igt@kms_psr@pr-cursor-plane-move:
- shard-dg2: [SKIP][300] ([i915#1072] / [i915#9673] / [i915#9732]) -> [SKIP][301] ([i915#1072] / [i915#9732]) +8 other tests skip
[300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-11/igt@kms_psr@pr-cursor-plane-move.html
[301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-3/igt@kms_psr@pr-cursor-plane-move.html
* igt@kms_psr@pr-no-drrs:
- shard-dg2: [SKIP][302] ([i915#1072] / [i915#9732]) -> [SKIP][303] +3 other tests skip
[302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_psr@pr-no-drrs.html
[303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_psr@pr-no-drrs.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-270:
- shard-dg2: [SKIP][304] ([i915#4235] / [i915#5190]) -> [SKIP][305] ([i915#2575] / [i915#5190])
[304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
[305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_rotation_crc@primary-y-tiled-reflect-x-270.html
* igt@kms_rotation_crc@sprite-rotation-90-pos-100-0:
- shard-dg2: [SKIP][306] ([i915#4235]) -> [SKIP][307] ([i915#2575])
[306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
[307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90-pos-100-0.html
* igt@kms_scaling_modes@scaling-mode-center:
- shard-dg2: [SKIP][308] ([i915#3555]) -> [SKIP][309] ([i915#2575])
[308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_scaling_modes@scaling-mode-center.html
[309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_scaling_modes@scaling-mode-center.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-dg2: [SKIP][310] ([i915#8623]) -> [SKIP][311] ([i915#2575])
[310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@kms_tiled_display@basic-test-pattern.html
[311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@kms_tiled_display@basic-test-pattern.html
* igt@perf@gen8-unprivileged-single-ctx-counters:
- shard-dg2: [SKIP][312] ([i915#2436]) -> [SKIP][313] ([i915#5608])
[312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@perf@gen8-unprivileged-single-ctx-counters.html
[313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@perf@gen8-unprivileged-single-ctx-counters.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [INCOMPLETE][314] ([i915#5493]) -> [CRASH][315] ([i915#9351])
[314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-8/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@prime_vgem@basic-write:
- shard-dg2: [SKIP][316] ([i915#3291] / [i915#3708]) -> [SKIP][317] ([i915#2575])
[316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@prime_vgem@basic-write.html
[317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@prime_vgem@basic-write.html
* igt@sriov_basic@enable-vfs-autoprobe-off:
- shard-dg2: [SKIP][318] ([i915#9917]) -> [SKIP][319] ([i915#2575])
[318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_14785/shard-dg2-5/igt@sriov_basic@enable-vfs-autoprobe-off.html
[319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/shard-dg2-11/igt@sriov_basic@enable-vfs-autoprobe-off.html
[i915#10047]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10047
[i915#10055]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10055
[i915#10131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10131
[i915#10278]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10278
[i915#10291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10291
[i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
[i915#10378]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10378
[i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
[i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
[i915#10446]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10446
[i915#10513]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10513
[i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
[i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1982
[i915#2122]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2122
[i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
[i915#2437]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2672
[i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2842
[i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
[i915#2876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2876
[i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
[i915#3359]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3359
[i915#3361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
[i915#3966]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3966
[i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4087
[i915#4212]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4212
[i915#4235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
[i915#4281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4281
[i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
[i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
[i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
[i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
[i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
[i915#4852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
[i915#5176]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
[i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
[i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5493
[i915#5608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5608
[i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
[i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6268
[i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
[i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
[i915#6621]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
[i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
[i915#7213]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7213
[i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
[i915#7711]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
[i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8381
[i915#8414]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
[i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
[i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
[i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
[i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
[i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8709
[i915#8717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8717
[i915#8806]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8806
[i915#8812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8812
[i915#8850]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8850
[i915#8925]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8925
[i915#9157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9157
[i915#9196]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9196
[i915#9227]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9227
[i915#9295]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9295
[i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
[i915#9351]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9351
[i915#9407]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9407
[i915#9408]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9408
[i915#9423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9423
[i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
[i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
[i915#9519]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9519
[i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
[i915#9606]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9606
[i915#9643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9643
[i915#9673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9673
[i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
[i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
[i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
[i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
[i915#9766]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9766
[i915#9779]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9779
[i915#9820]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9820
[i915#9849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9849
[i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
[i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
[i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934
[i915#9980]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9980
Build changes
-------------
* Linux: CI_DRM_14785 -> Patchwork_133701v3
CI-20190529: 20190529
CI_DRM_14785: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7863: fa1dc232d5d840532521df8a6fcf1fe82c514304 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_133701v3: 1ba62f8cea9c797427d45108df1d453f4b343240 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_133701v3/index.html
[-- Attachment #2: Type: text/html, Size: 104218 bytes --]
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
2024-05-16 13:56 ` [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() Ville Syrjala
@ 2024-05-23 9:15 ` Jani Nikula
2024-05-23 12:06 ` Ville Syrjälä
0 siblings, 1 reply; 49+ messages in thread
From: Jani Nikula @ 2024-05-23 9:15 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
> for the SEL_FETCH_PLANE registers. A bit more tedious to have
> to define 8 raw register offsets for everything, but perhaps
> a bit easier to understand since we use a standard mechanism
> now instead of hand rolling the arithmetic.
>
> Also bloat-o-meter says:
> add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326)
> Function old new delta
> icl_plane_update_arm 510 446 -64
> icl_plane_disable_sel_fetch_arm.isra 158 54 -104
> icl_plane_update_noarm 1898 1740 -158
> Total: Before=2574502, After=2574176, chg -0.01%
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
I just don't understand the old one.
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 ------------
> .../i915/display/skl_universal_plane_regs.h | 68 +++++++++++++++++++
> 2 files changed, 68 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index f0bd0a726d7a..289c371c98d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -251,51 +251,6 @@
> #define _PIPE_SRCSZ_ERLY_TPT_B 0x71074
> #define PIPE_SRCSZ_ERLY_TPT(pipe) _MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
>
> -#define _SEL_FETCH_PLANE_BASE_1_A 0x70890
> -#define _SEL_FETCH_PLANE_BASE_2_A 0x708B0
> -#define _SEL_FETCH_PLANE_BASE_3_A 0x708D0
> -#define _SEL_FETCH_PLANE_BASE_4_A 0x708F0
> -#define _SEL_FETCH_PLANE_BASE_5_A 0x70920
> -#define _SEL_FETCH_PLANE_BASE_6_A 0x70940
> -#define _SEL_FETCH_PLANE_BASE_7_A 0x70960
> -#define _SEL_FETCH_PLANE_BASE_CUR_A 0x70880
> -#define _SEL_FETCH_PLANE_BASE_1_B 0x71890
> -
> -#define _SEL_FETCH_PLANE_BASE_A(plane) _PICK(plane, \
> - _SEL_FETCH_PLANE_BASE_1_A, \
> - _SEL_FETCH_PLANE_BASE_2_A, \
> - _SEL_FETCH_PLANE_BASE_3_A, \
> - _SEL_FETCH_PLANE_BASE_4_A, \
> - _SEL_FETCH_PLANE_BASE_5_A, \
> - _SEL_FETCH_PLANE_BASE_6_A, \
> - _SEL_FETCH_PLANE_BASE_7_A, \
> - _SEL_FETCH_PLANE_BASE_CUR_A)
> -#define _SEL_FETCH_PLANE_BASE_1(pipe) _PIPE(pipe, _SEL_FETCH_PLANE_BASE_1_A, _SEL_FETCH_PLANE_BASE_1_B)
> -#define _SEL_FETCH_PLANE_BASE(pipe, plane) (_SEL_FETCH_PLANE_BASE_1(pipe) - \
> - _SEL_FETCH_PLANE_BASE_1_A + \
> - _SEL_FETCH_PLANE_BASE_A(plane))
> -
> -#define _SEL_FETCH_PLANE_CTL_1_A 0x70890
> -#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> - _SEL_FETCH_PLANE_CTL_1_A - \
> - _SEL_FETCH_PLANE_BASE_1_A)
> -#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
> -
> -#define _SEL_FETCH_PLANE_POS_1_A 0x70894
> -#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> - _SEL_FETCH_PLANE_POS_1_A - \
> - _SEL_FETCH_PLANE_BASE_1_A)
> -
> -#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898
> -#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> - _SEL_FETCH_PLANE_SIZE_1_A - \
> - _SEL_FETCH_PLANE_BASE_1_A)
> -
> -#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089C
> -#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO(_SEL_FETCH_PLANE_BASE(pipe, plane) + \
> - _SEL_FETCH_PLANE_OFFSET_1_A - \
> - _SEL_FETCH_PLANE_BASE_1_A)
> -
> #define _ALPM_CTL_A 0x60950
> #define ALPM_CTL(dev_priv, tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A)
> #define ALPM_CTL_ALPM_ENABLE REG_BIT(31)
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> index cb3bdd71b6b2..a6528e0d719e 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h
> @@ -17,6 +17,17 @@
> #define _MMIO_SKL_PLANE_DW(pipe, plane, dw, reg_1_a, reg_1_b, reg_2_a, reg_2_b) \
> _MMIO(_SKL_PLANE_DW((pipe), (plane), (dw), (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b)))
>
> +#define _SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
> + _PICK_EVEN_2RANGES((plane), PLANE_5, \
> + _PIPE((pipe), (reg_1_a), (reg_1_b)), \
> + _PIPE((pipe), (reg_2_a), (reg_2_b)), \
> + _PIPE((pipe), (reg_5_a), (reg_5_b)), \
> + _PIPE((pipe), (reg_6_a), (reg_6_b)))
> +#define _MMIO_SEL_FETCH(pipe, plane, reg_1_a, reg_1_b, reg_2_a, reg_2_b, reg_5_a, reg_5_b, reg_6_a, reg_6_b) \
> + _MMIO(_SEL_FETCH((pipe), (plane), \
> + (reg_1_a), (reg_1_b), (reg_2_a), (reg_2_b), \
> + (reg_5_a), (reg_5_b), (reg_6_a), (reg_6_b)))
> +
> #define _PLANE_CTL_1_A 0x70180
> #define _PLANE_CTL_2_A 0x70280
> #define _PLANE_CTL_1_B 0x71180
> @@ -367,4 +378,61 @@
> #define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
>
> +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 /* mtl+ */
> +#define _SEL_FETCH_PLANE_CTL_2_A 0x708b0
> +#define _SEL_FETCH_PLANE_CTL_5_A 0x70920
> +#define _SEL_FETCH_PLANE_CTL_6_A 0x70940
> +#define _SEL_FETCH_PLANE_CTL_1_B 0x71890
> +#define _SEL_FETCH_PLANE_CTL_2_B 0x718b0
> +#define _SEL_FETCH_PLANE_CTL_5_B 0x71920
> +#define _SEL_FETCH_PLANE_CTL_6_B 0x71940
> +#define SEL_FETCH_PLANE_CTL(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
> + _SEL_FETCH_PLANE_CTL_1_A, _SEL_FETCH_PLANE_CTL_1_B, \
> + _SEL_FETCH_PLANE_CTL_2_A, _SEL_FETCH_PLANE_CTL_2_B, \
> + _SEL_FETCH_PLANE_CTL_5_A, _SEL_FETCH_PLANE_CTL_5_B, \
> + _SEL_FETCH_PLANE_CTL_6_A, _SEL_FETCH_PLANE_CTL_6_B)
> +#define SEL_FETCH_PLANE_CTL_ENABLE REG_BIT(31)
> +
> +#define _SEL_FETCH_PLANE_POS_1_A 0x70894 /* mtl+ */
> +#define _SEL_FETCH_PLANE_POS_2_A 0x708b4
> +#define _SEL_FETCH_PLANE_POS_5_A 0x70924
> +#define _SEL_FETCH_PLANE_POS_6_A 0x70944
> +#define _SEL_FETCH_PLANE_POS_1_B 0x71894
> +#define _SEL_FETCH_PLANE_POS_2_B 0x718b4
> +#define _SEL_FETCH_PLANE_POS_5_B 0x71924
> +#define _SEL_FETCH_PLANE_POS_6_B 0x71944
> +#define SEL_FETCH_PLANE_POS(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
> + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
> + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
> + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
> + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
> +
> +#define _SEL_FETCH_PLANE_SIZE_1_A 0x70898 /* mtl+ */
> +#define _SEL_FETCH_PLANE_SIZE_2_A 0x708b8
> +#define _SEL_FETCH_PLANE_SIZE_5_A 0x70928
> +#define _SEL_FETCH_PLANE_SIZE_6_A 0x70948
> +#define _SEL_FETCH_PLANE_SIZE_1_B 0x71898
> +#define _SEL_FETCH_PLANE_SIZE_2_B 0x718b8
> +#define _SEL_FETCH_PLANE_SIZE_5_B 0x71928
> +#define _SEL_FETCH_PLANE_SIZE_6_B 0x71948
> +#define SEL_FETCH_PLANE_SIZE(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
> + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
> + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
> + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
> + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
> +
> +#define _SEL_FETCH_PLANE_OFFSET_1_A 0x7089c /* mtl+ */
> +#define _SEL_FETCH_PLANE_OFFSET_2_A 0x708bc
> +#define _SEL_FETCH_PLANE_OFFSET_5_A 0x7092c
> +#define _SEL_FETCH_PLANE_OFFSET_6_A 0x7094c
> +#define _SEL_FETCH_PLANE_OFFSET_1_B 0x7189c
> +#define _SEL_FETCH_PLANE_OFFSET_2_B 0x718bc
> +#define _SEL_FETCH_PLANE_OFFSET_5_B 0x7192c
> +#define _SEL_FETCH_PLANE_OFFSET_6_B 0x7194c
> +#define SEL_FETCH_PLANE_OFFSET(pipe, plane) _MMIO_SEL_FETCH((pipe), (plane),\
> + _SEL_FETCH_PLANE_POS_1_A, _SEL_FETCH_PLANE_POS_1_B, \
> + _SEL_FETCH_PLANE_POS_2_A, _SEL_FETCH_PLANE_POS_2_B, \
> + _SEL_FETCH_PLANE_POS_5_A, _SEL_FETCH_PLANE_POS_5_B, \
> + _SEL_FETCH_PLANE_POS_6_A, _SEL_FETCH_PLANE_POS_6_B)
> +
> #endif /* __SKL_UNIVERSAL_PLANE_REGS_H__ */
--
Jani Nikula, Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
* Re: [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES()
2024-05-23 9:15 ` Jani Nikula
@ 2024-05-23 12:06 ` Ville Syrjälä
0 siblings, 0 replies; 49+ messages in thread
From: Ville Syrjälä @ 2024-05-23 12:06 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Thu, May 23, 2024 at 12:15:53PM +0300, Jani Nikula wrote:
> On Thu, 16 May 2024, Ville Syrjala <ville.syrjala@linux.intel.com> wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Instead of that huge _PICK() let's use PICK_EVEN_2RANGES()
> > for the SEL_FETCH_PLANE registers. A bit more tedious to have
> > to define 8 raw register offsets for everything, but perhaps
> > a bit easier to understand since we use a standard mechanism
> > now instead of hand rolling the arithmetic.
> >
> > Also bloat-o-meter says:
> > add/remove: 0/0 grow/shrink: 0/3 up/down: 0/-326 (-326)
> > Function old new delta
> > icl_plane_update_arm 510 446 -64
> > icl_plane_disable_sel_fetch_arm.isra 158 54 -104
> > icl_plane_update_noarm 1898 1740 -158
> > Total: Before=2574502, After=2574176, chg -0.01%
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I just don't understand the old one.
>
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
>
>
> > ---
> > drivers/gpu/drm/i915/display/intel_psr_regs.h | 45 ------------
> > .../i915/display/skl_universal_plane_regs.h | 68 +++++++++++++++++++
> > 2 files changed, 68 insertions(+), 45 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > index f0bd0a726d7a..289c371c98d1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
<snip>
> > @@ -367,4 +378,61 @@
> > #define PLANE_BUF_START_MASK REG_GENMASK(11, 0)
> > #define PLANE_BUF_START(start) REG_FIELD_PREP(PLANE_BUF_START_MASK, (start))
> >
> > +#define _SEL_FETCH_PLANE_CTL_1_A 0x70890 /* mtl+ */
I noticed I had these bogus mtl+ comments here too, so changed
those to tgl+ while pushing.
Entire series is in now. Thanks for slogging through it.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 49+ messages in thread
end of thread, other threads:[~2024-05-23 12:06 UTC | newest]
Thread overview: 49+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-05-16 13:56 [PATCH 00/13] drm/i915: Plane register cleanups Ville Syrjala
2024-05-16 13:56 ` [PATCH 01/13] drm/i915: Add skl+ plane name aliases to enum plane_id Ville Syrjala
2024-05-17 15:33 ` Jani Nikula
2024-05-17 15:55 ` Ville Syrjälä
2024-05-17 17:12 ` [PATCH v2 " Ville Syrjala
2024-05-20 8:56 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 02/13] drm/i915: Clean up the cursor register defines Ville Syrjala
2024-05-20 9:10 ` Jani Nikula
2024-05-20 16:23 ` Ville Syrjälä
2024-05-20 16:34 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 03/13] drm/i915: Add separate define for SEL_FETCH_CUR_CTL() Ville Syrjala
2024-05-20 9:27 ` Jani Nikula
2024-05-20 17:08 ` Ville Syrjälä
2024-05-20 17:14 ` [PATCH v2 " Ville Syrjala
2024-05-16 13:56 ` [PATCH 04/13] drm/i915: Simplify PIPESRC_ERLY_TPT definition Ville Syrjala
2024-05-20 9:35 ` Jani Nikula
2024-05-20 9:37 ` Jani Nikula
2024-05-20 9:56 ` Hogander, Jouni
2024-05-16 13:56 ` [PATCH 05/13] drm/i915: Rename selective fetch plane registers Ville Syrjala
2024-05-20 9:39 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 06/13] drm/i915: Define SEL_FETCH_PLANE registers via PICK_EVEN_2RANGES() Ville Syrjala
2024-05-23 9:15 ` Jani Nikula
2024-05-23 12:06 ` Ville Syrjälä
2024-05-16 13:56 ` [PATCH 07/13] drm/i915: Add separate defines for cursor WM/DDB register bits Ville Syrjala
2024-05-20 13:24 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 08/13] drm/i915: Move PIPEGCMAX to intel_color_regs.h Ville Syrjala
2024-05-20 13:07 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 09/13] drm/i915: Extract i9xx_plane_regs.h Ville Syrjala
2024-05-20 13:09 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 10/13] drm/i915: Polish pre-skl primary plane registers Ville Syrjala
2024-05-20 13:12 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 11/13] drm/i915: Document a few pre-skl primary plane platform dependencies Ville Syrjala
2024-05-20 13:16 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 12/13] drm/i915: Polish sprite plane register definitions Ville Syrjala
2024-05-20 13:17 ` Jani Nikula
2024-05-20 13:18 ` Jani Nikula
2024-05-16 13:56 ` [PATCH 13/13] drm/i915: Document which platforms use which sprite registers Ville Syrjala
2024-05-20 13:18 ` Jani Nikula
2024-05-16 14:36 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups Patchwork
2024-05-16 14:36 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-16 18:21 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-05-17 18:07 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev2) Patchwork
2024-05-17 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-17 18:26 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-18 5:46 ` ✗ Fi.CI.IGT: failure " Patchwork
2024-05-20 18:08 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Plane register cleanups (rev3) Patchwork
2024-05-20 18:08 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-05-20 18:20 ` ✓ Fi.CI.BAT: success " Patchwork
2024-05-21 5:29 ` ✗ Fi.CI.IGT: failure " Patchwork
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